ON MMBT6517LT1 High voltage transistor(npn silicon) Datasheet

ON Semiconductor
High Voltage Transistor
MMBT6517LT1
NPN Silicon
3
1
2
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Collector–Emitter Voltage
VCEO
350
Vdc
Collector–Base Voltage
VCBO
350
Vdc
Emitter–Base Voltage
VEBO
5.0
Vdc
Base Current
IB
250
mAdc
Collector Current — Continuous
IC
500
mAdc
Symbol
Max
Unit
PD
225
mW
1.8
mW/°C
RJA
556
°C/W
PD
300
mW
2.4
mW/°C
RJA
417
°C/W
TJ, Tstg
–55 to +150
°C
CASE 318–08, STYLE 6
SOT–23 (TO–236AB)
COLLECTOR
3
1
BASE
THERMAL CHARACTERISTICS
Characteristic
Total Device Dissipation FR–5 Board(1)
TA = 25°C
Derate above 25°C
Thermal Resistance, Junction to Ambient
Total Device Dissipation
Alumina Substrate,(2) TA = 25°C
Derate above 25°C
Thermal Resistance, Junction to Ambient
Junction and Storage Temperature
2
EMITTER
DEVICE MARKING
MMBT6517LT1 = 1Z
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
350
—
350
—
6.0
—
—
50
—
50
Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage
(IC = 1.0 mAdc)
V(BR)CEO
Collector–Base Breakdown Voltage
(IC = 100 Adc)
V(BR)CBO
Emitter–Base Breakdown Voltage
(IE = 10 Adc)
V(BR)EBO
Collector Cutoff Current
(VCB = 250 Vdc)
ICBO
Emitter Cutoff Current
(VEB = 5.0 Vdc)
IEBO
Vdc
Vdc
Vdc
nAdc
nAdc
1. FR–5 = 1.0 0.75 0.062 in.
2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina.
 Semiconductor Components Industries, LLC, 2001
November, 2001 – Rev. 2
1
Publication Order Number:
MMBT6517LT1/D
MMBT6517LT1
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Symbol
Characteristic
Min
Max
20
30
30
20
15
—
—
200
200
—
—
—
—
—
0.30
0.35
0.50
1.0
—
—
—
0.75
0.85
0.90
—
2.0
40
200
—
6.0
—
80
Unit
ON CHARACTERISTICS
DC Current Gain
(IC = 1.0 mAdc, VCE = 10 Vdc)
(IC = 10 mAdc, VCE = 10 Vdc)
(IC = 30 mAdc, VCE = 10 Vdc)
(IC = 50 mAdc, VCE = 10 Vdc)
(IC = 100 mAdc, VCE = 10 Vdc)
hFE
Collector–Emitter Saturation Voltage (3)
(IC = 10 mAdc, IB = 1.0 mAdc)
(IC = 20 mAdc, IB = 2.0 mAdc)
(IC = 30 mAdc, IB = 3.0 mAdc)
(IC = 50 mAdc, IB = 5.0 mAdc)
VCE(sat)
Base–Emitter Saturation Voltage
(IC = 10 mAdc, IB = 1.0 mAdc)
(IC = 20 mAdc, IB = 2.0 mAdc)
(IC = 30 mAdc, IB = 3.0 mAdc)
VBE(sat)
Base–Emitter On Voltage
(IC = 100 mAdc, VCE = 10 Vdc)
VBE(on)
—
Vdc
Vdc
Vdc
SMALL–SIGNAL CHARACTERISTICS
Current Gain — Bandwidth Product
(IC = 10 mAdc, VCE = 20 Vdc, f = 20 MHz)
fT
Collector–Base Capacitance
(VCB = 20 Vdc, f = 1.0 MHz)
Ccb
Emitter–Base Capacitance
(VEB = 0.5 Vdc, f = 1.0 MHz)
Ceb
3. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2.0%.
Figure 1.
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2
MHz
pF
pF
VCE = 10 V
TJ = 125°C
100
25°C
70
50
-55°C
30
20
10
1.0
2.0
3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
50 70 100
100
70
50
20
10
1.0
Figure 1. DC Current Gain
TJ = 25°C
1.0
0.8
VBE(sat) @ IC/IB = 10
0.6
VBE(on) @ VCE = 10 V
2.5
1.5
VCE(sat) @ IC/IB = 5.0
3.0
5.0 7.0 10
20 30
50 70 100
IC, COLLECTOR CURRENT (mA)
0.5
0
RθVC for VCE(sat)
-55°C to 25°C
-2.0
-55°C to 125°C
RθVB for VBE
-2.5
1.0
2.0
Figure 3. “On” Voltages
3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
TJ = 25°C
Ceb
30
20
10
7.0
5.0
Ccb
3.0
2.0
0.5
50
Figure 4. Temperature Coefficients
100
70
50
1.0
0.2
100
25°C to 125°C
1.0
-1.5
VCE(sat) @ IC/IB = 10
2.0
50 70
IC
10
IB
2.0
-1.0
0.2
0
1.0
3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
-0.5
0.4
C, CAPACITANCE (pF)
V, VOLTAGE (VOLTS)
1.2
2.0
Figure 2. Current–Gain — Bandwidth Product
RθV, TEMPERATURE COEFFICIENTS (mV/°C)
1.4
TJ = 25°C
VCE = 20 V
f = 20 MHz
30
f,
T CURRENT-GAIN
hFE , DC CURRENT GAIN
200
BANDWIDTH PRODUCT (MHz)
MMBT6517LT1
1.0 2.0
5.0
10
20
VR, REVERSE VOLTAGE (VOLTS)
Figure 5. Capacitance
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50 100 200
70
100
MMBT6517LT1
1.0k
700
500
200
tr
100
70
50
2.0k
1.0k
700
500
30
300
20
200
10
1.0
2.0
3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
50
ts
3.0k
t, TIME (ns)
t, TIME (ns)
VCE(off) = 100 V
IC/IB = 5.0
TJ = 25°C
td @ VBE(off) = 2.0 V
300
10k
7.0k
5.0k
100
1.0
70 100
VCE(off) = 100 V
IC/IB = 5.0
IB1 = IB2
TJ = 25°C
tf
2.0 3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
50
70 100
Figure 7. Turn–Off Time
Figure 6. Turn–On Time
+VCC
VCC ADJUSTED
FOR VCE(off) = 100 V
+10.8 V
2.2 k
20 k
50 Ω SAMPLING SCOPE
1.0 k
50
1/2MSD7000
-9.2 V
PULSE WIDTH ≈ 100 µs
tr, tf ≤ 5.0 ns
DUTY CYCLE ≤ 1.0%
FOR PNP TEST CIRCUIT,
REVERSE ALL VOLTAGE POLARITIES
APPROXIMATELY
-1.35 V
(ADJUST FOR V(BE)off = 2.0 V)
r(t), TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
Figure 8. Switching Time Test Circuit
1.0
0.7
0.5
0.3
D = 0.5
0.2
0.2
0.1
0.07
0.05
0.1
P(pk)
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) RθJC(t)
SINGLE PULSE
0.03
t1
ZθJC(t) = r(t) • RθJC
ZθJA(t) = r(t) • RθJA
0.02
0.01
0.1
SINGLE PULSE
0.05
0.2
0.5
1.0
t2
DUTY CYCLE, D = t1/t2
2.0
5.0
10
20
50
t, TIME (ms)
100
Figure 9. Thermal Response
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4
200
500
1.0k
2.0k
5.0k 10k
MMBT6517LT1
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
SOLDERING PRECAUTIONS
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature
of the die, RθJA, the thermal resistance from the device
junction to ambient, and the operating temperature, TA.
Using the values provided on the data sheet for the SOT–23
package, PD can be calculated as follows:
PD =
The melting temperature of solder is higher than the
rated temperature of the device. When the entire device is
heated to a high temperature, failure to complete soldering
within a short time could result in device failure. Therefore, the following items should always be observed in
order to minimize the thermal stress to which the devices
are subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage
to the device.
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
PD =
150°C – 25°C
556°C/W
= 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher
power dissipation from the SOT–23 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
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MMBT6517LT1
PACKAGE DIMENSIONS
SOT–23 (TO–236)
CASE 318–08
ISSUE AF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
A
L
3
1
V
B S
2
G
C
D
H
K
J
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
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DIM
A
B
C
D
G
H
J
K
L
S
V
INCHES
MIN
MAX
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
0.0005 0.0040
0.0034 0.0070
0.0140 0.0285
0.0350 0.0401
0.0830 0.1039
0.0177 0.0236
MILLIMETERS
MIN
MAX
2.80
3.04
1.20
1.40
0.89
1.11
0.37
0.50
1.78
2.04
0.013
0.100
0.085
0.177
0.35
0.69
0.89
1.02
2.10
2.64
0.45
0.60
MMBT6517LT1
Notes
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MMBT6517LT1
Thermal Clad is a trademark of the Bergquist Company.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MMBT6517LT1/D
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