Rochester EP610DC-35 High-performance, 16-macrocell classic epld pipelined data rates of up to 100 mhz Datasheet

EP610
© 2013 Rochester Electronics, LLC. All Rights Reserved 04112013
Features
High-performance, 16-macrocell Classic EPLD
- Combinatorial speeds with tPD as low as 10 ns
- Counter frequencies of up to 100 MHz
- Pipelined data rates of up to 100 MHz
Programmable I/O architecture with up to 20 inputs or 16 outputs
and 2 Clock pins
The following devices are pin-, function-, and programming
file-compatible: EP610, EP610I, EP610T, EP610-XX/B, EP600I, and
PALCE610
Programmable Clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in windowed ceramic and one-time-programmable (OTP)
plastic packages (see Figure 1):
- 24-pin small-outline integrated circuit (plastic SOIC only)
- 24-pin dual in-line package (CerDIP and PDIP)
- 28-pin plastic J-lead chip carrier (PLCC)
Figure 1. EP610 Package Pin-Out Diagrams
22
I/O
I/O
4
21
I/O
I/O
3
INPUT
I/O
VCC
INPUT
VCC
VCC
23
CLK1
24
2
INPUT
1
4
3
2
1
28
27
26
I/O
5
25
I/O
I/O
6
24
I/O
I/O
7
23
I/O
INPUT
22
I/O
I/O
5
20
I/O
I/O
4
21
I/O
I/O
6
19
I/O
I/O
8
22
I/O
I/O
5
20
I/O
I/O
6
19
I/O
I/O
7
18
I/O
I/O
9
21
I/O
I/O
7
18
I/O
I/O
8
17
I/O
I/O
10
20
I/O
I/O
8
17
I/O
I/O
9
16
I/O
I/O
9
16
I/O
I/O
10
15
I/O
NC
11
19
NC
I/O
10
15
I/O
INPUT
11
14
INPUT
INPUT
11
14
INPUT
GND
12
13
CLK2
GND
12
13
CLK2
12
13
14
15
16
17
18
I/O
23
3
INPUT
2
I/O
CLK2
INPUT
GND
VCC
GND
24
INPUT
1•
I/O
CLK1
CLK1
INPUT
I/O
Package outlines not drawn to scale. Windows in ceramic packages only.
24-Pin SOIC
24-Pin DIP
28-Pin J-Lead
EP610
EP610T
EP610
EP610T
EP610-XX/B
EP610I
EP610
EP610T
EP610I
For complete Rochester ordering guide, please refer to page 2
Please contact factory for specific package availability and
Military/Aerospace specifications/availability.
Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes
only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves
the right to make changes without further notice to any specification herein.
Specification Number EP610-CI (AT) REV -
Page 1 of 9
EP610
Rochester Ordering Guide
*Most products can also be offered as RoHS compliant, designated by a –G suffix. Please contact factory for more information.
Package
Temperature
EP610DC-25
Rochester Part Number
EP610DC-25
Altera Part Number
CDIP-24
0° to +70°C
EP610DC-30
EP610DC-30
CDIP-24
0° to +70°C
EP610DC-35
EP610DC-35
CDIP-24
0° to +70°C
EP610DI-30
EP610DI-30
CDIP-24
-40° to +85°C
EP610DI-35
EP610DI-35
CDIP-24
-40° to +85°C
EP610DM-35
EP610DM-35
CDIP-24
-55° to +125°C
EP610DM/B
EP610DM883B
CDIP-24
-55° to +125°C
EP610JC-25
EP610JC-25
LDCC-28, Ceramic
0° to +70°C
EP610JC-30
EP610JC-30
LDCC-28, Ceramic
0° to +70°C
EP610JC-35
EP610JC-35
LDCC-28, Ceramic
0° to +70°C
EP610JI-30
EP610JI-30
LDCC-28, Ceramic
-40° to +85°C
EP610JI-35
EP610JI-35
LDCC-28, Ceramic
-40° to +85°C
EP610JM-35
EP610JM-35
LDCC-28, Ceramic
-55° to +125°C
EP610JM-40
EP610JM-40
LDCC-28, Ceramic
-55° to +125°C
EP610LC-15
EP610LC-15
LDCC-28, Plastic
0° to +70°C
EP610LC-20
EP610LC-20
LDCC-28, Plastic
0° to +70°C
EP610LC-25
EP610LC-25
LDCC-28, Plastic
0° to +70°C
EP610LC-30
EP610LC-30
LDCC-28, Plastic
0° to +70°C
EP610LI-20
EP610LI-20
LDCC-28, Plastic
-40° to +85°C
EP610LI-30
EP610LI-30
LDCC-28, Plastic
-40° to +85°C
EP610LI-35
EP610LI-35
LDCC-28, Plastic
-40° to +85°C
EP610PC-15
EP610PC-15
PDIP-24
0° to +70°C
EP610PC-20
EP610PC-20
PDIP-24
0° to +70°C
EP610PC-25
EP610PC-25
PDIP-24
0° to +70°C
EP610PC-30
EP610PC-30
PDIP-24
0° to +70°C
EP610PC-35
EP610PC-35
PDIP-24
0° to +70°C
EP610PI-30
EP610PI-30
PDIP-24
-40° to +85°C
EP610PI-35
EP610PI-35
PDIP-24
-40° to +85°C
EP610SC-15
EP610SC-15
SOP-24, Plastic
0° to +70°C
EP610SC-20
EP610SC-20
SOP-24, Plastic
0° to +70°C
EP610SC-25
EP610SC-25
SOP-24, Plastic
0° to +70°C
EP610SC-30
EP610SC-30
SOP-24, Plastic
0° to +70°C
Specification Number EP610-CI (AT) REV -
Page 2 of 9
EP610
Table 1 summarizes EP610 device features
Table 1. EP610 Device Features
Feature
EP610
EP610T
EP610-XX/B
EP610I
tPD
15 ns
15 ns
35 ns
10 ns
Counter frequency
83 MHz
83 MHz
28.5 MHz
100 MHz
Pipeline data rates
83 MHz
83 MHz
37 MHz
100 MHz
Packages
24-pin SOIC
24-pin CerDIP
24-pin PDIP
24-pin PLCC
24-pin SOIC
24-pin PDIP
28-pin PLCC
24-pin CerDIP
24-pin CerDIP
24-pin PDIP
28-pin PLCC
General
Description
EP610 devices have 16 macrocells, 4 dedicated input pins, 16
I/O pins, and 2 global Clock pins (see Figure 2). Each macrocell
can access signals from the global bus, which consists of the
true and complement forms of the dedicated inputs and the
true complement forms of either the output of the macrocell of
the I/O input. CLK1 is a dedicated Clock input for the registers
in macrocells 9 through 16. CLK2 is a dedicated Clock input for
registers in macrocells 1 through 8.
Figure 2. EP610 Block Diagram
Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages.
2 (3) INPUT
INPUT 23 (27)
1 (2)
CLK2
CLK1
3 (4)
4 (5)
5 (6)
6 (7)
7 (8)
8 (9)
9 (10)
10 (12)
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
Global
Bus
11 (13) INPUT
Specification Number EP610-CI (AT) REV -
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
13 (16)
22 (26)
21 (25)
20 (24)
19 (23)
18 (22)
17 (21)
16 (20)
15 (18)
INPUT 14 (17)
Page 3 of 9
EP610
Absolute Maximum Ratings
EP610
EP610T
EP610-XX/B
Symbol
Parameter
VCC
Supply voltage
VI
DC input voltage
IMAX
Conditions
EP610I
Min
Max
-2.0
7.0
-2.0
7.0
V
-2.0
7.0
-0.5
VCC+
0.5
V
DC VCC or GND current
-175
175
mA
IOUT
DC output current, per pin
-25
25
mA
PD
Power dissipation
1000
mW
TSTG
Storage temperature
No bias
-65
150
-65
150
°C
TAMB
Ambient temperature
Under bias
-65
135 (125)
-10
85
°C
TJ
Junction temperature
Under bias
With respect
to GND
Min Max Unit
(150)
°C
Recommended Operating Conditions
EP610
EP610T
EP610-XX/B
Symbol
Parameter
VCC
Conditions
EP610I
Min
Max
Min Max Unit
Supply voltage
4.75 (4.5)
5.25 (5.5)
4.75
5.25
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
TA
Operating Temperature
For commerical use
0
70
0
70
°C
TA
Operating Temperature
For industrial use
-40
85
-40
85
°C
TC
Case Temperature
For military use
-55
125
tR
Input rise time
100 (50)
500
ns
tF
Input fall time
100 (50)
500
ns
°C
Recommended Operating Conditions
Symbol
Parameter
VIH
High-level input voltage
Conditions
Min
Typ
Max
Unit
2.0
VCC + 0.3
V
-0.3
0.8
V
VIL
Low-level input voltage
VOH
High-level TTL output voltage
IOH = -4 mA DC
2.4
V
VOH
High-level CMOS output voltage
IOH = -2 mA DC
3.84
V
VOL
Low-level output voltage
IOL = 4 mA DC
II
Input leakage output
VI = VCC or GND
IOZ
Tri-state output leakage current
VO = VCC or GND
Specification Number EP610-CI (AT) REV -
0.45
V
-10
10
µA
-10
10
µA
Page 4 of 9
EP610
Capacitance
EP610
EP610T
Symbol
Parameter
Conditions
CIN
Input pin capacitance
VIN = 0 V, f = 1.0 MHz
CI/O
I/O pin capacitance
CCLK1
CCLK2
EP610-XX/B
Min Max
Min
EP610I
Max
Min Max Unit
10
20
8
pF
VOUT = 0 V, f = 1.0 MHz
12
20
8
pF
CLK1 pin capacitance
VIN = 0 V, f = 1.0 MHz
20
20
10
pF
CLK2 pin capacitance
VIN = 0 V, f = 1.0 MHz
20
20
12
pF
ICC Supply Current: EP610 & EP610T
EP610
Speed
Grade
Min Typ
EP610T
Symbol
Parameter
Conditions
Max
Min Typ Max Unit
ICC1
VCC supply current
(non-turbo, standby)
VI = VCC or GND,
No load
20
150
µA
ICC2
VCC supply current
(non-turbo, active)
VI = VCC or GND,
No load,
f = 1.0 MHz
5
10 (15)
mA
ICC3
VCC supply current
(turbo, active)
-15, -20
60
90 (115)
60
90
mA
-25, -30, -35
45
60 (75)
60
90
mA
ICC Supply Current: EP610-XX/B & EP610I
EP610-XX/B
Symbol
Parameter
Conditions
ICC1
VCC supply current
(non-turbo, standby)
VI = VCC or GND, No load
900
20
150
µA
ICC2
VCC supply current
(non-turbo, active)
VI = VCC or GND, No load,
f = 1.0 MHz
25
3
8
mA
ICC3
VCC supply current
(turbo, active)
VI = VCC or GND, No load,
f = 1.0 MHz
140
65
105
mA
Specification Number EP610-CI (AT) REV -
Min Typ
EP610I
Max Min Typ
Max Unit
Page 5 of 9
EP610
AC Operating Conditions: EP610-15 & EP610-20
EP610-15 EP610-20 Non-Turbo
EP610-15T EP610-20T
Adder
Symbol
Parameter
Conditions Min Max Min Max
Unit
tPD1
Input to non-registered output
C1 = 35 pF
15
20
20
ns
tPD2
I/O input to non-registered output
C1 = 35 pF
17
22
20
ns
tPZX
Input to output enable
C1 = 35 pF
15
20
20
ns
tPXZ
Input to output disable
C1 = 5 pF
15
20
20
ns
tCLR
Asynchronous output clear time
C1 = 35 pF
15
20
20
ns
tIO
I/O input pad and buffer delay
2
2
0
ns
fMAX
Maximum clock frequency
83.3
62.5
0
MHz
tSU
Global clock input setup time
9
11
20
ns
tH
Global clock input hold time
0
0
0
ns
tCH
Global clock high time
6
8
0
ns
6
tCL
Global clock low time
0
ns
tCO1
Global clock to output delay
11
8
13
0
ns
tCNT
Global clock minimum period
12
16
0
ns
fCNT
Global clock internal maximum frequency
83.3
62.5
0
MHz
tASU
Array clock input setup time
6
8
20
ns
tAH
Array clock input hold time
6
8
0
ns
tACH
Array clock high time
7
9
0
ns
7
tACL
Array clock low time
0
ns
tACO1
Array clock to output delay
15
20
20
ns
tACNT
Array clock minimum period
14
18
0
ns
fACNT
Array clock internal maximum frequency
0
MHz
Specification Number EP610-CI (AT) REV -
71.4
9
55.6
Page 6 of 9
EP610
AC Operating Conditions: EP610-15 & EP610-20
Note (1)
EP610-25 EP610-20
EP610-25T EP610-20T
Symbol
Parameter
tPD1
Input to non-registered output
EP610-35
NonTurbo
Adder
Conditions Min Max Min Max Min Max
C1 = 35 pF
Unit
25
30
35
30
ns
tPD2
I/O input to non-registered output
27
32
37
30
ns
tPZX
Input to output enable
25
30
35
30
ns
tPXZ
Input to output disable
C1 = 5 pF
Note (2)
25
30
35
30
ns
tCLR
Asynchronous output clear time
C1 = 35 pF
27
32
37
30
ns
2
tIO
I/O input pad and buffer delay
fMAX
Maximum clock frequency
2
tSU
Global clock input setup time
tH
Global clock input hold time
0
tCH
Global clock high time
10
10
Note (3)
0
ns
47.6
41.7
2
37.0
0
MHz
21
24
27
30
ns
0
0
0
ns
11
12
0
ns
tCL
Global clock low time
0
ns
tCO1
Global clock to output delay
15
17
20
0
ns
tCNT
Global clock minimum period
25
30
35
0
ns
fCNT
Global clock internal maximum
frequency
tASU
Note (4)
11
12
40.0
33.3
28.6
0
MHz
Array clock input setup time
8
8
8
30
ns
tAH
Array clock input hold time
12
12
12
0
ns
tACH
Array clock high time
10
11
12
0
ns
tACL
Array clock low time
10
0
ns
tACO1
Array clock to output delay
27
32
37
30
ns
tACNT
Array clock minimum period
25
30
35
0
ns
fACNT
Array clock internal maximum
frequency
0
MHz
Note (4)
40.0
11
33.3
12
28.6
Notes to tables:
(1) Operating conditions: VCC = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
VCC = 5 V ± 10%, TA = -40° C to 85° C for industrial use.
VCC = 5 V ± 10%, TC = -55° C to 125° C for military use.
(2) Sample-tested only for an output change of 500 mV.
(3) The fMAX values represent the highest frequency for pipelined data.
(4) Measured with a device programmed as a 16-bit counter. ICC measured at 0° C.
Specification Number EP610-CI (AT) REV -
Page 7 of 9
EP610
AC Operating Conditions: EP610-XX/B
Symbol
Parameter
tPD1
Input to non-registered output
tPD2
I/O input to non-registered output
tPZX
Input to output enable
tPXZ
Input to output disable
Note (1)
Conditions
C1 = 35 pF
C1 = 5 pF
Min
Notes (2), (3)
Notes (2), (3), (4), (5)
C1 = 35 pF
Notes (2), (3)
Max
Unit
35
ns
37
ns
35
ns
35
ns
tCLR
Asynchronous output clear time
fMAX
Maximum clock frequency
Note (2), (6), (7)
37.0
37
MHz
ns
tSU
Global clock input setup time
Note (2), (3)
27
ns
tH
Global clock input hold time
Note (3)
0
ns
tCH
Global clock high time
Note (4)
12
ns
tCL
Global clock low time
Note (4)
12
tCO1
Global clock to output delay
ns
20
35
ns
tCNT
Global clock minimum period
Note (4), (8)
fCNT
Global clock internal maximum frequency
Note (8)
28.5
MHz
ns
tASU
Array clock input setup time
Notes (2), (3), (4)
8
ns
tAH
Array clock input hold time
Notes (2), (3), (4)
12
ns
tACH
Array clock high time
Notes (3), (4)
12
ns
12
tACL
Array clock low time
Notes (3), (4)
tACO1
Array clock to output delay
Notes (2), (3)
37
ns
tACNT
Array clock minimum period
Notes (4), (8)
35
ns
fACNT
Array clock internal maximum frequency
Notes (4), (8)
28.6
ns
MHz
Notes to tables:
(1) Screening and characterization of AC delay parameters are conducted at 10 MHz or less.
Operating conditions: VCC = 5 V ± 10%, TC = -55° C to 125° C for military use.
(2) All array-dependent delays are specified for an XOR pattern. This pattern includes two product terms and two
pure inputs; all other product terms in the macrocell are held low by one EPROM cell. Other patterns may result
in longer delays. Delays for patterns involving only one product term (such as tPXZ ) are specified for an XOR
pattern in which only one pure input switches at a time.
(3) When the Turbo Bit is not set (non-turbo mode), a non-turbo adder of 30 ns (maximum) is added to this
parameter to determine worst-case timing. Parameters may not be tested in non-turbo mode, but are
guaranteed to the limits specified. Devices operating in non-turbo mode require one input or I/O transition to
guarantee that the device will enter the correct power-up state.
(4) These parameters may not be tested, but are guaranteed to the limits specified in the table under “Absolute
Maximum Ratings” on page 3.
(5) Not tested directly, but guaranteed by testing tPD.
(6) The fMAX values represent the highest frequency for pipelined data.
(7) Not tested directly, but derived from tSU.
(8) Specified with device programmed as a 16-bit counter with no output loading.
Specification Number EP610-CI (AT) REV -
Page 8 of 9
EP610
AC Operating Conditions: EP610I
Note (1)
EP610I-10 EP610I-15 EP610I-25
Symbol
Parameter
Non-Turbo
Adder
Min Max Min Max Min Max
Unit
tPD1
Input to non-registered output, Note (2)
10
15
25
25
ns
tPD2
I/O input to non-registered output, Note (2)
10
15
25
25
ns
tPZX
Input to output enable
15
18
25
25
ns
tPXZ
Input to output disable, Note (3)
13
18
25
25
ns
tCLR
Asynchronous output clear time
13
18
25
25
ns
fMAX
Maximum clock frequency
111
83.3
66
0
MHz
tSU
Global clock input setup time
7
12
15
25
ns
tH
Global clock input hold time
0
0
0
0
ns
tCH
Global clock high time
5
6
7.5
0
ns
tCL
Global clock low time
5
6
7.5
0
ns
tCO1
Global clock to output delay
6.5
8
10
0
ns
tCNT
Global clock minimum period
10
15
25
25
ns
fCNT
Global clock internal maximum frequency,
Note (4)
100
66
40
0
MHz
tASU
Array clock input setup time
2
4
5
25
ns
tAH
Array clock input hold time
3
6
8
0
ns
tACH
Array clock high time
5
7.5
10
0
ns
tACL
Array clock low time
5
7.5
10
0
ns
tACO1
Array clock to output delay
12
16
25
25
ns
tACNT
Array clock minimum period, Note (4)
10
15
25
25
ns
fACNT
Array clock internal maximum frequency,
Note (4)
0
MHz
100
66
40
Notes to tables:
(1) Operating conditions: VCC = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
VCC = 5 V ± 10%, TA = -40° C to 85° C for industrial use.
(2) Measured with eight outputs switching.
(3) Sample-tested only for an output change of 500 mV.
(4) Measured with a device programmed as a 16-bit counter.
Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes
only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves
the right to make changes without further notice to any specification herein.
Specification Number EP610-CI (AT) REV -
Page 9 of 9
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