ICST ICS954201YGLNT Programmable timing control hubâ ¢ for mobile p4â ¢ system Datasheet

ICS954201
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub™ for Mobile P4™ Systems
Recommended Application:
CK410M clock, Intel Yellow Cover part
Output Features:
•
2 - 0.7V current-mode differential CPU pairs
•
7 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
•
1 - 0.7V current-mode differential CPU/SRC selectable
pair
•
4 - PCI (33MHz)
•
2 - PCICLK_F, (33MHz) free-running
•
1 - USB, 48MHz
•
1 - DOT, 96MHz, 0.7V current differential pair
•
1 - REF, 14.318MHz
Features/Benefits:
•
Supports tight ppm accuracy clocks for Serial-ATA and
PCI-Express
•
Supports spread spectrum modulation, 0 to -0.5%
down spread
•
Supports CPU clocks up to 400MHz
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
•
Supports undriven differential CPU, SRC pair in PD#
for power management.
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC outputs cycle-cycle jitter < 125ps
•
PCI outputs cycle-cycle jitter < 500ps
•
+/- 300ppm frequency accuracy on CPU & SRC clocks
•
+/- 100ppm frequency accuracy on USB clocks
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ICS954201
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
ITP_EN/PCICLK_F0
PCICLK_F1
Vtt_PwrGd#/PD
VDD48
USB_48MHz/FS_A
GND
DOTT_96MHz
DOTC_96MHz
FS_B/TEST_MODE
SRCCLKT0
SRCCLKC0
SRCCLKT1
SRCCLKC1
VDDSRC
SRCCLKT2
SRCCLKC2
SRCCLKT3
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
Functionality
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCICLK2
PCI/SRC_STOP#
CPU_STOP#
FS_C/TEST_SEL
REFOUT
GND
X1
X2
VDDREF
SDATA
1.
SCLK
GND
2.
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
IREF
GNDA
VDDA
CPUCLKT2_ITP/SRCCLKT7
CPUCLKC2_ITP/SRCCLKC7
VDDSRC
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
GND
56-pin SSOP & TSSOP
0819G—12/06/04
1
FS_C
0
0
0
0
1
1
1
1
2
2
FS_B FS_A
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CPU
SRC
MHz
MHz
266.66
100.00
133.33
100.00
200.00
100.00
166.66
100.00
333.33
100.00
100.00
100.00
400.00
100.00
RESERVED
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
REF
MHz
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
USB
MHz
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
DOT
MHz
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
ICS954201
Integrated
Circuit
Systems, Inc.
Pin Description
PIN # PIN NAME
PIN
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
PWR
DESCRIPTION
1
2
3
4
5
6
7
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
8
ITP_EN/PCICLK_F0
9
PCICLK_F1
10
Vtt_PwrGd#/PD
11
VDD48
12
USB_48MHz/FS_A
13
14
GND
DOTT_96MHz
PWR
OUT
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
Free running PCI clock not affected by PCI_STOP# .
Vtt_PwrGd# is an active low input used to determine when
latched inputs are ready to be sampled. PD is an asynchronous
active high input pin used to put the device into a low power
state. The internal clocks, PLLs and the crystal oscillator are
stopped.
Power pin for the 48MHz output.3.3V
Frequency select latch input pin / Fixed 48MHz USB clock
output. 3.3V.
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
15
DOTC_96MHz
OUT
Complement clock of differential pair for 96.00MHz DOT clock.
I/O
OUT
IN
PWR
I/O
16
FS_B/TEST_MODE
IN
17
18
19
20
21
22
23
24
25
26
27
28
SRCCLKT0
SRCCLKC0
SRCCLKT1
SRCCLKC1
VDDSRC
SRCCLKT2
SRCCLKC2
SRCCLKT3
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
3.3V tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values.
TEST_MODE is a real time input to select between Hi-Z and
REF/N divider mode while in test mode. Refer to Test
Clarification Table.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC/SATA pair.
Complement clock of differential SRC/SATA pair.
Supply for SRC clocks, 3.3V nominal
0819G—12/06/04
2
ICS954201
Integrated
Circuit
Systems, Inc.
Pin Description (Continued)
PIN #
29
30
31
32
33
34
PIN NAME
GND
SRCCLKC5
SRCCLKT5
SRCCLKC6
SRCCLKT6
VDDSRC
TYPE
PWR
OUT
OUT
OUT
OUT
PWR
35
CPUCLKC2_ITP/SRCCLKC7
OUT
36
CPUCLKT2_ITP/SRCCLKT7
OUT
37
38
VDDA
GNDA
PWR
PWR
39
IREF
OUT
40
CPUCLKC1
OUT
41
CPUCLKT1
OUT
42
VDDCPU
PWR
43
CPUCLKC0
OUT
44
CPUCLKT0
OUT
45
46
47
48
49
50
51
52
GND
SCLK
SDATA
VDDREF
X2
X1
GND
REFOUT
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
53
FS_C/TEST_SEL
IN
54
CPU_STOP#
IN
55
PCI/SRC_STOP#
IN
56
PCICLK2
OUT
DESCRIPTION
Ground pin.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Complimentary clock of CPU_ITP/SRC differential pair
CPU_ITP/SRC output. These are current mode outputs.
External resistors are required for voltage bias. Selected by
ITP_EN input.
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are
required for voltage bias. Selected by ITP_EN input.
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
True clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
True clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
Reference Clock output
3.3V tolerant input for CPU frequency selection. Low voltage
threshold inputs, see input electrical characteristics for Vil_FS
and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and SRCCLKs besides the free-running
clocks at logic 0 level, when input low
PCI clock output.
0819G—12/06/04
3
ICS954201
Integrated
Circuit
Systems, Inc.
General Description
ICS954201 is a CK410M Yellow Cover clock synthesizer. ICS954201 provides a single-chip solution for mobile systems built
with Intel P4-M processors and Intel mobile chipsets. ICS954201 is driven with a 14.318MHz crystal and generates CPU
outputs up to 400MHz. It provides the tight ppm accuracy required by Serial ATA and PCI-Express.
Block Diagram
REF
USB_48MHz
X1
X2
XTAL
OSC.
FIXED PLL
DIVIDER
DOT_96MHz
PCICLK(5:2)
PCICLK_F(1:0)
PROG.
SPREAD
MAIN PLL
SRCCLK(6:0)
PROG.
DIVIDERS
CPUCLK2_ITP/SRCCLK7
CPUCLK(1:0)
PCI/SRC_STOP#
CPU_STOP#
FS(C:A)
ITP_EN
TEST_MODE
TEST_SEL
VTT_PWRGD#/PD
CONTROL
LOGIC
SDATA
SCLK
IREF
Power Groups
Pin Number
VDD
GND
48
51
1,7
2,6
21,28,34
29
37
38
11
13
42
45
Description
Xtal, Ref
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
DOT, USB, PLL_48
CPUCLK clocks
0819G—12/06/04
4
ICS954201
Integrated
Circuit
Systems, Inc.
General I2C serial interface information for the ICS954201
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WRite
WR
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
0819G—12/06/04
5
Not acknowledge
stoP bit
ICS954201
Integrated
Circuit
Systems, Inc.
Absolute Max
Symbol
Parameter
VDD_A
VDD_In
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
ESD prot
Min
Max
Units
GND - 0.5
V DD + 0.5V
V DD + 0.5V
V
V
-65
0
°
C
°C
°C
150
70
115
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
Input High Voltage
V IH
3.3 V +/-5%
2
Input Low Voltage
Input High Current
V IL
I IH
I IL1
Input Low Current
I IL2
Low Threshold Input High
Voltage
3.3 V +/-5%
V SS - 0.3
V IN = VDD
-5
VIN = 0 V; Inputs with no pull-up
-5
resistors
V IN = 0 V; Inputs with pull-up
-200
resistors
1
V
uA
1
1
uA
1
uA
1
V
1
V SS - 0.3
0.35
V
1
400
70
12
7
5
6
5
mA
mA
mA
MHz
nH
pF
pF
pF
3
1
1
1
1
1.8
ms
1,2
33
kHz
1
10
ns
1
300
us
1
5
5
ns
ns
1
2
10
ns
1
5
5
5.5
0.4
ns
ns
V
V
mA
1
2
1
1
1
1000
ns
1,3
300
ns
1,3
Powerdown Current
I DD3.3PD
Full Active, CL = Full load;
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
Fi
Lpin
CIN
COUT
CINX
TSTAB
Modulation Frequency
Tdrive_SRC
Tdrive_PD
Tfall_PD
Trise_PD
Tdrive_CPU_STOP
Tfall_CPU_STOP
Trise_CPU_STOP#
SMBus Voltage
Low-level Output Voltage
Current sinking
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
V
0.8
5
VDD + 0.3
I DD3.3OP
Clk Stabilization1,2
VDD + 0.3
0.7
3.3 V +/-5%
Input Capacitance1
UNITS Notes
3.3 V +/-5%
VIL_FS
Input Frequency
Pin Inductance1
MAX
VIH_FS
Low Threshold Input Low
Voltage
Operating Supply Current
3
TYP
V DD
V OL
I PULLUP
TRI2C
TFI2C
Logic Inputs
Output pin capacitance
X1 & X2 pins
From V DD Power-Up or deassertion of PD# to 1st clock
Triangular Modulation
SRC output enable after
PCI_STOP de-assertion
Differential output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
CPU output enable after
CPU_STOP de-assertion
CPU_STOP fall time of
CPU_STOP rise time of
278
67
4.8
14.31818
1.3
30
8
8
2.7
SDATA, SCLK @ I PULLUP
VOL = 0.4 V
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
4
1
Guaranteed by design, not 100% tested in production.
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
2
0819G—12/06/04
6
ICS954201
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
Current Source Output
Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
CONDITIONS
MIN
Zo1
VO = Vx
3000
VHigh
VLow
Vovs
Vuds
Vcross
(abs)
Statistical measurement on single
ended signal using oscilloscope
Measurement on single ended
signal using absolute value.
660
-150
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min/max period
Tabs
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
tr
tf
d-tr
d-tf
Variation of crossing over all
edges
see Tperiod min-max values
100.00MHz non-spread
100.00MHz spread
100.00MHz non-spread
100.00MHz spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V, VOL = 0.175V
TYP
MAX
UNITS Notes
Ω
850
150
1150
-300
760
2
782
-33
250
344
550
mV
1
97
140
mV
1
300
10.0030
10.0533
10.1280
10.1783
700
700
125
125
ppm
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
1,2
1,2
1
1
1
1
-300
9.9970
9.8720
175
175
9.9999
9.9999
260
212
20
13
mV
mV
Measurement from differential
45
51
55
%
wavefrom
VT = 50%
tsk3
87
250
ps
Skew
Measurement from differential
tjcyc-cyc
Jitter, Cycle to cycle
37
125
ps
wavefrom
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Duty Cycle
dt3
0819G—12/06/04
7
1
1,3
1,3
1
1
1
1
1
ICS954201
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
Current Source Output
Impedance
SYMBOL
CONDITIONS
MIN
Zo
VO = Vx
3000
Voltage High
VHigh
Statistical measurement on single
ended signal using oscilloscope
math function.
Measurement on single ended
signal using absolute value.
660
Voltage Low
VLow
Max Voltage
Min Voltage
Vovs
Vuds
Vcross
(abs)
Crossing Voltage (abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Absolute min/max period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Tperiod
Tabs
tr
tf
d-tr
d-tf
Variation of crossing over all
edges
see Tperiod min-max values
400MHz non-spread
400MHz spread
333.33MHz non-spread
333.33MHz spread
266.66MHz non-spread
266.66MHz spread
200MHz non-spread
200MHz spread
166.66MHz non-spread
166.66MHz spread
133.33MHz non-spread
133.33MHz spread
100.00MHz non-spread
100.00MHz spread
400MHz non-spread
400MHz spread
333.33MHz non-spread
333.33MHz spread
266.66MHz non-spread
266.66MHz spread
200MHz non-spread
200MHz spread
166.66MHz non-spread
166.66MHz spread
133.33MHz non-spread
133.33MHz spread
100.00MHz non-spread
100.00MHz spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
TYP
MAX
UNITS Notes
Ω
727
850
1,3
mV
-150
-2
150
752
-21
1150
-300
250
348
39
-300
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.9135
5.9132
7.4128
9.9120
175
175
2.4999
3.0000
3.7509
4.9998
6.0000
7.5017
10.0000
2.4970
2.9940
3.7430
4.9940
5.9950
7.4970
10.0000
230
206
15
14
1,3
mV
1
1
550
mV
1
140
mV
1
300
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
2.5750
2.5983
3.0859
3.1010
3.8361
3.8550
5.0865
5.1116
6.0868
6.1170
7.5873
7.6250
10.0880
10.1383
700
700
125
125
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
Measurement from differential
45
51
55
%
wavefrom
CPU(1:0), VT = 50%
7.5
100
ps
tsk3
Skew
CPU2_ITP, VT = 50%
145
150
ps
Differential waveform
t
36
85
ps
Jitter, Cycle to cycle
jcyc-cyc
measurement, CPU(1:0)
Differential waveform
tjcyc-cyc
96
125
ps
Jitter, Cycle to cycle
measurement, CPU2_ITP
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Duty Cycle
dt3
0819G—12/06/04
8
1
1
1
1
1
1
ICS954201
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
Long Accuracy
ppm
Clock period
Tperiod
Absolute min/max period
Tabs
Output High Voltage
Output Low Voltage
VOH
VOL
Output High Current
I OH
Output Low Current
I OL
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
tr1
tf1
dt1
tsk1
Jitter
tjcyc-cyc
CONDITIONS
MIN
see Tperiod min-max values
-300
33.33MHz output non-spread
29.9910
33.33MHz output spread
33.33MHz output non-spread
29.4910
33.33MHz output spread
IOH = -1 mA
2.4
IOL = 1 mA
-33
V OH @MIN = 1.0 V
VOH@ MAX = 3.135 V
30
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
1
Falling edge rate
1
VOL = 0.4 V, VOH = 2.4 V
0.5
VOH = 2.4 V, VOL = 0.4 V
0.5
VT = 1.5 V
45
VT = 1.5 V
VT = 1.5 V
TYP
MAX
35
29.9989
30.0752
300
30.0090
30.1598
30.5090
30.6598
3.25
0.05
-62
-10
61
23
1.60
1.71
1.25
1.17
50
81
250
UNITS Notes
38
4
4
2
2
55
500
ppm
ns
ns
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
ns
ns
%
ps
1,2
2
2
1,2
1,2
1
1
1
1
1
1
1
1
1
1
1
1
500
ps
1
0.55
-33
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
2
Electrical Characteristics - 48MHz, USB
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Long Accuracy
Clock period
Absolute min/max period
Output High Voltage
Output Low Voltage
ppm
Tperiod
Tabs
VOH
VOL
see Tperiod min-max values
48.00000 MHz output
48.00000 MHz output
IOH = -1 mA
IOL = 1 mA
VOH @ MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
-100
20.8313
20.4813
2.4
0.25
20.8333
100
20.8354
21.1854
1
1
3.25
0.05
-53
-6.2
61
23
1.53
1.68
Output High Current
Output Low Current
I OH
I OL
Edge Rate
Edge Rate
-29
29
UNITS Notes
27
2
2
ppm
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
1,2
2
1,2
1
1
1
1
1
1
1
1
0.55
-23
Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
1
1.31
2
ns
1
Fall Time
Duty Cycle
tf1
dt1
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
45
1.19
52
2
55
ns
%
1
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
139
350
ps
1
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
2
0819G—12/06/04
9
ICS954201
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - DOT, 96MHz 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
Current Source Output
Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
CONDITIONS
MIN
Zo1
VO = Vx
3000
VHigh
VLow
Vovs
Vuds
Vcross
(abs)
Statistical measurement on single
ended signal using oscilloscope
Measurement on single ended
signal using absolute value.
660
-150
Crossing Voltage (var)
d-Vcross
Long Accuracy
Average period
Absolute min/max period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
ppm
Tperiod
Tabs
tr
tf
d-tr
d-tf
Variation of crossing over all
edges
see Tperiod min-max values
96.00MHz
96.00MHz
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V, VOL = 0.175V
TYP
MAX
UNITS Notes
Ω
1
850
150
1150
-300
749
1.5
778
-51
250
358
550
mV
1
26
140
mV
1
10.4167
10.4100
210
180
23
50
100
10.4177
10.6677
700
700
125
125
ppm
ns
ns
ps
ps
ps
ps
1,2
2
1,2
1
1
1
1
-100
10.4156
10.1656
175
175
mV
mV
1,3
1,3
1
1
Measurement from differential
45
49
55
%
wavefrom
Measurement from differential
tjcyc-cyc
98
250
ps
Jitter, Cycle to cycle
wavefrom
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Duty Cycle
dt3
1
1
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
SYMBO
PARAMETER
CONDITIONS
MIN
L
Long Accuracy
ppm
see Tperiod min-max values
-300
14.318MHz output nominal
69.8270
Clock period
Tperiod
Output High Voltage
V OH
IOH = -1 mA
2.4
Output Low Voltage
V OL
IOL = 1 mA
-33
VOH @ MIN = 1.0 V
Output High Current (1X)
IOH
VOH@ MAX = 3.135 V
VOL @MIN = 1.95 V
30
Output Low Current (1X)
I OL
VOL @ MAX = 0.4 V
VOH @ MIN = 1.0 V
-33
Output High Current (2X)
IOH
VOH@ MAX = 3.135 V
VOL @MIN = 1.95 V
Output Low Current (2X)
I OL
VOL @ MAX = 0.4 V
VOL = 0.4 V, V OH = 2.4 V
1
Rise Time
tr1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
1
Duty Cycle
dt1
VT = 1.5 V
Jitter
tjcyc-cyc
VT = 1.5 V
45
1
TYP
69.841
3.25
0.05
-53
-6
60.9
23
-110
-12
110
47
1.7
1.9
MAX
300
69.8550
0.4
-33
38
-33
2
2
UNITS Notes
ppm
ns
V
V
mA
mA
mA
mA
mA
mA
mA
mA
ns
ns
1
1
1
1
1
1
1
1
1
1
1
1
1
1,2
54
55
%
1,2
197
1000
ps
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
2
0819G—12/06/04
10
ICS954201
Integrated
Circuit
Systems, Inc.
SMBus Table: Output Control Register
Byte 0
Pin #
Name
Control Function
Type
0
1
PWD
Output Enable
RW
DISABLE
ENABLE
1
Output
Output
Output
Output
Output
Output
Output
RW
RW
RW
RW
RW
RW
RW
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
1
1
1
1
1
1
1
Type
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
RW
RW
Disable
Disable
Spread Off
RW
SPREAD OFF
Enable
Enable
SPREAD
ON
PWD
1
1
1
1
1
1
1
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
RESERVED
RESERVED
RESERVED
Output Enable
Type
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
RW
Disable
Enable
Bit 7
-
CPUCLK2_ITP/SRCCLK7 Enable
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
SRCCLK6 Enable
SRCCLK5 Enable
SRCCLK4 Enable
SRCCLK3 Enable
SRCCLK2 Enable
SRCCLK1 Enable
SRCCLK0 Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
SMBus Table: Spreading and Device Behavior Control Register
Control Function
Pin #
Name
Byte 1
PCI_F0 Enable
Output Enable
Bit 7
DOT_96MHz Enable
Output Enable
Bit 6
USB_48MHz Enable
Output Enable
Bit 5
REFOUT Enable
Output Enable
Bit 4
RESERVED
Bit 3
CPUCLK1
Output Enable
Bit 2
CPUCLK0
Output Enable
Bit 1
Bit 0
Spread Spectrum Mode
SMBus Table: Output Control Register
Byte 2
Pin #
Name
PCICLK5
Bit 7
PCICLK4
Bit 6
PCICLK3
Bit 5
PCICLK2
Bit 4
Bit 3
Bit 2
Bit 1
PCI_F1 Enable
Bit 0
0819G—12/06/04
11
0
PWD
1
1
1
1
1
1
1
1
ICS954201
Integrated
Circuit
Systems, Inc.
SMBus Table: SRC Stop Control Register
Pin #
Name
Byte 3
36,35
SRCCLK7
Bit 7
33,32
SRCCLK6
Bit 6
31,30
SRCCLK5
Bit 5
26,27
SRCCLK4
Bit 4
24,25
SRCCLK3
Bit 3
22,23
SRCCLK2
Bit 2
19,20
SRCCLK1
Bit 1
17,18
SRCCLK0
Bit 0
SMBus Table: Stop and Output Control Register
Byte 4
Pin #
Name
Bit 7
14,15
DOT_96MHz
Bit 6
Bit 5
Bit 4
9
PCI_F1
Bit 3
8
PCI_F0
Bit 2
Bit 1
Bit 0
36,35
41,40
44,43
CPUCLK2_ITP
CPUCLK1
CPUCLK0
SMBus Table: Output Control Register
Byte 5
Pin #
Bit 7
SRCCLK(7:0)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
36,35
41,40
44,43
SRCCLK(7:0)
36,35
41,40
44,43
Name
SRC_STOP Drive Mode
Type
RW
RW
Allow assertion of
RW
PCI_STOP# or setting of
RW
PCI_STOP control bit in
RW
SMBus register to stop
RW
SRC clocks
RW
RW
0
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
1
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
PWD
0
0
0
0
0
0
0
0
Control Function
Type
RESERVED
Driven in PD
RW
RESERVED
Allow assertion of
PCI_STOP# or setting of RW
PCI_STOP control bit in
SMBus register to stop
RW
PCICLK_F outputs
0
1
Driven
Hi-Z
PWD
X
0
0
Free-Running
Stoppable
0
Free-Running
Stoppable
0
Free-Running
Free-Running
Free-Running
Stoppable
Stoppable
Stoppable
1
1
1
Control Function
Allow assertion of
CPU_STOP# to stop
CPUCLK outputs
RW
RW
RW
Control Function
Driven in
PCI/SRC_STOP#
Type
0
1
PWD
RW
Driven
Hi-Z
0
RW
RW
RW
RW
RW
RW
RW
Driven
Driven
Driven
Driven
Driven
Driven
Driven
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
0
0
0
0
0
CPUCLK2_ITP_STOP Drive Mode
Driven in CPU_STOP#
CPUCLK1_STOP Drive Mode
CPUCLK0_STOP Drive Mode
SRC_PD Drive Mode
Driven in Powerdown
CPUCLK2_ITP_PD Drive Mode
(PD)
CPUCLK1_PD Drive Mode
CPUCLK0_PDDrive Mode
0819G—12/06/04
12
ICS954201
Integrated
Circuit
Systems, Inc.
SMBus Table: Test and Readback Control Register
Name
Pin #
Byte 6
Test Mode Selection
Bit 7
Test Clock Mod eEntry
Bit 6
Bit 5
REFOUT STRENGTH
Bit 4
Bit 3
-
PCI/SRC_STOP
Bit 2
Bit 1
Bit 0
-
FS_C
FS_B
FS_A
Control Function
Test Mode Selection
Test Mode
RESERVED
Strength Prog
Stop all PCI and SRC
clocks
readback
readback
readback
Type
RW
RW
0
Hi-Z
Disable
1
REF/N
Enable
RW
1X
2X
PWD
0
0
0
1
RW
Enabled
Disabled
1
R
R
R
-
-
LATCHED
LATCHED
LATCHED
Control Function
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
0
0
0
1
0
0
0
1
SMBus Table: Vendor & Revision ID Register
Byte 7
Name
Pin #
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
REVISION ID
VENDOR ID
Test Clarification Table
HW
Comments
· FS_C/TEST_SEL is a 3-level latched input.
o Power-up w/ V >= 2.0V to select TEST
o Power-up w/ V < 2.0V to have pin function as
FS_C.
· When pin is FS_C, VIH_FS and VIL_FS levels
apply.
· FS_B/TEST_MODE is a low-threshold input
o VIH_FS and VIL_FS levels apply.
o TEST_MODE is a real time input
· TEST_SEL can be invoked after power up
through SMBus B6b6.
o If TEST is selected by B6b6, only B6b7 controls
TEST_MODE. The FS_B/TEST_Mode pin is not
used.
· Power must be cycled to exit TEST.
SW
TEST
FS_C/TEST FS_B/TEST ENTRY
BIT
_SEL
_MODE
B6b6
HW PIN HW PIN
0
X
0
1
0
X
REF/N or
HI-Z
B6b7
OUTPUT
X
NORMAL
0
HI-Z
1
0
X
1
REF/N
1
1
X
0
REF/N
1
1
X
1
REF/N
0
X
1
0
HI-Z
0
X
1
1
REF/N
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
0819G—12/06/04
13
ICS954201
Integrated
Circuit
Systems, Inc.
c
N
56-Lead, 300 mil Body, 25 mil, SSOP
L
E1
INDEX
AREA
E
1 2
α
h x 45°
D
A
A1
A
A1
b
c
D
E
E1
e
h
L
N
a
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
-C-
e
SYMBOL
SEATING
PLANE
b
.10 (.004) C
N
56
D mm.
MIN
18.31
D (inch)
MAX
18.55
MIN
.720
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS954201yFLNT
Example:
ICS XXXX y F LN T
Designation for tape and reel packaging
Annealed Lead Free
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0819G—12/06/04
14
MAX
.730
ICS954201
Integrated
Circuit
Systems, Inc.
c
N
L
E1
INDEX
AREA
E
1 2
a
D
A
A2
A1
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
a
0°
8°
0°
8°
aaa
-0.10
-.004
-Ce
b
SEATING
PLANE
VARIATIONS
N
aaa C
56
D mm.
MIN
MAX
13.90
14.10
D (inch)
MIN
.547
Reference Doc.: JEDEC Publicat ion 95, M O-153
10-0039
Ordering Information
ICS954201yGLNT
Example:
ICS XXXX y G LN T
Designation for tape and reel packaging
Annealed Lead Free
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0819G—12/06/04
15
MAX
.555
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