STMicroelectronics M28010-20KA6T 1 mbit 128k x 8 parallel eeprom with software data protection Datasheet

M28010
1 Mbit (128K x 8) Parallel EEPROM
With Software Data Protection
PRELIMINARY DATA
■
Fast Access Time: 100 ns
■
Single Supply Voltage:
– 4.5 V to 5.5 V for M28010
– 2.7 V to 3.6 V for M28010-W
– 1.8 V to 2.4 V for M28010-R
■
Low Power Consumption
■
Fast BYTE and PAGE WRITE (up to 128 Bytes)
■
Enhanced Write Detection and Monitoring:
32
1
PDIP32 (BA)
– Data Polling
– Toggle Bit
– Page Load Timer Status
■
JEDEC Approved Bytewide Pin-Out
■
Software Data Protection
■
Hardware Data Protection
■
Software Chip Erase
■
100000 Erase/Write Cycles (minimum)
■
Data Retention (minimum): 10 Years
DESCRIPTION
The M28010 devices consist of 128Kx8 bits of low
power, parallel EEPROM, fabricated with
STMicroelectronics’ proprietary double polysilicon
CMOS technology. The devices offer fast access
time, with low power dissipation, and require a
single voltage supply (5V, 3V or 2V, depending on
the option chosen).
TSOP32 (NA)
8 x 20 mm
PLCC32 (KA)
Figure 1. Logic Diagram
VCC
17
8
A0-A16
DQ0-DQ7
Table 1. Signal Names
A0-A16
Address Input
DQ0-DQ7
Data Input / Output
W
Write Enable
E
Chip Enable
G
Output Enable
VCC
Supply Voltage
VSS
Ground
W
M28010
E
G
VSS
AI02221
February 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/23
M28010
Figure 2C. TSOP Connections
Figure 2A. DIP Connections
DU
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
W
DU
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
M28010 25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
DU
W
VCC
DU
A16
A15
A12
A7
A6
A5
A4
1
8
9
16
AI02222
32
M28010
25
24
17
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
AI02224
Note: 1. DU = Do Not Use
Figure 2B. PLCC Connections
data retention. The organization of the data in a 4
byte (32-bit) “word” format leads to significant
savings in power consumption. Once a byte has
been read, subsequent byte read cycles from the
same “word” (with addresses differing only in the
two least significant bits) are fetched from the
previously loaded Read Buffer, not from the
memory array. As a result, the power consumption
for these subsequent read cycles is much lower
than the power consumption for the first cycle. By
careful design of the memory access patterns, a
50% reduction in the power consumption is
possible.
A12
A15
A16
DU
VCC
W
DU
Note: 1. DU = Do Not Use
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
M28010
9
25
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
17
AI02223
Note: 1. DU = Do Not Use
The device has been designed to offer a flexible
microcontroller interface, featuring both hardware
and software hand-shaking, with Data Polling and
Toggle Bit. The device supports a 128 byte Page
Write operation. Software Data Protection (SDP)
is also supported, using the standard JEDEC
algorithm.
The M28010 is designed for applications requiring
as much as 100,000 write cycles and ten years of
2/23
SIGNAL DESCRIPTION
The external connections to the device are
summarized in Table 1, and their use in Table 3.
Addresses (A0-A16). The address inputs are
used to select one byte from the memory array
during a read or write operation.
Data In/Out (DQ0-DQ7). The contents of the data
byte are written to, or read from, the memory array
through the Data I/O pins.
Chip Enable (E). The chip enable input must be
held low to enable read and write operations.
When Chip Enable is high, power consumption is
reduced.
Output Enable (G). The Output Enable input
controls the data output buffers, and is used to
initiate read operations.
M28010
Table 2. Absolute Maximum Ratings 1
Symbol
Parameter
Value
Unit
Ambient Operating Temperature
–40 to 85
°C
T STG
Storage Temperature
–65 to 150
°C
VCC
Supply Voltage
–0.3 to VCCMAX+1
V
VIO
Input or Output Voltage (except A9)
–0.3 to V CC+0.6
V
VI
Input Voltage
–0.3 to 4.5
V
2000
V
TA
Electrostatic Discharge Voltage (Human Body model) 2
VESD
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
A7-A16
(Page Address)
A0-A6
ADDRESS
LATCH
ADDRESS
LATCH
X DECODE
Figure 3. Block Diagram
1Mbit ARRAY
LATCH PAGE
REFERENCES
Y DECODE
E
G
CONTROL
LOGIC
VPP GEN
VREAD GEN
PROGRAMMING
STATE
MACHINE
SENSE PAGE & DATA LATCH
ECC (1) & MULTIPLEXER
W
I/O BUFFERS
DQ0-DQ7
AI02225
3/23
M28010
Table 3. Operating Modes 1
Mode
E
G
W
DQ0-DQ7
Read
VIL
V IL
VIH
Data Out
Write
VIL
VIH
VIL
Data In
Stand-by / Write Inhibit
V IH
X
X
Hi-Z
Write Inhibit
X
X
VIH
Data Out or Hi-Z
Write Inhibit
X
V IL
X
Data Out or Hi-Z
Output Disable
X
VIH
X
Hi-Z
Note: 1. X = VIH or VIL.
Write Enable (W). The Write Enable input controls
whether the addressed location is to be read, from
or written to.
DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal VCC comparator
inhibits the Write operations if the V CC voltage is
lower than VWI (see Table 4A to Table 4C). Once
the voltage applied on the VCC pin goes over the
VWI threshold (VCC>VWI), write access to the
memory is allowed after a time-out tPUW, as
specified in Table 4A to Table 4C.
Further protection against data corruption is
offered by the E and W low pass filters: any glitch,
on the E and W inputs, with a pulse width less than
10 ns (typical) is internally filtered out to prevent
inadvertent write operations to the memory.
Table 4A. Power-Up Timing1 for M28010 (5V range)
(TA = –40 to 85 °C; VCC = 4.5 to 5.5 V)
Symbol
Parameter
Min.
Max.
Unit
tPUR
Time Delay to Read Operation
5
ms
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
5
ms
VWI
Write Inhibit Threshold
3.0
4.2
V
Min.
Max.
Unit
Note: 1. Sampled only, not 100% tested.
Table 4B. Power-Up Timing1 for M28010-W (3V range)
(TA = –40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol
Parameter
tPUR
Time Delay to Read Operation
5
ms
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
5
ms
VWI
Write Inhibit Threshold
2.0
2.6
V
Min.
Max.
Unit
Note: 1. Sampled only, not 100% tested.
Table 4C. Power-Up Timing1 for M28010-R (2V range)
(TA = –40 to 85 °C; VCC = 1.8 to 2.4 V)
Symbol
Parameter
tPUR
Time Delay to Read Operation
5
ms
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
5
ms
VWI
Write Inhibit Threshold
Note: 1. Sampled only, not 100% tested.
4/23
1.2
1.7
V
M28010
Read
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/O pins.
Otherwise, when either G or E is high, the I/O pins
revert to their high impedance state.
Write
Write operations are initiated when both W and E
are low and G is high. The device supports both
W-controlled and E-controlled write cycles (as
shown in Figure 12 and Figure 13). The address is
latched during the falling edge of W or E (which
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first).
After a delay, tWLQ5H, that cannot be shorter than
the value specified in Table 9A to Table 9C, the
internal write cycle starts. It continues, under
internal timing control, until the write operation is
complete. The commencement of this period can
be detected by reading the Page Load Timer
Status on DQ5. The end of the internal write cycle
Figure 4. Software Data Protection Enable Algorithms (with or without Memory Write)
Page Write
Timing
SDP is Disabled and Application
needs to Enable it, and Write Data
SDP is Disabled and
Application needs to Enable it
Write AAh in
Address 5555h
Write AAh in
Address 5555h
Write 55h in
Address 2AAAh
Write 55h in
Address 2AAAh
Write A0h in
Address 5555h
Page Write
Timing
Write A0h in
Address 5555h
Write
is enabled
Time Out (tWLQ5H)
Write data
in any addresses
within one page
Wait for write completion (tQ5HQ5X)
SDP is set
Page Write
Timing
Time Out (tWLQ5H)
Write AAh in
Address 5555h
Wait for write completion (tQ5HQ5X)
Write 55h in
Address 2AAAh
DATA has been written
and SDP is Enabled
Write A0h in
Address 5555h
Write
is enabled
Write data
in any addresses
within one page
Time Out (tWLQ5H)
Wait for write completion (tQ5HQ5X)
DATA has been written
and SDP is Enabled
AI02227B
5/23
M28010
Figure 5. Software Data Protection Disable Algorithms (with or without Memory Write)
Page Write
Timing
SDP is Enabled and
Application needs to Disable it
SDP is Enabled and
Application needs to Write Data
Write AAh in
Address 5555h
Write AAh in
Address 5555h
Write 55h in
Address 2AAAh
Write 55h in
Address 2AAAh
Write 80h in
Address 5555h
Page Write
Timing
Write 80h in
Address 5555h
Write AAh in
Address 5555h
Write AAh in
Address 5555h
Write 55h in
Address 2AAAh
Write 55h in
Address 2AAAh
Write 20h in
Address 5555h
Write 20h in
Address 5555h
Time Out (tWLQ5H)
Physical
Write
Instructions
Write data
in any addresses
within one page
Wait for write completion (tQ5HQ5X)
SDP is Disabled
Time Out (tWLQ5H)
Wait for write completion (tQ5HQ5X)
DATA has been written
and SDP is Disabled
AI02226B
can be detected by reading the status of the Data
Polling and the Toggle Bit functions on DQ7 and
DQ6.
Page Write
The Page Write mode allows up to 128 bytes to be
written on a single page in a single go. This is
achieved through a series of successive Write
operations, no two of which are separated by more
than the tWLQ5H value (as specified in Table 9A to
Table 9C).
The page write can be initiated during any byte
write operation. Following the first Byte Write
instruction, the host may send another address
and data with a minimum data transfer rate of:
1/t WLQ5H.
The internal write cycle can start at any instant
after tWLQ5H. Once initiated, the write operation is
6/23
internally timed, and continues, uninterrupted,
until completion.
All bytes must be located on the same page
address (A16-A7 must be the same for all bytes).
Otherwise, the Page Write operation is not
executed. The Page Write Abort event is indicated
to the application via DQ1 (as described on page
8).
As with the single byte Write operation, described
above, the DQ5, DQ6 and DQ7 lines can be used
to detect the beginning and end of the internally
controlled phase of the Page Write cycle.
Software Data Protection (SDP)
The device offers a software-controlled writeprotection mechanism that allows the user to
inhibit all write operations to the device, including
chip erase. This can be useful for protecting the
M28010
Figure 6. Software Chip Erase Algorithm
Write AAh in
Address 5555h
Write 55h in
Address 2AAAh
Page Write
Timing
Figure 7. Status Bit Assignment
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DP
TB
PLTS
X
X
X
PWA
SDP
DP
TB
PLTS
X
PWA
SDP
Write 80h in
Address 5555h
= Data Polling
= Toggle Bit
= Page Load Timer Status
= undefined
= Page Write Abort
= Software Data Protection
AI02486B
Write AAh in
Address 5555h
Figure 8. Software Data Protection Status Read
Algorithm
Write 55h in
Address 2AAAh
Write 10h in
Address 5555h
Write AAh in
Address 5555h
Time Out (tWLQ5H)
Page Write
Timing
Write 55h in
Address 2AAAh
Wait for write completion (tQ5HQ5X)
Write 20h in
Address 5555h
Whole Array has been Set to FFh
AI02236C
memory from inadvertent write cycles that may
occur during periods of instability (uncontrolled
bus conditions when excessive noise is detected,
or when power supply levels are outside their
specified values).
By default, the device is shipped in the
“unprotected” state: the memory contents can be
freely changed by the user. Once the Software
Data Protection Mode is enabled, all write
commands are ignored, and have no effect on the
memory contents.
The device remains in this mode until a valid
Software Data Protection disable sequence is
received. The device reverts to its “unprotected”
state.
The status of the Software Data Protection
(enabled or disabled) is represented by a nonvolatile latch, and is remembered across periods
of the power being off.
The Software Data Protection Enable command
consists of the writing of three specific data bytes
to three specific memory locations (each location
being on a different page), as shown in Figure 4.
Read SDP
on DQ0
Write xxh in
Address xxxxh
Normal User Mode
AI02237B
Similarly, to disable the Software Data Protection,
the user has to write specific data bytes into six
different locations, as shown in Figure 5. This
complex series of operations protects against the
chance of inadvertent enabling or disabling of the
Software Data Protection mechanism.
When SDP is enabled, the memory array can still
have data written to it, but the sequence is more
complex (and hence better protected from
inadvertent use). The sequence is as shown in
Figure 5. This consists of an unlock key, to enable
the write action, at the end of which the SDP
continues to be enabled. This allows the SDP to
be enabled, and data to be written, within a single
Write cycle (tWC).
7/23
M28010
Software Chip Erase
The device can be erased (with all bytes set to
FFh) by using a six-byte software command code.
This operation can be initiated only if the user
loads, with a Page Write addressing mode, six
specific data bytes to six specific locations (as
shown in Figure 6). The complexity of the
sequence has been designed to guard against
inadvertent use of the command.
Status Bits
The devices provide five status bits (DQ7, DQ6,
DQ5, DQ1 and DQ0) for use during write
operations. These allow the application to use the
write time latency of the device for getting on with
other work. These signals are available on the I/O
port bits DQ7, DQ6, DQ5, DQ1 and DQ0 (but only
during the internal write cycle, tQ5HQ5X).
Data Polling bit (DQ7). The internally timed write
cycle starts as soon as tWLQ5H (defined in Table
9A to Table 9C) has elapsed since the previous
byte was latched in to the memory. The value of
the DQ7 bit of this last byte, is used as a signal
throughout this write operation: it is inverted while
the internal write operation is underway, and is
inverted back to its original value once the
operation is complete.
Toggle bit (DQ6). The device offers another way
for determining when the internal write cycle is
running. During the internal write cycle, DQ6
toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first read
value being ’0’) on subsequent attempts to read
any byte of the memory. When the internal write
cycle is complete, the toggling is stopped, and the
values read on DQ7-DQ0 are those of the
addressed memory byte. This indicates that the
device is again available for new Read and Write
operations.
Page Load Timer Status bit (DQ5). An internal
timer is used to measure the period between
successive Write operations, up to tWLQ5H
(defined in Table 9A to Table 9C). The DQ5 line is
held low to show when this timer is running (hence
showing that the device has received one write
operation, and is waiting for the next). The DQ5
line is held high when the counter has overflowed
(hence showing that the device is now starting the
internal write to the memory array).
Page Write Abort bit (DQ1). During a page write
operation, the A16 to A7 signals should be kept
constant. They should not change while
successive data bytes are being transferred to the
internal latches of the memory device. If a change
occurs on any of the pins, A16 to A7, during the
page write operation (that is, before the falling
edge of W or E, which ever occurs later), the
internal write cycle is not started, and the internal
circuitry is completely reset.
The abort signal can be observed on the DQ1 pin,
using a normal read operation. This can be
performed at any time during the byte load cycle,
tWLQ5H, or while the W input is being held high
between two load cycles. The default value of DQ1
is initially set to ’0’ and changes to ’1’ if the internal
circuitry has detected a change on any of the
address pins A16 to A7. This PWA bit can be
checked regardless of whether Software Data
Protection is enabled or disabled.
Table 5A. Read Mode DC Characteristics for M28010 (5V range)
(TA = –40 to 85 °C; VCC = 4.5 to 5.5 V)
Symbol
Parameter
Test Condition
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC 1
ICC1 1
Supply Current (CMOS inputs)
Supply Current (Stand-by) CMOS
Min.
Max.
Unit
0 V ≤ V IN ≤ VCC
5
µA
0 V ≤ VOUT ≤ VCC
5
µA
E = VIL, G = VIL, f = 0.1 MHz
2
mA
E = VIL, G = VIL, f = 5 MHz
22
mA
E = VIL, G = VIL, f = 10 MHz
40
mA
E > VCC – 0.3 V
50
µA
V IL
Input Low Voltage
–0.3
0.8
V
V IH
Input High Voltage
2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
VOH
Output High Voltage
IOH = –400 µA
Note: 1. All inputs and outputs open circuit.
8/23
2.4
V
M28010
Table 5B. Read Mode DC Characteristics for M28010-W (3V range)
(TA = –40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol
Parameter
Test Condition
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC 1
ICC1 1
Supply Current (CMOS inputs)
Max.
Unit
0 V ≤ V IN ≤ VCC
5
µA
0 V ≤ VOUT ≤ VCC
5
µA
E = VIL, G = VIL, f = 0.1 MHz
2
mA
E = VIL, G = VIL, f = 5 MHz
15
mA
E = VIL, G = VIL , f = 10 MHz
26
mA
E > VCC – 0.3 V
30
µA
Supply Current (Stand-by) CMOS
Min.
V IL
Input Low Voltage
–0.3
0.6
V
V IH
Input High Voltage
2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 1.6 mA
0.45
V
VOH
Output High Voltage
IOH = –100 µA
2.4
V
Note: 1. All inputs and outputs open circuit.
Table 5C. Read Mode DC Characteristics for M28010-R (2V range)
(TA = –40 to 85 °C; VCC = 1.8 to 2.4 V)
Symbol
Parameter
Test Conditio n
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC 1
Supply Current (CMOS inputs)
ICC1 1
Supply Current (Stand-by) CMOS
Min.
Max.
Unit
0 V ≤ VIN ≤ V CC
5
µA
0 V ≤ VOUT ≤ VCC
5
µA
E = V IL, G = VIL, f = 0.1 MHz, VCC = 2.4 V
2
mA
E = VIL, G = VIL, f = 5 MHz, VCC = 2.4 V
12
mA
E > VCC – 0.3 V
30
µA
V IL
Input Low Voltage
–0.3
0.2
V
V IH
Input High Voltage
VCC–0.3
VCC+0.3
V
VOL
Output Low Voltage
IOL = 0.4 mA
0.15
V
VOH
Output High Voltage
I OH = –100 µA
VCC–0.15
V
Note: 1. All inputs and outputs open circuit.
Software Data Protection bit (DQ0). Reading the
SDP bit (DQ0) allows the user to determine
whether the Software Data Protection mode has
been enabled (SDP=1) or disabled (SDP=0). The
SDP bit (DQ0) can be read by using a dedicated
algorithm (as shown in Figure 8), or can be
combined with the reading of the DP bit (DQ7), TB
bit (DQ6) and PLTS bit (DQ5).
9/23
M28010
Table 6. Input and Output Parameters1 (TA = 25 °C, f = 1 MHz)
Symbol
Parameter
Test Condition
Input Capacitance
C IN
C OUT
Output Capacitance
Min.
Max.
Unit
V IN = 0 V
6
pF
VOUT = 0 V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 7. AC Measurement Conditions
Figure 10. AC Testing Equivalent Load Circuit
≤ 5 ns
Input Rise and Fall Times
0 V to VCC
Input Pulse Voltages
Input and Output Timing Ref. Voltages
VCC/2
IOL
Figure 9. AC Testing Input Output Waveforms
DEVICE
UNDER
TEST
OUT
IOH
VCC
CL = 30pF
VCC/2
0V
AI02228
CL includes JIG capacitance
AI02578
Table 8A. Read Mode AC Characteristics for M28010 (5V range)
(TA = –40 to 85 °C; VCC = 4.5 to 5.5 V)
Symbol
Alt.
Parameter
Test
Condi t
ion
M28010
–10
Min
–12
Max
Min
Unit
Max
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
100
120
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
100
120
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
40
45
ns
tEHQZ1
tDF
Chip Enable High to Output Hi-Z
G = VIL
0
40
0
45
ns
tGHQZ1
tDF
Output Enable High to Output Hi-Z
E = VIL
0
40
0
45
ns
tAXQX
tOH
Address Transition to Output
Transition
E = VIL,
G = VIL
0
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
10/23
0
ns
M28010
Table 8B. Read Mode AC Characteristics for M28010-W (3V range)
(TA = –40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol
Alt.
Parameter
Test
Condi t
ion
M28010-W
–10
Min
–12
Max
Min
–15
Max
Min
Unit
Max
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
100
120
150
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
100
120
150
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
70
80
100
ns
tEHQZ1
tDF
Chip Enable High to Output Hi-Z
G = VIL
0
50
0
60
0
70
ns
tGHQZ1
tDF
Output Enable High to Output Hi-Z
E = VIL
0
50
0
60
0
70
ns
tAXQX
tOH
Address Transition to Output
Transition
E = VIL,
G = VIL
0
0
0
ns
–25
Unit
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Table 8C. Read Mode AC Characteristics for M28010-R (2V range)
(TA = –40 to 85 °C; VCC = 1.8 to 2.4 V)
Symbol
Alt.
Parameter
Test
Condi t
ion
M28010-R
–20
Min
Max
Min
Max
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
200
250
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
200
250
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
80
90
ns
tEHQZ1
tDF
Chip Enable High to Output Hi-Z
G = VIL
0
50
0
60
ns
tGHQZ1
tDF
Output Enable High to Output Hi-Z
E = VIL
0
50
0
60
ns
tAXQX
tOH
Address Transition to Output
Transition
E = VIL,
G = VIL
0
0
ns
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
11/23
M28010
Figure 11. Read Mode AC Waveforms (with Write Enable, W, high)
A0-A16
VALID
tAVQV
tAXQX
E
tGLQV
tEHQZ
G
tELQV
DQ0-DQ7
tGHQZ
Hi-Z
DATA OUT
AI02229
Note: 1. Write Enable (W) = VIH
Table 9A. Write Mode AC Characteristics for M28010 (5V range)
(TA = –40 to 85 °C; VCC = 4.5 to 5.5 V)
M28010
Symbol
Alt.
Parameter
Test Condit ion
Unit
Min
Max
tAVWL
tAS
Address Valid to Write Enable Low
E = VIL, G = VIH
0
ns
tAVEL
tAS
Address Valid to Chip Enable Low
G = VIH, W= VIL
0
ns
tELWL
tCES
Chip Enable Low to Write Enable Low
G = VIH
0
ns
tGHWL
tOES
Output Enable High to Write Enable Low
E = VIL
0
ns
tGHEL
tOES
Output Enable High to Chip Enable Low
W = VIL
0
ns
tWLEL
tWES
Write Enable Low to Chip Enable Low
G = VIH
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
70
ns
tELAX
tAH
Chip Enable Low to Address Transition
70
ns
tELEH
tWP
Chip Enable Low to Chip Enable High
100
ns
tWHEH
tCEH
Write Enable High to Chip Enable High
0
ns
tWHGL
tOEH
Write Enable High to Output Enable Low
0
ns
tEHWH
tWEH
Chip Enable High to Write Enable High
0
ns
tWHDX
tDH
Write Enable High to Input Transition
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
50
ns
tWLWH
tWP
Write Enable Low to Write Enable High
100
ns
tWLQ5H
tBLC
Time-out after the last byte write
150
µs
tQ5HQ5X
tWC
tDVWH
tDS
Data Valid before Write Enable High
50
ns
tDVEH
tDS
Data Valid before Chip Enable High
50
ns
12/23
Byte Write Cycle time
5
ms
Page Write Cycle time (up to 128 bytes)
10
ms
M28010
Table 9B. Write Mode AC Characteristics for M28010-W (3V range)
(TA = –40 to 85 °C; VCC = 2.7 to 3.6 V)
M28010-W
Symbol
Alt.
Parameter
Test Condit ion
Unit
Min
Max
tAVWL
tAS
Address Valid to Write Enable Low
E = VIL, G = VIH
0
ns
tAVEL
tAS
Address Valid to Chip Enable Low
G = VIH, W= VIL
0
ns
tELWL
tCES
Chip Enable Low to Write Enable Low
G = VIH
0
ns
tGHWL
tOES
Output Enable High to Write Enable Low
E = VIL
0
ns
tGHEL
tOES
Output Enable High to Chip Enable Low
W = VIL
0
ns
tWLEL
tWES
Write Enable Low to Chip Enable Low
G = VIH
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
70
ns
tELAX
tAH
Chip Enable Low to Address Transition
70
ns
tELEH
tWP
Chip Enable Low to Chip Enable High
100
ns
tWHEH
tCEH
Write Enable High to Chip Enable High
0
ns
tWHGL
tOEH
Write Enable High to Output Enable Low
0
ns
tEHWH
tWEH
Chip Enable High to Write Enable High
0
ns
tWHDX
tDH
Write Enable High to Input Transition
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
50
ns
tWLWH
tWP
Write Enable Low to Write Enable High
100
ns
tWLQ5H
tBLC
Time-out after the last byte write
150
µs
tQ5HQ5X
tWC
tDVWH
tDS
Data Valid before Write Enable High
80
ns
tDVEH
tDS
Data Valid before Chip Enable High
80
ns
Byte Write Cycle time
5
ms
Page Write Cycle time (up to 128 bytes)
10
ms
13/23
M28010
Table 9C. Write Mode AC Characteristics for M28010-R (2V range)
(TA = –40 to 85 °C; VCC = 1.8 to 2.4 V)
M28010-R
Symbol
Alt.
Parameter
Test Condit ion
Unit
Min
Max
tAVWL
tAS
Address Valid to Write Enable Low
E = VIL, G = VIH
0
ns
tAVEL
tAS
Address Valid to Chip Enable Low
G = VIH, W= VIL
0
ns
tELWL
tCES
Chip Enable Low to Write Enable Low
G = VIH
0
ns
tGHWL
tOES
Output Enable High to Write Enable Low
E = VIL
0
ns
tGHEL
tOES
Output Enable High to Chip Enable Low
W = VIL
0
ns
tWLEL
tWES
Write Enable Low to Chip Enable Low
G = VIH
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
120
ns
tELAX
tAH
Chip Enable Low to Address Transition
120
ns
tELEH
tWP
Chip Enable Low to Chip Enable High
120
ns
tWHEH
tCEH
Write Enable High to Chip Enable High
0
ns
tWHGL
tOEH
Write Enable High to Output Enable Low
0
ns
tEHWH
tWEH
Chip Enable High to Write Enable High
0
ns
tWHDX
tDH
Write Enable High to Input Transition
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
100
ns
tWLWH
tWP
Write Enable Low to Write Enable High
120
ns
tWLQ5H
tBLC
Time-out after the last byte write
150
µs
tWHRH
tWC
tDVWH
tDS
Data Valid before Write Enable High
120
ns
tDVEH
tDS
Data Valid before Chip Enable High
120
ns
14/23
Byte Write Cycle time
5
ms
Page Write Cycle time (up to 128 bytes)
10
ms
M28010
Figure 12. Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A16
VALID
tAVWL
tWLAX
E
tELWL
tWHEH
G
tGHWL
tWLWH
tWHGL
W
tWHWL
DATA IN
DQ0-DQ7
tDVWH
tWHDX
AI02230
Figure 13. Write Mode AC Waveforms (Chip Enable, E, controlled)
A0-A16
VALID
tAVEL
tELAX
E
tGHEL
tELEH
G
tWLEL
tEHGL
W
tEHWH
DQ0-DQ7
DATA IN
tDVEH
tEHDX
AI02231
15/23
M28010
Figure 14. Page Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A16
Addr 0
Addr 1
Addr 2
Addr n
E
G
tWHWL
W
tWLWH
Byte 0
DQ0-DQ7 (in)
Byte 1
Byte 2
Byte n
DQ5 (out)
tWLQ5H
tQ5HQ5X
AI02829B
Figure 15. Software Protected Write Cycle Waveforms
A0-A6
Byte Add 0
5555h
2AAAh
Byte Add n
5555h
A7-A16
Page Add
1
E
G
tWHWL
W
tWLWH
DQ0-DQ7
tDVWH
AAh
55h
tWHDX
A0h
Byte 0
Byte n
AI02233B
Note: 1. A16 to A7 must specify the same page address during each high-to-low transition of W (or E). G must be high only when W and E
are both low.
16/23
M28010
Figure 16. Data Polling Sequence Waveforms
A0-A16
Address of the last byte of the Page Write instruction
E
G
tWHGL
W
DQ7
DQ7
DQ7
LAST BYTE
LOADED
DQ7
DQ7
INTERNAL WRITE SEQUENCE
OR
TIME BETWEEN TWO CONSECUTIVE
BYTES LOADING
DQ7
READY
AFTER INTERNAL
WRITE SEQUENCE
AI02234
Figure 17. Toggle Bit Sequence Waveforms
A0-A16
Address of the last byte of the Page Write instruction
E
G
W
DQ6
(1)
LAST BYTE
LOADED
TOGGLE
INTERNAL WRITE SEQUENCE
OR
TIME BETWEEN TWO CONSECUTIVE
BYTES LOADING
READY
AFTER INTERNAL
WRITE SEQUENCE
AI02235
Note: 1. The Toggle Bit is first set to ‘0’.
17/23
M28010
Table 10. Ordering Information Scheme
Example:
M28010
–10
W
KA
6
T
Option
T
Tape & Reel Packing
Speed
-10
100 ns
Temperature Range
-12
120 ns
11
0 to 70 °C
-15
150 ns
6
–40 to 85 °C
-20
200 ns
-25
250 ns
Operating Voltage
Package
blank 4.5 V to 5.5 V
BA
PDIP32
W
2.7 V to 3.6 V
KA
PLCC32
R
1.8 V to 2.4 V
NA
TSOP32: 8 x 20mm
Note: 1. This temperature range on request only.
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 10. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact the ST
Sales Office nearest to you.
18/23
M28010
Table 11. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data
mm
Symbol
Min.
Max.
Min.
Max.
A
–
5.08
–
0.200
A1
0.38
–
0.015
–
A2
3.56
4.06
0.140
0.160
B
0.38
0.51
0.015
0.020
–
–
–
–
C
0.20
0.30
0.008
0.012
D
41.78
42.04
1.645
1.655
B1
Typ.
inches
1.52
Typ.
0.060
D2
38.10
–
–
1.500
–
–
E
15.24
–
–
0.600
–
–
13.59
13.84
0.535
0.545
E1
e1
2.54
–
–
0.100
–
–
eA
15.24
–
–
0.600
–
–
eB
15.24
17.78
0.600
0.700
L
3.18
3.43
0.125
0.135
S
1.78
2.03
0.070
0.080
α
0°
10°
0°
10°
N
32
32
Figure 18. PDIP32 (BA)
A2
A1
B1
B
A
L
e1
α
eA
D2
C
eB
D
S
N
E1
E
1
PDIP
Note: 1. Drawing is not to scale.
19/23
M28010
Table 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Symbol
Typ.
inches
Min.
Max.
A
2.54
A1
Typ.
Min.
Max.
3.56
0.100
0.140
1.52
2.41
0.060
0.095
A2
–
0.38
–
0.015
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
12.32
12.57
0.485
0.495
D1
11.35
11.56
0.447
0.455
D2
9.91
10.92
0.390
0.430
E
14.86
15.11
0.585
0.595
E1
13.89
14.10
0.547
0.555
E2
12.45
13.46
0.490
0.530
–
–
–
–
0.00
0.25
0.000
0.010
–
–
–
–
e
1.27
F
R
0.89
0.050
0.035
N
32
32
Nd
7
7
Ne
9
9
CP
0.10
0.004
Figure 19. PLCC32 (KA)
D
D1
A1
A2
1 N
B1
E1 E
Ne
e
D2/E2
F
B
0.51 (.020)
1.14 (.045)
A
Nd
R
PLCC
Note: 1. Drawing is not to scale.
20/23
CP
M28010
Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data
mm
inches
Symbol
Typ.
Min.
Max.
A
Typ.
Min.
1.20
Max.
0.047
A1
0.05
0.17
0.002
0.006
A2
0.95
1.05
0.037
0.041
B
0.15
0.27
0.006
0.011
C
0.10
0.21
0.004
0.008
D
19.80
20.20
0.780
0.795
D1
18.30
18.50
0.720
0.728
E
7.90
8.10
0.311
0.319
–
–
–
–
L
0.50
0.70
0.020
0.028
α
0°
5°
0°
5°
N
32
e
0.50
0.020
32
CP
0.10
0.004
Figure 20. TSOP32 (NS)
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
A1
α
L
Note: 1. Drawing is not to scale.
21/23
M28010
Table 14. Revision History
Date
Description of Revision
15-Feb-2000
ICC1(max), in Read Mode DC Char table for 5V, changed from 30 µA to 50 µA.
28-Feb-2000
tDVWH(min) and tDVEH(min), in Write Mode AC Char table for 3V, changed from 50 ns to 80 ns
22/23
M28010
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics.
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23/23
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