IDT IDT7134LA55FB High-speed 4k x 8 dual-port static ram Datasheet

IDT7134SA/LA
HIGH-SPEED
4K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
FEATURES:
• High-speed access
— Military: 25/35/45/55/70ns (max.)
— Commercial: 20/25/35/45/55/70ns (max.)
• Low-power operation
— IDT7134SA
Active: 500mW (typ.)
Standby: 5mW (typ.)
— IDT7134LA
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• Battery backup operation—2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available in several popular hermetic and plastic packages
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (–40°C to +85°C) is available,
tested to military electrical specifications
DESCRIPTION:
The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM
designed to be used in systems where on-chip hardware port
arbitration is not needed. This part lends itself to those
systems which cannot tolerate wait states or are designed to
be able to externally arbitrate or withstand contention when
both sides simultaneously access the same Dual-Port RAM
location.
The IDT7134 provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. It is the user’s responsibility to ensure data integrity
when simultaneously accessing the same memory location
from both ports. An automatic power down feature, controlled
by CE, permits the on-chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT’s CMOS high-performance
technology, these Dual-Port typically on only 500mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each port typically consuming 200µW
from a 2V battery.
The IDT7134 is packaged on either a sidebraze or plastic
48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin Ceramic
Flatpack. Military grade product is manufactured in compliance
with the latest revision of MIL-STD-883, Class B, making it
ideally suited to military temperature applications demanding
the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
R/ WL
R/ WR
OE L
OE R
CER
CE L
COLUMN
I/O
I/O0L- I/O 7L
A0L - A11L
LEFT SIDE
ADDRESS
DECODE
LOGIC
COLUMN
I/O
MEMORY
ARRAY
I/O0R - I/O 7R
RIGHT SIDE
ADDRESS
DECODE
LOGIC
A0R- A 11R
2720 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.04
OCTOBER 1996
DSC-2720/4
1
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7 6 5
1
A10R
WR
N/C
A11R
R/
VCC
CER
W
2
52 51 50 49 48 47
8
46
OER
A2L
A3L
9
10
45
44
A4L
11
12
43
42
A0R
A1R
A2R
A3R
39
38
A5R
A6R
A7R
37
36
A8R
A9R
19
35
34
20
21 22 23 24 25 26 27 28 29 30 31 32 33
N/C
15
16
TOP VIEW (3)
17
18
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
6 5 4 3 2
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
GND
I/O0R
I/O1R
I/O2R
I/O7L
I/O3L
I/O4L
I/O0L
I/O1L
I/O2L
I/O6L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
(2)
48 47 46 45 44 43
1
7
42
8
41
9
40
10
39
IDT7134
11
38
L48-1
&
12
37
F48-1
LCC/Flatpack
13
36
14
35
TOP VIEW (3)
15
34
16
33
17
32
18
31
19 20 21 22 23 24 25 26 27 28 29 30
I/O5L
A1L
A2L
2720 drw 04
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of actual part-marking.
I/O7R
2720 drw 03
OER
A10R
WR
A11R
CER
R/
VCC
W
CEL
OEL
A10L
A11L
R/ L
A0L
2720 drw 02
INDEX
A4R
I/O6R
I/O1L
I/O2L
I/O3L
41
40
I/O4R
I/O5R
A9L
I/O0L
IDT7134
J52-1
PLCC
13
14
I/O3R
A5L
A6L
A7L
A8L
I/O2R
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
4 3
A1L
I/O0R
I/O1R
OER
CEL
INDEX
W
R/ R
A11R
A10R
N/C
R/ L
OEL
CER
N/C
GND
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O 2L
I/O 3L
I/O 4L
I/O 5L
I/O 6L
I/O 7L
GND
VCC
I/O6L
I/O7L
OEL
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9 IDT7134 40
10 P48–1 39
&
11
38
12 C48–2 37
DIP
13
36
14
35
TOP
15 VIEW (3) 34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
A0L
W
I/O4L
I/O5L
CEL
R/ L
A11L
A10L
A10L
A11L
PIN CONFIGURATIONS(1,2)
Rating
Com’l.
Mil.
Unit
Terminal Voltage
with Respect
to Ground
–0.5 to +7.0
–0.5 to +7.0
V
TA
Operating
Temperature
0 to +70
–55 to +125
°C
TBIAS
Temperature
Under Bias
–55 to +125
–65 to +135
°C
TSTG
Storage
Temperature
–55 to +125
–65 to +150
°C
PT(3)
Power Dissipation
1.5
1.5
W
IOUT
DC Output Current
50
50
mA
2720 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25%of the cycle time or
10 ns maximum, and is limited to < 20mA for the period of VTERM > Vcc
+0.5V.
CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dv
11
pF
VOUT = 3dv
11
pF
2720 tbl 02
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dv references the interpolated capacitance when the input and output
signals switch from 0V to 3V and from 3V to 0V.
6.04
2
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Ambient
Temperature
GND
VCC
–55°C to +125°C
0V
5.0V ± 10%
0°C to +70°C
0V
5.0V ± 10%
Parameter
2720 tbl 03
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
Supply Voltage
VCC
GND
Ground
0
0
0
V
VIH
Input High Voltage
2.2
—
6.0(2)
V
VIL
Input Low Voltage
–0.5(1)
—
0.8
NOTES:
1. VIL (min.) > –1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
V
2720 tbl 04
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (VCC = 5V ± 10%)
IDT7134SA
Symbol
Parameter
Test Conditions
(1)
VCC = 5.5V, VIN = 0V to VCC
IDT7134LA
Min.
Max.
Min.
Max.
Unit
—
10
—
5
µA
|ILI|
Input Leakage Current
|ILO|
Output Leakage Current
CE = VIH, VOUT = 0V to VCC
—
10
—
5
µA
VOL
Output Low Voltage
IOL = 6mA
—
0.4
—
0.4
V
IOL = 8mA
—
0.5
—
0.5
V
VOH
Output High Voltage
IOH = –4mA
2.4
—
2.4
—
V
NOTE:
1. At Vcc ≤ 2.0V input leakages are undefined.
2720 tbl 05
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
7134X20(4)
Symbol
Parameter
ICC
Dynamic Operating
Current
ISB1
Test Conditions
CE = VIL
ISB4
MIL.
(2)
Max. Typ.
7134X35
(2)
7134X45
(2)
Max. Typ.
Max. Typ.
7134X55
(2)
Max. Typ.
7134X70
Max. Typ.(2) Max. Unit
—
—
160
160
310 150
260 150
300 140
250 140
280
240
140
140
270
220
140 270
140 220
170
170
280
240
160
160
280 150
220 150
260 140
210 140
240
200
140
140
240
200
140 240
140 200
S
L
—
—
—
—
25
25
100
80
25
25
75
55
25
25
70
50
25
25
70
50
25
25
70
50
COM’L. S
L
25
25
110
80
25
25
80
50
25
25
75
45
25
25
70
40
25
25
70
40
25
25
70
40
MIL.
—
—
—
—
95
95
210
170
85
85
200
160
75
75
190
150
75
75
180
150
75
75
180
150
105
105
180
150
95
95
180
140
85
85
170
130
75
75
160
130
75
75
160
130
75
75
160
130
S
L
—
—
—
—
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
CMOS Level Inputs) VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V, f = 0(3)
COM’L. S
L
1.0
0.2
15
4.5
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
Full Standby Current One Port CE"A" or
(One Port—All
CE"B" ≥ VCC - 0.2V
MIL.
—
—
—
—
95
95
210
150
85
85
190
130
75
75
180
120
75
75
170
120
75
75
170
120
105
105
170
130
95
95
170
120
85
85
160
110
75
75
150
100
75
75
150
100
75
75
150
100
(Both Ports Active)
f = fMAX(3)
Standby Current
(Both Ports—TTL
CEL and CER = VIH MIL.
f = fMAX(3)
Standby Current
(One Port—TTL
CE"A" = VIL and
CE"B" = VIH
S
L
7134X25
—
—
Level Inputs)
ISB3
Version Typ.
Outputs Open
Level Inputs)
ISB2
(2)
COM’L. S
L
S
L
Active Port Outputs COM’L. S
Open, f = fMAX(3)
L
Full Standby Current Both Ports CEL and MIL.
(Both Ports—All
CER ≥ VCC - 0.2V
S
L
CMOS Level Inputs) VIN ≥ VCC - 0.2V or COM’L. S
L
VIN ≤ 0.2V
Active Port Outputs
Open, f = fMAX(3)
mA
mA
mA
mA
mA
NOTES:
2720 tbl 06
1. “X” in part number indicates power rating (SA or LA).
2. VCC = 5V, TA = +25°C for typical, and parameters are not production tested.
3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level
standby ISB3.
4. (Commercial only) 0°C to +70°C temperature range.
6.04
3
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Symbol
Parameter
Test Condition
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR(3)
tR
(3)
VCC = 2V
Min.
Typ.(1)
Max.
Unit
2.0
—
—
V
µA
CE ≥ VHC
MIL.
—
100
4000
VIN ≥ VHC or < VLC
COM’L.
—
100
1500
0
—
—
ns
—
—
ns
Chip Deselect to Data Retention Time
Operation Recovery Time
tRC
(2)
NOTES:
1. VCC = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but not production tested.
2720 tbl 07
DATA RETENTION WAVEFORM
DATA RETENTION MODE
4.5V
VCC
VDR ≥ 2V
4.5V
tCDR
CE
tR
VDR
VIH
VIH
2720 drw 05
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1 and 2
2720 tbl 08
+5V
+5V
1250Ω
1250Ω
DATAOUT
775Ω
DATAOUT
30pF *
775Ω
2720 drw 06
5pF *
2720 drw 07
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig
Figure 1. AC Output Test Load
6.04
4
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4)
7134X20(3)
Symbol
Parameter
Min.
7134X25
Max.
Min.
7134X35
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
—
25
—
35
—
ns
tAA
Address Access Time
—
20
—
25
—
35
ns
tACE
Chip Enable Access Time
—
20
—
25
—
35
ns
tAOE
Output Enable Access Time
—
15
—
15
—
20
ns
tOH
Output Hold from Address Change
0
—
0
—
0
—
ns
0
—
0
—
0
—
ns
—
15
—
15
—
20
ns
0
—
0
—
0
—
ns
—
20
—
25
—
35
ns
tLZ
tHZ
tPU
tPD
(1, 2)
Output Low-Z Time
(1, 2)
Output High-Z Time
(2)
Chip Enable to Power Up Time
(2)
Chip Disable to Power Down Time
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4) (CONT'D)
7134X45
Symbol
Parameter
7134X55
7134X70
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
45
—
55
—
70
—
ns
tAA
Address Access Time
—
45
—
55
—
70
ns
tACE
Chip Enable Access Time
—
45
—
55
—
70
ns
tAOE
Output Enable Access Time
—
25
—
30
—
40
ns
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time
0
—
0
—
0
—
ns
(1, 2)
5
—
5
—
5
—
ns
(1, 2)
—
20
—
25
—
30
ns
0
—
0
—
0
—
ns
—
45
—
50
—
50
ns
tHZ
Output High-Z Time
tPU
Chip Enable to Power Up Time(2)
tPD
Chip Disable to Power Down Time
(2)
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. (Commercial only) 0°C to +70°C temperature range only.
4. “X” in part number indicates power rating (SA or LA).
2720 tbl 09
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1, 2, 3)
tRC
ADDRESS
tAA
tOH
DATAOUT
tOH
PREVIOUS DATA VALID
DATA VALID
2720 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH.
6.04
5
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(1, 3)
tACE
CE
tAOE(4)
tHZ(2)
OE
tLZ(1)
tHZ(2)
DATAOUT
VALID DATA (4)
tLZ(1)
tPU
ICC
CURRENT
tPD
50%
ISB
50%
2720 drw 09
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH.
4. Start of valid data depends on which timing becomes effective , tAOE, tACE or tAA
5. tAA for RAM Address Access and tSAA for Semaphore Address Access.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6)
Symbol
7134X20(5)
Min.
Max.
Parameter
7134X25
Min.
Max.
7134X35
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
20
—
25
—
35
—
ns
tEW
Chip Enable to End-of-Write
15
—
20
—
30
—
ns
tAW
Address Valid to End-of-Write
15
—
20
—
30
—
ns
tAS
Address Set-up Time
0
—
0
—
0
—
ns
tWP
Write Pulse Width
15
—
20
—
25
—
ns
tWR
Write RecoveryTime
0
—
0
—
0
—
ns
tDW
Data Valid to End-of-Write
15
—
15
—
20
—
ns
—
15
—
15
—
20
ns
tHZ
tDH
tWZ
tOW
tWDD
tDDD
(1, 2)
Output High-Z Time
Data Hold Time
(3)
0
—
0
—
3
—
ns
(1, 2)
—
15
—
15
—
20
ns
(1, 2, 3)
3
—
3
—
3
—
ns
—
40
—
50
—
60
ns
—
30
—
30
—
35
ns
Write Enabled to Output in High-Z
Output Active from End-of-Write
(4)
Write Pulse to Data Delay
(4, 7)
Write Data Valid to Read Data Delay
NOTES:
2720 tbl 10
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. (Commercial only), 0°C to +70°C temperature range .
6. “X” in part number indicates power rating (SA or LA).
7. tDDD = 35ns for military temperature range.
6.04
6
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6) (CONT'D)
Symbol
7134X45
Min.
Max.
Parameter
7134X55
Min.
Max.
7134X70
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
45
—
55
—
70
—
ns
tEW
Chip Enable to End-of-Write
40
—
50
—
60
—
ns
tAW
Address Valid to End-of-Write
40
—
50
—
60
—
ns
tAS
Address Set-up Time
0
—
0
—
0
—
ns
tWP
Write Pulse Width
40
—
50
—
60
—
ns
tWR
Write RecoveryTime
0
—
0
—
0
—
ns
tDW
Data Valid to End-of-Write
20
—
25
—
30
—
ns
—
20
—
25
—
30
ns
3
—
3
—
3
—
ns
tWZ
(1, 2)
Write Enabled to Output in High-Z
—
20
—
25
—
30
ns
tOW
Output Active from End-of-Write(1, 2, 3)
3
—
3
—
3
—
ns
—
70
—
80
—
90
ns
—
45
—
55
—
70
tHZ
Output High-Z Time
tDH
Data Hold Time(3)
(1, 2)
Write Pulse to Data Delay
tWDD
(4)
(4)
Write Data Valid to Read Data Delay
tDDD
ns
2720 tbl 10
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. (Commercial only), 0°C to +70°C temperature range .
6. “X” in part number indicates power rating (SA or LA).
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ (1)
tWC
ADDR "A"
MATCH
tWP
tAW
W "A"
R/
tDW
VALID
DATAIN "A"
ADDR "B"
MATCH
tWDD
DATAOUT "B"
VALID
tDDD
2720 drw 10
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CEL = CER = VIL. OE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.04
7
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1, 5, 8)
tWC
ADDRESS
OE
tAS(6)
tWR(3)
tAW
CE
tHZ(7)
tWP(2)
W
R/
DATAOUT
tHZ(7)
tWZ (7)
tLZ
tOW
(4)
(4)
tDW
tDH
DATAIN
2720 drw 11
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1, 5)
tWC
ADDRESS
tAW
CE
tAS(6)
tEW(2)
in
t1.20
WR(3)
W
R/
tDW
tDH
DATAIN
2720 drw 12
NOTES:
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going High to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal ( CE or R/W )is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the Output
Test Load (Figure 2).
8. If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to
be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified tWP.
6.04
8
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – READ/WRITE CONTROL(2)
FUNCTIONAL DESCRIPTION
The IDT7134 provides two ports with separate control,
address, and I/O pins that permit independent access for
reads or writes to any location in memory. These devices have
an automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the
respective port to go into standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output
Enable control (OE). In the read mode, the port’s OE turns on
the output drivers when set LOW. Non-contention READ/
WRITE conditions are illustrated in the table below.
Left or Right Port(1)
R/W
CE OE
D0-7
X
H
X
Z
X
H
X
Z
L
L
X
DATAIN
Function
Port Disabled and in Power
Down Mode, ISB2 or ISB4
CER = CEL = H, Power Down
Mode, ISB1 or ISB3
H
L
L
DATAOUT
X
X
H
Z
Data on port written into
memory
Data in memory output on port
High impedance outputs
2720 tbl 11
NOTES:
1. AOL - A11L ≠ AOR - A11R
2. "H" = HIGH, "L" = LOW, "X" = Don’t Care, and "Z" = High-impedance
ORDERING INFORMATION
IDT
XXXX
Device Type
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
P
C
J
L48
F
48-pin Plastic DIP (P48-1)
48-pin Ceramic DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
20
25
35
45
55
70
Commercial Only
LA
SA
Low Power
Standard Power
7134
32K (4K x 8-Bit) Dual-Port RAM
Speed in nanoseconds
2720 drw 13
6.04
9
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