ON MC74VHC1G135DFT1 2−input nand schmitt−trigger with open drain output Datasheet

MC74VHC1G135
2−Input NAND
Schmitt−Trigger with
Open Drain Output
Features
•
•
•
•
•
•
High Speed: tPD = 4.9 ns (Typ) at VCC = 5 V
Low Internal Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 70; Equivalent Gates = 18
Pb−Free Packages are Available
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MARKING
DIAGRAMS
5
5
1
SC−88A/SOT−353/SC−70
DF SUFFIX
CASE 419A
M
The MC74VHC1G135 is a single gate CMOS Schmitt NAND
trigger with an open drain output fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
The internal circuit is composed of three stages, including an open
drain output which provides the capability to set the output switching
level. This allows the MC74VHC1G135 to be used to interface 5 V
circuits to circuits of any voltage between VCC and 7 V using an
external resistor and power supply.
The MC74VHC1G135 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage.
The MC74VHC1G135 can be used to enhance noise immunity or to
square up slowly changing waveforms.
VZ M G
G
1
5
5
VZ M G
G
1
TSOP−5/SOT−23/SC−59
DT SUFFIX
CASE 483
1
VZ = Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
PIN ASSIGNMENT
IN B
1
5
1
VCC
OVT
IN A
GND
2
3
4
IN B
2
IN A
3
GND
4
OUT Y
5
VCC
OUT Y
FUNCTION TABLE
Inputs
Figure 1. Pinout (Top View)
IN A
IN B
&
Output
A
B
Y
L
L
H
H
L
H
L
H
Z
Z
Z
L
OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2007
February, 2007 − Rev. 15
1
Publication Order Number:
MC74VHC1G135/D
MC74VHC1G135
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Characteristics
−0.5 to +7.0
V
VIN
DC Input Voltage
−0.5 to +7.0
V
VOUT
DC Output Voltage
−0.5 to 7.0
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
+20
mA
IOUT
DC Output Current, per Pin
+25
mA
ICC
DC Supply Current, VCC and GND
+50
mA
PD
Power dissipation in still air
SC−88A, TSOP−5
200
mW
qJA
Thermal resistance
SC−88A, TSOP−5
333
°C/W
TL
Lead temperature, 1 mm from case for 10 secs
260
°C
TJ
Junction temperature under bias
+150
°C
°C
VOUT < GND; VOUT > VCC
Tstg
Storage temperature
−65 to +150
MSL
Moisture Sensitivity
Level 1
FR
Flammability Rating
VESD
Oxygen Index: 28 to 34
ESD Withstand Voltage
ILatchup
Latchup Performance
UL 94 V−0 @ 0.125 in
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
Above VCC and Below GND at 125°C (Note 4)
> 2000
> 200
N/A
V
±500
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
VCC
DC Supply Voltage
2.0
5.5
V
VIN
DC Input Voltage
0.0
5.5
V
DC Output Voltage
0.0
7.0
V
−55
+125
°C
0
0
100
20
ns/V
VOUT
TA
Operating Temperature Range
tr , tf
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
Input Rise and Fall Time
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80° C
117.8
TJ = 90° C
1,032,200
TJ = 100° C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110° C
Time, Years
TJ = 120° C
Time, Hours
TJ = 130° C
Junction
Temperature °C
NORMALIZED FAILURE RATE
Device Junction Temperature versus
Time to 0.1% Bond Failures
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1G135
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
TA ≤ 85°C
TA = 25°C
−55 ≤ TA ≤ 125°C
VCC
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
VT+
Positive Threshold
Voltage
3.0
4.5
5.5
1.50
2.35
2.80
1.88
2.66
3.21
2.25
3.10
3.70
1.50
2.35
2.80
2.25
3.10
3.70
1.50
2.35
2.80
2.25
3.10
3.70
V
VT−
Negative Threshold
Voltage
3.0
4.5
5.5
0.65
1.10
1.45
1.03
1.62
2.02
1.40
2.10
2.60
0.65
1.10
1.45
1.40
2.10
2.60
0.65
1.10
1.45
1.40
2.10
2.60
V
VH
Hysteresis Voltage
3.0
4.5
5.5
0.30
0.40
0.50
0.85
1.05
1.20
1.60
2.00
2.25
0.30
0.40
0.50
1.60
2.00
2.25
0.30
0.40
0.50
1.60
2.00
2.25
V
VOL
Maximum Low−Level
Output Voltage
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN = VIH or VIL
IOL = 50 mA
2.0
3.0
4.5
IOL = 4 mA
IOL = 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
1.0
20
40
mA
IOFF
Power Off−Output
Leakage Current
VOUT = 5.5 V
VIN = 5.5 V
0
0.25
2.5
5
mA
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AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr/tf = 3.0 ns
TA ≤ 85°C
TA = 25°C
Typ
Max
Min
Max
Min
Max
Unit
VCC = 3.3 ± 0.3 V CL = 15 pF
RL = RI = 500 W
CL = 50 pF
7.6
10.1
11.9
15.4
1.0
1.0
14.0
17.5
1.0
1.0
16.1
19.6
ns
VCC = 5.0 ± 0.5 V CL = 15 pF
RL = RI = 500 W
CL = 50 pF
4.9
6.4
7.7
9.7
1.0
1.0
9.0
11.0
1.0
1.0
10.3
12.3
VCC = 3.3 ± 0.3 V CL = 50 pF
RL = RI = 500 W
10.1
15.4
17.5
19.6
VCC = 5.0 ± 0.5 V CL = 50 pF
RL = RI = 500 W
6.4
9.7
11.0
12.3
5.0
10
10
10
Symbol
Parameter
Test Conditions
tPZL
Maximum Output
Enable Time, A or B to Y
tPLZ
Maximum Output
Disable Time
CIN
Maximum Input
Capacitance
CPD
Power Dissipation Capacitance (Note 5)
Min
−55 ≤ TA ≤ 125°C
ns
pF
Typical @ 25°C, VCC = 5.0 V
16
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
MC74VHC1G135
VCC
VCC − 7 V
VCC
A or B
A
50%
RL
OVT
GND
tPZL
B
tPLZ
HIGH
IMPEDANCE
50% VCC
Y
Figure 4. Output Voltage Mismatch Application
VOL +0.3 V
Figure 5. Switching Waveforms
VCC
VCC x 2
R1
PULSE
GENERATOR
DUT
RT
CL
RL
CL = 50 pF equivalent (Includes jig and probe capacitance)
RL = R1 = 500 W or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 6. Test Circuit
MC74VHC1G135
VCC
A
2.2 kW
B
MC74VHC1G03
C
D
E = (A • B) + (C+D)
Figure 7. Complex Boolean Functions
VCC
B
1
A
2
3
VCC
MC74VHC1G135
1.5 V
3.3 V
5
R LED
A
4
220 W
GTL
B
Figure 8. LED Driver
Figure 9. GTL Driver
ORDERING INFORMATION
Device
Package
MC74VHC1G135DFT1
SC70−5 / SC−88A / SOT−353
M74VHC1G135DFT1G
SC70−5 / SC−88A / SOT−353
(Pb−Free)
MC74VHC1G135DFT2
SC70−5 / SC−88A / SOT−353
M74VHC1G135DFT2G
SC70−5 / SC−88A / SOT−353
(Pb−Free)
MC74VHC1G135DTT1
SOT23−5 / TSSOP−5 / SC59−5
M74VHC1G135DTT1G
SOT23−5 / TSSOP−5 / SC59−5
(Pb−Free)
Shipping †
3000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1G135
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
M
B
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
−−−
0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
−−−
0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
MC74VHC1G135
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE F
NOTE 5
2X
0.10 T
2X
0.20 T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
D 5X
0.20 C A B
5
1
4
2
3
M
B
S
K
L
DETAIL Z
G
A
DIM
A
B
C
D
G
H
J
K
L
M
S
DETAIL Z
J
C
0.05
SEATING
PLANE
H
T
MILLIMETERS
MIN
MAX
3.00 BSC
1.50 BSC
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
1.25
1.55
0_
10 _
2.50
3.00
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC1G135/D
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