ISSI IS62LV12816L-70BI 128k x 16 cmos static ram Datasheet

ISSI®
ISSI
IS62LV12816L
IS62LV12816L
®
ADVANCE INFORMATION
AUGUST 1998
128K x 16 CMOS STATIC RAM
1
FEATURES
DESCRIPTION
• High-speed access time: 70, 100, and 120 ns
• CMOS low power operation
– 120 mW (typical) operating
– 6 µW (typical) CMOS standby
• TTL compatible interface levels
• Single 3V ± 10% VCC power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA
The ISSI IS62LV12816L is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated
using ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
2
3
4
5
The IS62LV12816L is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA.
6
FUNCTIONAL BLOCK DIAGRAM
7
A0-A16
DECODER
128K x 16
MEMORY ARRAY
8
VCC
9
GND
I/O0-I/O7
Lower Byte
I/O
DATA
CIRCUIT
I/O8-I/O15
Upper Byte
10
COLUMN I/O
11
CE
OE
WE
CONTROL
CIRCUIT
12
UB
LB
The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
1
ISSI
IS62LV12816L
®
PIN CONFIGURATIONS
48-Pin mini BGA
44-Pin TSOP (Type II)
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
N/C
B
I/O8
UB
A3
A4
CE
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
GND
I/O11
NC
A7
I/O3
Vcc
E
Vcc
I/O12
NC
A16
I/O4
GND
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE
I/O7
H
NC
A8
A9
A10
A11
NC
PIN DESCRIPTIONS
A0-A16
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
LB
UB
Chip Enable Input
NC
No Connection
Output Enable Input
Vcc
Power
Write Enable Input
GND
Ground
CE
OE
WE
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
2
WE
CE
OE
LB
UB
X
H
X
H
H
H
L
L
L
H
L
L
L
L
L
L
L
L
X
H
X
L
L
L
X
X
X
X
X
H
L
H
L
L
H
L
X
X
H
H
L
L
H
L
L
I/O PIN
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
Vcc Current
ISB1, ISB2
ICC
ICC
ICC
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
ISSI
IS62LV12816L
®
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.0V ± 10%
3.0V ± 10%
1
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
VCC
TSTG
PT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Vcc Related to GND
Storage Temperature
Power Dissipation
Value
–0.5 to Vcc+0.5
–40 to +85
–0.3 to +4.0
–65 to +150
1.0
2
Unit
V
°C
V
°C
W
3
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
4
5
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –1 mA
2.0
—
V
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
—
0.4
V
VIH
Input HIGH Voltage
2.2
VCC + 0.2
V
VIL(1)
Input LOW Voltage
–0.2
0.4
V
ILI
Input Leakage
GND ≤ VIN ≤ VCC
–1
1
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
–1
1
µA
6
7
8
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
9
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-70
Min. Max.
-100
Min. Max.
-120
Min. Max.
Symbol Parameter
Test Conditions
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
40
60
—
—
30
50
—
—
20
40
mA
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH , f = 0
Com.
Ind.
—
—
0.4
1.0
—
—
0.4
1.0
—
—
0.4
1.0
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
Com.
Ind.
—
—
15
25
—
—
15
25
—
—
15
25
µA
CE ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
10
Unit
11
12
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
3
ISSI
IS62LV12816L
®
CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0.4V to 2.2V
5 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
3070 Ω
3070 Ω
2.8V
2.8V
OUTPUT
OUTPUT
100 pF
Including
jig and
scope
Figure 1
4
3150 Ω
3150 Ω
5 pF
Including
jig and
scope
Figure 2
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
ISSI
IS62LV12816L
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
Min.
-70
Max.
-100
Min. Max.
-120
Min. Max.
Unit
tRC
Read Cycle Time
70
—
100
—
120
—
ns
tAA
Address Access Time
—
70
—
100
—
120
ns
tOHA
Output Hold Time
10
—
15
—
15
—
ns
tACE
CE Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
—
70
—
100
—
120
ns
—
35
—
50
—
60
ns
—
25
—
30
0
40
ns
5
—
5
—
5
—
ns
0
25
0
30
0
40
ns
10
—
10
—
10
—
ns
—
35
—
50
—
60
ns
0
25
0
35
0
50
ns
0
—
0
—
0
—
ns
tDOE
tHZOE(2)
tLZOE
(2)
tHZCE
(2)
tLZCE(2)
tBA
tHZB
tLZB
1
2
3
4
5
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels
of 0.4 to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
6
7
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
8
tRC
ADDRESS
tAA
tOHA
DOUT
PREVIOUS DATA VALID
9
tOHA
DATA VALID
10
11
12
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
5
ISSI
IS62LV12816L
®
AC WAVEFORMS
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tHZOE
tDOE
tLZOE
CE
tACE
tHZCE
tLZCE
LB, UB
tBA
DOUT
HIGH-Z
tHZB
tLZB
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
Parameter
Min.
-70
Max.
-100
Min. Max.
-120
Min. Max.
Unit
tWC
Write Cycle Time
70
—
100
—
120
—
ns
tSCE
CE to Write End
65
—
80
—
100
—
ns
tAW
Address Setup Time to Write End
65
—
80
—
100
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
ns
tPWB
60
—
80
—
100
—
ns
tPWE
LB, UB Valid to End of Write
WE Pulse Width
60
—
80
—
100
—
ns
tSD
Data Setup to Write End
30
—
40
—
50
—
ns
tHD
Data Hold from Write End
0
—
0
—
0
—
ns
tHZWE(3)
WE LOW to High-Z Output
WE HIGH to Low-Z Output
—
30
—
40
—
50
ns
5
—
5
—
5
—
ns
tLZWE(3)
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to
2.2V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
6
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
ISSI
IS62LV12816L
®
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (WE Controlled)
1
tWC
ADDRESS
2
tHA
tSCE
CE
tPWB
3
LB, UB
tAW
tPWE
4
WE
tSA
WRITE(1)
5
tSD
tHD
DIN
tHZWE
DOUT
HIGH-Z
6
tLZWE
UNDEFINED
HIGH-Z
UNDEFINED
7
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE
inputs and at least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
8
9
10
11
12
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
7
ISSI
IS62LV12816L
®
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Max.
Unit
VDR
Vcc for Data Retention
See Data Retention Waveform
1.5
3.3
V
IDR
Data Retention Current
Vcc = 2.0V, CE ≥ Vcc – 0.2V
—
15
µA
tSDR
Data Retention Setup Time
See Data Retention Waveform
0
—
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
—
ns
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VCC
2.3V
2.0V
VDR
CE ≥ VCC – 0.2V
CE
GND
8
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
ISSI
IS62LV12816L
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part No.
Package
70
70
IS62LV12816L-70T
IS62LV12816L-70B
TSOP (Type II)
Mini BGA
100
100
IS62LV12816L-100T
IS62LV12816L-100B
TSOP (Type II)
Mini BGA
120
120
IS62LV12816L-120T
IS62LV12816L-120B
TSOP (Type II)
Mini BGA
1
2
3
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
70
70
IS62LV12816L-70TI
IS62LV12816L-70BI
TSOP (Type II)
Mini BGA
100
100
IS62LV12816L-100TI TSOP (Type II)
IS62LV12816L-100BI Mini BGA
120
120
IS62LV12816L-120TI TSOP (Type II)
IS62LV12816L-120BI Mini BGA
4
5
6
7
8
9
10
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Fax: (408) 588-0806
Toll Free: 1-800-379-4774
email: [email protected]
http://www.issi.com
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
9
11
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