AD ADT7475ARQZ-REEL7 Dbcool remote thermal monitor and fan controller Datasheet

dBCool® Remote Thermal
Monitor and Fan Controller
ADT7475
FEATURES
GENERAL DESCRIPTION
Controls and monitors up to 4 fans
High and low frequency fan drive signal
1 on-chip and 2 remote temperature sensors
Extended temperature measurement range, up to 191°C
Automatic fan speed control mode controls system cooling
based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel® Pentium® 4 processor
Thermal control circuit via THERM input
3-wire and 4-wire fan speed measurement
Limit comparison of all monitored values
Meets SMBus 2.0 electrical specifications
(fully SMBus 1.1 compliant)
Fully RoHS compliant
The ADT7475 dBCool controller is a thermal monitor and
multiple PWM fan controller for noise-sensitive or powersensitive applications requiring active system cooling. The
ADT7475 can drive a fan using either a low or high frequency
drive signal, monitor the temperature of up to two remote
sensor diodes plus its own internal temperature, and measure
and control the speed of up to four fans, so they operate at the
lowest possible speed for minimum acoustic noise.
The automatic fan speed control loop optimizes fan speed
for a given temperature. The effectiveness of the system’s
thermal solution can be monitored using the THERM input.
The ADT7475 also provides critical thermal protection to the
system using the bidirectional THERM pin as an output to
prevent system or component overheating.
FUNCTIONAL BLOCK DIAGRAM
SCL SDA SMBALERT
ADT7475
PWM1
PWM2
PWM3
PWM
REGISTERS
AND
CONTROLLERS
(HF AND LF)
SERIAL BUS
INTERFACE
ACOUSTIC
ENHANCEMENT
CONTROL
AUTOMATIC
FAN SPEED
CONTROL
ADDRESS
POINTER
REGISTER
PWM
CONFIGURATION
REGISTERS
FAN
SPEED
COUNTER
INTERRUPT
MASKING
PERFORMANCE
MONITORING
VCC
INTERRUPT
STATUS
REGISTERS
THERMAL
PROTECTION
THERM
VCC TO ADT7475
D1+
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
D1–
D2+
D2–
VCCP
10-BIT
ADC
BAND GAP
REFERENCE
BAND GAP
TEMPERATURE
SENSOR
LIMIT
COMPARATORS
VALUE AND
LIMIT
REGISTERS
05381-001
TACH1
TACH2
TACH3
TACH4
GND
Figure 1.
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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©2006 Analog Devices, Inc. All rights reserved.
ADT7475
TABLE OF CONTENTS
Features .............................................................................................. 1
Temperature Measurement Method ........................................ 15
General Description ......................................................................... 1
Factors Affecting Diode Accuracy........................................... 17
Functional Block Diagram .............................................................. 1
Additional ADC Functions for Temperature Measurement 18
Specifications..................................................................................... 3
Limits, Status Registers, and Interrupts....................................... 20
Timing Diagram ........................................................................... 4
Limit Values ................................................................................ 20
Absolute Maximum Ratings............................................................ 5
Interrupt Status Registers .......................................................... 21
Thermal Characteristics .............................................................. 5
THERM Timer ........................................................................... 23
ESD Caution.................................................................................. 5
Fan Drive Using PWM Control ............................................... 26
Pin Configuration and Function Descriptions............................. 6
Operating from 3.3 V Standby ................................................. 31
Typical Performance Characteristics ............................................. 7
Standby Mode ............................................................................. 31
Product Description......................................................................... 9
XNOR Tree Test Mode .............................................................. 31
Quick Comparison Between ADT7473 and ADT7475 .......... 9
Power-On Default ...................................................................... 32
Recommended Implementation................................................. 9
Programming the Automatic Fan Speed Control Loop ............ 33
Serial Bus Interface......................................................................... 10
Automatic Fan Control Overview............................................ 33
Write Operations ........................................................................ 11
Step 1: Hardware Configuration .............................................. 34
Read Operations ......................................................................... 12
Step 2: Configuring the Mux .................................................... 37
Alert Response Address............................................................. 12
Step 3: TMIN Settings for Thermal Calibration Channels ...... 39
SMBus Timeout .......................................................................... 12
Step 4: PWMMIN for Each PWM (Fan) Output ...................... 40
Virus Protection.......................................................................... 12
Step 5: PWMMAX for PWM (Fan) Outputs .............................. 40
Voltage Measurement Input...................................................... 12
Step 6: TRANGE for Temperature Channels ................................ 41
Analog-to-Digital Converter .................................................... 12
Step 7: TTHERM for Temperature Channels ............................... 44
Input Circuitry............................................................................ 13
Step 8: THYST for Temperature Channels .................................. 45
Voltage Measurement Registers................................................ 13
Register Tables ................................................................................ 48
VCCP Limit Registers ................................................................... 13
Outline Dimensions ....................................................................... 65
Extended Resolution Registers ................................................. 13
Ordering Guide .......................................................................... 65
Additional ADC Functions for Voltage Measurements ........ 13
REVISION HISTORY
2/06—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 3
Changes to Quick Comparison Between ADT7473 and
ADT7475 Section ............................................................................. 9
Changes to Analog-to-Digital Converter section ...................... 13
Changes to TACH Inputs Section ................................................ 27
Changes to Fan Speed Measurement Section ............................. 28
Inserted Figure 42........................................................................... 32
Changes to Power-On Default Section........................................ 32
Changes to Step 5: PMWMAX For PWM (Fan)
Outputs Section .............................................................................. 40
Changes to Table 14 ....................................................................... 48
Changes to Table 23 ....................................................................... 53
Changes to Table 43 ....................................................................... 60
7/05—Revision 0: Initial Version
Rev. A | Page 2 of 68
ADT7475
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.1
Table 1.
Parameter
POWER SUPPLY
Supply Voltage
Supply Current, ICC
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy
Min
Typ
Max
Unit
Test Conditions/Comments
3.0
3.3
1.5
3.6
3
V
mA
Interface inactive, ADC active
±0.5
1.5
±2.5
°C
°C
°C
°C
°C
°C
µA
µΑ
Resolution
Remote Diode Sensor Accuracy
0.25
±0.5
Resolution
Remote Sensor Source Current
0.25
180
11
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error (TUE)
Differential Nonlinearity (DNL)
Power Supply Sensitivity
Conversion Time (Voltage Input)
Conversion Time (Local Temperature)
Conversion Time (Remote Temperature)
Total Monitoring Cycle Time
Input Resistance
FAN RPM-TO-DIGITAL CONVERTER
Accuracy
±1.5
±1
70
±0.1
11
12
38
145
19
120
±6
±10
65,535
Full-Scale Count
Nominal Input RPM
OPEN-DRAIN DIGITAL OUTPUTS
(PWM1 TO PWM3, XTO)
Current Sink, IOL
Output Low Voltage, VOL
High Level Output Current, IOH
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Current, IOH
SMBus DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
1.5
±2.5
%
LSB
%/V
ms
ms
ms
ms
ms
kΩ
0°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +125°C
0°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +125°C
High Level
Low Level
8 bits
Averaging enabled
Averaging enabled
Averaging enabled
Averaging enabled
Averaging disabled
For VCCP channel
%
%
0°C ≤ TA ≤ 70°C
−40°C ≤ TA ≤ +120°C
RPM
RPM
RPM
RPM
Fan count = 0xBFFF
Fan count = 0x3FFF
Fan count = 0x0438
Fan count = 0x021C
0.1
8.0
0.4
20
mA
V
µA
IOUT = −8.0 mA
VOUT = VCC
0.1
0.4
1.0
V
µA
IOUT = −4.0 mA
VOUT = VCC
0.4
V
V
mV
109
329
5000
10,000
2.0
500
Rev. A | Page 3 of 68
ADT7475
Parameter
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH
Min
Typ
Max
Unit
Test Conditions/Comments
3.6
V
V
Maximum input voltage
2.0
Input Low Voltage, VIL
0.8
V
V
V p-p
−0.3
Hysteresis
0.5
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING2
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Detect Clock Low Timeout, tTIMEOUT
0.75 × VCC
0.4
±1
±1
5
Minimum input voltage
V
V
µA
µA
pF
VIN = VCC
VIN = 0
See Figure 2
10
400
50
4.7
4.7
4.0
kHz
ns
µs
µs
µs
ns
µs
ns
ms
50
1000
300
250
15
35
Can be optionally disabled
1
All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA = 25°C and represent most likely parametric norm. Logic inputs accept
input high voltages up to VMAX even when device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge, and VIH =
2.0 V for a rising edge.
2
SMBus timing specifications are guaranteed by design and are not production tested.
TIMING DIAGRAM
tLOW
tR
tF
tHD;STA
SCL
SDA
tHD;DAT
tHIGH
tBUF
P
tSU;STA
tSU;DAT
S
S
Figure 2. Serial Bus Timing Diagram
Rev. A | Page 4 of 68
tSU;STO
P
05381-002
tHD;STA
ADT7475
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Positive Supply Voltage (VCC)
Voltage on Any Input or Output Pin
Input Current at Any Pin
Package Input Current
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
Lead Temperature, Soldering
IR Reflow Peak Temperature
Lead Temperature (Soldering 10 sec)
ESD rating
Rating
3.6 V
−0.3 V to +3.6 V
±5 mA
±20 mA
150°C
−65°C to +150°C
260°C
300°C
1500 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
16-lead QSOP package:
θJA = 150°C/W
θJC = 39°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 68
ADT7475
SCL
1
16
SDA
GND
2
15
PWM1/XTO
VCC
3
ADT7475
14
4
TOP VIEW
(Not to Scale)
VCCP
TACH3
13
D1+
PWM2/SMBALERT
5
12
D1–
TACH1
6
11
D2+
TACH2
7
10
D2–
PWM3
8
9
TACH4/THERM/GPIO/SMBALERT
05381-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
SCL
GND
VCC
TACH3
PWM2/SMBALERT
6
7
8
TACH1
TACH2
PWM3
9
TACH4/THERM/
GPIO/SMBALERT
10
11
12
13
14
15
D2−
D2+
D1−
D1+
VCCP
PWM1
16
XTO
SDA
Description
Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
Ground Pin.
Power Supply. VCC is also monitored through this pin.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
PWM2: Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated output to
control Fan 2 speed. Can be configured as a high or low frequency drive.
SMBALERT: Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output
to signal out-of-limit conditions.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.
Digital I/O (Open Drain). Pulse-width modulated output to control the speed of Fan 3 and Fan 4. Requires
10 kΩ typical pull-up. Can be configured as a high or low frequency drive.
TACH4: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
GPIO: General-Purpose Open Drain Digital I/O.
THERM: Digital I/O (Open Drain). Alternatively, this pin can be reconfigured as a bidirectional THERM pin
that can be used to time and monitor assertions on the THERM input. For example, the pin can be
connected to the PROCHOT output of an Intel Pentium 4 processor or to the output of a trip point
temperature sensor. This pin can be used as an output to signal overtemperature conditions.
SMBALERT: Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output
to signal out-of-limit conditions.
Cathode Connection to Second Thermal Diode.
Anode Connection to Second Thermal Diode.
Cathode Connection to First Thermal Diode.
Anode Connection to First Thermal Diode.
Analog Input. Monitors processor core voltage (0 V to 3 V).
Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ
typical pull-up.
Also functions as the output from the XNOR tree in XNOR test mode.
Digital I/O (Open Drain). SMBus bidirectional serial data. Requires 10 kΩ typical pull-up.
Rev. A | Page 6 of 68
ADT7475
TYPICAL PERFORMANCE CHARACTERISTICS
70
0
60
TEMPERATURE ERROR (°C)
–20
–30
–40
–50
0
2
4
6
8
10
14
12
16
18
20
40
30
100mV
20
60mV
40mV
10
0
05381-004
–60
50
–10
22
05381-007
TEMPERATURE ERROR (°C)
–10
0
100M
200M
300M
400M
500M
600M
NOISE FREQUENCY (Hz)
CAPACITANCE (nF)
Figure 4. Temperature Error vs. Capacitance between D+ and D−
Figure 7. Remote Temperature Error vs. Differential Mode Noise Frequency
1.20
30
1.18
1.16
1.14
10
1.12
D+ TO GND
0
IDD (mA)
D+ TO VCC
–10
1.10
1.08
1.06
–20
1.04
1.02
05381-005
–30
–40
0
20
40
80
60
05381-008
TEMPERATURE ERROR (°C)
20
1.00
0.98
3.0
100
3.1
3.2
LEAKAGE RESISTANCE (MΩ)
3.4
3.5
3.6
500M
600M
Figure 8. Normal IDD vs. Power Supply
Figure 5. Temperature Error vs. PCB Resistance
15
30
25
10
100mV
TEMPERATURE ERROR (°C)
20
15
60mV
10
5
5
100mV
0
250mV
–5
–10
05381-006
0
40mV
–5
0
100M
200M
300M
400M
500M
05381-009
TEMPERATURE ERROR (°C)
3.3
VDD (V)
–15
0
600M
100M
200M
300M
400M
FREQUENCY (Hz)
NOISE FREQUENCY (Hz)
Figure 6. Remote Temperature Error vs. Common-Mode Noise Frequency
Rev. A | Page 7 of 68
Figure 9. Internal Temperature Error vs. Power Supply Noise
ADT7475
6
3.0
2.5
250mV
2
TEMPERATURE ERROR (°C)
TEMPERATURE ERROR (°C)
4
0
–2
100mV
–4
–6
–8
2.0
1.5
1.0
0.5
0
–0.5
05381-010
–12
0
100M
200M
300M
400M
500M
–1.5
–2.0
600M
–40
FREQUENCY (Hz)
3.0
TEMPERATURE ERROR (°C)
2.5
2.0
1.5
1.0
0.5
0
–0.5
05381-011
–1.0
–1.5
–20
0
20
40
60
–20
0
20
40
60
85
105
125
OIL BATH TEMPERATURE (°C)
Figure 10. Remote Temperature Error vs. Power Supply Noise Frequency
–40
05381-012
–1.0
–10
85
105
125
OIL BATH TEMPERATURE (°C)
Figure 11. Internal Temperature Error vs. ADT7475 Temperature
Rev. A | Page 8 of 68
Figure 12. Remote Temperature Error vs. ADT7475 Temperature
ADT7475
PRODUCT DESCRIPTION
The ADT7475 is a complete thermal monitor and multiple fan
controller for any system requiring thermal monitoring and
cooling. The device communicates with the system via a serial
system management bus. The serial bus controller has a serial
data line for reading and writing addresses and data (Pin 16),
and an input line for the serial clock (Pin 1). All control and
programming functions for the ADT7475 are performed over
the serial bus. In addition, a pin can be reconfigured as an
SMBALERT output to signal out-of-limit conditions.
RECOMMENDED IMPLEMENTATION
QUICK COMPARISON BETWEEN ADT7473 AND
ADT7475
•
The ADT7473 supports Advanced Dynamic TMIN features
while the ADT7475 does not.
•
Acoustic smoothing is improved on the ADT7475.
•
THERM can be selected as an output only on the
ADT7475.
•
The ADT7475 has two additional configuration registers.
•
The ADT7475 has other minor register changes.
•
The ADT7475 is similar to the ADT7473 in that it is
powered by a supply no greater than 3.6 V. Exceeding this
specification results in irreversible damage to the
ADT7475. Signal pins (TACH/PWM) should be pulled up
or clamped to 3.6 V maximum. See the Specifications
section for more information.
Configuring the ADT7475 as shown in Figure 13 allows the
system designer to use the following features:
•
Two PWM outputs for fan control of up to three fans
(the front and rear chassis fans are connected in parallel).
•
Three TACH fan speed measurement inputs.
•
VCC measured internally through Pin 3.
•
CPU temperature measured using Remote 1 temperature
channel.
•
Ambient temperature measured through Remote 2
temperature channel.
•
Bidirectional THERM pin. This feature allows Intel
Pentium 4 PROCHOT monitoring and can function as
an overtemperature THERM output. The THERM pin
can alternatively be programmed as an SMBALERT system
interrupt output.
ADT7475
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
CPU FAN
PWM1
TACH2
TACH1
PWM3
D2+
TACH3
D2–
THERM
CPU
PROCHOT
D1+
SDA
D1–
SCL
SMBALERT
GND
Figure 13. ADT7475 Configuration
Rev. A | Page 9 of 68
ICH
05381-015
AMBIENT
TEMPERATURE
ADT7475
SERIAL BUS INTERFACE
In the ADT7475, write operations contain either one or two
bytes, and read operations contain one byte. To write data to
one of the device data registers or read data from it, the address
pointer register must be set so that the correct data register is
addressed, and then data can be written to that register or read
from it. The first byte of a write operation always contains an
address that is stored in the address pointer register. If data is
to be written to the device, the write operation contains a
second data byte that is written to the register selected by the
address pointer register.
On PCs and servers, control of the ADT7475 is carried out
using the SMBus. The ADT7475 is connected to this bus as
a slave device, under the control of a master controller, which
is usually (but not necessarily) the ICH.
The ADT7475 has a fixed 7-bit serial bus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address
(01011100 or 0x5C). Data is sent over the serial bus in sequences
of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low-to-high transition
when the clock is high might be interpreted as a stop signal. The
number of data bytes that can be transmitted over the serial bus
in a single read or write operation is limited only by what the
master and slave devices can handle.
This write operation is shown in Figure 14. The device address
is sent over the bus, and then R/W is set to 0. This is followed
by two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When reading data from a register, there are two possibilities:
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the tenth clock pulse to assert a stop condition.
In read mode, the master device overrides the acknowledge bit
by pulling the data line high during the low period before the
ninth clock pulse; this is known as No Acknowledge. The
master takes the data line low during the low period before
the tenth clock pulse, and then high during the tenth clock
pulse to assert a stop condition.
•
A read operation is then performed consisting of the serial
bus address; R/W bit set to 1, followed by the data byte
read from the data register (see Figure 16).
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined
at the beginning and cannot subsequently be changed without
starting a new operation.
1
If the ADT7475’s address pointer register value is unknown
or not the desired value, it must first be set to the correct
value before data can be read from the desired data register.
This is done by performing a write to the ADT7475 as
before, but only the data byte containing the register
address is sent, because no data is written to the register
(see Figure 15).
•
9
If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register (see Figure 16).
9
1
SCL
0
1
0
1
1
1
0
D7
R/W
START BY
MASTER
D6
ACK. BY
ADT7475
FRAME 1
SERIAL BUS ADDRESS BYTE
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7475
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
FRAME 3
DATA BYTE
D1
D0
ACK. BY
ADT7475
Figure 14. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
Rev. A | Page 10 of 68
STOP BY
MASTER
05381-016
SDA
ADT7475
1
9
9
1
SCL
0
1
START BY
MASTER
0
1
1
1
0
D7
R/W
D6
ACK. BY
ADT7475
FRAME 1
SERIAL BUS ADDRESS BYTE
D4
D5
D2
D3
D1
D0
ACK. BY
ADT7475
FRAME 2
ADDRESS POINTER REGISTER BYTE
STOP BY
MASTER
05381-017
SDA
Figure 15. Writing to the Address Pointer Register Only
1
9
9
1
SCL
0
1
START BY
MASTER
0
1
1
1
0
R/W
D7
D6
ACK. BY
ADT7475
FRAME 1
SERIAL BUS ADDRESS BYTE
D4
D5
D2
D3
D1
D0
NO ACK. BY STOP BY
MASTER
MASTER
FRAME 2
DATA BYTE FROM ADT745
05381-018
SDA
Figure 16. Reading Data from a Previously Selected Register
In addition to supporting the send byte and receive byte protocols, the ADT7475 also supports the read byte protocol.
(See System Management Bus Specifications Rev. 2.0 for more
information; this document is available from Intel.)
If several read or write operations must be performed in
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
4.
The master sends a command code.
5.
The slave asserts ACK on SDA.
6.
The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7475, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This operation is shown in Figure 17.
1
2
3
SLAVE
S
W A
ADDRESS
4
5 6
REGISTER
ADDRESS
A P
05381-019
It is possible to read a data byte from a data register without
first writing to the address pointer register, if the address
pointer register is already at the correct value. However, it is
not possible to write data to a register without writing to the
address pointer register, because the first data byte of a write
is always written to the address pointer register.
Figure 17. Setting a Register Address for a Subsequent Read
WRITE OPERATIONS
The SMBus specification defines several protocols for different types of read and write operations. The ones used in the
ADT7475 are discussed in this section. The following
abbreviations are used in the diagrams:
If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start
condition immediately after the final ACK and carry out a
single byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device as follows:
S—START
P—STOP
R—READ
W—WRITE
A—ACKNOWLEDGE
A—NO ACKNOWLEDGE
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
The ADT7475 uses the following SMBus write protocols.
4.
The master sends a command code.
Send Byte
5.
The slave asserts ACK on SDA.
In this operation, the master device sends a single command
byte to a slave device as follows:
6.
The master sends a data byte.
7.
The slave asserts ACK on SDA.
1.
The master device asserts a start condition on SDA.
8.
2.
The master sends the 7-bit slave address followed by
the write bit (low).
The master asserts a stop condition on SDA and the
transaction ends.
3.
The addressed slave device asserts ACK on SDA.
Rev. A | Page 11 of 68
ADT7475
1
2
3
SLAVE
S ADDRESS W A
4
5
6
7 8
REGISTER
ADDRESS
A
DATA
A P
05381-020
The byte write operation is shown in Figure 18.
4.
If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accordance with normal SMBus arbitration.
5.
Once the ADT7475 has responded to the alert response
address, the master must read the status registers, and the
SMBALERT is cleared only if the error condition has gone
away.
Figure 18. Single Byte Write to a Register
READ OPERATIONS
The ADT7475 uses the following SMBus read protocols.
SMBus TIMEOUT
Receive Byte
The ADT7475 includes an SMBus timeout feature. If there is
no SMBus activity for 35 ms, the ADT7475 assumes that the
bus is locked and releases the bus. This prevents the device
from locking or holding the SMBus expecting data. Some
SMBus controllers cannot handle the SMBus timeout feature,
so it can be disabled.
This operation is useful when repeatedly reading a single
register. The register address needs to have been set up
previously. In this operation, the master device receives a single
byte from a slave device as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
read bit (high).
3.
The addressed slave device asserts ACK on SDA.
4.
The master receives a data byte.
5.
The master asserts NO ACK on SDA.
6.
The master asserts a stop condition on SDA and the
transaction ends.
VIRUS PROTECTION
3
4
5 6
DATA
A P
To prevent rogue programs or viruses from accessing critical
ADT7475 register settings, the lock bit can be set. Setting Bit 1
of Configuration Register 1 (0x40) sets the lock bit and locks
critical registers. In this mode, certain registers can no longer be
written to until the ADT7475 is powered down and powered up
again. For more information on which registers are locked. See
the Register Tables section.
VOLTAGE MEASUREMENT INPUT
05381-021
2
SLAVE
S ADDRESS R A
Bit 6 TODIS = 0; SMBus timeout enabled (default).
Bit 6 TODIS = 1; SMBus timeout disabled.
In the ADT7475, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation. This operation
is shown in Figure 19.
1
Configuration Register 1 (0x40)
Figure 19. Single Byte Read from a Register
ALERT RESPONSE ADDRESS
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the master.
If a device’s SMBALERT line goes low, the following events
occur:
1.
SMBALERT is pulled low.
2.
The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This general call
address must not be used as a specific device address.
3.
The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
The ADT7475 has one external voltage measurement channel.
It can also measure its own supply voltage, VCC. Pin 14 can
measure VCCP. The VCC supply voltage measurement is carried
out through the VCC pin (Pin 3). The VCCP input can be used to
monitor a chipset supply voltage in computer systems.
ANALOG-TO-DIGITAL CONVERTER
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. This has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the
input has built-in attenuators to allow measurement of VCCP
without any external components. To allow for the tolerance of
the supply voltage, the ADC produces an output of 3/4 full scale
(decimal 768 or 300 hex) for the nominal input voltage and so
has adequate headroom to deal with overvoltages.
Rev. A | Page 12 of 68
ADT7475
INPUT CIRCUITRY
The internal structure for the VCCP analog input is shown in
Figure 20. The input circuit consists of an input protection
diode, an attenuator, and a capacitor to form a first-order, lowpass filter that gives the input immunity to high frequency
noise.
52.5kΩ
35pF
A number of other functions are available on the ADT7475 to
offer the system designer increased flexibility.
Turn-Off Averaging
For each voltage measurement read from a value register,
16 readings have been made internally, and the results averaged,
before being placed into the value register. For instances where
faster conversions are needed, setting Bit 4 of Configuration
Register 2 (0x73) turns averaging off. This effectively gives a
reading 16 times faster (711 µs), but the reading may be noisier.
17.5kΩ
05381-022
VCCP
ADDITIONAL ADC FUNCTIONS FOR VOLTAGE
MEASUREMENTS
Figure 20. Structure of Analog Inputs
VOLTAGE MEASUREMENT REGISTERS
Bypass Voltage Input Attenuator
Register 0x21, VCCP Reading = 0x00 default
Register 0x22, VCC Reading = 0x00 default
VCCP LIMIT REGISTERS
Associated with the VCCP measurement channel is a high and
low limit register. Exceeding the programmed high or low limit
causes the appropriate status bit to be set. Exceeding either limit
can also generate SMBALERT interrupts.
Register 0x46, VCCP Low Limit = 0x00 default
Register 0x47, VCCP High Limit = 0xFF default
Table 5 shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 711 µs and averages 16 conversions to reduce noise; a
measurement takes nominally 11.38 ms.
EXTENDED RESOLUTION REGISTERS
Voltage measurements can be made with higher accuracy using
the extended resolution registers (0x76 and 0x77). Whenever
the extended resolution registers are read, the corresponding
data in the voltage measurement registers is locked until their
data is read. That is, if extended resolution is required, then the
extended resolution register must be read first, immediately
followed by the appropriate voltage measurement register.
Setting Bit 5 of Configuration Register 2 (0x73) removes the
attenuation circuitry from the VCCP input. This allows the user
to directly connect external sensors, or to rescale the analog
voltage measurement inputs for other applications. The input
range of the ADC without the attenuators is 0 V to 2.25 V.
Single Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (0x73) places the
ADT7475 into single channel ADC conversion mode. In this
mode, the ADT7475 can be made to read a single voltage channel only. If the internal ADT7475 clock is used, the selected
input is read every 711 µs. The appropriate ADC channel is
selected by writing to Bits [7:5] of the TACH1 minimum high
byte register (0x55).
Table 4. Single Channel ADC Conversion
Register 0x55, Bits [7:5]
001
010
101
110
111
Channel Selected
VCCP
VCC
Remote 1 Temperature
Local Temperature
Remote 2 Temperature
Configuration Register 2 (0x73)
Bit 4 = 1; averaging off.
Bit 5 = 1; bypass input attenuators.
Bit 6 = 1; single channel convert mode.
TACH1 Minimum High Byte (0x55)
Bits [7:5] selects ADC channel for single channel convert mode.
Rev. A | Page 13 of 68
ADT7475
Table 5. 10-Bit A/D Output Code vs. VIN
VCC (3.3 VIN)1
<0.0042
0.0042 to 0.0085
0.0085 to 0.0128
0.0128 to 0.0171
0.0171 to 0.0214
0.0214 to 0.0257
0.0257 to 0.0300
0.0300 to 0.0343
0.0343 to 0.0386
VCCP
<0.00293
0.0293 to 0.0058
0.0058 to 0.0087
0.0087 to 0.0117
0.0117 to 0.0146
0.0146 to 0.0175
0.0175 to 0.0205
0.0205 to 0.0234
0.0234 to 0.0263
1.100 to 1.1042
0.7500 to 0.7529
2.200 to 2.2042
1.5000 to 1.5029
3.300 to 3.3042
2.2500 to 2.2529
4.3527 to 4.3570
4.3570 to 4.3613
4.3613 to 4.3656
4.3656 to 4.3699
4.3699 to 4.3742
4.3742 to 4.3785
4.3785 to 4.3828
4.3828 to 4.3871
4.3871 to 4.3914
4.3914 to 4.3957
>4.3957
2.9677 to 2.9707
2.9707 to 2.9736
2.9736 to 2.9765
2.9765 to 2.9794
2.9794 to 2.9824
2.9824 to 2.9853
2.9853 to 2.9882
2.9882 to 2.9912
2.9912 to 2.9941
2.9941 to 2.9970
>2.9970
1
A/D Output
Decimal
0
1
2
3
4
5
6
7
8
•
•
•
256 (1/4-scale)
•
•
•
512 (1/2-scale)
•
•
•
768 (3/4 scale)
•
•
•
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
The VCC output codes listed assume that VCC is 3.3 V, and VCC should never exceed 3.6 V.
Rev. A | Page 14 of 68
Binary (10 Bits)
00000000 00
00000000 01
00000000 10
00000000 11
00000001 00
00000001 01
00000001 10
00000001 11
00000010 00
01000000 00
10000000 00
11000000 00
11111101 01
11111101 10
11111101 11
11111110 00
11111110 01
11111110 10
11111110 11
11111111 00
11111111 01
11111111 10
11111111 11
ADT7475
TEMPERATURE MEASUREMENT METHOD
Remote Temperature Measurement
Local Temperature Measurement
The ADT7475 can measure the temperature of two remote diode
sensors or diode-connected transistors connected to Pin 10 and
Pin 11, or Pin 12 and Pin 13.
The ADT7475 contains an on-chip band gap temperature sensor
whose output is digitized by the on-chip, 10-bit ADC. The 8-bit
MSB temperature data is stored in the temperature registers
(0x25, 0x26, and 0x27). Because both positive and negative
temperatures can be measured, the temperature data is stored in
Offset 64 format or twos complement format, as shown in Table 6
and Table 7.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about –2 mV/°C. Unfortunately, the absolute value
of VBE varies from device to device and individual calibration is
required to null this out, so the technique is unsuitable for mass
production.
Theoretically, the temperature sensor and ADC can measure
temperatures from −63°C to +127°C (or −61°C to +191°C in
the extended temperature range) with a resolution of 0.25°C.
However, this exceeds the operating temperature range of
the device, so local temperature measurements outside the
ADT7475 operating temperature range are not possible.
VDD
CPU
I
D+
THERMDC
D–
IBIAS
VOUT+
TO ADC
BIAS
DIODE
LOW-PASS FILTER
fC = 65kHz
Figure 21. Signal Conditioning for Remote Diode Temperature Sensors
Rev. A | Page 15 of 68
VOUT–
05381-023
REMOTE
SENSING
TRANSISTOR
THERMDA
N×I
ADT7475
The technique used in the ADT7475 is to measure the change
in VBE when the device is operated at two different currents.
This is given by
ΔVBE = KT/q × 1n(N)
where:
A remote temperature measurement takes nominally 38 ms. The
results of remote temperature measurements are stored in 10-bit,
twos complement format, as shown in Table 6. The extra resolution for the temperature measurements is held in the Extended
Resolution Register 2 (0x77). This gives temperature readings
with a resolution of 0.25°C.
Noise Filtering
Figure 21 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows the
external sensor as a substrate transistor, provided for temperature
monitoring on some microprocessors. It could also be a discrete
transistor such as a 2N3904/2N3906.
If a discrete transistor is used, the collector is not grounded
and should be linked to the base. If a PNP transistor is used,
the base is connected to the D− input and the emitter to the
D+ input. If an NPN transistor is used, the emitter is connected
to the D− input and the base to the D+ input. Figure 22 and
Figure 23 show how to connect the ADT7475 to an NPN
or PNP transistor for temperature measurement. To prevent
ground noise from interfering with the measurement, the more
negative terminal of the sensor is not referenced to ground, but
is biased above ground by an internal diode at the D− input.
For temperature sensors operating in noisy environments,
previous practice was to place a capacitor across the D+ pin and
D− pin to help combat the effects of noise. However, large capacitances affect the accuracy of the temperature measurement,
leading to a recommended maximum capacitor value of 1000 pF.
This capacitor reduces the noise, but does not eliminate it.
Sometimes, this sensor noise is a problem in a very noisy
environment. In most cases, a capacitor is not required as
differential inputs, by their very nature, have a high immunity
to noise.
ADT7475
2N3904
NPN
D+
D–
05381-025
K is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvin.
N is the ratio of the two currents.
Figure 22. Measuring Temperature Using an NPN Transistor
ADT7475
2N3906
PNP
D–
05381-026
D+
To measure ΔVBE, the sensor is switched between operating
currents of I and N × I. The resulting waveform is passed
through a 65 kHz low-pass filter to remove noise, and to a
chopper-stabilized amplifier that performs the functions of
amplification and rectification of the waveform to produce
a dc voltage proportional to ΔVBE. This voltage is measured
by the ADC to give a temperature output in 10-bit, twos
complement format. To further reduce the effects of noise,
digital filtering is performed by averaging the results of
16 measurement cycles.
Figure 23. Measuring Temperature Using a PNP Transistor
Rev. A | Page 16 of 68
ADT7475
Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23
packages, are suitable devices to use.
FACTORS AFFECTING DIODE ACCURACY
Remote Sensing Diode
The ADT7475 is designed to work with either substrate
transistors built into processors or with discrete transistors.
Substrate transistors are generally PNP types with the collector
connected to the substrate. Discrete types can be either PNP
or NPN transistors connected as a diode (base-shorted to the
collector). If an NPN transistor is used, the collector and base
are connected to D+ and the emitter to D−. If a PNP transistor
is used, the collector and base are connected to D− and the
emitter is connected to D+.
To reduce the error due to variations in both substrate and
discrete transistors, a number of factors should be taken into
consideration:
•
The ideality factor, nf, of the transistor is a measure of the
deviation of the thermal diode from ideal behavior. The
ADT7475 is trimmed for an nf value of 1.008. Use the
following equation to calculate the error introduced at a
temperature, T (°C), when using a transistor whose nf
does not equal 1.008. See the processor data sheet for the
nf values.
∆T = (nf − 1.008) × (273.15 K + T)
To factor this in, the user can write the ∆T value to the
offset register. The ADT7475 automatically adds it to or
subtracts it from the temperature measurement.
•
Some CPU manufacturers specify the high and low current
levels of the substrate transistors. The high current level of
the ADT7475, IHIGH, is 180 µA and the low level current,
ILOW, is 11 µA. If the ADT7475 current levels do not match
the current levels specified by the CPU manufacturer, it
might be necessary to remove an offset. The CPU’s data
sheet advises whether this offset needs to be removed and
how to calculate it. This offset can be programmed to the
offset register. If more than one offset must be considered,
the algebraic sum of these offsets must be programmed to
the offset register.
If a discrete transistor is used with the ADT7475, the best
accuracy is obtained by choosing devices according to the
following criteria:
•
Base-emitter voltage greater than 0.25 V at 11 µA, at the
highest operating temperature.
•
Base-emitter voltage less than 0.95 V at 180 µA, at the
lowest operating temperature.
•
Base resistance less than 100 Ω.
•
Small variation in hFE (approximately 50 to 150) that
indicates tight control of VBE characteristics.
Table 6. Twos Complement Temperature Data Format
Temperature
–128°C
–50°C
–25°C
–10°C
0°C
10.25°C
25.5°C
50.75°C
75°C
100°C
125°C
127°C
1
Digital Output (10-Bit)1
1000 0000 00 (diode fault)
1100 1110 00
1110 0111 00
1111 0110 00
0000 0000 00
0000 1010 01
0001 1001 10
0011 0010 11
0100 1011 00
0110 0100 00
0111 1101 00
0111 1111 00
Bold numbers denote 2 LSB of measurement in Extended Resolution
Register 2 (0x77) with 0.25°C resolution.
Table 7. Extended Range, Temperature Data Format
Temperature
–64°C
–1°C
0°C
1°C
10°C
25°C
50°C
75°C
100°C
125°C
191°C
1
Digital Output (10-Bit)1
0000 0000 00 (diode fault)
0011 1111 00
0100 0000 00
0100 0001 00
0100 1010 00
0101 1001 00
0111 0010 00
1000 1001 00
1010 0100 00
1011 1101 00
1111 1111 00
Bold numbers denote 2 LSB of measurement in Extended Resolution
Register 2 (0x77) with 0.25°C resolution.
Nulling Out Temperature Errors
As CPUs run faster, it is more difficult to avoid high frequency
clocks when routing the D+/D– traces around a system board.
Even when recommended layout guidelines are followed, some
temperature errors may still be attributable to noise coupled
onto the D+/D– lines. Constant high frequency noise usually
attenuates, or increases, temperature measurements by a linear,
constant value.
The ADT7475 has two temperature offset registers, Register
0x70 and Register 0x72) for the Remote 1 and Remote 2
temperature channels. By doing a one-time calibration of
the system, the user can determine the offset caused by system
board noise and null it out using the offset registers. The offset
registers automatically add a twos complement 8-bit reading to
every temperature measurement.
Rev. A | Page 17 of 68
ADT7475
Changing Bit 1 of Configuration Register 5 (0x7C) changes the
resolution and therefore the range of the temperature offset as
either having a range of –63°C to +127°C, with a resolution of
1°C, or having a range of −63°C to +64°C, with a resolution of
0.5°C. This temperature offset can be used to compensate for
linear temperature errors introduced by noise.
Reading Temperature from the ADT7475
Temperature Offset Registers
If the 10-bit measurement is required, this involves a 2-register
read for each measurement. The Extended Resolution Register
2 (0x77) should be read first. This causes all temperature
reading registers to be frozen until all temperature reading
registers have been read from. This prevents an MSB reading
from being updated while its two LSBs are being read and
vice versa.
Register 0x70, Remote 1 Temperature Offset = 0x00 (0°C default)
Register 0x71, Local Temperature Offset = 0x00 (0°C default)
Register 0x72, Remote 2 Temperature Offset = 0x00 (0°C default)
ADT7463/ADT7475 Backwards Compatible Mode
By setting Bit 0 of Configuration Register 5 (0x7C), all temperature measurements are stored in the zone temperature value
registers (0x25, 0x26, and 0x27) in twos complement in the
range −63°C to +127°C. The temperature limits must be
reprogrammed in twos complement.
If a twos complement temperature below −63°C is entered, the
temperature is clamped to −63°C. In this mode, the diode fault
condition remains −128°C = 1000 0000, while in the extended
temperature range (−63°C to +191°C), the fault condition is
represented by −64°C = 0000 0000.
Temperature Measurement Registers
Register 0x25, Remote 1 Temperature
It is important to note that temperature can be read from the
ADT7475 as an 8-bit value (with 1°C resolution) or as a 10-bit
value (with 0.25°C resolution). If only 1°C resolution is required,
the temperature readings can be read back at any time and in no
particular order.
ADDITIONAL ADC FUNCTIONS FOR
TEMPERATURE MEASUREMENT
A number of other functions are available on the ADT7475 to
offer the system designer increased flexibility.
Turn-Off Averaging
For each temperature measurement read from a value register,
16 readings have actually been made internally, and the results
averaged, before being placed into the value register. Sometimes
it is necessary to take a very fast measurement. Setting Bit 4 of
Configuration Register 2 (0x73) turns averaging off. The default
round-robin cycle time takes 146.5 ms.
Table 8. Conversion Time with Averaging Disabled
Register 0x26, Local Temperature
Channel
Voltage Channels
Remote Temperature 1
Remote Temperature 2
Local Temperature
Register 0x27, Remote 2 Temperature
Register 0x77, Extended Resolution 2 = 0x00 default
Bits [7:6] TDM2, Remote 2 temperature LSBs.
Measurement Time (ms)
0.7
7
7
1.3
When Bit 7 of Configuration Register 6 (0x10) is set, the default
round-robin cycle time increases to 240 ms.
Bits [5:4] LTMP, local temperature LSBs.
Bits [3:2] TDM1, Remote 1 temperature LSBs.
Table 9. Conversion Time with Averaging Enabled
Temperature Measurement Limit Registers
Associated with each temperature measurement channel are high
and low limit registers. Exceeding the programmed high or low
limit causes the appropriate status bit to be set. Exceeding either
limit can also generate SMBALERT interrupts (depending on the
way the interrupt mask register is programmed and assuming
that SMBALERT is set as an output on the appropriate pin).
Channel
Voltage Channels
Remote Temperature 1
Remote Temperature 2
Local Temperature
Register 0x4E, Remote 1 Temperature Low Limit = 0x81 default
Register 0x4F, Remote 1 Temperature High Limit = 0x7F default
Register 0x50, Local Temperature Low Limit = 0x81 default
Register 0x51, Local Temperature High Limit = 0x7F default
Register 0x52, Remote 2 Temperature Low Limit = 0x81 default
Register 0x53, Remote 2 Temperature High Limit = 0x7F default
Rev. A | Page 18 of 68
Measurement Time (ms)
11
39
39
12
ADT7475
Single Channel ADC Conversions
Setting Bit 6 of Configuration Register 2 (0x73) places the
ADT7475 into single channel ADC conversion mode. In this
mode, the ADT7475 can be made to read a single temperature
channel only. The appropriate ADC channel is selected by
writing to Bits [7:5] of the TACH1 minimum high byte
register (0x55).
The fans run at this speed until the temperature drops below
THERM minus hysteresis. This can be disabled by setting the
boost bit in Configuration Register 3 (0x78), Bit 2. The
hysteresis value for the THERM temperature limit is the value
programmed into Register 0x6D and Register 0x6E (hysteresis
registers). The default hysteresis value is 4°C.
THERM LIMIT
Table 10. Programming Single Channel ADC Mode
for Temperatures
HYSTERESIS (°C)
Channel Selected
Remote 1 temperature
Local temperature
Remote 2 temperature
TEMPERATURE
100%
FANS
Configuration Register 2 (0x73)
05381-027
Register 0x55, Bits [7:5]
101
110
111
Figure 24. THERM Temperature Limit Operation
Bit 4 = 1, averaging off.
TACH1 Minimum High Byte Register ( 0x55)
THERM can be disabled on specific temperature channels using
Bits [7:5] of Configuration Register 5 (0x7C). THERM can also
be disabled by:
Bits [7:5] selects ADC channel for single channel convert mode.
• In Offset 64 mode, writing −64°C to the appropriate THERM
Bit 6 = 1, single channel convert mode.
temperature limit.
Overtemperature Events
Overtemperature events on any of the temperature channels can
be detected and dealt with automatically in automatic fan speed
control mode. Register 0x6A to Register 0x6C are the THERM
temperature limit registers. When a temperature exceeds its
THERM temperature limit, all PWM outputs run at the
maximum PWM duty cycle (Register 0x38, Register 0x39, and
Register 0x3A). This effectively runs the fans at the fastest
allowed speed.
• In twos complement mode, writing −128°C to the
appropriate THERM temperature limit.
Rev. A | Page 19 of 68
ADT7475
LIMITS, STATUS REGISTERS, AND INTERRUPTS
LIMIT VALUES
Register 0x56, TACH2 Minimum Low Byte = 0x00 default
Associated with each measurement channel on the ADT7475
are high and low limits. These can form the basis of system
status monitoring; a status bit can be set for any out-of-limit
condition and detected by polling the device. Alternatively,
SMBALERT interrupts can be generated to flag a processor
or microcontroller of out-of-limit conditions.
Register 0x57, TACH2 Minimum High Byte = 0x00 default
8-Bit Limits
Register 0x5B, TACH4 Minimum High Byte = 0x00 default
The following is a list of 8-bit limits on the ADT7475.
Register 0x58, TACH3 Minimum Low Byte = 0x00 default
Register 0x59, TACH3 Minimum High Byte = 0x00 default
Register 0x5A, TACH4 Minimum Low Byte = 0x00 default
Out-of-Limit Comparisons
Voltage Limit Registers
Once all limits have been programmed, the ADT7475 can
be enabled for monitoring. The ADT7475 measures all voltage
and temperature measurements in round-robin format and
sets the appropriate status bit for out-of-limit conditions.
TACH measurements are not part of this round-robin cycle.
Comparisons are done differently, depending on whether
the measured value is being compared to a high or low limit.
Register 0x46, VCCP Low Limit = 0x00 default
Register 0x47, VCCP High Limit = 0xFF default
Register 0x48, VCC Low Limit = 0x00 default
Register 0x49, VCC High Limit = 0xFF default
Temperature Limit Registers
High Limit > Comparison Performed
Register 0x4E, Remote 1 Temperature Low Limit = 0x01 default
Low Limit ≤ Comparison Performed
Register 0x4F, Remote 1 Temperature High Limit = 0x7F default
Register 0x50, Local Temperature Low Limit = 0x01 default
Voltage and temperature channels use a window comparator
for error detecting and, therefore, have high and low limits.
Fan speed measurements use only a low limit. This fan limit
is needed only in manual fan control mode.
Register 0x51, Local Temperature High Limit = 0x7F default
Analog Monitoring Cycle Time
Register 0x6A, Remote 1 THERM Limit = 0x64 default
Register 0x6B, Local THERM Limit = 0x64 default
Register 0x52, Remote 2 Temperature Low Limit = 0x01 default
Register 0x53, Remote 2 Temperature High Limit = 0x7F
default
Register 0x6C, Remote 2 THERM Limit = 0x64 default
THERM Limit Register
As the ADC is normally left to free-run in this manner, the time
taken to monitor all the analog inputs is normally not of interest, because the most recently measured value of any input can
be read out at any time.
Register 0x7A, THERM Timer Limit = 0x00 default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TACH
limits are also 16 bits, consisting of a high byte and low byte.
Because fans running under speed or stalled are normally the
only conditions of interest, only high limits exist for fan TACHs.
Because the fan TACH period is actually being measured,
exceeding the limit indicates a slow or stalled fan.
Fan Limit Registers
Register 0x54, TACH1 Minimum Low Byte = 0x00 default
Register 0x55, TACH1 Minimum High Byte = 0x00 default
The analog monitoring cycle begins when a 1 is written to
the start bit (Bit 0) of Configuration Register 1 (0x40).
By default, the ADT7475 powers up with this bit set. The ADC
measures each analog input in turn and, as each measurement
is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues
unless disabled by writing a 0 to Bit 0 of Configuration
Register 1.
For applications where the monitoring cycle time is important, it can easily be calculated. The total number of channels
measured is
•
One dedicated supply voltage input (VCCP)
•
Supply voltage (VCC pin)
•
Local temperature
•
Two remote temperatures
Rev. A | Page 20 of 68
ADT7475
As mentioned previously, the ADC performs round-robin
conversions. The total monitoring cycle time for averaged
voltage and temperature monitoring is 146 ms. The total
monitoring cycle time for voltage and temperature monitoring with averaging disabled is 19 ms. The ADT7475 is a
derivative of the ADT7467. As a result, the total conversion
time in the ADT7475 is the same as the total conversion time
of the ADT7467.
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
The state of the various measurement channels can be polled by
reading the status registers over the serial bus. In Bit 7 (OOL) of
Interrupt Status Register 1 (0x41), 1 means that an out-of-limit
event has been flagged in Interrupt Status Register 2. This means
that the user needs only to read Interrupt Status Register 2 when
this bit is set. Alternatively, Pin 5 or Pin 9 can be configured as an
SMBALERT output. This automatically notifies the system
supervisor of an out-of-limit condition. Reading the status
registers clears the appropriate status bit as long as the error
condition that caused the interrupt has cleared.
Status register bits are sticky. Whenever a status bit is set,
indicating an out-of-limit condition, it remains set even if the
event that caused it has gone away (until read). The only way to
clear the status bit is to read the status register after the event
has gone away. Interrupt status mask registers (0x74 and 0x75)
allow individual interrupt sources to be masked from causing
an SMBALERT. However, if one of these masked interrupt
sources goes out-of-limit, its associated status bit is set in the
interrupt status registers.
Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has
been exceeded.
Bit 6 (D1) = 1, indicates an open or short on D1+/D1– inputs.
Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum
speed. Alternatively, indicates the THERM limit has been
exceeded, if the THERM function is used.
Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below minimum
speed.
Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below minimum
speed.
Bit 1 (OVT) = 1, indicates a THERM overtemperature limit has
been exceeded.
SMBALERT Interrupt Behavior
The ADT7475 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. Note
how the SMBALERT output and status bits behave when
writing interrupt handler software.
HIGH LIMIT
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
STICKY
STATUS BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
05381-028
The results of limit comparisons are stored in Interrupt Status
Register 1 and Interrupt Status Register 2. The status register bit for
each channel reflects the status of the last measurement and limit
comparison on that channel. If a measurement is within limits, the
corresponding status register bit is cleared to 0. If the measurement
is out-of-limits, the corresponding status register bit is set to 1.
Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and
Interrupt Status Register 2 should be read.
Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.
Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum
speed.
INTERRUPT STATUS REGISTERS
Interrupt Status Register 1 (0x41)
Status Register 2 (0x42)
Figure 25. SMBALERT and Status Bit Behavior
Figure 25 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides and the status register is read. The status bits are referred
to as sticky, because they remain set until read by software. This
ensures an out-of-limit event cannot be missed, if software is
polling the device periodically. Note the SMBALERT output
remains low for the entire duration that a reading is out-of-limit
and until the interrupt status register has been read. This has
implications on how software handles the interrupt.
Bit 5 (LT) = 1, local temperature high or low limit has been
exceeded.
Bit 4 (R1T) = 1, Remote 1 temperature high or low limit has
been exceeded.
Bit 2 (VCC) = 1, VCC high or low limit has been exceeded.
Bit 1 (VCCP) = 1, VCCP high or low limit has been exceeded.
Rev. A | Page 21 of 68
ADT7475
Handling SMBALERT Interrupts
Interrupt Mask Register 2 (0x75)
To prevent the system from being tied up servicing interrupts, it
is recommended to handle the SMBALERT interrupt as follows:
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
1.
Detect the SMBALERT assertion.
2.
Enter the interrupt handler.
3.
Read the status registers to identify the interrupt source.
4.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (0x74 and 0x75).
5.
Take the appropriate action for a given interrupt source.
6.
Exit the interrupt handler.
7.
Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
behave as shown in Figure 26.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4 failure.
If the TACH4 pin is being used as the THERM input, this bit
masks SMBALERT for a THERM event.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
HIGH LIMIT
Bit 1 (OVT) = 1, masks SMBALERT for over temperature
(exceeding THERM limits).
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by default. Pin 5
or Pin 9 can be reconfigured as an SMBALERT output to signal
out-of-limit conditions.
Table 11. Configuring Pin 5 as SMBALERT Output
TEMPERATURE
Register
Configuration Register 3 (0x78)
CLEARED ON READ
(TEMP BELOW LIMIT)
STICKY
STATUS BIT
Assigning THERM Functionality to a Pin
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
(SMBALERT RE-ARMED)
05381-029
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
Bit Setting
[0] ALERT = 1
Figure 26. How Masking the Interrupt Source
Affects SMBALERT Output
Masking Interrupt Sources
Interrupt Mask Register 1 (0x74) and Interrupt Mask Register 2
(0x75) allow individual interrupt sources to be masked out to
prevent SMBALERT interrupts. Note that masking an interrupt
source prevents only the SMBALERT output from being
asserted; the appropriate status bit is set normally.
Pin 9 on the ADT7475 has four possible functions: SMBus
ALERT, THERM, GPIO, and TACH4. The user chooses the
required functionality by setting Bit 0 and Bit 1 of Configuration Register 4 (0x7D).
Table 12. Pin 9 Configuration
Bit 0
0
0
1
1
Bit 1
0
1
0
1
Function
TACH4
THERM
SMBus ALERT
GPIO
Once Pin 9 is configured as THERM, it must be enabled (Bit 1,
Configuration Register 3 (0x78)).
THERM as an Input
Interrupt Mask Register 1 (0x74)
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in Interrupt Status Register 2.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature.
When THERM is configured as an input, the user can time
assertions on the THERM pin. This can be useful for connecting to the PROCHOT output of a CPU to gauge system
performance.
Bit 5 (LT) = 1, masks SMBALERT for local temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature.
Bit 2 (VCC) = 1, masks SMBALERT for VCC channel.
Bit 0 (VCCP) = 1, masks SMBALERT for VCCP channel.
Rev. A | Page 22 of 68
ADT7475
The user can also set up the ADT7475 so when the THERM pin
is driven low externally, the fans run at 100%. The fans run at
100% for the duration of the time that the THERM pin is
pulled low. This is done by setting the BOOST bit (Bit 2) in
Configuration Register 3 (0x78) to 1. This works only if the fan
is already running, for example, in manual mode when the
current duty cycle is above 0x00, or in automatic mode when the
temperature is above TMIN. If the temperature is below TMIN or if
the duty cycle in manual mode is set to 0x00, then pulling the
THERM low externally has no effect. See Figure 27 for more
information.
The 8-bit THERM timer status register (0x79) is designed so
that the Bit 0 is set to 1 on the first THERM assertion. Once the
cumulative THERM assertion time has exceeded 45.52 ms, Bit 1
of the THERM timer is set and Bit 0 now becomes the LSB of
the timer with a resolution of 22.76 ms (see Figure 28).
When using the THERM timer, be aware of the following.
After a THERM timer read (Register 0x79):
1.
The contents of the timer are cleared on read.
2.
The F4P bit (Bit 5) of Interrupt Status Register 2 needs to
be cleared (assuming that the THERM timer limit has been
exceeded).
TMIN
If the THERM timer is read during a THERM assertion, the
following happens:
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100% BECAUSE
TEMPERATURE IS ABOVE TMIN AND FANS
ARE ALREADY RUNNING.
The contents of the timer are cleared.
2.
Bit 0 of the THERM timer is set to 1 (because a THERM
assertion is occurring).
3.
The THERM timer increments from zero.
4.
If the THERM timer limit (Register 0x7A) = 0x00, then the
F4P bit is set.
05381-030
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100% BECAUSE
TEMPERATURE IS BELOW TMIN.
1.
Figure 27. Asserting THERM Low as an Input in Automatic Fan Speed Control
Mode
THERM
THERM
TIMER
(REG. 0x79)
THERM TIMER
The ADT7475 has an internal timer to measure THERM
assertion time. For example, the THERM input can be connected to the PROCHOT output of a Pentium 4 CPU to
measure system performance. The THERM input can also be
connected to the output of a trip point temperature sensor.
The timer is started on the assertion of the ADT7475’s THERM
input and stopped when THERM is unasserted. The timer counts
THERM times cumulatively, that is, the timer resumes counting
on the next THERM assertion. The THERM timer continues to
accumulate THERM assertion times until the timer is read (it is
cleared on read) or until it reaches full scale. If the counter
reaches full scale, it stops at that reading until cleared.
0 0 0 0 0 0 0 1
7 6 5 4 3 2 1 0
THERM ASSERTED
≤ 22.76ms
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0
THERM ASSERTED
≥ 45.52ms
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 1 0 1
7 6 5 4 3 2 1 0 THERM ASSERTED ≥ 113.8ms
(91.04ms + 22.76ms)
Figure 28. Understanding the THERM Timer
Rev. A | Page 23 of 68
05381-031
THERM
ADT7475
Generating SMBALERT Interrupts from THERM Timer
Events
If the THERM timer value exceeds the THERM timer limit
value, then the F4P bit (Bit 5) of Interrupt Status Register 2 is
set, and an SMBALERT is generated. Note the F4P bit (Bit 5) of
Interrupt Mask Register 2 (0x75) masks out SMBALERTs, if this
bit is set to 1; although the F4P bit of Interrupt Status Register 2
still is set, if the THERM timer limit is exceeded.
The ADT7475 can generate SMBALERTs when a programmable THERM timer limit has been exceeded. This allows the
system designer to ignore brief, infrequent THERM assertions,
while capturing longer THERM timer events. Register 0x7A is
the THERM timer limit register. This 8-bit register allows a
limit from 0 seconds (first THERM assertion) to 5.825 seconds
to be set before an SMBALERT is generated. The THERM timer
value is compared with the contents of the THERM timer limit
register.
Figure 29 is a functional block diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (0x7A) causes SMBALERT to be
generated on the first THERM assertion. A THERM timer limit
value of 0x01 generates an SMBALERT, once cumulative
THERM assertions exceed 45.52 ms.
2.914s
1.457s
728.32ms
364.16ms THERM TIMER
182.08ms (REGISTER 0x79)
91.04ms
45.52ms
22.76ms
2.914s
1.457s
728.32ms
364.16ms
THERM
TIMER LIMIT 182.08ms
(REGISTER 0x7A) 91.04ms
45.52ms
22.76ms
0 1 2 3 4 5 6 7
7 6 5 4 3 2 1 0
THERM
THERM TIMER CLEARED ON READ
COMPARATOR
IN
OUT
LATCH
F4P BIT (BIT 5)
INTERRUPT STATUS
REGISTER 2
SMBALERT
RESET
CLEARED
ON READ
F4P BIT (BIT 5)
INTERRUPT MASK REGISTER 2
(REGISTER 0x75)
Figure 29. Functional Block Diagram of ADT7475’s THERM Monitoring Circuitry
Rev. A | Page 24 of 68
05381-032
1 = MASK
ADT7475
Configuring the THERM Behavior
Configure the relevant pin as the THERM timer input.
Setting Bit 1 (THERM) of Configuration Register 3
(0x78) enables the THERM timer monitoring
functionality. This is disabled on Pin 9 by default.
Setting Bit 0 and Bit 1 (PIN9FUNC) of Configuration
Register 4 (0x7D) enables THERM timer/output functionality on Pin 9 (Bit 1, THERM, of Configuration
Register 3, must also be set). Pin 9 can also be used as
TACH4.
2.
Select the desired fan behavior for THERM timer
events.
Assuming that the fans are running, setting Bit 2
(BOOST bit) of Configuration Register 3 (0x78)
causes all fans to run at 100% duty cycle whenever
THERM is asserted. This allows fail-safe system
cooling. If this bit is 0, the fans run at their current
settings and are not affected by THERM events. If the
fans are not already running when THERM is
asserted, the fans do not run to full speed.
3.
Select whether THERM timer events should generate
SMBALERT interrupts.
Bit 5 (F4P) of Interrupt Mask Register 2 (0x75), when
set, masks out SMBALERTs when the THERM timer
limit value is exceeded. This bit should be cleared if
SMBALERTs based on THERM events are required.
4.
Select a suitable THERM limit value.
This value determines whether an SMBALERT is
generated on the first THERM assertion, or only if a
cumulative THERM assertion time limit is exceeded.
A value of 0x00 causes an SMBALERT to be generated
on the first THERM assertion.
5.
Select a THERM monitoring time.
Configuring the THERM Pin as an Output
In addition to monitoring THERM as an input, the ADT7475
can optionally drive THERM low as an output. In cases where
PROCHOT is bidirectional, THERM can be used to throttle the
processor by asserting PROCHOT. The user can preprogram
system-critical thermal limits. If the temperature exceeds a
thermal limit by 0.25°C, THERM asserts low. If the temperature is still above the thermal limit on the next monitoring
cycle, THERM stays low. THERM remains asserted low until
the temperature is equal to or below the thermal limit. Because
the temperature for that channel is measured only once for
every monitoring cycle, after THERM asserts it is guaranteed
to remain low for at least one monitoring cycle.
The THERM pin can be configured to assert low, if the Remote 1,
local, or Remote 2 THERM temperature limits are exceeded
by 0.25°C. The THERM temperature limit registers are at
Register 0x6A, Register 0x6B, and Register 0x6C, respectively.
Setting Bit 3 of Register 0x5F, Register 0x60, and Register 0x61
enables the THERM output feature for the Remote 1, local, and
Remote 2 temperature channels, respectively. Figure 30 shows
how the THERM pin asserts low as an output in the event of a
critical over temperature.
THERM LIMIT
0.25°C
THERM LIMIT
TEMP
THERM
This value specifies how often OS or BIOS level
software checks the THERM timer. For example,
BIOS could read the THERM timer once an hour to
determine the cumulative THERM assertion time.
If, for example, the total THERM assertion time is
<22.76 ms in Hour 1, >182.08 ms in Hour 2, and
>5.825 s in Hour 3, this can indicate that system
performance is degrading significantly because
THERM is asserting more frequently on an hourly
basis.
MONITORING
CYCLE
05381-033
1.
Alternatively, OS- or BIOS-level software can timestamp
when the system is powered on. If an SMBALERT is generated due to the THERM timer limit being exceeded,
another timestamp can be taken. The difference in time
can be calculated for a fixed THERM timer limit time.
For example, if it takes one week for a THERM timer limit
of 2.914 sec to be exceeded and the next time it takes only
1 hour, then this is an indication of a serious degradation
in system performance.
Figure 30. Asserting THERM as an Output, Based on Tripping
THERM Limits
An alternative method of disabling THERM is to program the
THERM temperature limit to −64°C or less in Offset 64 mode,
or −128°C or less in twos complement mode; that is, for
THERM temperature limit values less than −63°C or −128°C,
respectively, THERM is disabled.
Rev. A | Page 25 of 68
ADT7475
Enabling and Disabling THERM on Individual Channels
THERM can be enabled/disabled for individual or combinations of temperature channels using Bits [7:5] of Configuration
Register 5 (0x7C).
THERM Hysteresis
The only other stipulation is that the MOSFET should have a
gate voltage drive, VGS < 3.3 V, for direct interfacing to the
PWM output pin. The MOSFET should also have a low on
resistance to ensure that there is not significant voltage drop
across the FET, which would reduce the voltage applied across
the fan and, therefore, the maximum operating speed of the fan.
Figure 31 shows how to drive a 3-wire fan using PWM control.
12V
If THERM hysteresis is enabled and THERM is disabled (Bit 2
of Configuration Register 4, 0x7D), the THERM pin does not
assert low when a THERM event occurs. If THERM hysteresis
is disabled and THERM is disabled (Bit 2 of Configuration
Register 4, 0x7D and assuming the appropriate pin is configured as THERM), the THERM pin asserts low when a THERM
event occurs.
12V
10kΩ
TACH/AIN
10kΩ
12V
FAN
1N4148
4.7kΩ
ADT7475
3.3V
10kΩ
Q1
NDT3055L
PWM
05381-034
Setting Bit 0 of Configuration Register 7 (0x11) disables
THERM hysteresis.
Figure 31. Driving a 3-Wire Fan Using an N-Channel MOSFET
If THERM and THERM hysteresis are both enabled, the
THERM output asserts as expected.
THERM Operation in Manual mode
In manual mode, THERM events do not cause fans to go to full
speed, unless Bit 3 of Configuration Register 6 (0x10) is set to 1.
Additionally, Bit 3 of Configuration Register 4 (0x7D) can
be used to select PWM speed on THERM event (100% or
maximum PWM).
Bit 2 in Configuration Register 4 (0x7D) can be set to disable
THERM events from affecting the fans.
FAN DRIVE USING PWM CONTROL
The ADT7475 uses pulse-width modulation (PWM) to control
fan speed. This relies on varying the duty cycle (or on/off ratio)
of a square wave applied to the fan to vary the fan speed. The
external circuitry required to drive a fan using PWM control is
extremely simple. For 4-wire fans, the PWM drive might need
only a pull-up resistor. In many cases, the 4-wire fan PWM
input has a built-in pull-up resistor.
Figure 31 uses a 10 kΩ pull-up resistor for the TACH signal. This
assumes that the TACH signal is an open-collector from the fan.
In all cases, the TACH signal from the fan must be kept below
3.6 V maximum to prevent damaging the ADT7475. If in doubt
as to whether the fan used has an open-collector or totem pole
TACH output, use one of the input signal conditioning circuits
shown in the Fan Speed Measurement section.
Figure 32 shows a fan drive circuit using an NPN transistor
such as a general-purpose MMBT2222. While these devices
are inexpensive, they tend to have much lower current handling capabilities and higher on resistance than MOSFETs.
When choosing a transistor, care should be taken to ensure
that it meets the fan’s current requirements.
Ensure that the base resistor is chosen, so the transistor is
saturated when the fan is powered on.
12V
10kΩ
TACH
10kΩ
4.7kΩ
The ADT7475 PWM frequency can be set to a selection of
low frequencies or a single high PWM frequency. The low
frequency options are usually used for 3-wire fans, while the
high frequency option is usually used with 4-wire fans.
12V
ADT7475
TACH
12V
FAN
1N4148
3.3V
PWM
For 3-wire fans, a single N-channel MOSFET is the only drive
device required. The specifications of the MOSFET depend on
the maximum current required by the fan being driven. Typical
notebook fans draw a nominal 170 mA, so SOT devices can be
used where board space is a concern. In desktops, fans can
typically draw 250 mA to 300 mA each. If you drive several
fans in parallel from a single PWM output or drive larger
server fans, the MOSFET must handle the higher current
requirements.
Rev. A | Page 26 of 68
Q1
MMBT2222
Figure 32. Driving a 3-Wire Fan Using an NPN Transistor
05381-035
665Ω
ADT7475
Because 4-wire fans are powered continuously, the fan speed is
not switched on or off as with previous PWM driven/powered
fans. This enables it to perform better than 3-wire fans, especially for high frequency applications. Figure 33 shows a typical
drive circuit for 4-wire fans.
12V 12V
12V, 4-WIRE FAN
10kΩ
TACH measurements for fans are synchronized to particular
PWM channels; for example, TACH1 is synchronized to
PWM1. TACH3 and TACH4 are both synchronized to PWM3,
so PWM3 can drive two fans. Alternatively, PWM3 can be programmed to synchronize TACH2, TACH3, and TACH4 to the
PWM3 output. This allows PWM3 to drive two or three fans.
In this case, the drive circuitry looks the same, as shown in
Figure 37 and Figure 38. The SYNC bit in Register 0x62 enables
this function.
TACH
TACH
4.7kΩ
ADT7475
Driving up to Three Fans from PWM3
VCC
10kΩ
TACH
PWM
3.3V
05381-036
2kΩ
PWM
Figure 33. Driving a 4-Wire Fan
Driving Two Fans from PWM3
The ADT7475 has four TACH inputs available for fan speed
measurement, but only three PWM drive outputs. If a fourth
fan is being used in the system, it should be driven from the
PWM3 output in parallel with the third fan. Figure 34 shows
how to drive two fans in parallel using low cost NPN
transistors. Figure 35 shows the equivalent circuit using a
MOSFET.
Synchronization is not required in high frequency mode when
used with 4-wire fans.
Bit 4 (SYNC) Enhance Acoustics Register 1 (0x62)
SYNC = 1, synchronizes TACH2, TACH3, and TACH4
to PWM3.
TACH Inputs
12V
3.3V
3.3V
1N4148
ADT7475
TACH3
1kΩ
PWM3
2.2kΩ
TACH4
Q1
MMBT3904
10Ω
Q2
MMBT2222
05381-037
10Ω
Q3
MMBT2222
Because the MOSFET can handle up to 3.5 A, it is simply a
matter of connecting another fan directly in parallel with the
first. Care should be taken in designing drive circuits with
transistors and FETs to ensure that the PWM pins are not
required to source current and that they sink less than the
8 mA maximum current specified on the data sheet.
Figure 34. Interfacing Two Fans in Parallel to the PWM3 Output Using Low
Cost NPN Transistors
3.3V
10kΩ
TYPICAL
Pin 4, Pin 6, Pin 7, and Pin 9, when configured as TACH
inputs, are open-drain TACH inputs intended for fan speed
measurement.
Signal conditioning in the ADT7475 accommodates the slow
rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 3.6 V. In the event these inputs
are supplied from fan outputs that exceed 0 V to 3.6 V, either
resistive attenuation of the fan signal or diode clamping must be
included to keep inputs within an acceptable range.
Figure 36 to Figure 39 show circuits for most common fan
TACH outputs. If the fan TACH output has a resistive pull-up
to VCC, it can be connected directly to the fan input, as shown
in Figure 36.
TACH4
+V
3.3V
12V
10kΩ
TYPICAL
TACH3
TACH
5V OR
12V FAN
1N4148
TACH
5V OR
12V FAN
3.3V
TACH
OUTPUT
10kΩ
TYPICAL
Q1
NDT3055L
05381-038
PWM3
PULL-UP
4.7kΩ
TYPICAL
Figure 35. Interfacing Two Fans in Parallel to the PWM3 Output Using a
Single N-Channel MOSFET
Rev. A | Page 27 of 68
TACH
FAN SPEED
COUNTER
ADT7475
Figure 36. Fan with TACH Pull-Up to V CC
B
05381-039
ADT7475
VCC
+V
ADT7475
If the fan output has a resistive pull-up to 12 V, or other voltage
greater than 3.6 V, the fan output can be clamped with a Zener
diode, as shown in Figure 37. The Zener diode voltage should
be chosen so that it is greater than VIH of the TACH input but
less than 3.6 V, allowing for the voltage tolerance of the Zener.
A value between 3 V and 3.6 V is suitable.
VCC
PULL-UP
4.7kΩ
TYPICAL
TACH
OUTPUT
TACH
ZD11
FAN SPEED
COUNTER
ADT7475
05381-040
12V
1 CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × V .
CC
Figure 37. Fan with TACH Pull-Up to Voltage > 3.6 V (For Example, 12 V)
Clamped with Zener Diode
VCC
TACH
OUTPUT
TACH
ZD1
ZENER*
Once the corresponding high byte has been read, TACH
measurements are unlocked and interrupts are processed as
normal.
FAN SPEED
COUNTER
ADT7475
05381-041
R1
10kΩ
N, the number of pulses counted, is determined by the settings of Register 0x7B (TACH pulses per revolution register).
This register contains two bits for each fan, allowing one, two
(default), three, or four TACH pulses to be counted.
When the ADT7475 starts up, TACH measurements are locked.
In effect, an internal read of the low byte has been made for
each TACH input. The net result of this is that all TACH
readings are locked until the high byte is read from the
corresponding TACH registers. All TACH related interrupts are
also ignored until the appropriate high byte is read.
FAN
PULL-UP TYP
<1kΩ OR
TOTEM POLE
The fan counter does not count the fan TACH output pulses
directly, because the fan speed could be less than 1000 RPM and it
would take several seconds to accumulate a reasonably large and
accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 90 kHz oscillator into the input of a 16bit counter for N periods of the fan TACH output (see Figure 40),
so the accumulated count is actually proportional to the fan
tachometer period and inversely proportional to the fan speed.
Measuring fan TACH
If the fan has a strong pull-up (less than 1 kΩ) to 12 V or a
totem-pole output, then a series resistor can be added to limit
the Zener current, as shown in Figure 38.
5V OR 12V
Fan Speed Measurement
1 CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × V .
CC
CLOCK
Figure 38. Fan with Strong TACH Pull-Up to > VCC or Totem-Pole Output,
Clamped with Zener and Resistor
PWM
Alternatively, a resistive attenuator can be used, as shown in
Figure 39. R1 and R2 should be chosen such that
TACH
2 V < VPULL-UP × R2/(RPULL-UP + R1 + R2) < 3.6 V
1
3
The fan inputs can have an input resistance of 160 kΩ to 5.1 kΩ
to ground, which should be taken into account when calculating resistor values.
With a pull-up voltage of 12 V and pull-up resistor less than
1 kΩ, suitable values for R1 and R2 would be 100 kΩ and 33 kΩ,
respectively. This gives a high input voltage of 2.95 V.
VCC
12V
4
Figure 40. Fan Speed Measurement
Fan Speed Measurement Registers
The fan tachometer readings are 16-bit values consisting of a
2-byte read from the ADT7475.
Register 0x28, TACH1 Low Byte = 0x00 default
Register 0x29, TACH1 High Byte = 0x00 default
Register 0x2A, TACH2 Low Byte = 0x00 default
R11
TACH
OUTPUT
TACH
R21
1 SEE TEXT.
FAN SPEED
COUNTER
ADT7475
Register 0x2B, TACH2 High Byte = 0x00 default
05381-042
<1kΩ
Figure 39. Fan with Strong TACH Pull-Up to > VCC or Totem-Pole Output,
Attenuated with R1/R2
Register 0x2C, TACH3 Low Byte = 0x00 default
Register 0x2D, TACH3 High Byte = 0x00 default
Register 0x2E, TACH4 Low Byte = 0x00 default
Register 0x2F, TACH4 High Byte = 0x00 default
Rev. A | Page 28 of 68
05381-043
2
ADT7475
Reading Fan Speed from the ADT7475
Calculating Fan Speed
The measurement of fan speeds involves a 2-register read for
each measurement. The low byte should be read first. This
causes the high byte to be frozen until both high and low byte
registers have been read, preventing erroneous TACH readings.
The fan tachometer reading registers report back the number of
11.11 µs period clocks (90 kHz oscillator) gated to the fan speed
counter, from the rising edge of the first fan TACH pulse to the
rising edge of the third fan TACH pulse (assuming two pulses per
revolution are being counted). Because the device is essentially
measuring the fan TACH period, the higher the count value, the
slower the fan is actually running. A 16-bit fan tachometer reading of 0xFFFF indicates either that the fan has stalled or is
running very slowly (<100 RPM).
Assuming a fan with a two pulses per revolution (and two
pulses per revolution being measured) fan speed is calculated
by the following:
Fan Speed (RPM) = (90,000 × 60)/Fan TACH Reading
where Fan TACH Reading is the 16-bit fan tachometer reading.
Example
TACH1 High Byte (Register 0x29) = 0x17
TACH1 Low Byte (Register 0x28) = 0xFF
What is Fan 1 speed in RPM?
Fan 1 TACH Reading = 0x17FF = 6143 (decimal)
High Limit > Comparison Performed
RPM = (f × 60)/Fan 1 TACH Reading
Because the actual fan TACH period is being measured, falling
below a fan TACH limit by 1 sets the appropriate status bit and
can be used to generate an SMBALERT.
RPM = (90000 × 60)/6143
Fan Speed = 879 RPM
Fan TACH Limit Registers
Fan Pulses per Revolution
The fan TACH limit registers are 16-bit values consisting of
two bytes.
Different fan models can output either 1, 2, 3, or 4 TACH pulses
per revolution. Once the number of fan TACH pulses has been
determined, it can be programmed into the fan pulses per
revolution register (Register 0x7B) for each fan.
Register 0x54, TACH1 Minimum Low Byte = 0xFF default
Register 0x55, TACH1 Minimum High Byte = 0xFF default
Alternatively, this register can be used to determine the number
or pulses per revolution output by a given fan. By plotting fan
speed measurements at 100% speed with different pulses per
revolution setting, the smoothest graph with the lowest ripple
determines the correct pulses per revolution value.
Register 0x56, TACH2 Minimum Low Byte = 0xFF default
Register 0x57, TACH2 Minimum High Byte = 0xFF default
Register 0x58, TACH3 Minimum Low Byte = 0xFF default
Register 0x59, TACH3 Minimum High Byte = 0xFF default
Register 0x5A, TACH4 Minimum Low Byte = 0xFF default
Fan Pulses per Revolution Register
Register 0x5B, TACH4 Minimum High Byte = 0xFF default
Bits [1:0] Fan 1 default = 2 pulses per revolution.
Fan Speed Measurement Rate
Bits [3:2] Fan 2 default = 2 pulses per revolution.
The fan TACH readings are normally updated once every
second. The FAST bit (Bit 3) of Configuration Register 3 (0x78),
when set, updates the fan TACH readings every 250 ms.
Bits [5:4] Fan 3 default = 2 pulses per revolution.
Bits [7:6] Fan 4 default = 2 pulses per revolution.
00 = 1 pulse per revolution
If any of the fans are not being driven by a PWM channel but
are powered directly from 5 V or 12 V, their associated dc bit
in Configuration Register 3 should be set. This allows TACH
readings to be taken on a continuous basis for fans connected
directly to a dc source. For optimal results, the associated dc bit
should always be set when using 4-wire fans.
Rev. A | Page 29 of 68
01 = 2 pulses per revolution
10 = 3 pulses per revolution
11 = 4 pulses per revolution
ADT7475
Fan Spin-Up
PWM2 Configuration Register (0x5D)
The ADT7475 has a unique fan spin-up function. It spins the fan
at 100% PWM duty cycle until two TACH pulses are detected on
the TACH input. Once two TACH pulses have been detected, the
PWM duty cycle goes to the expected running value, for example,
33%. The advantage is that fans have different spin-up characteristics and take different times to overcome inertia. The
ADT7475 runs the fans just fast enough to overcome inertia
and is quieter on spin-up than fans programmed to spin up for
a given spin-up time.
Bit 4 INV
0 = Logic high for 100% PWM duty cycle.
1 = Logic low for 100% PWM duty cycle.
Fan Startup Timeout
The PWM drive frequency can be adjusted for the application.
Register 0x5F to Register 0x61 configure the PWM frequency
for PWM1 to PWM3, respectively. In high frequency mode, the
PWM drive frequency is always 22.5 kHz.
To prevent the generation of false interrupts as a fan spins up
(because it is below running speed), the ADT7475 includes a
fan startup timeout function. During this time, the ADT7475
looks for two TACH pulses. If two TACH pulses are not
detected, an interrupt is generated. Using Configuration
Register 4 (0x40), Bit 5 (FSPDIS), this functionality can be
changed (see the Disabling Fan Startup Timeout section).
PWM1, PWM2, PWM3 Configuration Registers (0x5C,
0x5D, and 0x5E)
PWM3 Configuration Register (0x5E)
Bit 4 INV
0 = Logic high for 100% PWM duty cycle.
1 = Logic low for 100% PWM duty cycle.
Low Frequency Mode PWM Drive Frequency
High Frequency Mode PWM Drive
Setting Bit 3 of Register 0x5F, Register 0x60, and Register 0x61
enables high frequency mode for Fan 1, Fan 2, and Fan 3,
respectively.
PWM Frequency Registers (0x5F to 0x61)
Bits [2:0] SPIN, startup timeout for PWM1 = 0x5C, PWM2 =
0x5D, and PWM3 = 0x5E.
Bits [2:0] FREQ
000 = 11.0 Hz
000 = No startup timeout
001 = 14.7 Hz
001 = 100 ms
010 = 22.1 Hz
010 = 250 ms default
011 = 29.4 Hz
011 = 400 ms
100 = 35.3 Hz default
100 = 667 ms
101 = 44.1 Hz
101 = 1 sec
110 = 58.8 Hz
110 = 2 sec
111 = 88.2 Hz
Fan Speed Control
111 = 4 sec
Disabling Fan Startup Timeout
Although fan startup makes fan spin-ups much quieter than
fixed-time spin-ups, the option exists to use fixed spin-up
times. Setting Bit 5 (FSPDIS) to 1 in Configuration Register 1
(0x40) disables the spin-up for two TACH pulses. Instead, the
fan spins up for the fixed time as selected in Register 0x5C to
Register 0x5E.
The ADT7475 controls fan speed using automatic mode and
manual mode as follows:
•
In automatic fan speed control mode, fan speed is
automatically varied with temperature and without CPU
intervention, once initial parameters are set up. The
advantage of this is, if the system hangs, the user is
guaranteed the system is protected from overheating. For
more information and how to program the automatic fan
speed control loop, see the Programming the Automatic
Fan Speed Control Loop section.
•
In manual fan speed control mode, the ADT7475 allows
the duty cycle of any PWM output to be manually
adjusted. This can be useful if the user wants to change fan
speed at the software level or adjust PWM duty cycle
output for test purposes. Bits [7:5] of Register 0x5C to
Register 0x5E (PWM configuration) control the behavior
of each PWM output.
PWM Logic State
The PWM outputs can be programmed high for 100% duty
cycle (noninverted) or low for 100% duty cycle (inverted).
PWM1 Configuration Register (0x5C)
Bit 4 INV
0 = Logic high for 100% PWM duty cycle.
1 = Logic low for 100% PWM duty cycle.
Rev. A | Page 30 of 68
ADT7475
PWM Configuration Registers (0x5C to 0x5E)
When the VCCP voltage drops below the VCCP low limit, the
following occurs:
Bits [7:5] BHVR
111 = manual mode.
Once under manual control, each PWM output can be manually updated by writing to Register 0x30 to Register 0x32
(PWMx current duty cycle registers).
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8-bit registers, which
allow the PWM duty cycle for each output to be set anywhere
from 0% to 100% in steps of 0.39%.
1.
Status Bit 1 (VCCP) in Status Register 1 is set.
2.
SMBALERT is generated, if enabled.
3.
THERM monitoring is disabled. The THERM timer
should hold its value prior to the S3 or S5 state.
Once the core voltage, VCCP, goes above the VCCP low limit,
everything is re-enabled and the system resumes normal
operation.
XNOR TREE TEST MODE
The value to be programmed into the PWMMIN register is
given by
The ADT7475 includes an XNOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XNOR tree, it is
possible to detect opens or shorts on the system board.
Value (decimal) = PWMMIN/0.39
Example 1: For a PWM duty cycle of 50%,
Figure 41 shows the signals that are exercised in the XNOR
tree test mode. The XNOR tree test is invoked by setting Bit 0
(XEN) of the XNOR tree test enable register (0x6F).
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 0x80 (hex)
Example 2: For a PWM duty cycle of 33%,
TACH1
TACH2
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) or 0x54 (hex)
TACH3
PWM Current Duty Cycle Registers
TACH4
Register 0x30, PWM1 Duty Cycle = 0x00 (0% default)
Register 0x32, PWM3 Duty Cycle = 0x00 (0% default)
PWM3
By reading the PWMx current duty cycle registers, the user can
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode. See the Programming the
Automatic Fan Speed Control Loop section for details.
OPERATING FROM 3.3 V STANDBY
The ADT7475 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5 states,
the core voltage of the processor is lowered in these states.
When monitoring THERM, the THERM timer should be
disabled during these states.
STANDBY MODE
The ADT7475 has been specifically designed to respond to the
STBY supply. In computers that support S3 and S5 states, the
core voltage of the processor is lowered in these states. When
monitoring THERM, the THERM timer should be disabled
during these states.
Rev. A | Page 31 of 68
PWM1/XTO
Figure 41. XNOR Tree Test
05381-044
PWM2
Register 0x31, PWM2 Duty Cycle = 0x00 (0% default)
ADT7475
POWER-ON DEFAULT
ADT7475 IS POWERED UP
When the ADT7475 is powered up, it polls the VCCP input.
Y
HAS THE ADT7475 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
If VCCP stays below 0.75 V (the system CPU power rail is not
powered up), the ADT7475 assumes the functionality of the
default registers after the ADT7475 is addressed via any valid
SMBus transaction.
N
IS VCCP ABOVE 0.75V?
N
CHECK V CCP
Y
If VCC goes high (the system processor power rail is powered
up), a fail-safe timer begins to count down. If the ADT7475 is
not addressed by any valid SMBus transactions before the failsafe timeout (4.6 seconds) lapses, the ADT7475 drives the fans
to full speed. If the ADT7475 is addressed by a valid SMBus
transaction after this point, the fans stop, and the ADT7475
assumes its default settings and begins normal operation.
START FAIL-SAFE TIMER
HAS THE ADT7475 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
N
FAIL-SAFE TIMER ELAPSES
AFTER THE FAIL-SAFE TIMEOUT
HAS THE ADT7475 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
N
RUNS THE FANS
TO FULL SPEED
Y
HAS THE ADT7475 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
N
If VCCP goes high (the system processor power rail is powered
up), then a fail-safe timer begins to count down. If the
ADT7475 is addressed by a valid SMBus transaction before the
fail-safe timeout (4.6 seconds) lapses, then the ADT7475
operates normally, assuming the functionality of all the default
registers. See the flow chart in Figure 42.
Y
START UP THE
ADT7475 NORMALLY
SWITCH OFF FANS
05381-045
Y
Figure 42.
Rev. A | Page 32 of 68
ADT7475
PROGRAMMING THE AUTOMATIC FAN SPEED CONTROL LOOP
This section provides the system designer with an understanding
of the automatic fan control loop, and provides step-by-step
guidance on effectively evaluating and selecting critical system
parameters. To optimize the system characteristics, the designer
needs to give some thought to system configuration, including
the number of fans, where they are located, and what temperatures are being measured in the particular system.
The mechanical or thermal engineer who is tasked with the
system thermal characterization should also be involved at
the beginning of this process.
AUTOMATIC FAN CONTROL OVERVIEW
The ADT7475 can automatically control the speed of fans based
upon the measured temperature. This is done independently of
CPU intervention once initial parameters are set up.
The ADT7475 has a local temperature sensor and two remote
temperature channels that can be connected to a CPU on-chip
thermal diode (available on Intel Pentium® class and other
CPUs). These three temperature channels can be used as the
basis for automatic fan speed control to drive fans using pulsewidth modulation (PWM).
Automatic fan speed control reduces acoustic noise by
optimizing fan speed according to accurately measured
temperature. Reducing fan speed can also decrease system
current consumption.
THERMAL CALIBRATION
The automatic fan speed control mode is very flexible owing to
the number of programmable parameters, including TMIN and
TRANGE. The TMIN and TRANGE values for a temperature channel,
and, therefore, for a given fan are critical because they define
the thermal characteristics of the system. The thermal validation of the system is one of the most important steps in the
design process, so select these values carefully.
Figure 43 gives a top-level overview of the automatic fan control
circuitry on the ADT7475. From a systems-level perspective,
up to three system temperatures can be monitored and used to
control three PWM outputs. The three PWM outputs can be used
to control up to four fans. The ADT7475 allows the speed of four
fans to be monitored. Each temperature channel has a thermal
calibration block, allowing the designer to individually configure
the thermal characteristics of each temperature channel.
For example, one can decide to run the CPU fan when CPU
temperature increases above 60°C and a chassis fan when the
local temperature increases above 45°C. At this stage, the
designer has not assigned these thermal calibration settings
to a particular fan drive (PWM) channel. The right side of
Figure 43 shows controls that are fan-specific. The designer
has individual control over parameters such as minimum
PWM duty cycle, fan speed failure thresholds, and even ramp
control of the PWM outputs. Automatic fan control, then,
ultimately allows graceful fan speed changes that are less
perceptible to the system user.
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
REMOTE 1
TEMP
TMIN
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
GENERATOR
MUX
LOCAL
TEMP
TMIN
TRANGE
THERMAL CALIBRATION
100%
PWM
CONFIG
PWM
GENERATOR
REMOTE 2
TEMP
TMIN
TRANGE
TACHOMETER 3
AND 4
MEASUREMENT
0%
Figure 43. Automatic Fan Control Block Diagram
Rev. A | Page 33 of 68
PWM1
TACH1
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 2
MEASUREMENT
0%
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM2
TACH2
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM3
TACH3
05381-046
To more efficiently understand the automatic fan speed control
loop, it is strongly recommended to use the ADT7475 evaluation board and software while reading this section.
ADT7475
STEP 1: HARDWARE CONFIGURATION
During system design, the motherboard sensing and control
capabilities should be addressed early in the design stages.
Decisions about how these capabilities are used should involve
the system thermal/mechanical engineer. Ask the following
questions:
How many fans will be supported in the system, three or
four? This influences the choice of whether to use the
TACH4 pin or to reconfigure it for the THERM function.
3.
Is the CPU fan to be controlled using the ADT7475 or will
it run at full speed 100% of the time?
If run at 100%, this frees up a PWM output, but the system
is louder.
What ADT7475 functionality will be used?
•
PWM2 or SMBALERT?
•
TACH4 fan speed measurement or overtemperature
THERM function?
4.
Where will the ADT7475 be physically located in the
system?
This influences the assignment of the temperature measurement channels to particular system thermal zones.
For example, locating the ADT7475 close to the VRM
controller circuitry allows the VRM temperature to be
monitored using the local temperature channel.
The ADT7475 offers multifunctional pins that can be
reconfigured to suit different system requirements and
physical layouts. These multifunction pins are software
programmable.
THERMAL CALIBRATION
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
TMIN
REMOTE 1 =
AMBIENT TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TMIN
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
GENERATOR
MUX
PWM
CONFIG
TRANGE
0%
TACHOMETER 3
AND 4
MEASUREMENT
REMOTE 2 =
CPU TEMP
PWM1
TACH1
CPU FAN SINK
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 2
MEASUREMENT
PWM
GENERATOR
TMIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM2
TACH2
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
FRONT CHASSIS
PWM3
TACH3
REAR CHASSIS
Figure 44. Hardware Configuration Example
Rev. A | Page 34 of 68
05381-047
1.
2.
ADT7475
Recommended Implementation 1
•
Configuring the ADT7475 as in Figure 45 provides the system
designer with the following features:
CPU temperature measured using the Remote 1
temperature channel.
•
Ambient temperature measured through the Remote 2
temperature channel.
•
Bidirectional THERM pin allows the monitoring
of PROCHOT output from an Intel Pentium 4 processor,
for example, or can be used as an overtemperature
THERM output.
•
SMBALERT system interrupt output.
Two PWM outputs for fan control of up to three fans. (The
front and rear chassis fans are connected in parallel.)
•
Three TACH fan speed measurement inputs.
•
VCC measured internally through Pin 4.
•
CPU core voltage measurement (VCORE).
•
VRM temperature using local temperature sensor.
ADT7475
FRONT
CHASSIS
FAN
TACH2
PWM1
TACH1
CPU FAN
PWM3
REAR
CHASSIS
FAN
D2+
TACH3
D2–
THERM
PROCHOT
AMBIENT
TEMPERATURE
D1+
CPU
SDA
SCL
D1–
SMBALERT
GND
ICH
Figure 45. Recommended Implementation 1
Rev. A | Page 35 of 68
05381-048
•
ADT7475
Recommended Implementation 2
•
Configuring the ADT7475 as in Figure 46 provides the system
designer with the following features:
CPU temperature measured using the Remote 1
temperature channel.
•
Ambient temperature measured through the Remote 2
temperature channel.
•
Bidirectional THERM pin allows the monitoring of
PROCHOT output from an Intel Pentium 4 processor, for
example, or can be used as an overtemperature THERM
output.
Three PWM outputs for fan control of up to three fans.
(All three fans can be individually controlled.)
•
Three TACH fan speed measurement inputs.
•
VCC measured internally through Pin 4.
•
CPU core voltage measurement (VCORE).
ADT7475
FRONT
CHASSIS
FAN
TACH2
PWM1
TACH1
CPU FAN
PWM3
REAR
CHASSIS
FAN
D2+
TACH3
D2–
THERM
PROCHOT
AMBIENT
TEMPERATURE
CPU
SDA
D1+
SCL
D1–
GND
Figure 46. Recommended Implementation 2
Rev. A | Page 36 of 68
ICH
05381-049
•
ADT7475
STEP 2: CONFIGURING THE MUX
010 = Remote 2 temperature controls PWMx
After the system hardware configuration is determined,
the fans can be assigned to particular temperature channels.
Not only can fans be assigned to individual channels, but the
behavior of the fans is also configurable. For example, fans can
be run under automatic fan control, manually under software
control, or at the fastest speed calculated by multiple
temperature channels. The mux is the bridge between
temperature measurement channels and the three PWM
outputs.
101 = Fastest speed calculated by local and Remote 2
temperature controls PWMx
110 = Fastest speed calculated by all three temperature
channel controls PWMx
The Fastest Speed Calculated options pertain to controlling
one PWM output based on multiple temperature channels.
The thermal characteristics of the three temperature zones
can be set to drive a single fan. An example would be the fan
turning on when Remote 1 temperature exceeds 60°C, or if
the local temperature exceeds 45°C.
Bits [7:5] (BHVR) of Register 0x5C, Register 0x5D, and Register
0x5E (PWM configuration registers) control the behavior of the
fans connected to the PWM1, PWM2, and PWM3 outputs.
The values selected for these bits determine how the mux
connects a temperature measurement channel to a PWM
output.
Other Mux Options
Bits [7:5] (BHVR), Register 0x5C, Register 0x5D, and Register
0x5E.
Automatic Fan Control Mux Options
011 = PWMx runs full speed
Bits [7:5] (BHVR), Register 0x5C, Register 0x5D, and Register
0x5E.
100 = PWMx disabled (default)
111 = manual mode. PWMx is running under software control. In this mode, PWM duty cycle registers
(0x30 to 0x32) are writable and control the PWM outputs.
000 = Remote 1 temperature controls PWMx
001 = local temperature controls PWMx
MUX
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
TMIN
REMOTE 1 =
AMBIENT TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TMIN
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
GENERATOR
MUX
PWM
CONFIG
TRANGE
0%
PWM1
TACH1
CPU FAN SINK
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 2
MEASUREMENT
PWM
GENERATOR
TMIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM2
TACH2
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
REMOTE 2 =
CPU TEMP
FRONT CHASSIS
PWM3
TACH3
REAR CHASSIS
Figure 47. Assigning Temperature Channels to Fan Channels
Rev. A | Page 37 of 68
05381-050
THERMAL CALIBRATION
ADT7475
Mux Configuration Example
Example Mux Settings
This is an example of how to configure the mux in a system
using the ADT7475 to control three fans. The CPU fan sink
is controlled by PWM1, the front chassis fan is controlled by
PWM2, and the rear chassis fan is controlled by PWM3. The
mux is configured for the following fan control behavior:
Bits [7:5] (BHVR), PWM1 Configuration Register (0x5C).
•
101 = Fastest speed calculated by local and Remote 2
temperature controls PWM1
Bits [7:5] (BHVR), PWM2 Configuration Register (0x5D).
000 = Remote 1 temperature controls PWM2
PWM1 (CPU fan sink) is controlled by the fastest speed
calculated by the local (VRM temperature) and Remote 2
(processor) temperatures. In this case, the CPU fan sink is
also being used to cool the VRM.
Bits [7:5] (BHVR), PWM3 Configuration Register (0x5E).
•
PWM2 (front chassis fan) is controlled by the Remote 1
temperature (ambient).
These settings configure the mux, as shown in Figure 48.
•
PWM3 (rear chassis fan) is controlled by the Remote 1
temperature (ambient).
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
0%
MUX
100%
PWM
MIN
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
GENERATOR
TMIN
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
PWM
CONFIG
TRANGE
0%
TACHOMETER 3
AND 4
MEASUREMENT
PWM1
TACH1
CPU FAN SINK
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 2
MEASUREMENT
PWM
GENERATOR
TMIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM2
TACH2
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
FRONT CHASSIS
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
Figure 48. Mux Configuration Example
Rev. A | Page 38 of 68
05381-051
THERMAL CALIBRATION
000 = Remote 1 temperature controls PWM3
ADT7475
TMIN Registers
STEP 3: TMIN SETTINGS FOR THERMAL
CALIBRATION CHANNELS
Register 0x67, Remote 1 Temperature TMIN = 0x9A (90°C)
TMIN is the temperature at which the fans start to turn on under
automatic fan control. The speed at which the fan runs at TMIN is
programmed later in the process. The TMIN values chosen are
temperature channel specific, for example, 25°C for ambient
channel, 30°C for VRM temperature, and 40°C for processor
temperature.
Register 0x68, Local Temperature TMIN = 0x9A (90°C)
Register 0x69, Remote 2 Temperature TMIN = 0x9A (90°C)
Enhance Acoustics Register 1 (0x62)
Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
TMIN is an 8-bit value, either twos complement or Offset 64,
that can be programmed in 1°C increments. There is a
TMIN register associated with each temperature measurement channel: Remote 1, local, and Remote 2 temperatures.
Once the TMIN value is exceeded, the fan turns on and runs at
the minimum PWM duty cycle. The fan turns off once the
temperature has dropped below TMIN − THYST.
Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle
below TMIN − THYST.
Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle
below TMIN − THYST.
To overcome fan inertia, the fan is spun up until two valid
TACH rising edges are counted. See the Fan Startup Timeout
section for more details. In some cases, primarily for psychoacoustic reasons, it is desirable that the fan never switch off
below TMIN. Bits [7:5] of Enhance Acoustics Register 1 (0x62),
when set, keep the fans running at the PWM minimum duty
cycle, if the temperature should fall below TMIN.
Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle
below TMIN − THYST.
PWM DUTY CYCLE
100%
0%
TMIN
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TMIN
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
GENERATOR
MUX
PWM
CONFIG
TRANGE
0%
TACHOMETER 3
AND 4
MEASUREMENT
PWM1
TACH1
CPU FAN SINK
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 2
MEASUREMENT
PWM
GENERATOR
TMIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM2
TACH2
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
FRONT CHASSIS
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
Figure 49. Understanding the TMIN Parameter
Rev. A | Page 39 of 68
05381-052
THERMAL CALIBRATION
ADT7475
STEP 4: PWMMIN FOR EACH PWM (FAN) OUTPUT
Programming the PWMMIN Registers
PWMMIN is the minimum PWM duty cycle at which each fan in
the system runs. It is also the start speed for each fan under
automatic fan control once the temperature rises above TMIN.
For maximum system acoustic benefit, PWMMIN should be
as low as possible. Depending on the fan used, the PWMMIN
setting is usually in the 20% to 33% duty cycle range.
This value can be found through fan validation.
The PWMMIN registers are 8-bit registers that allow the
minimum PWM duty cycle for each output to be configured
anywhere from 0% to 100%. This allows the minimum PWM
duty cycle to be set in steps of 0.39%.
The value to be programmed into the PWMMIN register is
given by
Value (decimal) = PWMMIN/0.39
PWM DUTY CYCLE
100%
Example 1: For a minimum PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
Example 2: For a minimum PWM duty cycle of 33%,
PWMMIN
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) or 54 (hex)
TMIN
TEMPERATURE
05381-055
0%
PWMMIN Registers
Figure 50. PWMMIN Determines Minimum PWM Duty Cycle
More than one PWM output can be controlled from a single
temperature measurement channel. For example, Remote 1
temperature can control PWM1 and PWM2 outputs. If two
different fans are used on PWM1 and PWM2, the fan
characteristics can be set up differently. As a result, Fan 1
driven by PWM1 can have a different PWMMIN value than
that of Fan 2 connected to PWM2. Figure 51 illustrates this as
PWM1MIN (front fan) turns on at a minimum duty cycle of 20%,
while PWM2MIN (rear fan) turns on at a minimum of 40% duty
cycle. Note: Both fans turn on at exactly the same temperature,
defined by TMIN.
PWM DUTY CYCLE
100%
M2
PW
PW
PWM2MIN
Register 0x64, PWM1 Minimum Duty Cycle = 0x80 (50%
default)
Register 0x65, PWM2 Minimum Duty Cycle = 0x80 (50%
default)
Register 0x66, PWM3 Minimum Duty Cycle = 0x80 (50%
default)
Note on Fan Speed and PWM Duty Cycle
The PWM duty cycle does not directly correlate to fan speed in
RPM. Running a fan at 33% PWM duty cycle does not equate to
running the fan at 33% speed. Driving a fan at 33% PWM duty
cycle actually runs the fan at closer to 50% of its full speed. This
is because fan speed in %RPM generally relates to the square
root of PWM duty cycle. Given a PWM square wave as the
drive signal, fan speed in RPM approximates to
% fanspeed = PWM duty cycle × 10
M1
STEP 5: PWMMAX FOR PWM (FAN) OUTPUTS
PWM1MIN
TMIN
TEMPERATURE
05381-056
0%
Figure 51. Operating Two Different Fans from a Single Temperature Channel
PWMMAX is the maximum duty cycle that each fan in the system
runs at under the automatic fan speed control loop. For maximum system acoustic benefit, PWMMAX should be as low as
possible, but should be capable of maintaining the processor
temperature limit at an acceptable level. If the THERM
temperature limit is exceeded, the fans are still boosted to
100% for fail-safe cooling.
There is a PWMMAX limit for each fan channel. The default
value of all PWMMAX registers is 0xFF.
Rev. A | Page 40 of 68
ADT7475
STEP 6: TRANGE FOR TEMPERATURE CHANNELS
TRANGE is the range of temperature over which automatic fan
control occurs once the programmed TMIN temperature has
been exceeded. TRANGE is the temperature range between PWMMIN
and 100% PWM where the fan speed changes linearly. Otherwise
stated, it is the line drawn between the TMIN/PWMMIN and
the (TMIN + TRANGE)/PWM 100% intersection points.
PWMMAX
PWMMIN
0%
TEMPERATURE
100%
PWM DUTY CYCLE
Figure 52. PWMMAX Determines Maximum PWM Duty Cycle Below the THERM
Temperature Limit
Programming the PWMMAX Registers
The PWMMAX registers are 8-bit registers that allow the
maximum PWM duty cycle for each output to be configured
anywhere from 0% to 100%. This allows the maximum PWM
duty cycle to be set in steps of 0.39%.
PWMMIN
0%
TMIN
The value to be programmed into the PWMMAX register is
given by
Value (decimal) = PWMMAX/0.39
Example 1: For a maximum PWM duty cycle of 50%,
Value (decimal) − 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
The TRANGE is determined by the following procedure:
1.
Determine the maximum operating temperature for that
channel (for example, 70°C).
2.
Determine, experimentally, the fan speed (PWM duty cycle
value) that does not exceed the temperature at the worstcase operating points. (For example, 70°C is reached when
the fans are running at 50% PWM duty cycle.)
3.
Determine the slope of the required control loop to meet
these requirements.
4.
Using the ADT7475 evaluation software, you can
graphically program and visualize this functionality.
Ask your local Analog Devices representative for details.
PWMMAX Registers
Register 0x38, PWM1 Maximum Duty Cycle = 0xFF
(100% default)
Register 0x39, PWM2 Maximum Duty Cycle = 0xFF
(100% default)
TEMPERATURE
Figure 53. TRANGE Parameter Affects Cooling Slope
Example 2: For a minimum PWM duty cycle of 75%,
Value (decimal) = 75/0.39 = 85 (decimal)
Value = 192 (decimal) or C0 (hex)
05381-058
TMIN
05381-057
TRANGE
As PWMMIN is changed, the automatic fan control slope also
changes.
Register 0x3A, PWM3 Maximum Duty Cycle = 0xFF
(100% default)
PWM DUTY CYCLE
100%
50%
33%
0%
30°C
TMIN
05381-059
PWM DUTY CYCLE
100%
Figure 54. Adjusting PWMMIN Changes the Automatic Fan Control Slope
Rev. A | Page 41 of 68
ADT7475
As TRANGE is changed, the slope also changes. As TRANGE
gets smaller, the fans reach 100% speed with a smaller
temperature change.
Table 13. Selecting a TRANGE Value
Bits [7:4]1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PWM DUTY CYCLE
100%
10%
0%
30°C
40°C
45°C
54°C
TMIN
05381-060
TMIN – HYST
Figure 55. Increasing TRANGE Changes the AFC Slope
1
PWM DUTY CYCLE
100%
TRANGE (°C)
2
2.5
3.33
4
5
6.67
8
10
13.33
16
20
26.67
32 (default)
40
53.33
80
Register 0x5F configures Remote 1 TRANGE; Register 0x60 configures Local
TRANGE; Register 0x61 configures Remote 2 TRANGE.
Actual Changes in PWM Output (Advanced
Acoustics Settings)
MAX
PWM
10%
TRANGE
TMIN – HYST
05381-061
0%
Figure 56. Changing PWMMAX Does Not Change the AFC Slope
Selecting TRANGE
The TRANGE value can be selected for each temperature channel:
Remote 1, local, and Remote 2 temperatures. Bits [7:4]
(RANGE) of Register 0x5F to Register 0x61 define the TRANGE
value for each temperature channel.
While the automatic fan control algorithm describes the general
response of the PWM output, the enhance acoustics registers
(0x62 and 0x63) can be used to set/clamp the maximum rate of
change of PWM output for a given temperature zone. This means
if TRANGE is programmed with a steep AFC slope, a relatively small
change in temperature can cause a large change in PWM output
and an audible change in fan speed, which may be noticeable/
annoying to end users. Decreasing the PWM output’s maximum
rate of change, by programming the smoothing on the appropriate temperature channels (Register 0x62 and Register 0x63),
clamps the fan speed’s maximum rate of change in the event of a
temperature spike. Slowly the PWM duty cycle increases, until
the PWM duty cycle reaches the appropriate duty cycle as defined
by the AFC curve.
Figure 57 shows PWM duty cycle versus temperature for each
TRANGE setting. The lower graph shows how each TRANGE setting
affects fan speed vs. temperature. As can be seen from the
graph, the effect on fan speed is nonlinear.
Rev. A | Page 42 of 68
ADT7475
100
2.5°C
90
PWM DUTY CYCLE (%)
6.67°C
8°C
10°C
50
13.3°C
16°C
40
20°C
30
26.6°C
20
10
3.33°C
4°C
5°C
70
6.67°C
8°C
60
10°C
50
13.3°C
16°C
40
20°C
30
32°C
20
40°C
10
26.6°C
32°C
40°C
53.3°C
53.3°C
20
40
60
80
TEMPERATURE ABOVE TMIN
100
120
0
0
80°C
20
2°C
90
4°C
80
FAN SPEED (% OF MAX)
5°C
70
6.67°C
8°C
60
10°C
50
13.3°C
16°C
40
20°C
30
26.6°C
32°C
20
120
80°C
5°C
70
6.67°C
60
8°C
10°C
50
13.3°C
16°C
40
20°C
30
0
0
(B)
26.6°C
32°C
40°C
53.3°C
20
40
60
80
TEMPERATURE ABOVE TMIN
100
120
80°C
(B)
Figure 57. TRANGE vs. Actual Fan Speed (not PWM Drive) Profile
Figure 58. TRANGE and % Fan Speed Slopes with PWMMIN = 20%
The graphs in Figure 57 assume the fan starts from 0% PWM
duty cycle. Clearly, the minimum PWM duty cycle, PWMMIN,
needs to be factored in to see how the loop actually performs
in the system. Figure 58 shows how TRANGE is affected when
the PWMMIN value is set to 20%. It can be seen that the fan
actually runs at about 45% fan speed when the temperature
exceeds TMIN.
Example: Determining TRANGE for Each Temperature
Channel
The following example shows how the different TMIN and TRANGE
settings can be applied to three different thermal zones. In this
example, the following TRANGE values apply:
TRANGE = 80°C for ambient temperature
TRANGE = 53.33°C for CPU temperature
TRANGE = 40°C for VRM temperature
4°C
10
53.3°C
100
3.33°C
20
40°C
10
2.5°C
80
05381-062
FAN SPEED (% OF MAX)
80°C
2°C
90
3.33°C
40
60
80
TEMPERATURE ABOVE TMIN
120
100
2.5°C
20
100
(A)
(A)
100
0
0
40
60
80
TEMPERATURE ABOVE TMIN
05381-063
PWM DUTY CYCLE (%)
5°C
60
2.5°C
80
4°C
70
2°C
90
3.33°C
80
0
0
100
2°C
This example uses the mux configuration described in Step 2:
Configuring the Mux, with the ADT7475 connected as shown
in Figure 48. Both CPU temperature and VRM temperature
drive the CPU fan connected to PWM1. Ambient temperature
drives the front chassis fan and rear chassis fan connected to
PWM2 and PWM3. The front chassis fan is configured to run
at PWMMIN = 20%. The rear chassis fan is configured to run at
PWMMIN = 30%. The CPU fan is configured to run at
PWMMIN = 10%.
Note: The control range for 4-wire fans is much wider than that
for 3-wire fans. In many cases, 4-wire fans can start with a
PWM drive of as little as 20% or less. In extreme cases, some
3-wire fans do not run unless a PWM drive of 60% or more is
applied.
Rev. A | Page 43 of 68
ADT7475
100
The TTHERM limit should be considered the maximum worst-case
VRM TEMPERATURE
90
operating temperature of the system. Because exceeding any
TTHERM limit runs all fans at 100%, it has very negative acoustic
PWM DUTY CYCLE (%)
80
70
effects. Ultimately, this limit should be set up as a fail-safe, and
one should ensure that it is not exceeded under normal system
operating conditions.
CPU TEMPERATURE
60
50
AMBIENT TEMPERATURE
40
Note: TTHERM limits are nonmaskable and affect the fan speed no
30
matter how automatic fan control settings are configured. This
allows some flexibility, because a TRANGE value can be selected
based on its slope, while a hard limit (such as 70°C) can be
programmed as TMAX (the temperature at which the fan reaches
full speed) by setting TTHERM to that limit (for example, 70°C).
20
10
0
0
10
20
30
40
50
60
70
80
90
100
TEMPERATURE ABOVE TMIN
100
THERM Registers
VRM TEMPERATURE
90
Register 0x6A, Remote 1 THERM Temperature Limit = 0x64
(100°C default)
FAN SPEED (% MAX RPM)
80
70
CPU TEMPERATURE
60
Register 0x6B, Local THERM Temperature Limit = 0x64 (100°C
default)
AMBIENT TEMPERATURE
50
Register 0x6C, Remote 2 THERM Temperature Limit = 0x64
(100°C default)
40
30
20
THERM Hysteresis
0
0
10
20
30
40
50
60
70
80
90
100
TEMPERATURE ABOVE TMIN
05381-064
10
Figure 59. TRANGE and % Fan Speed Slopes for VRM, Ambient, and
CPU Temperature Channels
Hysteresis Registers
STEP 7: TTHERM FOR TEMPERATURE CHANNELS
Register 0x6D, Remote 1 and Local Temperature/TMIN
Hysteresis Register
TTHERM is the absolute maximum temperature allowed on a
temperature channel. Above this temperature, a component
such as the CPU or VRM might be operating beyond its safe
operating limit. When the temperature measured exceeds
TTHERM, all fans drive at 100% PWM duty cycle (full speed) to
provide critical system cooling.
Bits [7:4] (HYSR1), Remote 1 temperature hysteresis (4°C
default).
Bits [3:0] (HYSL), local temperature hysteresis (4°C default).
Register 0x6E, Remote 2 Temperature TMIN Hysteresis Register
The fans remain running at 100% until the temperature drops
below TTHERM −hysteresis, where hysteresis is the number
programmed into the hysteresis registers (0x6D and 0x6E).
The default hysteresis value is 4°C.
THERM hysteresis on a particular channel is configured via the
hysteresis settings below (Register 0x6D and Register 0x6E). For
example, setting hysteresis on the Remote 1 channel also sets
the hysteresis on Remote 1 THERM.
Bits [7:4] (HYSR2), Remote 2 temperature hysteresis (4°C
default).
Because each hysteresis setting is four bits, hysteresis values are
programmable from 1°C to 15°C. It is not recommended that
hysteresis values ever be programmed to 0°C, because this disables hysteresis. In effect, this causes the fans to cycle (during a
THERM event) between normal speed and 100% speed, or,
while operating close to TMIN, between normal speed and off,
creating unsettling acoustic noise.
Rev. A | Page 44 of 68
ADT7475
TRANGE
PWM DUTY CYCLE
100%
0%
TTHERM
THERMAL CALIBRATION
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TMIN
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
GENERATOR
MUX
PWM
CONFIG
TRANGE
CPU FAN SINK
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM2
TACH2
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
0%
PWM1
TACH1
TACHOMETER 2
MEASUREMENT
PWM
GENERATOR
TMIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
FRONT CHASSIS
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
05381-065
TMIN
Figure 60. How TTHERM Relates to Automatic Fan Control
STEP 8: THYST FOR TEMPERATURE CHANNELS
THYST is the amount of extra cooling a fan provides after the
temperature measured has dropped back below TMIN before the
fan turns off. The premise for temperature hysteresis (THYST) is
that, without it, the fan would merely chatter, or cycle on and
off regularly, whenever the temperature is hovering at about the
TMIN setting.
The THYST value chosen determines the amount of time needed
for the system to cool down or heat up as the fan is turning on
and off. Values of hysteresis are programmable in the range 1°C
to 15°C. Larger values of THYST prevent the fans from chattering
on and off. The THYST default value is set at 4°C.
In some applications, it is required that fans not turn off below
TMIN, but remain running at PWMMIN. Bits [7:5] of Enhance
Acoustics Register 1 (0x62) allow the fans to be turned off or to
be kept spinning below TMIN. If the fans are always on, the THYST
value has no effect on the fan when the temperature drops
below TMIN.
THERM Hysteresis
Any hysteresis programmed via Register 0x6D and Register
0x6E also applies to hysteresis on the appropriate THERM
channel.
The THYST setting applies not only to the temperature hysteresis
for fan on/off, but the same setting is used for the TTHERM
hysteresis value, described in Step 6: TRANGE for Temperature
Channels. Therefore, programming Register 0x6D and Register
0x6E sets the hysteresis for both fan on/off and the THERM
function.
Rev. A | Page 45 of 68
ADT7475
TRANGE
PWM DUTY CYCLE
100%
0%
TTHERM
THERMAL CALIBRATION
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TMIN
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
GENERATOR
MUX
PWM
CONFIG
TRANGE
CPU FAN SINK
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM2
TACH2
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
0%
PWM1
TACH1
TACHOMETER 2
MEASUREMENT
PWM
GENERATOR
TMIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
FRONT CHASSIS
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
05381-066
TMIN
Figure 61. The THYST Value Applies to Fan On/Off Hysteresis and THERM Hysteresis
Enhance Acoustics Register 1 (0x62)
Bit 1 (SLOW), 1 slows the ramp rate for PWM changes
associated with the Local temperature channel by 4.
Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle
below TMIN − THYST.
Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle
below TMIN − THYST.
Bit 2 (SLOW), 1 slows the ramp rate for PWM changes
associated with the Remote 2 temperature channel by 4.
Bit 7 (ExtraSlow), 1 slows the ramp rate for all fans by a factor
of 39.2%.
The following sections list the ramp-up times when the SLOW
bit is set for each temperature monitoring channel.
Enhanced Acoustics Register 1 (0x62)
Bits [2:0] (ACOU1), selects the ramp rate for PWM outputs
associated with the Remote 1 temperature input.
Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle
below TMIN − THYST.
Configuration Register 6 (0x10)
Bit 0 (SLOW), 1 slows the ramp rate for PWM changes
associated with the Remote 1 temperature channel by 4.
Configuration Register 6 (0x10)
Rev. A | Page 46 of 68
000 = 37.5 sec
001 = 18.8 sec
010 = 12.5 sec
011 = 7.5 sec
100 = 4.7 sec
101 = 3.1 sec
110 = 1.6 sec
111 = 0.8 sec
ADT7475
Enhance Acoustics Register 2 (0x63)
Bits [2:0] (ACOU3), selects the ramp rate for PWM outputs
associated with the local temperature channel.
000 = 37.5 sec
001 = 18.8 sec
010 = 12.5 sec
011 = 7.5 sec
100 = 4.7 sec
101 = 3.1 sec
110 = 1.6 sec
111 = 0.8 sec
Bits [6:4] (ACOU2), selects the ramp rate for PWM outputs
associated with the Remote 2 temperature input.
When Bit 7 of Configuration Register 6 (0x10) = 1, then the
ramp rates change to the values below.
000 = 52.2 sec
001 = 26.1 sec
010 = 17.4 sec
011 = 10.4 sec
100 = 6.5 sec
101 = 4.4 sec
110 = 2.2 sec
111 = 1.1 sec
Setting the appropriate SLOW bits [2:0] of Configuration
Register 6 (0x10) slows the ramp rate further by a factor of 4.
000 = 37.5 sec
001 = 18.8 sec
010 = 12.5 sec
011 = 7.5 sec
100 = 4.7 sec
101 = 3.1 sec
110 = 1.6 sec
111 = 0.8 sec
Rev. A | Page 47 of 68
ADT7475
REGISTER TABLES
Table 14. ADT7475 Registers
Address
R/W
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
0x10
R/W
Configuration
Register 6
ExtraSlow
VccpLow
RES
RES
THERM
SLOW
Remote 2
SLOW
Local
SLOW
Remote 1
0x00
RES
RES
DisTHERMHys
0x00
0x11
R
Configuration
Register 7
RES
RES
RES
RES
in
Manual
RES
0x21
0x22
0x25
R
R
R
9
9
9
8
8
8
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
0x00
0x00
0x80
0x26
R
9
8
7
6
5
4
3
2
0x80
0x27
R
9
8
7
6
5
4
3
2
0x80
0x28
R
7
6
5
4
3
2
1
0
0x00
0x29
R
15
14
13
12
11
10
9
8
0x00
0x2A
R
7
6
5
4
3
2
1
0
0x00
0x2B
R
15
14
13
12
11
10
9
8
0x00
0x2C
R
7
6
5
4
3
2
1
0
0x00
0x2D
R
15
14
13
12
11
10
9
8
0x00
0x2E
R
7
6
5
4
3
2
1
0
0x00
0x2F
R
15
14
13
12
11
10
9
8
0x00
0x30
R/W
7
6
5
4
3
2
1
0
0x00
0x31
R/W
7
6
5
4
3
2
1
0
0x00
0x32
R/W
7
6
5
4
3
2
1
0
0x00
0x38
R/W
7
6
5
4
3
2
1
0
0xFF
0x39
R/W
7
6
5
4
3
2
1
0
0xFF
0x3A
R/W
7
6
5
4
3
2
1
0
0xFF
0x3D
R
7
6
5
4
3
2
1
0
0x75
0x3E
R
7
6
5
4
3
2
1
0
0x41
0x40
R/W
RES
TODIS
FSPDIS
Vx1
FSPD
RDY
LOCK
STRT
0x04
0x41
R
OOL
R2T
LT
R1T
RES
VCC
VCCP
RES
0x00
0x42
R
D2
D1
F4P
FAN3
FAN2
FAN1
OVT
RES
0x00
0x46
0x47
R/W
R/W
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
0x00
0xFF
0x48
0x49
R/W
R/W
VCCP Reading
VCC Reading
Remote 1
Temperature
Local
Temperature
Remote 2
Temperature
TACH1 Low
Byte
TACH1 High
Byte
TACH2 Low
Byte
TACH2 High
Byte
TACH3 Low
Byte
TACH3 High
Byte
TACH4 Low
Byte
TACH4 High
Byte
PWM1 Current
Duty Cycle
PWM2 Current
Duty Cycle
PWM3 Current
Duty Cycle
PWM1 Max
Duty Cycle
PWM2 Max
Duty Cycle
PWM3 Max
Duty Cycle
Device ID
Register
Company ID
Number
Configuration
Register 1
Interrupt
Status
Register 1
Interrupt
Status
Register 2
VCCP Low Limit
VCCP High
Limit
VCC Low Limit
VCC High Limit
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
0x00
0xFF
Rev. A | Page 48 of 68
Lockable
Yes
ADT7475
Address
0x4E
R/W
R/W
0x4F
R/W
0x50
R/W
0x51
R/W
0x52
R/W
0x53
R/W
0x54
R/W
0x55
R/W
0x56
R/W
0x57
R/W
0x58
R/W
0x59
R/W
0x5A
R/W
0x5B
R/W
0x5C
R/W
0x5D
R/W
0x5E
R/W
0x5F
R/W
0x60
R/W
0x61
R/W
0x62
R/W
0x63
R/W
Description
Remote 1
Temp Low
Limit
Remote 1
Temp High
Limit
Local Temp
Low Limit
Local Temp
High Limit
Remote 2
Temp Low
Limit
Remote 2
Temp High
Limit
TACH1
Minimum Low
Byte
TACH1
Minimum
High Byte
TACH2
Minimum Low
Byte
TACH2
Minimum
High Byte
TACH3
Minimum Low
Byte
TACH3
Minimum
High Byte
TACH4
Minimum Low
Byte
TACH4
Minimum
High Byte
PWM1
Configuration
Register
PWM2
Configuration
Register
PWM3
Configuration
Register
Remote 1
TRANGE/PWM1
Frequency
Local
TRANGE/PWM2
Frequency
Remote 2
TRANGE/PWM3
Frequency
Enhance
Acoustics
Register 1
Enhance
Acoustics
Register 2
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
Default
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
BHVR
BHVR
BHVR
INV
RES
SPIN
SPIN
SPIN
0x62
Yes
BHVR
BHVR
BHVR
INV
RES
SPIN
SPIN
SPIN
0x62
Yes
BHVR
BHVR
BHVR
INV
RES
SPIN
SPIN
SPIN
0x62
Yes
RANGE
RANGE
RANGE
RANGE
HF/LF
FREQ
FREQ
FREQ
0xC4
Yes
RANGE
RANGE
RANGE
RANGE
HF/LF
FREQ
FREQ
FREQ
0xC4
Yes
RANGE
RANGE
RANGE
RANGE
HF/LF
FREQ
FREQ
FREQ
0xC4
Yes
MIN3
MIN2
MIN1
SYNC
EN1
ACOU1
ACOU1
ACOU1
0x00
Yes
EN2
ACOU2
ACOU2
ACOU2
EN3
ACOU3
ACOU3
ACOU3
0x00
Yes
Rev. A | Page 49 of 68
Lockable
ADT7475
Address
0x64
R/W
R/W
0x65
R/W
0x66
R/W
0x67
R/W
0x68
R/W
0x69
R/W
0x6A
R/W
0x6B
R/W
0x6C
R/W
0x6D
R/W
0x6E
R/W
0x6F
R/W
0x70
R/W
0x71
R/W
0x72
R/W
0x73
R/W
0x74
R/W
0x75
R/W
0x76
R/W
0x77
R/W
0x78
R/W
0x79
R
0x7A
R/W
0x7B
R/W
Description
PWM1 Min
Duty Cycle
PWM2 Min
Duty Cycle
PWM3 Min
Duty Cycle
Remote 1
Temp TMIN
Local Temp
TMIN
Remote 2
Temp TMIN
Remote 1
THERM Temp
Limit
Local THERM
Temp Limit
Remote 2
THERM Temp
Limit
Remote 1 and
Local
Temp/TMIN
Hysteresis
Remote 2
Temp/TMIN
Hysteresis
XNOR Tree
Test Enable
Remote 1
Temperature
Offset
Local
Temperature
Offset
Remote 2
Temperature
Offset
Configuration
Register 2
Interrupt
Mask Reg. 1
Interrupt
Mask Reg. 2
Extended
Resolution 1
Extended
Resolution 2
Configuration
Register 3
THERM Timer
Status
Register
THERM Timer
Limit Register
TACH Pulses
per
Revolution
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
Default
0x80
Lockable
Yes
7
6
5
4
3
2
1
0
0x80
Yes
7
6
5
4
3
2
1
0
0x80
Yes
7
6
5
4
3
2
1
0
0x5A
Yes
7
6
5
4
3
2
1
0
0x5A
Yes
7
6
5
4
3
2
1
0
0x5A
Yes
7
6
5
4
3
2
1
0
0x64
Yes
7
6
5
4
3
2
1
0
0x64
Yes
7
6
5
4
3
2
1
0
0x64
Yes
HYSR1
HYSR1
HYSR1
HYSR1
HYSL
HYSL
HYSL
HYSL
0x44
Yes
HYSR2
HYSR2
HYSR2
HYSR2
RES
RES
RES
RES
0x40
Yes
RES
RES
RES
RES
RES
RES
RES
XEN
0x00
Yes
7
6
5
4
3
2
1
0
0x00
Yes
7
6
5
4
3
2
1
0
0x00
Yes
7
6
5
4
3
2
1
0
0x00
Yes
SHDN
CONV
ATTN
AVG
RES
RES
RES
RES
0x00
Yes
OOL
R2T
LT
R1T
RES
VCC
VCCP
RES
0x00
D2
D1
F4P
FAN3
FAN2
FAN1
OVT
RES
0x00
RES
RES
VCC
VCC
VCCP
VCCP
RES
RES
0x00
TDM2
TDM2
LTMP
LTMP
TDM1
TDM1
RES
RES
0x00
DC4
DC3
DC2
DC1
FAST
BOOST
THERM
0x00
TMR
TMR
TMR
TMR
TMR
TMR
TMR
ALERT
Enable
ASRT/TMRO
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
0x00
FAN4
FAN4
FAN3
FAN3
FAN2
FAN2
FAN1
FAN1
0x55
Rev. A | Page 50 of 68
0x00
Yes
ADT7475
Address
0x7C
R/W
R/W
Description
Configuration
Register 5
Bit 7
Bit 6
Bit 5
R2
THERM
O/P Only
Local
THERM
O/P Only
R1
THERM
O/P
Only
0x7D
R/W
Configuration
Register 4
RES
RES
BpAtt
VCCP
0x7E
0x7F
R
R
Test Register 1
Test Register 2
Bit 4
RES
Bit 3
GPIOP
Bit 2
GPIOD
RES
Max/Full
on
THERM
THERM
Disable
Bit 1
Bit 0
Temp
Offset
TWOS
COMPL
PIN9
FUNC
PIN9FUNC
DO NOT WRITE TO THESE REGISTERS
DO NOT WRITE TO THESE REGISTERS
Default
0x01
Lockable
Yes
0x00
Yes
0x00
0x00
Yes
Yes
Table 15. Register 0x11—Configuration Register 7 (Power-On Default = 0x00)
Bit
[0]
Name
DisTHERMHys
R/W
R/W
Description
Setting this bit to 1 disables THERM hysteresis.
[7:1]
Reserved
N/A
Reserved. Do not write to these bits.
Table 16. Register 0x10—Configuration Register 6 (Power-On Default = 0x00)1, 2
Bit
[0]
Name
SLOW Remote 1
R/W
R/W
[1]
SLOW Local
R/W
[2]
SLOW Remote 3
R/W
[3]
THERM in Manual
R/W
[5:4]
[6]
Reserved
VCCPLow
N/A
R/W
[7]
1
2
ExtraSlow
Description
When this bit is set, Fan 1 smoothing times are multiplied ×4 for Remote 1
temperature channel (as defined in Register 0x62).
When this bit is set, Fan 2 smoothing times are multiplied ×4 for local temperature
channel (as defined in Register 0x63).
When this bit is set, Fan 3 smoothing times are multiplied ×4 for Remote 2
temperature channel (as defined in Register 0x63).
When this bit is set, THERM is enabled in manual mode.1
Reserved. Do not write to these bits.
VCCPLO = 1. When the power is supplied from 3.3 V STANDBY and the core voltage
(VCCP) drops below its VCCP low limit value (Register 0x46), the following occurs:
•
Bit 1 in Interrupt Status Register 1 is set.
•
SMBALERT is generated, if enabled.
•
PROCHOT monitoring is disabled.
•
•
Everything is re-enabled once VCCP increases above the VCCP low limit.
When VCCP increases above the low limit:
•
PROCHOT monitoring is enabled.
•
Fans return to their programmed state after a spin-up cycle.
When this bit is set, all fan smoothing times are increased by a further 39.2%.
R/W
A THERM event always overrides any fan setting (even when fans are disabled).
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 17. Register 0x11—Configuration Register 7 (Power-On Default = 0x00)1
Bit
[0]
Name
DisTHERMHys
R/W
R/W
Description
Setting this bit to 1 disables THERM hysteresis.
[7:1]
Reserved
N/A
Reserved. Do not write to these bits
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 18. Voltage Reading Registers (Power-On Default = 0x00)1, 2
Register Address
0x21
0x22
R/W
Read-only
Read-only
Description
Reflects the voltage measurement at the VCCP input on Pin 14 (8 MSBs of reading).1
Reflects the voltage measurement at the VCC input on Pin 3 (8 MSBs of reading).2
1
If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended
resolution registers have been read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen.
2
VCC (Pin 3) is the supply voltage for the ADT7475.
Rev. A | Page 51 of 68
ADT7475
Table 19. Temperature Reading Registers (Power-On Default = 0x80)1, 2
Register Address
0x25
0x26
0x27
R/W
Read-only
Read-only
Read-only
Description
Remote 1 temperature reading (8 MSBs of reading).3, 4
Local temperature reading (8 MSBs of reading).
Remote 2 temperature reading (8 MSBs of reading).
1
These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C).
If the extended resolution bits of these readings are also being read, the extended resolution registers (0x76 and 0x77) must be read first. Once the extended
resolution registers have been read, all associated MSB reading registers get frozen until read. Both the extended resolution registers and the MSB registers are frozen.
3
In twos complement mode, a temperature reading of −128°C (0x80) indicates a diode fault (open or short) on that channel.
2
4
In Offset 64 mode, a temperature reading of −64°C (0x00) indicates a diode fault (open or short) on that channel.
Table 20. Fan Tachometer Reading Registers (Power-On Default = 0x00)1
Register Address
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
R/W
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Description
TACH1 low byte.
TACH1 high byte.
TACH2 low byte.
TACH2 high byte.
TACH3 low byte.
TACH3 high byte.
TACH4 low byte.
TACH4 high byte.
1
These registers count the number of 11.11 µs periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2).
The number of TACH pulses used to count can be changed using the TACH pulses per revolution register (0x7B). This allows the fan speed to be accurately measured.
Because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. Both the low and high bytes are then frozen until read. At
power-on, these registers contain 0x0000 until such time as the first valid fan TACH measurement is read into these registers. This prevents false interrupts from
occurring while the fans are spinning up.
A count of 0xFFFF indicates that a fan is one of the following:
Stalled or blocked (object jamming the fan).
Failed (internal circuitry destroyed).
Not populated. (The ADT7475 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should be
set to 0xFFFF.)
Alternate function, for example, TACH4 reconfigured as a THERM pin.
Table 21. Current PWM Duty Cycle Registers (Power-On Default = 0x00)1
Register Address
0x30
0x31
0x32
1
R/W
R/W
R/W
R/W
Description
PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7475 reports the PWM duty cycles
back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers
report back 0x00. In software mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.
Table 22. Maximim PWM Duty Cycle Registers (Power-On Default = 0xFF)1, 2
Register Address
0x38
0x39
0x3A
1
2
R/W
R/W
R/W
R/W
Description
Maximum duty cycle for PWM1 output, default = 100% (0xFF).
Maximum duty cycle for PWM2 output, default = 100% (0xFF).
Maximum duty cycle for PWM3 output, default = 100% (0xFF).
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
These registers set the maximum PWM duty cycle of the PWM output.
Rev. A | Page 52 of 68
ADT7475
Table 23. Register 0x40—Configuration Register 1 (Power-On Default = 0x04)
Bit
[0]
Name
STRT1, 2
R/W
R/W
[1]
LOCK
Write once
[2]
RDY
Read-only
[3]
FSPD
R/W
[4]
Vx1
R/W
[5]
FSPDIS
R/W
[6]
TODIS
R/W
[7]
RES
1
2
Description
Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.
Logic 0 disables monitoring and PWM control based on the default power-up limit settings.
Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the default
settings are enabled. This bit does not become locked once Bit 1 (LOCK) has been set.
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become readonly and cannot be modified until the ADT7475 is powered down and powered up again. This prevents
rogue programs such as viruses from modifying critical system limit settings. This bit is lockable.
This bit is set to 1 by the ADT7475 to indicate only that the device is fully powered up and ready to begin
system monitoring.
When set to 1, this bit runs all fans at max speed as programmed in the PWM current duty cycle registers
(0x30 to 0x32). Power-on default = 0. This bit is not locked at any time.
BIOS should set this bit to a 1 when the ADT7475 is configured to measure current from an ADI ADOPT®
VRM controller and to measure the CPU’s core voltage. This bit allows monitoring software to display CPU
watts usage. This bit is lockable.
Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan spinup timeout selected.
When this bit is set to 1, the SMBus timeout feature is enabled. This allows the ADT7475 to be used with
SMBus controllers that cannot handle SMBus timeouts. This bit is lockable.
Reserved.
Bit 0 (STRT) of Configuration Register 1 (0x40) remains writable after lock bit is set.
When monitoring is disabled, PWM outputs always go to 100% for thermal protection.
Table 24. Register 0x41—Interrupt Status Register 1 (Power-On Default = 0x00)
Bit
[1]
Name
VCCP
R/W
Read-only
[2]
VCC
Read-only
[4]
R1T
Read-only
[5]
LT
Read-only
[6]
R2T
Read-only
[7]
OOL
Read-only
Description
VCCP = 1 indicates that the VCCP high or low limit has been exceeded. This bit is cleared on a read of the status
register only if the error condition has subsided.
VCC = 1 indicates that the VCC high or low limit has been exceeded. This bit is cleared on a read of the status
register only if the error condition has subsided.
R1T = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared on a read
of the status register only if the error condition has subsided.
LT = 1 indicates that the local low or high temperature has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided.
R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared on a read
of the status register only if the error condition has subsided.
OOL = 1 indicates that an out-of-limit event has been latched in Interrupt Status Register 2. This bit is a logical
OR of all status bits in Interrupt Status Register 2. Software can test this bit in isolation to determine whether
any of the voltage, temperature, or fan speed readings represented by Interrupt Status Register 2 are out-oflimit, which saves the need to read Interrupt Status Register 2 every interrupt or polling cycle.
Rev. A | Page 53 of 68
ADT7475
Table 25. Register 0x42—Interrupt Status Register 2 (Power-On Default = 0x00)
Bit
[1]
Name
OVT
R/W
Read-only
[2]
FAN1
Read-only
[3]
FAN2
Read-only
[4]
FAN3
Read-only
[5]
F4P
Read-only
R/W
Read-only
[6]
[7]
D1
D2
Read-only
Read-only
Description
OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared on a
read of the status register when the temperature drops below THERM – THYST.
FAN1 = 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is not set when the
PWM1 output is off.
FAN2 = 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is not set when the
PWM2 output is off.
FAN3 = 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is not set when the
PWM3 output is off.
F4P = 1 indicates that Fan 4 has dropped below minimum speed or has stalled. This bit is not set when the
PWM3 output is off.
When Pin 9 is programmed as a GPIO output, writing to this bit determines the logic output of the GPIO.
If Pin 9 is configured as the THERM timer input for THERM monitoring, then this bit is set when the THERM
assertion time exceeds the limit programmed in the THERM timer limit register (0x7A).
D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs.
D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
Table 26. Voltage Limit Registers 1
1
Register Address
0x46
0x47
0x48
0x49
1
2
R/W
R/W
R/W
R/W
R/W
Description2
VCCP low limit.
VCCP high limit.
VCC low limit.
VCC high limit.
Power-On Default
0x00
0xFF
0x00
0xFF
Setting the Configuration Register 1 lock bit has no effect on these registers.
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its
low limit (≤ comparison).
Table 27. Temperature Limit Registers1
Register Address
0x4E
0x4F
0x50
0x51
0x52
0x53
1
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description2
Remote 1 temperature low limit.
Remote 1 temperature high limit.
Local temperature low limit.
Local temperature high limit.
Remote 2 temperature low limit.
Remote 2 temperature high limit.
Power-On Default
0x81
0x7F
0x81
0x7F
0x81
0x7F
Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock
bit has no effect on these registers.
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its
low limit (≤ comparison).
Table 28. Fan Tachometer Limit Registers1
Register Address
0x54
0x55
R/W
R/W
R/W
0x56
0x57
0x58
0x59
0x5A
0x5B
R/W
R/W
R/W
R/W
R/W
R/W
1
Description
TACH1 minimum low byte.
TACH1 minimum high byte/single channel ADC
channel select.
TACH2 minimum low byte.
TACH2 minimum high byte.
TACH3 minimum low byte.
TACH3 minimum high byte.
TACH4 minimum low byte.
TACH4 minimum high byte.
Power-On Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2
to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.
Rev. A | Page 54 of 68
ADT7475
Table 29. Register 0x55—TACH1 Minimum High Byte (Power-On Default = 0xFF)
Bits
[4:0]
Name
Reserved
R/W
Read-only
[7:5]
SCADC
R/W
Description
These bits are reserved when Bit 6 of Configuration Register 2 (0x73) is set (single channel ADC mode).
Otherwise, these bits represent Bits [4:0] of the TACH1 minimum high byte register.
When Bit 6 of Configuration Register 2 (0x73) is set (single channel ADC mode), these bits are used to
select the only channel from which the ADC makes measurements. Otherwise, these bits represent Bits
[7:5] of the TACH1 minimum high byte register.
Table 30. PWM Configuration Registers1
R/W1
R/W
R/W
R/W
Register Address
0x5C
0x5D
0x5E
1
Description
PWM1 configuration.
PWM2 configuration.
PWM3 configuration.
Power-On Default
0x62
0x62
0x62
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 31. Register 0x5C, Register 0x5D, and Register 0x5E—PWM Configuration Registers (Power-On Default = 0x62)
Bit
[2:0]
Name
SPIN
R/W
R/W
[4]
INV
R/W
[7:5]
BHVR
R/W
Description
These bits control the startup timeout for PWMx. The PWM output stays high until two valid TACH
rising edges are seen from the fan. If there is not a valid TACH signal during the fan TACH
measurement directly after the fan startup timeout period, then the TACH measurement reads 0xFFFF
and Interrupt Status Register 2 reflects the fan fault. If the TACH minimum high and low bytes contain
0xFFFF or 0x0000, then the Interrupt Status Register 2 bit is not set, even if the fan has not started.
000 = No startup timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for 100%
duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle corresponds to a logic low
output.
These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 temperature controls PWMx (automatic fan control mode).
001 = Local temperature controls PWMx (automatic fan control mode).
010 = Remote 2 temperature controls PWMx (automatic fan control mode).
011 = PWMx runs full speed.
100 = PWMx disabled (default).
101 = Fastest speed calculated by local and Remote 2 temperature controls PWMx.
110 = Fastest speed calculated by all three temperature channel controls PWMx.
111 = Manual Mode. PWM duty cycle registers (0x30 to 0x32) become writable.
Rev. A | Page 55 of 68
ADT7475
Table 32. Temp TRANGE/PWM Frequency Registers
R/W1
R/W
R/W
R/W
Register Address
0x5F
0x60
0x61
1
Description
Remote 1 TRANGE/PWM1 frequency.
Local temperature TRANGE/PWM2 frequency.
Remote 2 TRANGE/PWM3 frequency.
Power-On Default
0xC4
0xC4
0xC4
These registers become read-only when the Configuration Register 1 lock bit is set. Any subsequent attempts to write to these registers fail.
Table 33. Register 0x5F, Register 0x60, and Register 0x61—Temp TRANGE/PWM Frequency Registers (Power-On Default = 0xC4)
Bit
[2:0]
Name
FREQ
R/W
R/W
[3]
HF/LF
R/W
[7:4]
RANGE
R/W
Description
These bits control the PWMx frequency.
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
HF/LF =1, enables high frequency PWM output for 4-wire fans. Once enabled, 3-wire fan-specific settings have no
effect (this means, pulse stretching).
These bits determine the PWM duty cycle vs. the temperature slope for automatic fan control.
0000 = 2°C
0001 = 2.5°C
0010 = 3.33°C
0011 = 4°C
0100 = 5°C
0101 = 6.67°C
0110 = 8°C
0111 = 10°C
1000 = 13.33°C
1001 = 16°C
1010 = 20°C
1011 = 26.67°C
1100 = 32°C (default)
1101 = 40°C
1110 = 53.33°C
1111 = 80°C
Rev. A | Page 56 of 68
ADT7475
Table 34. Register 0x62—Enhance Acoustics Register 1 (Power-On Default = 0x00)
Bit
[2:0]
Name
ACOU1
R/W1
R/W
[3]
[4]
EN1
SYNC
R/W
R/W
[5]
MIN1
R/W
[6]
MIN2
R/W
[7]
MIN3
R/W
1
Description
Assuming that PWMx is associated with the Remote 1 temperature channel, these bits define the maximum
rate of change of the PWMx output for Remote 1 temperature related changes. Instead of the fan speed
jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by
these bits. This feature ultimately enhances the acoustics of the fan.
When Bit 7 of Configuration Register 6 (0x10) is 0
Time Slot Increase
Time for 0% to 100%
000 = 1
37.5 sec
001 = 2
18.8 sec
010 = 3
12.5 sec
011 = 4
7.5 sec
100 = 8
4.7 sec
101 = 12
3.1 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When Bit 7 of Configuration Register 6 (0x10) is 1
Time Slot Increase
Time for 0% to 100%
000 = 1
52.2 sec
001 = 2
26.1 sec
010 = 3
17.4 sec
011 = 4
10.4 sec
100 = 8
6.5 sec
101 = 12
4.4 sec
110 = 24
2.2 sec
111 = 48
1.1 sec
When this bit is 1, smoothing is enabled on Remote 1 temperature channel.
SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to
three fans to be driven from PWM3 output and their speeds to be measured.
SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output.
When the ADT7475 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle)
or at PWM1 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value.
0 = 0% duty cycle below TMIN – hysteresis.
1 = PWM1 minimum duty cycle below TMIN – hysteresis.
When the ADT7475 is in automatic fan speed control mode, this bit defines whether PWM2 is off (0% duty
cycle) or at PWM2 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis
value.
0 = 0% duty cycle below TMIN – hysteresis.
1 = PWM 2 minimum duty cycle below TMIN – hysteresis.
When the ADT7475 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty
cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis
value.
0 = 0% duty cycle below TMIN – hysteresis.
1 = PWM3 minimum duty cycle below TMIN – hysteresis.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Rev. A | Page 57 of 68
ADT7475
Table 35. Register 0x63—Enhance Acoustics Register 2 (Power-On Default = 0x00)
Bit
[2:0]
Name
ACOU3
R/W1
R/W
[3]
[6:4]
EN3
ACOU2
R/W
R/W
[7]
EN2
R/W
1
Description
Assuming that PWMx is associated with the local temperature channel, these bits define the maximum
rate of change of the PWMx output for local temperature related changes. Instead of the fan speed
jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by
these bits. This feature ultimately y enhances the acoustics of the fan.
When Bit 7 of Configuration Register 6 (0x10) is 0
Time Slot Increase
Time for 0% to 100%
000 = 1
37.5 sec
001 = 2
18.8 sec
010 = 3
12.5 sec
011 = 4
7.5 sec
100 = 8
4.7 sec
101 = 12
3.1 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When Bit 7 of Configuration Register 6 (0x10) is 1
Time Slot Increase
Time for 0% to 100%
000 = 1
52.2 sec
001 = 2
26.1 sec
010 = 3
17.4 sec
011 = 4
10.4 sec
100 = 8
6.5 sec
101 = 12
4.4 sec
110 = 24
2.2 sec
111 = 48
1.1 sec
When this bit is 1, smoothing is enabled on the Local temperature channel.
Assuming that PWMx is associated with the Remote 2 temperature channel, these bits define the
maximum rate of change of the PWMx output for Remote 2 temperature related changes. Instead of
the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate
determined by these bits. This feature ultimately enhances the acoustics of the fan.
When Bit 7 of Configuration Register 6 (0x10) is 0
Time Slot Increase
Time for 0% to 100%
000 = 1
37.5 sec
001 = 2
18.8 sec
010 = 3
12.5 sec
011 = 4
7.5 sec
100 = 8
4.7 sec
101 = 12
3.1 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When Bit 7 of Configuration Register 6 (0x10) is 1
Time Slot Increase
Time for 0% to 100%
000 = 1
52.2 sec
001 = 2
26.1 sec
010 = 3
17.4 sec
011 = 4
10.4 sec
100 = 8
6.5 sec
101 = 12
4.4 sec
110 = 24
2.2 sec
111 = 48
1.1 sec
When this bit is 1, smoothing is enabled on the Remote 2 temperature channel.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Rev. A | Page 58 of 68
ADT7475
Table 36. PWM Minimum Duty Cycle Registers
R/W1
R/W
R/W
R/W
Register Address
0x64
0x65
0x66
1
Description
PWM1 minimum duty cycle.
PWM2 minimum duty cycle.
PWM3 minimum duty cycle.
Power-On Default
0x80 (50% duty cycle)
0x80 (50% duty cycle)
0x80 (50% duty cycle)
These registers become read-only when the ADT7475 is in automatic fan control mode.
Table 37. Register 0x64, Register 0x65, Register 0x66—PWM Minimum Duty Cycle Registers (Power-On Default = 0x80; 50% duty cycle)
Bit
[7:0]
1
Name
PWM duty cycle
R/W1
R/W
Description
These bits define the PWMMIN duty cycle for PWMx.
0x00 = 0% duty cycle (fan off ).
0x40 = 25% duty cycle.
0x80 = 50% duty cycle.
0xFF = 100% duty cycle (fan full speed).
These registers become read-only when the ADT7475 is in automatic fan control mode.
Table 38. TMIN Registers1
Register Address
0x67
0x68
0x69
R/W2
R/W
R/W
R/W
Description
Remote 1 temperature TMIN.
Local temperature TMIN.
Remote 2 temperature TMIN.
Power-On Default
0x5A (90°C)
0x5A (90°C)
0x5A (90°C)
1
These are the TMIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan runs at minimum speed and increases
with temperature according to TRANGE.
2
These registers become read-only when the Configuration Register 1 lock bit is set. Any subsequent attempts to write to these registers fail.
Table 39. THERM Temperature Limit Registers1
R/W2
R/W
Description
Remote 1 THERM limit.
Power-On Default
0x64 (100°C)
0x6B
R/W
Local THERM limit.
0x64 (100°C)
0x6C
R/W
Remote 2 THERM limit.
0x64 (100°C)
Register Address
0x6A
If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the
system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is
disabled. The PWM output remains at 100% until the temperature drops below a THERM Limit − Hysteresis. If the THERM pin is programmed as an output, then
exceeding these limits by 0.25°C can cause the THERM pin to assert low as an output.
2
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
1
Table 40. Temperature/TMIN Hysteresis Registers1
Register Address
0x6D
Bit Name
R/W2
R/W
HYSL [3:0]
HYSR1 [7:4]
0x6E
R/W
HYSR2 [7:4]
Description
Remote 1 and local temperature hysteresis.
Local temperature hysteresis. 0°C to 15°C of
hysteresis can be applied to the local
temperature and AFC loops.
Remote 1 temperature hysteresis. 0°C to
15°C of hysteresis can be applied to the
Remote 1 temperature and AFC loops.
Remote 2 temperature hysteresis.
Local temperature hysteresis. 0°C to 15°C of
hysteresis can be applied to the local
temperature and AFC loops.
1
Power-On Default
0x44
0x40
Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its
TMIN value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN − hysteresis. Up to 15°C of hysteresis can be assigned to any temperature
channel. The hysteresis value chosen also applies to that temperature channel, if its THERM limit is exceeded. The PWM output being controlled goes to 100%, if the
THERM limit is exceeded and remains at 100% until the temperature drops below THERM − hysteresis. For acoustic reasons, it is recommended that the hysteresis
value not be programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to TMIN.
2
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Rev. A | Page 59 of 68
ADT7475
Table 41. XNOR Tree Test Enable Register
Register Address
0x6F
R/W1
R/W
Bit Name
XEN [0]
RES [7:1]
1
Description
XNOR tree test enable register.
If the XEN bit is set to 1, the device enters
the XNOR tree test mode. Clearing the bit
removes the device from the XNOR tree test
mode.
Unused. Do not write to these bits.
Power-On Default
0x00
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 42. Remote 1 Temperature Offset Register
Register Address
0x70
1
R/W1
R/W
Bit
[7:0]
Description
Remote 1 temperature offset.
Allows a twos complement offset value to
be automatically added to or subtracted
from the Remote 1 temperature reading.
This is to compensate for any inherent
system offsets such as PCB trace resistance.
LSB value = 0.5°C.
Power-On Default
0x00
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 43. Local Temperature Offset Register
Register Address
0x71
1
Bit
[7:0]
R/W1
R/W
Description
Local temperature offset.
Allows a twos complement offset value to be
automatically added to or subtracted from the local
temperature reading. LSB value = 0.5°C.
Power-On Default
0x00
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 44. Remote 2 Temperature Offset Register1
Register Address
0x72
1
Bit
[7:0]
R/W
R/W
Description
Remote 2 temperature offset.
Allows a twos complement offset value to be
automatically added to or subtracted from the
Remote 2 temperature reading. This is to
compensate for any inherent system offsets
such as PCB trace resistance. LSB value = 0.5°C.
Power-On Default
0x00
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Rev. A | Page 60 of 68
ADT7475
Table 45. Register 0x73—Configuration Register 2 (Power-On Default = 0x00)
R/W1
Bit
[0:3]
[4]
Name
RES
AVG
R/W
[5]
ATTN
R/W
[6]
CONV
R/W
[7]
SHDN
R/W
1
Description
Reserved.
AVG = 1, averaging on the temperature and voltage measurements is turned off.
This allows measurements on each channel to be made much faster.
ATTN = 1, the ADT7475 removes the attenuators from the VCCP input. The VCCP input
can be used for other functions such as connecting up external sensors.
CONV = 1, the ADT7475 is put into a single channel ADC conversion mode. In this
mode, the ADT7475 can be made to read continuously from one input only, for
example, Remote 1 temperature. The appropriate ADC channel is selected by
writing to Bits [7:5] of TACH1 minimum high byte register (0x55).
Register 0x55, Bits [7:5]
000
Reserved
001
VCCP
010
VCC (3.3 V)
011
Reserved
100
Reserved
101
Remote 1 temperature
110
Local temperature
111
Remote 2 temperature
SHDN = 1, ADT7475 goes into shutdown mode. All PWM outputs assert low (or
high depending on state of INV bit) to switch off all fans. The PWM current duty
cycle registers read 0x00 to indicate that the fans are not being driven.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 46. Register 0x74—Interrupt Mask Register 1 (Power-On Default <7:0> = 0x00)
Bit
[1]
Name
VCCP
R/W
R/W
Description
VCCP = 1, masks SMBALERT for out-of-limit conditions on the VCCP channel.
[2]
VCC
R/W
VCC = 1, masks SMBALERT for out-of-limit conditions on the VCC channel.
[4]
R1T
R/W
R1T = 1, masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.
[5]
LT
R/W
LT = 1, masks SMBALERT for out-of-limit conditions on the local temperature channel.
[6]
R2T
R/W
R2T = 1, masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.
[7]
OOL
R/W
OOL = 0, then when one or more alerts are generated in Interrupt Status Register 2, assuming all the
mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT are still asserted.
OOL = 1, then when one or more alerts are generated in Interrupt Status Register 2, assuming all the
mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT are not asserted.
Table 47. Register 0x75—Interrupt Mask Register 2 (Power-On Default <7:0> = 0x00)
Bit
[1]
Name
OVT
R/W
Read only
OVT = 1, masks SMBALERT for overtemperature THERM conditions.
Description
[2]
FAN1
R/W
FAN1 = 1, masks SMBALERT for a Fan 1 fault.
[3]
FAN2
R/W
FAN2 = 1, masks SMBALERT for a Fan 2 fault.
[4]
FAN3
R/W
FAN3 = 1, masks SMBALERT for a Fan 3 fault.
[5]
F4P
R/W
F4P = 1, masks SMBALERT for a Fan 4 fault. If the TACH4 pin is being used as the THERM input,
this bit masks SMBALERT for a THERM timer event.
[6]
D1
R/W
D1 = 1, masks SMBALERT for a diode open or short on a Remote 1 channel.
[7]
D2
R/W
D2 = 1, masks SMBALERT for a diode open or short on a Remote 2 channel.
Rev. A | Page 61 of 68
ADT7475
Table 48. Register 0x76—Extended Resolution Register 11
Bit
[3:2]
[5:4]
1
Name
VCCP
VCC
R/W
Read-only
Read-only
Description
VCCP LSBs. Holds the 2 LSBs of the 10-bit VCCP measurement.
VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement.
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 49. Register 0x77—Extended Resolution Register 21
Bit
[3:2]
[5:4]
[7:6]
1
Name
TDM1
LTMP
TDM2
R/W
Read-only
Read-only
Read-only
11
Description
Remote 1 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement.
Local temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement.
Remote 2 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement.
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 50. Register 0x78—Configuration Register 3 (Power-On Default = 0x00)
Bit
[0]
Name
ALERT
R/W1
R/W
[1]
THERM
R/W
[2]
BOOST
R/W
[3]
FAST
R/W
[4]
DC1
R/W
[5]
DC2
R/W
[6]
DC3
R/W
[7]
DC4
R/W
1
Description
ALERT = 1, Pin 10 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate
out-of-limit error conditions.
THERM Enable = 1 enables THERM timer monitoring functionality on Pin 9. Also determined by Bits
0 and 1 (PIN9FUNC) of Configuration Register 4. When THERM is asserted, if the fans are running
and the boost bit is set, the fans run at full speed. Alternatively, THERM can be programmed so that
a timer is triggered to time how long THERM has been asserted.
When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum
programmed duty cycle for fail-safe cooling.
FAST = 1, enables fast TACH measurements on all channels. This increases the TACH measurement
rate from once per second to once every 250 ms (4×).
DC1 = 1, enables TACH measurements to be continuously made on TACH1. Fans must be driven
by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
DC2 = 1, enables TACH measurements to be continuously made on TACH2. Fans must be driven
by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
DC3 = 1, enables TACH measurements to be continuously made on TACH3. Fans must be driven
by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
DC4 = 1, enables TACH measurements to be continuously made on TACH4. Fans must be driven
by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 51. Register 0x79—THERM Timer Status Register (Power-On Default = 0x00)
Bit
[7:1]
Name
TMR
R/W
Read-only
[0]
ASRT/
TMR0
Read-only
Description
Times how long THERM input is asserted. These seven bits read zero until the THERM assertion time
exceeds 45.52 ms.
This bit is set high on the assertion of the THERM input, and is cleared on read. If the THERM
assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading.
This allows THERM assertion times from 45.52 ms to 5.82 sec to be reported back with a resolution
of 22.76 ms.
Table 52. Register 0x7A—THERM Timer Limit Register (Power-On Default = 0x00)
Bit
[7:0]
Name
LIMT
R/W
R/W
Description
Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8-bit
limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 sec to be
programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status
Register 2 (0x42) is set. If the limit value is 0x00, then an interrupt is generated immediately on the
assertion of the THERM input.
Rev. A | Page 62 of 68
ADT7475
Table 53. Register 0x7B—TACH Pulses per Revolution Register (Power-On Default = 0x55)
Bit
[1:0]
Name
FAN1
R/W
R/W
[3:2]
FAN2
R/W
[5:4]
FAN3
R/W
[7:6]
FAN4
R/W
Description
Sets number of pulses to be counted when measuring Fan 1 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Sets number of pulses to be counted when measuring Fan 2 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Sets number of pulses to be counted when measuring Fan 3 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Sets number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Table 54. Register 0x7C—Configuration Register 5 (Power-On Default = 0x00)
Bit
[0]
Name
TWOS
COMPL
[1]
TempOffset
[2]
GPIOD
[3]
GPIOP
[4]
[5]
RES
R1 THERM
R/W1
R/W
R/W
Description
Twos complement = 1, sets the temperature range to twos complement temperature range.
Twos complement = 0, changes the temperature range to Offset 64. When this bit is changed, the
ADT7475 interprets all relevant temperature register values as defined by this bit.
TempOffset = 0, sets offset range to −63°C to +64°C with 0.5°C resolution.
TempOffset = 1, sets offset range to −63°C to +127°C with 1°C resolution.
These settings apply to registers 0x70, 0x71, and 0x72 (Remote 1, internal, and Remote 2 temperature
offset registers.
GPIO direction. When GPIO function is enabled, this determines whether the GPIO is an input (0) or an
output (1).
GPIO polarity. When the GPIO function is enabled and is programmed as an output, this bit
determines whether the GPIO is active low (0) or high (1).
Reserved.
R1 THERM = 0 , THERM temperature limit functionality enabled for Remote 1 temperature channel.
THERM can also be disabled on any channel by the following:
In offset 64 mode, writing −64°C to the appropriate THERM temperature limit.
In twos complement mode, writing −128°C to the appropriate THERM temperature limit.
Rev. A | Page 63 of 68
ADT7475
Bit
[6]
Name
Local
THERM
R/W1
R/W
Description
Local THERM = 0, THERM temperature limit functionality enabled for local temperature channel.
THERM can also be disabled on any channel by the following:
In Offset 64 mode, writing −64°C to the appropriate THERM temperature limit.
In twos complement mode, writing −128°C to the appropriate THERM temperature limit.
[7]
R2 THERM
R/W
R2 THERM = 0, THERM temperature limit functionality enabled for Remote 2 temperature channel.
THERM can also be disabled on any channel by the following:
In offset 64 mode, writing −64˚C to the appropriate THERM temperature limit.
In twos complement mode, writing −128˚C to the appropriate THERM temperature limit.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 55. Register 0x7D—Configuration Register 4 (Power-On Default = 0x00)
Bit
[1:0]
Name
Pin9FUNC
R/W1
R/W
[2]
THERM
Disable
R/W
[3]
Max/Full
on THERM
R/W
[4:7]
[5]
RES
BpAttVCCP
[6:7]
RES
1
R/W
Description
These bits set the functionality of Pin 9:
00 = TACH4 (default)
01 = Bidirectional THERM
10 = SMBALERT
11 = GPIO
THERM Disable = 0, THERM overtemperature output is enabled assuming THERM is correctly
configured (Register 0x78, Register 0x7C, and Register 0x7D).
THERM Disable = 1, THERM overtemperature output is disabled on all channels.
THERM can also be disabled on any channel by the following:
In Offset 64 mode, writing −64°C to the appropriate THERM temperature limit
In twos complement mode, writing −128°C to the appropriate THERM temperature limit
Max/Full on THERM = 0. When THERM limit is exceeded, fans go to full speed.
Max/Full on THERM = 1. When THERM limit is exceeded, fans go to maximum speed as defined in
Register 0x38, Register 0x39, and Register 0x3A.
Unused.
Bypass VCCP attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to
2.2965 V (0xFF) .
Unused.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 56. Register 0x7E—Manufacturer’s Test Register 1 (Power-On Default = 0x00)
Bit
[7:0]
Name
Reserved
R/W
Read-only
Description
Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not
be written to under normal operation.
Table 57. Register 0x7F—Manufacturer’s Test Register 2 (Power-On Default = 0x00)
Bit
[7:0]
Name
Reserved
R/W
Read-only
Description
Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not
be written to under normal operation.
Rev. A | Page 64 of 68
ADT7475
OUTLINE DIMENSIONS
0.197
0.193
0.189
9
16
0.158
0.154
0.150
1
8
0.244
0.236
0.228
PIN 1
0.069
0.053
0.065
0.049
0.010
0.025
0.004
BSC
COPLANARITY
0.004
0.012
0.008
SEATING
PLANE
0.010
0.006
8°
0°
0.050
0.016
COMPLIANT TO JEDEC STANDARDS MO-137-AB
Figure 62. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
ORDERING GUIDE
Model
ADT7475ARQZ1
ADT7475ARQZ-REEL1
ADT7475ARQZ-REEL71
EVAL-ADT7475EB
1
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
Evaluation Board
Z = Pb-free part.
Rev. A | Page 65 of 68
Package Option
RQ-16
RQ-16
RQ-16
ADT7475
NOTES
Rev. A | Page 66 of 68
ADT7475
NOTES
Rev. A | Page 67 of 68
ADT7475
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05381-0-2/06(A)
Rev. A | Page 68 of 68
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