IDT IDT70T631S10DDI High-speed 2.5v 512/256k x 18 asynchronous dual-port static ram with 3.3v 0r 2.5v interface Datasheet

HIGH-SPEED 2.5V
512/256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
Features
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Full hardware support of semaphore signaling between
ports on-chip
On-chip port arbitration logic
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Sleep Mode Inputs on both ports
Supports JTAG features compliant to IEEE 1149.1 in
BGA-208 and BGA-256 packages
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 256-ball Ball Grid Array, 144-pin Thin Quad
Flatpack and 208-ball fine pitch Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 8/10/12/15ns (max.)
– Industrial: 10/12ns (max.)
RapidWrite Mode simplifies high-speed consecutive write
cycles
Dual chip enables allow for depth expansion without
external logic
IDT70T633/1 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
PRELIMINARY
IDT70T633/1S
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◆
◆
◆
◆
◆
◆
◆
◆
Functional Block Diagram
UBL
UB R
LBL
LB R
R/W L
R/WR
B
E
0
L
CE0L
B
E
1
R
B
E
1
L
B
E
0
R
CE0R
CE1R
CE1L
OER
OEL
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
512/256K x 18
MEMORY
ARRAY
Din_L
I/O0L - I/O17L
A18L(1)
A 0L
Address
Decoder
Din_R
ADDR_L
I/O0R - I/O17R
A18R (1)
Address
Decoder
ADDR_R
A0R
TDI
OEL
CE0L
CE1L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
R/WL
OER
TDO
JTAG
TCK
TMS
TRST
CE0R
CE1R
R/WR
BUSYL(2,3)
BUSYR(2,3)
M/S
SEM L
SEM R
INTL(3)
INTR(3)
(4)
ZZL
ZZ
CONTROL
LOGIC
ZZR
(4)
NOTES:
1. Address A 18x is a NC for IDT70T631.
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3 BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
5670 drw 01
NOVEMBER 2003
1
©2003 Integrated Device Technology, Inc.
DSC-5670/3
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Description
The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous
Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a
stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider
memory system applications results in full-speed, error-free operation
without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
Preliminary
Industrial and Commercial Temperature Ranges
feature controlled by the chip enables (either CE0 or CE1) permit the
on-chip circuitry of each port to enter a very low standby power mode.
The IDT70T651/9 has a RapidWrite Mode which allows the designer
to perform back-to-back write operations without pulsing the R/W input
each cycle. This is especially significant at the 8 and 10ns cycle times of
the IDT70T651/9, easing design considerations at these high performance levels.
The 70T633/1 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (VDD) remains at 2.5V.
2
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3)
70T633/1BC
BC-256(5,6)
256-Pin BGA
Top View
03/13/03
A1
NC
B1
NC
C1
NC
D1
NC
E1
A2
TDI
B2
NC
C2
I/O9L
D2
I/O9R
E2
I/O10R I/O 10L
F1
I/O11L
G1
NC
H1
NC
J1
F2
NC
G2
NC
H2
A3
NC
B3
A17L
B4
A5
A6
A 14L
A11L
B5
B6
TDO A18L(4) A15L
C3
VSS
D3
NC
E3
NC
F3
C4
A16L
D4
C5
A13L
D5
G3
E4
E5
VDDQL VDD
F4
F5
G4
G5
I/O12L VDDQR VSS
H3
H4
H5
NC VDDQR VSS
J3
J4
J5
I/O13L I/O 14R I/O13R VDDQL ZZ R
K1
NC
L1
I/O15L
M1
K2
NC
L2
NC
M2
I/O16R I/O 16L
N1
NC
P1
NC
R1
NC
T1
NC
N2
I/O17R
P2
K3
NC
T2
TCK
K5
L4
L5
I/O15R VDDQR VDD
M3
NC
N3
NC
P3
I/O 17L TMS
R2
K4
I/O14L VDDQL VSS
L3
R3
M4
VDDQR
N4
M5
VDD
NC
C6
A10L
D6
A8L
B7
A9L
C7
A7L
D7
A9
A8
NC
CE1L
B9
B8
UBL
NC
LBL
D9
D8
OEL
B10
CE0L R/WL
C9
C8
A10
C10
A11
INT L
B11
NC
C11
SEML BUSYL
D10
D11
A12
A5L
B12
A4L
C12
A6L
D12
A13
A2L
B13
A1L
C13
A3L
D13
N5
E6
VDD
F6
NC
G6
VSS
H6
VSS
J6
VSS
K6
VSS
L6
NC
M6
VDD
N6
E7
VSS
F7
VSS
G7
VSS
H7
VSS
J7
VSS
K7
VSS
L7
VSS
M7
VSS
N7
E8
E9
VSS
VSS
F9
F8
VSS
G8
VSS
G9
VSS
H8
VSS
H9
VSS
J8
VSS
J9
VSS
K8
VSS
K9
VSS
L8
VSS
L9
VSS
M8
VSS
M9
VSS
N8
VSS
N9
E10
VSS
F10
VSS
G10
VSS
H10
VSS
J10
VSS
K10
VSS
L10
VSS
M10
VSS
N10
E11
VDD
F11
VSS
G11
VSS
H11
VSS
J11
VSS
K11
VSS
L11
VSS
M11
VDD
N11
E12
E13
VDD VDDQR
F12
F13
P4
A16R
R4
P5
A13R
R5
T4
A17R
T5
A14R
P6
A10R
R6
A12R
T6
A11R
P7
A7R
R7
A9R
T7
A8R
P8
P9
NC
R8
R9
UBR
T8
R10
CE0R R/WR
T9
NC
P10
P11
LBR SEMR BUSYR
CE1R
T10
OER
R11
M/S
T11
INT R
A14
A0L
B14
NC
C14
OPTL
D14
NC
E14
NC
F14
VDD VDDQR I/O6R
G12
VSS
H12
VSS
J12
G13
G14
VDDQL I/O5L
H13
VDDQL
J13
H14
NC
J14
A15
NC
B15
NC
C15
NC
D15
NC
E15
A16
NC
B16
NC
C16
I/O8L
D16
I/O8R
E16
I/O7L I/O7R
F15
NC
G15
NC
H15
NC
J15
F16
I/O6L
G16
NC
H16
I/O5R
J16
ZZL VDDQR I/O4R I/O3R I/O 4L
K12
VSS
L12
VDD
M12
K13
K14
VDDQR NC
L13
L14
VDDQL I/O2L
M13
M14
K15
NC
L15
NC
M15
VDD VDDQL I/O1R I/O1L
N12
N13
VDD VDDQR VDDQR VDDQL VDDQL VDDQR V DDQR VDDQL VDDQL VDD
TRST A18R(4) A15R
T3
A12L
A7
VDD VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD
I/O11R VDDQL VDD
I/O12R
J2
A4
P12
A6R
R12
A4R
T12
A5R
P13
A3R
R13
A1R
T13
A2R
N14
NC
P14
NC
R14
OPTR
T14
A0R
N15
I/O0R
P15
NC
R15
NC
T15
NC
K16
I/O3L
L16
I/O2R
M16
NC
N16
NC
P16
I/O 0L
R16
NC
T16
NC
5670 drw 02c
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground supply.
4. A18X is a NC for IDT70T631.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
3
,
,
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
03/13/03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
70T633/1DD
DD-144(5,6,7)
144-Pin TQFP
Top View(8)
OPTL
VDDQR
VSS
I/O8L
I/O8R
I/O7L
I/O7R
I/O6L
I/O6R
VSS
VDDQL
I/O5L
I/O5R
VSS
VDDQR
VDD
VDD
VSS
VSS
ZZL
VDDQL
I/O4R
I/O4L
I/O3R
I/O3L
VSS
VDDQR
I/O2R
I/O2L
I/O1R
I/O1L
I/O0R
I/O0L
VSS
VDDQL
OPTR
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
A18R(4)
A17R
A16R
A15R
A14R
A13R
A12R
A11R
A10R
A9R
A8R
A7R
UBR
LBR
CE1R
CE0R
VDD
VSS
SEMR
OER
R/WR
BUSYR
INTR
M/S
A6R
A5R
A4R
A3R
A2R
A1R
A0R
VDD
VSS
VDD
NC
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
VDDQR
VSS
I/O9L
I/O9R
I/O10L
I/O10R
I/O11L
I/O11R
VDDQL
VSS
I/O12L
I/O12R
VDDQR
ZZR
VDD
VDD
VSS
VSS
VDDQL
VSS
I/O13R
I/O13L
I/O14R
I/O14L
VDDQR
VSS
I/O15R
I/O15L
I/O16R
I/O16L
I/O17R
I/O17L
VSS
VDDQL
NC
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
NC
NC
A18L(4)
A17L
A16L
A15L
A14L
A13L
A12L
A11L
A10L
A9L
A8L
A7L
UBL
LBL
CE1L
CE0L
VDD
VSS
SEML
OEL
R/WL
BUSYL
INTL
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
VDD
VSS
Pin Configurations(1,2,3,8) (con't.)
5670 drw 02a
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground.
4. A18X is a NC for IDT70T631.
5. Package body is approximately 20mm x 20mm x 1.4mm.
6. This package code is used to reference the package diagram.
7. 8ns Commercial and 10ns Industrial speed grades are not available in the DD-144 package.
8. This text does not indicate orientation of the actual part-marking.
9. Due to the restricted number of pins, JTAG is not supported in the DD-144 package.
4
,
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3)(con't.)
03/12/03
1
2
3
4
5
6
7
8
9
10 11
12
13 14
15
16 17
A
I/O 9L
NC
VS S
TDO
NC
A16L
A 12L
A 8L
NC
VDD
SEML
INTL
A4L
A0L
OPTL
NC
VSS
A
B
NC
VS S
NC
TDI
A 17L
A13L
A 9L
NC
CE0L
VSS
BUSYL
A5L
A 1L
VS S
VDD QR
I/O 8L
NC
B
C
V DD QL
I/O 9R
VDDQR
V DD
A18L (4 )
A14 L
A1 0L
UBL
CE1L
VSS
R/WL
A6L
A2L
VDD
I/O 8R
NC
VSS
C
D
NC
VSS
I/O 10L
NC
A 15 L
A 11L
A7 L
LBL
V DD
OE L
NC
A 3L
VDD
NC
VD DQL
I/O 7L
I/O7 R
D
E
I/O11L
NC
VD DQ R I/O 10 R
I/O6L
NC
V SS
NC
E
F
V DD QL
I/O 11R
NC
VSS
VS S
I/O 6R
NC
VD DQ R
F
G
NC
VS S
I/O 12L
NC
NC
V DD QL
I/O 5L
NC
G
H
VDD
NC
VD DQ R I/O 12R
VD D
NC
VSS
I/O5R
H
J
VDD QL
VD D
ZZ L
V DD
VSS
V DDQ R
J
K
I/O14R
VS S
I/O 13R
VS S
I/O3R
VD DQL
I/O 4R
V SS
K
L
NC
I/O14L
VD DQ R
I/O 13L
NC
I/O 3L
V SS
I/O4L
L
M
V DD QL
NC
I/O 15R
V SS
VS S
NC
I/O 2R
VDDQ R
M
N
NC
VS S
NC
I/O 15 L
I/O 1R
V DD QL
NC
I/O2L
N
P
I/O16R
I/O 16L
VD DQ R
NC
TRST
A16R
A 12R
A 8R
NC
VD D
SEM R
INTR
A 4R
NC
I/O 1L
V SS
NC
P
R
VS S
NC
I/O 17 R
TCK
A17R
A13R
A9R
NC
CE0R
VS S
BUSYR
A5R
A1R
VS S
VD DQ L
I/O0R
VDDQR
R
T
NC
I/O 17L
VD DQ L
TMS
A18R (4)
A14R
A1 0R
UB R
CE1R
VS S
R/ WR
A6R
A2R
VS S
NC
V SS
NC
T
U
VS S
NC
VDD
NC
A15R
A11R
A7R
LBR
VDD
OE R
M/S
A 3R
A0R
VDD
OPT R
I/O0L
U
VSS
70T633/1BF
BF-208(5,6)
ZZR
208-Ball BGA
Top View(7)
NC
5670 drw 02b
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground.
4. A18X is a NC for IDT70T631.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
5
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables (Input)
R/WL
R/WR
Read/Write Enable (Input)
OEL
Output Enable (Input)
OER
(1)
(1)
A0L - A18L
A0R - A18R
Address (Input)
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
SEML
SEMR
Semaphore Enable (Input)
INTL
INTR
Interrupt Flag (Output)
BUSYL
BUSYR
Busy Flag (Output)
UBL
UBR
Upper Byte Select (Input)
LBR
Lower Byte Select (Input)
LBL
VDDQL
VDDQR
Power (I/O Bus) (3.3V or 2.5V)(2) (Input)
OPTL
OPTR
Option for selecting VDDQX(2,3) (Input)
ZZL
ZZR
Sleep Mode Pin(4) (Input)
M/S
Master or Slave Select (Input)(5)
VDD
Power (2.5V)(2) (Input)
VSS
Ground (0V) (Input)
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Logic Clock (10MHz) (Input)
TMS
Test Mode Select (Input)
TRST
Reset (Initialize TAP Controller) (Input)
NOTES:
1. Address A18x is a NC for IDT70T631.
2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/OX.
3. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPT X is set to VSS (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are
not affected during sleep mode. It is recommended that boundry scan not be
operated during sleep mode.
5. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master
(M/S=V IH).
5670 tbl 01
6
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1)
OE
SEM
CE0
CE 1
UB
LB
R/W
ZZ
Upper Byte
I/O9-17
Lower Byte
I/O0-8
X
H
H
X
X
X
X
L
High-Z
High-Z
X
H
X
L
X
X
X
L
High-Z
High-Z
Deselected–Power Down
X
H
L
H
H
H
X
L
High-Z
High-Z
Both Bytes Deselected
X
H
L
H
H
L
L
L
High-Z
DIN
Write to Lower Byte
X
H
L
H
L
H
L
L
DIN
High-Z
Write to Upper Byte
MODE
Deselected–Power Down
X
H
L
H
L
L
L
L
DIN
DIN
L
H
L
H
H
L
H
L
High-Z
DOUT
Read Lower Byte
Write to Both Bytes
L
H
L
H
L
H
H
L
DOUT
High-Z
Read Upper Byte
L
H
L
H
L
L
H
L
DOUT
DOUT
Read Both Bytes
H
H
L
H
L
L
X
L
High-Z
High-Z
Outputs Disabled
X
X
X
X
X
X
X
H
High-Z
High-Z
High-Z Sleep Mode
5670 tbl 02
NOTE:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
Truth Table II – Semaphore Read/Write Control(1)
Inputs(1)
Outputs
CE(2)
R/W
OE
UB
LB
SEM
I/O1-17
I/O0
H
H
L
L
L
L
DATAOUT
DATAOUT
Read Data in Semaphore Flag (3)
H
↑
X
X
L
L
X
DATAIN
Write I/O0 into Semaphore Flag
L
X
X
X
X
L
______
______
Mode
Not Allowed
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A 0-A2.
2. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
3. Each byte is controlled by the respective UB and LB. To read data UB and/or LB = VIL.
7
5670 tbl 03
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Recommended DC Operating
Conditions with VDDQ at 2.5V
Recommended Operating
Temperature and Supply Voltage(1)
Unit
2.4
2.5
2.6
V
2.4
2.5
2.6
V
0
0
0
V
1.7
____
V DDQ + 100mV(2)
V
Input High Voltage _
JTAG
1.7
____
VDD + 100mV (2)
V
VIH
Input High Voltage ZZ, OPT, M/S
VDD - 0.2V
____
VDD + 100mV (2)
V
VIL
Input Low Voltage
-0.3(1)
____
0.7
V
VIL
Input Low Voltage ZZ, OPT, M/S
(1)
____
0.2
V
Core Supply Voltage
0 C to +70 C
0V
2.5V + 100mV
I/O Supply Voltage (3)
-40OC to +85OC
0V
2.5V + 100mV
VSS
Ground
VIH
Input High Volltage
(Address, Control &
Data I/O Inputs)(3)
VIH
5670 tbl 04
Absolute Maximum Ratings
Symbol
Rating
Commercial
& Industrial
Unit
VTERM
(V DD)
VDD Terminal Voltage
with Respect to GND
VTERM(2)
(V DDQ)
VDDQ Terminal Voltage
with Respect to GND
-0.3 to V DDQ + 0.3
V
VTERM(2)
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
-0.3 to V DDQ + 0.3
V
TBIAS(3)
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-65 to +150
o
C
TJN
Junction Temperature
+150
o
C
-0.5 to 3.6
V
IOUT(For V DDQ = 3.3V) DC Output Current
50
mA
IOUT(For V DDQ = 2.5V) DC Output Current
40
mA
5670 tbl 05
Recommended DC Operating
Conditions with VDDQ at 3.3V
Symbol
V DD
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any Input or I/O pin cannot exceed VDDQ during power
supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
(1)
Capacitance
Input Capacitance
Output Capacitance
Parameter
Core Supply Voltage
(3)
Min.
Typ.
Max.
Unit
2.4
2.5
2.6
V
3.15
3.3
3.45
V
0
0
0
V
2.0
____
VDDQ + 150mV(2)
V
1.7
____
VDD + 100mV (2)
V
VDD - 0.2V
____
VDD + 100mV (2)
V
VDDQ
I/O Supply Voltage
V SS
Ground
VIH
Input High Voltage
(Address, Control
&Data I/O Inputs)(3)
VIH
Input High Voltage
JTAG
VIH
Input High Voltage ZZ, OPT, M/S
VIL
Input Low Voltage
-0.3(1)
____
0.8
V
VIL
Input Low Voltage ZZ, OPT, M/S
-0.3(1)
____
0.2
V
_
5670 tbl 06
(TA = +25°C, F = 1.0MHZ) TQFP ONLY
Parameter
-0.3
NOTES:
1. VIL (min.) = -1.0V for pulse width less than t RC/2 or 5ns, whichever is less.
2. VIH (max.) = V DDQ + 1.0V for pulse width less than t RC/2 or 5ns, whichever is
less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VSS (0V), and VDDQX for that port must be
supplied as indicated above.
5670 tbl 07
COUT
Max.
VDD
(1)
(3)
Typ.
VDDQ
O
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
CIN
Min.
VDD
Commercial
Symbol
Parameter
GND
O
Industrial
Symbol
Ambient
Temperature
Grade
Preliminary
Industrial and Commercial Temperature Ranges
(2)
Conditions
Max.
Unit
VIN = 3dV
8
pF
VOUT = 3dV
10.5
pF
NOTES:
1. VIL (min.) = -1.0V for pulse width less than t RC/2 or 5ns, whichever is less.
2. VIH (max.) = V DDQ + 1.0V for pulse width less than t RC/2 or 5ns, whichever is
less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be
supplied as indicated above.
5670 tbl 08
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
8
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T633/1S
Symbol
Parameter
Test Conditions
(1)
|ILI|
Input Leakage Current
(1,2)
|ILI|
JTAG & ZZ Input Leakage Current
(1,3)
|ILO|
Min.
Max.
Unit
VDDQ = Max., VIN = 0V to VDDQ
___
10
µA
VDD = Max., VIN = 0V to VDD
___
+30
µA
Output Leakage Current
CE0 = V IH or CE 1 = VIL, VOUT = 0V to VDDQ
___
10
µA
VOL (3.3V)
Output Low Voltage (1)
IOL = +4mA, VDDQ = Min.
___
0.4
V
VOH (3.3V)
(1)
IOH = -4mA, VDDQ = Min.
2.4
___
V
(1)
IOL = +2mA, VDDQ = Min.
___
0.4
V
(1)
IOH = -2mA, VDDQ = Min.
2.0
___
VOL (2.5V)
VOH (2.5V)
Output High Voltage
Output Low Voltage
Output High Voltage
V
5670 tbl 09
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T633/1S8(6)
Com'l Only
Symbol
IDD
ISB1(6)
ISB2
(6)
ISB3
ISB4(6)
IZZ
Parameter
Test Condition
Version
70T633/1S10
Com'l
& Ind(6)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Unit
mA
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled
f = fMAX(1)
COM'L
S
350
475
300
405
300
355
225
305
IND
S
____
____
300
445
300
395
____
____
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L
S
115
140
90
120
75
105
60
85
IND
S
____
____
90
145
75
130
____
____
COM'L
S
240
315
200
265
180
230
150
200
IND
S
____
____
200
290
180
255
____
____
COM'L
S
2
10
2
10
2
10
2
10
IND
S
____
____
2
20
2
20
____
____
S
240
315
200
265
180
230
150
200
S
____
____
200
290
180
255
____
____
Standby Current
(One Port - TTL
Level Inputs)
(5)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
f = fMAX(1)
Full Standby Current Both Ports CEL and
(Both Ports - CMOS CER > VDD - 0.2V, VIN > VDD - 0.2V
Level Inputs)
or VIN < 0.2V, f = 0(2)
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) COM'L
VIN > VDD - 0.2V or VIN < 0.2V, Active
IND
Port, Outputs Disabled, f = fMAX(1)
Sleep Mode Current
(Both Ports - TTL
Level Inputs)
ZZL = ZZR = VIH
f = fMAX(1)
COM'L
S
2
10
2
10
2
10
2
10
IND
S
____
____
2
20
2
20
____
____
mA
mA
mA
mA
mA
5670 tbl 10
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS".
2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.
3. VDD = 2.5V, TA = 25°C for Typ. values, and are not production tested. IDD DC(f=0) = 100mA (Typ).
4. CE X = VIL means CE0X = VIL and CE1X = VIH
CE X = VIH means CE0X = VIH or CE1X = V IL
CE X < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V
CE X > V DDQX - 0.2V means CE 0X > V DDQX - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
5. ISB1, ISB2 and ISB4 will all reach full standby levels (I SB3) on the appropriate port(s) if ZZL and /or ZZ R = VIH.
6. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
9
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ = 3.3V/2.5V)
Input Pulse Levels
GND to 3.0V / GND to 2.5V
Input Rise/Fall Times
2ns Max.
Input Timing Reference Levels
1.5V/1.25V
Output Reference Levels
1.5V/1.25V
Output Load
Figure 1
5670 tbl 11
50Ω
50Ω
DATAOUT
1.5V/1.25
10pF
(Tester)
,
5670 drw 03
Figure 1. AC Output Test load.
4
3.5
3
∆ tAA/tACE
(Typical, ns)
2.5
2
1.5
1
0.5
0
0
20
40
60
80
100
120
∆ Capacitance (pF) from AC Test Load
140
5670 drw 04
Figure 3. Typical Output Derating (Lumped Capacitive Load).
10
160
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70T633/1S8(5)
Com'l Only
Symbol
Parameter
70T633/1S10
Com'l
& Ind(5)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
8
____
10
____
12
____
15
____
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address Access Time
____
8
____
10
____
12
____
15
ns
tACE
Chip Enable Access Time (3)
____
8
____
10
____
12
____
15
ns
tABE
Byte Enable Access Time
(3)
____
4
____
5
____
6
____
7
ns
tAOE
Output Enable Access Time
____
4
____
5
____
6
____
7
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time Chip Enable and Semaphore (1,2)
3
____
3
____
3
____
3
____
ns
ns
(1,2)
tLZOB
Output Low-Z Time Output Enable and Byte Enable
0
____
0
____
0
____
0
____
tHZ
Output High-Z Time(1,2)
0
3.5
0
4
0
6
0
8
ns
tPU
Chip Enable to Power Up Time (2)
0
____
0
____
0
____
0
____
ns
____
7
____
8
____
8
____
12
ns
____
4
____
4
____
6
____
8
ns
2
8
2
10
2
12
2
15
ns
____
5
____
5
____
6
____
7
(2)
tPD
Chip Disable to Power Down Time
tSOP
Semaphore Flag Update Pulse (OE or SEM)
tSAA
Semaphore Address Access Time
tSOE
Semaphore Output Enable Access Time
ns
5670 tbl 12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(4)
70T633/1S8(5)
Com'l Only
Symbol
Parameter
70T633/1S10
Com'l
& Ind(5)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
8
____
10
____
12
____
15
____
ns
tEW
Chip Enable to End-of-Write (3)
6
____
7
____
9
____
12
____
ns
tAW
Address Valid to End-of-Write
6
____
7
____
9
____
12
____
ns
0
____
0
____
0
____
0
____
ns
ns
(3)
tAS
Address Set-up Time
tWP
Write Pulse Width
6
____
7
____
9
____
12
____
tWR
Write Recovery Time
0
____
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
4
____
5
____
7
____
10
____
ns
tDH
Data Hold Time
0
____
0
____
0
____
0
____
ns
____
3.5
____
4
____
6
____
8
ns
3
____
3
____
3
____
3
____
ns
5
____
5
____
5
____
ns
5
____
5
____
5
____
tWZ
tOW
(1,2)
Write Enable to Output in High-Z
Output Active from End-of-Write
(1,2)
tSWRD
SEM Flag Write to Read Time
4
____
tSPS
SEM Flag Contention Window
4
____
ns
5670 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when
CE0 = VIL and CE1 = VIH. CE = VIH when CE 0 = VIH and/or CE1 = VIL.
4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
5. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
11
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
(6)
CE
tAOE
(4)
OE
tABE (4)
UB, LB
R/W
tOH
(1)
tLZ/tLZOB
DATAOUT
VALID DATA
(4)
tHZ
(2)
BUSYOUT
.
tBDD
(3,4)
5670 drw 06
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA, tABE, or tBDD.
5. SEM = VIH.
6. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
50%
50%
ISB
.
5670 drw 07
12
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
(9)
CE or SEM
(9)
UB, LB
tAS
(2)
(6)
tWR
tWP
(3)
R/W
(7)
tWZ (7)
tOW
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
.
5670 drw 10
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5,8)
tWC
ADDRESS
tAW
CE or SEM
(9)
(6)
tAS
tWR(3)
tEW (2)
UB, LB(9)
R/W
tDW
tDH
DATAIN
.
5670 drw 11
.
NOTES:
1. R/W or CE or UB or LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW . If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP .
9. To access RAM, CE = V IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = V IL when CE0 = V IL
and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
13
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
RapidWrite Mode Write Cycle
Preliminary
Industrial and Commercial Temperature Ranges
Care must be taken to still meet the Write Cycle time (tWC), the time in
which the Address inputs must be stable. Input data setup and hold times
(tDW and tDH) will now be referenced to the ending address transition. In
this RapidWrite Mode the I/O will remain in the Input mode for the duration
of the operations due to R/W being held low. All standard Write Cycle
specifications must be adhered to. However, tAS and tWR are only
applicable when switching between read and write operations. Also,
there are two additional conditions on the Address Inputs that must also
be met to ensure correct address controlled writes. These specifications,
the Allowable Address Skew (tAAS) and the Address Rise/Fall time (tARF),
must be met to use the RapidWrite Mode. If these conditions are not met
there is the potential for inadvertent write operations at random intermediate
locations as the device transitions between the desired write addresses.
Unlike other vendors' Asynchronous Random Access Memories,
the IDT70T651/9 is capable of performing multiple back-to-back write
operations without having to pulse the R/W, CE, or BEn signals high
during address transitions. This RapidWrite Mode functionality allows the
system designer to achieve optimum back-to-back write cycle performance
without the difficult task of generating narrow reset pulses every cycle,
simplifying system design and reducing time to market.
During this new RapidWrite Mode, the end of the write cycle is now
defined by the ending address transition, instead of the R/W or CE or BEn
transition to the inactive state. R/W, CE, and BEn can be held active
throughout the address transition between write cycles.
Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle(1,3)
(4)
tWC
tWC
tWC
ADDRESS
(2)
CE or SEM(6)
tEW
BEn
tWR
tWP
R/W
(5)
(5)
tWZ
tOW
DATAOUT
tDH
tDH
tDW
tDW
tDH
tDW
DATAIN
5670 drw 08
NOTES:
1. OE = VIL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state.
2. A write occurs during the overlap (tEW or tWP) of a CE = V IL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and
R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.
3. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.
5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
6. To access RAM, CE = V IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = V IL when CE0 = V IL
and CE1 = VIH. CE = V IH when CE0 = VIH and/or CE1 = VIL.
14
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics over the Operating Temperature Range
and Supply Voltage Range for RapidWrite Mode Write Cycle(1)
Symbol
Parameter
Min
tAAS
Allowable Address Skew for RapidWrite Mode
____
tARF
Address Rise/Fall Time for RapidWrite Mode
1.5
Max
Unit
1
ns
____
V/ns
5670 tbl 14
NOTE:
1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle.
Timing Waveform of Address Inputs for RapidWrite Mode Write Cycle
A0
tARF
tAAS
(1)
A18
tARF
5670 drw 09
NOTE:
1. A17 for IDT70T631.
15
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
tAW
VALID ADDRESS
tWR
tACE
tEW
SEM(1)
tOH
tSOP
tDW
DATA OUT(2)
VALID
DATA IN VALID
I/O
tAS
tWP
tDH
R/W
tSWRD
OE
tSOE
tSOP
Write Cycle
Read Cycle
5670 drw 12
.
NOTES:
1. CE0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for
appropriate UB/LB controls.
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O17 ) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
5670 drw 13 .
NOTES:
1. DOR = D OL = VIL, CE 0L = CE0R = VIH; CE 1L = CE1R = VIL. Refer also to Truth Table II for appropriate UB/LB controls.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
16
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70T633/1S8(6)
Com'l Only
Symbol
Parameter
70T633/1S10
Com'l
& Ind(6)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
8
____
10
____
12
____
15
ns
tBDA
BUSY Disable Time from Address Not Matched
____
8
____
10
____
12
____
15
ns
tBAC
BUSY Access Time from Chip Enable Low
____
8
____
10
____
12
____
15
ns
tBDC
BUSY Disable Time from Chip Enable High
____
8
____
10
____
12
____
15
ns
tAPS
Arbitration Priority Set-up Time (2)
2.5
____
2.5
____
2.5
____
2.5
____
ns
____
8
____
10
____
12
____
15
ns
6
____
7
____
9
____
12
____
ns
tBDD
tWH
(3)
BUSY Disable to Valid Data
Write Hold After BUSY
(5)
BUSY TIMING (M/S=VIL)
tWB
BUSY Input to Write(4)
0
____
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
6
____
7
____
9
____
12
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay (1)
____
12
____
14
____
16
____
20
ns
tDDD
Write Data Valid to Read Data Delay (1)
____
12
____
14
____
16
____
20
ns
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH )".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
5670 tbl 15
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2,3)
70T633/1S8(4)
Com'l Only
Symbol
Parameter
70T633/1S10
Com'l
& Ind(4)
70T6331S12
Com'l
& Ind
70T633/1S15
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
SLEEP MODE TIMING (ZZx=V IH)
tZZS
Sleep Mode Set Time
8
____
10
____
12
____
15
____
tZZR
Sleep Mode Reset Time
8
____
10
____
12
____
15
____
tZZPD
Sleep Mode Power Down Time (5)
8
____
10
____
12
____
15
____
tZZPU
Sleep Mode Power Up Time (5)
____
0
____
0
____
0
____
0
5670 tbl 15a
NOTES:
1. Timing is the same for both ports.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected
during sleep mode. It is recommended that boundary scan not be operated during sleep mode.
3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
4. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
5. This parameter is guaranteed by device characterization, but is not production tested.
17
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDH
tDW
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBDA
tBAA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
tDDD (3)
.
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CE0L = CE0R = VIL; CE1L = CE1R = VIH.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
tWB(3)
BUSY"B"
tWH
R/W"B"
(1)
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH.
3. tWB only applies to the slave mode.
5670 drw 15
18
.
5670 drw 14
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"(3)
CE"B"(3)
tAPS (2)
tBAC
tBDC
BUSY"B"
.
5670 drw 16
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1,3,4)
ADDR"A"
ADDRESS "N"
tAPS (2)
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
5670 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. CEX = VIL when CE0X = V IL and CE1X = VIH. CEX = VIH when CE 0X = VIH and/or CE1X = VIL.
4. CE0X = OEX = LBX = UBX = VIL. CE1X = V IH.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
70T633/1S8(3)
Com'l Only
Symbol
Parameter
70T633/1S10
Com'l
& Ind(3)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
0
____
ns
tINS
Interrupt Set Time
____
8
____
10
____
12
____
15
ns
tINR
Interrupt Reset Time
____
8
____
10
____
12
____
15
ns
NOTES:
1. Timing is the same for both ports.
2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
3. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
19
5670 tbl 16
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
(2)
ADDR"A"
INTERRUPT SET ADDRESS
tWR(5)
tAS(4)
CE"A"(3)
R/W"A"
tINS
(4)
INT"B"
.
5670 drw 18
tRC
ADDR"B"
INTERRUPT CLEAR ADDRESS
tAS
(2)
(4)
CE"B"(3)
OE"B"
tINR (4)
INT"B"
5670 drw 19
.
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. CEX = V IL means CE0X = VIL and CE 1X = V IH. CEX = VIH means CE0X = VIH and/or CE1X = VIL.
4. Timing depends on which enable signal (CE or R/W) is asserted last.
5. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1,4)
Left Port
Right Port
R/WL
CEL
OEL
A18L-A0L(5)
INTL
R/WR
CER
OER
A18R-A0R(5)
INTR
L
L
X
7FFFF
X
X
X
X
X
L(2)
X
X
X
X
X
L
X
X
L
X
X
7FFFE
X
(3)
Function
Set Right INTR Flag
Reset Right INTR Flag
X
L
L
7FFFF
H
(3)
L
L
X
7FFFE
X
Set Left INTL Flag
(2)
X
X
X
X
X
Reset Left INTL Flag
L
H
NOTES:
1. Assumes BUSYL = BUSYR =VIH. CEX = L means CE0X = VIL and CE1X = VIH.
2. If BUSYL = V IL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. A18x is a NC for IDT70T631. Therefore, Interrupt Addresses are 3FFFF and 3FFFE.
20
5670 tbl 17
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Truth Table IV —
Address BUSY Arbitration
Inputs
CEL(5) CER(5)
Outputs
A0L-A18L(4)
A0R-A18R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
5670 tbl 18
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70T633/1 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A18 is a NC for IDT70T631. Address comparison will be for A0 - A 17.
5. CEX = L means CE 0X = V IL and CE 1X = V IH. CEX = H means CE0X = VIH and/or CE1X = V IL.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D17 Left
D0 - D17 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T633/1.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17 ). These eight semaphores are addressed by A0 - A2.
3. CE0 = VIH, CE1 = SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
5670 tbl 19
flag (INTL) is asserted when the right port writes to memory location
7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location 7FFFE when CEL = OEL = VIL, R/W is a "don't care".
Likewise, the right port interrupt flag (INTR) is asserted when the left
port writes to memory location 7FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 7FFFF. The
message (18 bits) at 7FFFE or 7FFFF (3FFFF or 3FFFE for IDT70T631)
is user-defined since it is an addressable SRAM location. If the interrupt
function is not used, address locations 7FFFE and 7FFFF are not used
as mail boxes, but as part of the random access memory. Refer to Truth
Table III for the interrupt operation.
The IDT70T633/1 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70T633/1 has an automatic power down
feature controlled by CE. The CE0 and CE1 control the on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE = HIGH). When a port is enabled, access to the
entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
21
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Busy Logic
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70T633/1 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
Semaphores
The IDT70T633/1 is an extremely fast Dual-Port 512/256K x 18
CMOS Static RAM with an additional 8 address locations dedicated to
binary semaphore flags. These flags allow either processor on the left or
right side of the Dual-Port RAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an example,
the semaphore can be used by one processor to inhibit the
other from accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, with both ports
being completely independent of each other. This means that the
activity on the left port in no way slows the access time of the right port.
Both ports are identical in function to standard CMOS Static RAM and
can be read from or written to at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by CE0 and CE1, the Dual-Port RAM chip enables, and
SEM, the semaphore enable. The CE0, CE1, and SEM pins control onchip power down circuitry that permits the respective port to go into standby
mode when not selected.
Systems which can best use the IDT70T633/1 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the hardware
semaphores of the IDT70T633/1, which provide a lockout mechanism
without requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70T633/1 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
A19
CE0
MASTER
Dual Port RAM
BUSYL
BUSYR
CE0
SLAVE
Dual Port RAM
BUSYL
BUSYR
CE1
MASTER
Dual Port RAM
CE1
SLAVE
Dual Port RAM
BUSYL
BUSYL
BUSYR
BUSYR
5670 drw 20
Preliminary
Industrial and Commercial Temperature Ranges
.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70T633/1 Dual-Port RAMs.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70T633/1 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAMs
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70T633/1 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration on a master is based on the chip enable and
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This processor then
22
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
used instead, system contention problems could have occurred during
the gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the opposite side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
If the opposite side semaphore request latch has been written to
zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first request latch. The
verifies its success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side processor
has set the latch first, has the token and is using the shared resource.
The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70T633/1 in a
separate memory space from the Dual-Port RAM array. This address
space is accessed by placing a low input on the SEM pin (which acts as
a chip select for the semaphore flags) and using the other control pins
(Address, CE0, CE1, R/W and LB/UB) as they would be used in accessing
a standard Static RAM. Each of the flags has a unique address which can
be accessed by either side through address pins A0 – A2. When accessing
the semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to
a zero on that side and a one on the other side (see Truth Table V).
That semaphore can now only be modified by the side showing the zero.
When a one is written into the same location from the same side, the
flag will be set to a one for both sides (unless a semaphore request
from the other side is pending) and then can be written to by both sides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero
written into the same location from the other side will be stored in the
semaphore request latch for that side until the semaphore is freed by
the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros for a semaphore read, the SEM, BEn, and OE
signals need to be active. (Please refer to Truth Table II). Furthermore,
the read value is latched into one side’s output register when that side's
semaphore select (SEM, BEn) and output enable (OE) signals go active.
This serves to disallow the semaphore from changing state in the middle
of a read cycle due to a write cycle from the other side.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Table V). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side
during subsequent read. Had a sequence of READ/WRITE been
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
WRITE
D
SEMAPHORE
READ
Q
SEMAPHORE
REQUEST FLIP FLOP
Q
D
D0
WRITE
SEMAPHORE
READ
Figure 4. IDT70T633/1 Semaphore Logic
5670 drw 21
opposite side flag will now stay LOW until its semaphore request latch
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no
longer needs the resource, the entire system can hang up until a one
is written into that semaphore request latch.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one,
all semaphores on both sides should have a one written into them
at initialization from both sides to assure that they will be free
when needed.
23
24
VALID DATA
VALID ADDRESS
NOTES:
1. CE1 = V IH.
2. All timing is same for Left and Right ports.
IDD
DATA
ADDRESS
ZZ
CE0
Normal Operation
tZZS
tZZPD
No new reads or writes allowed
Timing Waveform of Sleep Mode(1,2)
IZZ
Sleep Mode
tZZPU
tZZR
No reads or writes allowed
,
5670 drw 22
Normal Operation
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Sleep Mode
The IDT70T633/1 is equipped with an optional sleep or low power
mode on both ports. The sleep mode pin on both ports is active high. During
normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the
port will enter sleep mode where it will have the lowest possible power
consumption. The sleep mode timing diagram demonstrates the modes of
operation: Normal Operation, No Read/Write Allowed and Sleep Mode.
For a period of time prior to sleep mode and after recovering from sleep
mode (tZZS and tZZR), new reads or writes are not allowed. If a write or read
operation occurs during these periods, the memory array may be
corrupted. Validity of data out from the RAM cannot be guaranteed
immediately after ZZ is asserted (prior to being in sleep).
During sleep mode the RAM automatically deselects itself and disconnects its internal buffer. All outputs will remain in high-Z state while in sleep
mode. All inputs are allowed to toggle, but the RAM will not be selected and
will not perform any reads or writes.
JTAG Timing Specifications
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST
x
5670 drw 23
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4,5)
70T633/1
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
tJR
JTAG Clock Rise Time
____
(1)
ns
tJF
JTAG Clock Fall Time
____
(1)
3
ns
tJRST
JTAG Reset
50
____
ns
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
25
ns
tJDC
JTAG Data Output Hold
0
____
ns
tJS
JTAG Setup
15
____
ns
tJH
JTAG Hold
15
____
3
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
5. JTAG cannot be tested in sleep mode.
ns
5670 tbl 20
25
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
IDT Device ID (27:12)
Description
0x0
0x33B
IDT JEDEC ID (11:1)
Reserved for version number
Defines IDT part number 70T633
(1)
0x33
ID Register Indicator Bit (Bit 0)
Allows unique identification of device vendor as IDT
1
Indicates the presence of an ID register
5670 tbl 21
NOTE:
1. Device ID for IDT70T631 is 0x33C.
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
Identification (IDR)
Boundary Scan (BSR)
32
Note (3)
5670 tbl 22
System Interface Parameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs (1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
1111
Places the bypass register (BYR) between TDI and TDO.
IDCODE
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
HIGHZ
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
0011
SAMPLE/PRELOAD
0001
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) and outputs (1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
All other codes
Several combinations are reserved. Do not use codes other than those
identified above.
RESERVED
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
26
5670 tbl 23
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BC
DD
BF
256-ball BGA (BC-256)
144-pin TQFP (DD-144)
208-ball fpBGA (BF-208)
8
10
12
15
Commercial Only(1)
Commercial & Industrial(1)
Commercial & Industrial
Commercial Only
S
Standard Power
.
Speed in nanoseconds
70T633 9Mbit (512K x 18) 2.5V Asynchronous Dual-Port RAM
70T631 4Mbit (256K x 18) 2.5V Asynchronous Dual-Port RAM
5670 drw 24
NOTE:
1. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only
Preliminary Datasheet: Definition
"PRELIMINARY' datasheets contain descriptions for products that are in early release.
Datasheet Document History:
04/25/03:
10/01/03:
10/20/03:
Initial Datasheet
Page 9 Added 8ns speed DC power numbers to DC Electrical Characteristics Table
Page 9 Updated DC power numbers for 10, 12 & 15ns speeds in the DC Electrical Characteristics Table
Page 9, 11, 15, 17 & 25 Added footnote that indicates that 8ns speed is available in BF-208 and BC-256 packages only
Page 10 Added Capacitance Derating Drawing
Page 11, 15 & 17 Added 8ns AC timing numbers to the AC Electrical Characteristics Tables
Page 11 Added tSOE and tLZOB to the AC Read Cycle Electrical Characteristics Table
Page 12 Added tLZOB to the Waveform of Read Cycles Drawing
Page 14 Added tSOE to Timing Waveform of Semaphore Read after Write Timing, Either Side Drawing
Page 1 & 25 Added 8ns speed grade and 10ns I-temp to features and to ordering information
Page 1, 14 & 15 Added RapidWrite Mode Write Cycle text and waveforms
Page 15 Corrected tARF to 1.5V/ns Min.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
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800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
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27
for Tech Support:
831-754-4613
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