FAIRCHILD 74LVTH322245G

Revised May 2002
74LVT322245 • 74LVTH322245
Low Voltage 32-Bit Transceiver with 3-STATE Outputs
and 25Ω Series Resistors in A Port Outputs
General Description
Features
The LVT322245 and LVTH322245 contain thirty-two noninverting bidirectional buffers with 3-STATE outputs and are
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 32-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
■ Input and output interface capability to systems at
5V VCC
The LVT322245 and LVTH322245 are designed with
equivalent 25Ω series resistance in both the HIGH and
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
The LVTH322245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The
LVT322245 and LVTH322245 are fabricated with an
advanced BiCMOS technology to achieve high speed
operation similar to 5V ABT while maintaining a low power
dissipation.
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH322245)
■ Also available without bushold feature (74LVT322245)
■ Live insertion/extraction permitted
■ Power Up/Power Down high impedance provides
glitch-free bus loading
■ A Port outputs include equivalent series resistance of
25Ω making external termination resistors unnecessary
and reducing overshoot and undershoot
■ A Port outputs source/sink ±12 mA
B Port outputs source/sink −32 mA/+64 mA
■ ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number
Package Number
Package Description
74LVT322245G
(Note 1) (Note 2)
BGA96A
(Preliminary)
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVTH322245G
(Note 1) (Note 2)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering code “G” indicates TRAYS.
Note 2: Devices also available in TAPE and REEL. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation
DS500408
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74LVT322245 • 74LVTH322245 Low Voltage 32-Bit Transceiver with 3-STATE Outputs and 25Ω Series Resistors in
A Port Outputs
May 2002
74LVT322245 • 74LVTH322245
Connection Diagram
FBGA Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
T/Rn
Transmit/Receive Input
A0–A31
Side A Inputs/3-STATE Outputs
B0–B31
Side B Inputs/3-STATE Outputs
Pin Assignments for FBGA
(Top Thru View)
1
2
3
4
5
6
A
B1
B0
T/R1
OE1
A0
A1
B
B3
B2
GND
GND
A2
A3
C
B5
B4
VCC1
VCC1
A4
A5
D
B7
B6
GND
GND
A6
A7
E
B9
B8
GND
GND
A8
A9
F
B11
B10
VCC1
VCC1
A10
A11
G
B13
B12
GND
GND
A12
A13
H
B14
B15
T/R2
OE2
A15
A14
J
B17
B16
T/R3
OE3
A16
A17
K
B19
B18
GND
GND
A18
A19
L
B21
B20
VCC2
VCC2
A20
A21
M
B23
B22
GND
GND
A22
A23
N
B25
B24
GND
GND
A24
A25
P
B27
B26
VCC2
VCC2
A26
A27
R
B29
B28
GND
GND
A28
A29
T
B30
B31
T/R4
OE4
A31
A30
Truth Tables
Inputs
OE1
Inputs
T/R1
Outputs
OE3
T/R3
Outputs
L
L
Bus B0–B7 Data to Bus A0–A7
L
L
L
H
Bus A0–A7 Data to Bus B0–B7
L
H
Bus A16–A23 Data to Bus B16–B23
H
X
HIGH-Z State on A0–A7, B0–B7
H
X
HIGH-Z State on A16–A23, B16–B23
Inputs
OE2
Bus B16–B23 Data to Bus A16–A23
Inputs
T/R2
Outputs
OE4
T/R4
Outputs
L
L
Bus B8–B15 Data to Bus A8–A15
L
L
L
H
Bus A8–A15 Data to Bus B8–B15
L
H
Bus A24–A31 Data to Bus B24–B31
H
X
HIGH-Z State on A8–A15, B8–B15
H
X
HIGH-Z State on A24–A31, B24–B31
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
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2
Bus B24–B31 Data to Bus A24–A31
The LVT322245 and LVTH322245 contain thirty-two non-inverting bidirectional buffers with 3-STATE outputs. The device is
byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together
to obtain 16-bit or full 32-bit operation.
Logic Diagrams
Byte 1
Byte 3
Byte 2
Byte 4
VCC1 is associated with Bytes 1 and 2.
VCC2 is associated with Bytes 3 and 4.
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVT322245 • 74LVTH322245
Functional Description
74LVT322245 • 74LVTH322245
Absolute Maximum Ratings(Note 3)
Symbol
Parameter
Value
Conditions
Units
VCC
Supply Voltage
−0.5 to +4.6
VI
DC Input Voltage
−0.5 to +7.0
VO
Output Voltage
−0.5 to +7.0
Output in 3-STATE
−0.5 to +7.0
Output in HIGH or LOW State (Note 4)
V
V
IIK
DC Input Diode Current
−50
VI < GND
IOK
DC Output Diode Current
−50
VO < GND
IO
DC Output Current
64
VO > VCC
Output at HIGH State
128
VO > VCC
Output at LOW State
V
mA
mA
mA
ICC
DC Supply Current per Supply Pin
±64
mA
IGND
DC Ground Current per Ground Pin
±128
mA
TSTG
Storage Temperature
−65 to +150
°C
Recommended Operating Conditions
Symbol
Parameter
VCC
Supply Voltage
VI
Input Voltage
IOH
HIGH Level Output Current
IOL
LOW Level Output Current
TA
Free Air Operating Temperature
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
Min
Max
2.7
3.6
V
0
5.5
V
B Port
−32
A Port
−12
B Port
64
A Port
12
Units
mA
mA
−40
+85
°C
0
10
ns/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
VCC
Parameter
(V)
VIK
Input Clamp Diode Voltage
VIH
Input HIGH Voltage
2.7–3.6
VIL
Input LOW Voltage
2.7–3.6
VOH
Output HIGH Voltage
Output LOW Voltage
A Port
A Port
B Port
II(HOLD)
Bushold Input Minimum Drive
Bushold Input Over-Drive
(Note 5)
Current to Change State
II
Input Current
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0.8
Conditions
V
II = −18 mA
V
VO ≤ 0.1V or
VO ≥ VCC − 0.1V
V
2.0
V
IOH = −12 mA
VCC− 0.2
V
IOH = −100 µA
2.7
2.4
3.0
2.0
V
3.0
0.8
V
2.7
0.2
V
2.7
0.5
3.0
0.4
3.0
0.5
3.0
0.55
75
500
10
3.6
±1
3.6
0
4
V
−5
IOL = 12 mA
IOL = 100 µA
IOL = 16 mA
IOL = 32 mA
VI = 0.8V
VI = 2.0V
(Note 6)
(Note 7)
VI = 5.5V
µA
VI = 0V or VCC
VI = 0V
VI = VCC
1
±100
IOH = −32 mA
IOL = 64 mA
µA
3.6
IOH = −8 mA
IOL = 24 mA
µA
−75
−500
Data Pins
Power Off Leakage Current
−1.2
2.0
Units
3.0
3.0
Control Pins
IOFF
Max
2.7–3.6
3.0
(Note 5)
II(OD)
Min
2.7
B Port
VOL
TA = −40°C to +85°C
µA
0V ≤ VI or VO ≤ 5.5V
Symbol
(Continued)
VCC
Parameter
TA = −40°C to +85°C
(V)
IPU/PD
Power Up/Down
3-STATE Current
Min
Units
Conditions
Max
0–1.5V
±100
µA
VO = 0.5V to 3.0V
VI = GND to VCC
IOZL
3-STATE Output Leakage Current
3.6
−5
µA
VO = 0.5V
IOZL
(Note 5)
3-STATE Output Leakage Current
3.6
−5
µA
VO = 0.0V
IOZH
3-STATE Output Leakage Current
3.6
5
µA
VO = 3.0V
IOZH
(Note 5)
3-STATE Output Leakage Current
3.6
5
µA
VO = 3.6V
IOZH+
3-STATE Output Leakage Current
3.6
10
µA
VCC < VO ≤ 5.5V
ICCH
Power Supply Current
VCC1 or VCC2
3.6
0.19
mA
Outputs HIGH
ICCL
Power Supply Current
VCC1 or VCC2
3.6
5
mA
Outputs LOW
ICCZ
Power Supply Current
VCC1 or VCC2
3.6
0.19
mA
ICCZ+
Power Supply Current
VCC1 or VCC2
∆ICC
Increase in Power Supply Current
(Note 8)
74LVT322245 • 74LVTH322245
DC Electrical Characteristics
VCC1 or VCC2
3.6
0.19
mA
3.6
0.2
mA
Outputs Disabled
VCC ≤ VO ≤ 5.5V,
Outputs Disabled
One Input at VCC − 0.6V
Other Inputs at VCC or GND
Note 5: Applies to bushold versions only (74LVTH322245).
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol
Parameter
(Note 9)
TA = 25°C
VCC
(V)
Min
Typ
Max
Conditions
Units
CL = 50 pF RL = 500Ω
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.8
V
(Note 10)
VOLV
Quiet Output Minimum Dynamic VOL
3.3
−0.8
V
(Note 10)
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA = −40°C to +85°C
Symbol
CL = 50 pF, RL = 500Ω
Parameter
VCC = 3.3V ± 0.3V
Propagation Delay Data to A Port Output
tPLH
tPHL
tPLH
Propagation Delay Data to B Port Output
tPHL
tPZH
Output Enable Time for A Port Output
tPZL
Output Enable Time for B Port Output
tPZH
tPZL
tPHZ
Output Disable Time for A Port Output
tPLZ
tPHZ
Output Disable Time for B Port Output
tPLZ
Capacitance
Symbol
Units
VCC = 2.7V
Min
Max
Min
Max
1.0
4.0
1.0
4.6
1.0
3.7
1.0
4.1
1.0
3.5
1.0
3.9
1.0
3.5
1.0
3.9
1.0
5.3
1.0
6.3
1.0
5.6
1.0
7.2
1.0
4.6
1.0
5.4
1.0
5.3
1.0
6.9
1.5
5.6
1.5
6.3
1.5
5.5
1.5
5.5
1.5
5.4
1.5
6.1
1.5
5.1
1.5
5.4
ns
ns
ns
ns
ns
ns
(Note 11)
Typical
Units
CIN
Input Capacitance
Parameter
VCC = 0V, VI = 0V or VCC
Conditions
4
pF
CI/O
Input/Output Capacitance
VCC = 3.0V, VO = 0V or VCC
8
pF
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74LVT322245 • 74LVTH322245 Low Voltage 32-Bit Transceiver with 3-STATE Outputs and 25Ω Series Resistors in
A Port Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA96A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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