Fairchild FMS6408MTC1412 Precision triple video filter driver for rgb and yuv signal Datasheet

FMS6408
Precision Triple Video Filter Driver for RGB and YUV Signals
Features
Description
ƒ
ƒ
ƒ
ƒ
7.6MHz 5th order RGB/YUV/YC CV filters
The FMS6408 provides three video signal paths;
including a two-input MUX, a video filter, and a 6dB gain
output driver. The filter bandwidth supports RGB and
YUV signals in NTSC or PAL formats.
ƒ
ƒ
AC coupled inputs and AC or DC coupled outputs
ƒ
Continuous time, low-pass filters for video antialiasing or reconstruction applications
ƒ
<1% differential gain with 0.5° differential phase on
all channels
ƒ
Integrated DC restore circuitry with low tilt
50dB stopband attenuation at 27MHz on all outputs
Better than 0.5dB flatness to 4.2MHz on all outputs
No external frequency selection components or
clocks
Supports both NTSC and PAL luminance
bandwidth
Applications
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Cable Set-top Boxes
The video filters approximate a 5th-order Butterworth
low-pass characteristic optimized for minimum
overshoot and flat group delay to provide excellent
image quality. Four different peaking options are
available. The video filters can be bypassed if desired.
In a typical application, the RGB or YUV DAC outputs
are AC coupled into the filters through the input MUX.
All channels have DC restore circuitry to clamp the DC
input levels during video sync. The clamp pulse derived
from the selected Y input controls three independent
feedback clamps. All outputs are capable of driving
2Vpp, AC or DC coupled, into either a single (150Ω) or
dual (75Ω) video load. The FMS6408 clamp levels can
be factory programmed for YUV / RGB (250mV for all
channels), YC / YPbPr (250mV on channel 1 and
1.125V on channels 2 and 3) or YC CV (250mV on
channels 1 and 3 and 1.125V on channel 2).
Satellite Set-top Boxes
Terrestrial Set-top Boxes
DVD Players
Personal Video Recorders (PVR)
Video-On-Demand (VOD)
Ordering Information
Part Number
Clamping
Mode
Peaking
Mode
(dB)
YOUT
Level
(mV)
UOUT
Level
(V)
FMS6408MTC141
YPbPr/YC
0
250
1.125
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
94 Units Tube
FMS6408MTC141X
YPbPr/YC
0
250
1.125
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
2500 Units
Tape and Reel
FMS6408MTC142
YPbPr/YC
0.4
250
1.125
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
94 Units Tube
FMS6408MTC143
YPbPr/YC
0.9
250
1.125
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
94 Units Tube
FMS6408MTC143X
YPbPr/YC
0.9
250
1.125
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
2500 Units
Tape and Reel
Packing
Method
Package
Continued on following page…
© 2004 Fairchild Semiconductor Corporation
FMS6408 Rev. 3.0.0
www.fairchildsemi.com
FMS6408 — Triple Video Filter Driver for RGB and YUV Signals
October 2007
Part Number
Clamping
Mode
Peaking
Mode
(dB)
YOUT
Level
(mV)
UOUT
Level
(V)
FMS6408MTC144
YPbPr/YC
1.3
250
1.125
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
94 Units Tube
FMS6408MTC145
YUV/RGB
0
250
250
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
94 Units Tube
FMS6408MTC146
YUV/RGB
0.4
250
250
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
94 Units Tube
FMS6408MTC147
YUV/RGB
0.9
250
250
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
94 Units Tube
FMS6408MTC148
YUV/RGB
1.3
250
250
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
94 Units Tube
FMS6408MTC149
YC/CV
0
250
1.125
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
94 Units Tube
FMS6408MTC1410
YC/CV
0.4
250
1.125
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
94 Units Tube
FMS6408MTC1411
YC/CV
0.9
250
1.125
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
94 Units Tube
FMS6408MTC1412
YC/CV
1.3
250
1.125
14-Lead, Thin Shrink Small Outline
Package (TSSOP)
94 Units Tube
Packing
Method
Package
Notes:
1.
2.
All packages are Pb-free per JEDEC J-STD-020B standard.
Factory programming options allow a single die to be configured for multiple operating modes.
Block Diagram
INMUX (A/B)
BYPASS (BYPASS/FILTER)
YINA
6d B
8MHz*
YINB
FMS6408 — Triple Video Filter Driver for RGB and YUV Signals
Ordering Information (Continued)
YOUT
gM
250mV
Sync Processing
UINA
6d B
UOUT
6d B
VOUT
8MHz*
UINB
gM
250mV or
1.125V *
VINA
8MHz*
VINB
gM
* Factory Selected Clamp
and Peaking Levels
250mV or
1.125V *
Figure 1. Block Diagram
© 2004 Fairchild Semiconductor Corporation
FMS6408 Rev. 3.0.0
www.fairchildsemi.com
2
1
YINA
VCC 14
2
UINA
YOUT 13
3
VINA
BYPASS 12
4
GND
UOUT 11
5
YINB
GND 10
6
UINB
VOUT
9
7
VINB
INMUX(A/B)
8
Figure 2. Pin Configuration
Pin Definitions
Pin#
Name
Type
1
YINA
Input
Y (Luminance) or Green input A, must be connected to a signal that
includes sync
2
UINA
Input
U or Blue input A
3
VINA
Input
V or Red input A
4
GND
Input
Must be tied to ground, do not float
5
YINB
Input
Y (Luminance) or Green input B, must be connected to a signal that
includes sync
6
UINB
Input
U or Blue input B
7
VINB
Input
V or Red input B
8
INMUX(A/B)
Input
MUX select, A = ‘1’, B = ‘0’, must be externally tied high or low
9
VOUT
Output
10
GND
Input
11
UOUT
Output
12
BYPASS(Bypass/Filter)
Input
13
YOUT
Output
14
VCC
Input
© 2004 Fairchild Semiconductor Corporation
FMS6408 Rev. 3.0.0
Description
FMS6408 — Triple Video Filter Driver for RGB and YUV Signals
Pin Configuration
V or Red output
Must be tied to ground; do not float
U or Blue output
Filter bypass, BYPASS = ‘1’, FILTER = ‘0’, must be externally tied
high or low
Y or Green output
+5V supply
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC
RS
Parameter
Min.
Max.
Unit
Supply Voltage
-0.3
6
V
Analog and Digital
-0.3
VCC + 0.3
V
Output Current, Any One Channel (Do not exceed)
50
mA
Input Source Resistance
300
Ω
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
TA
Temperature Range
VCC
VCC Range
Min.
Typ.
-40
Max.
Unit
+85
°C
+4.75
+5.00
+5.25
V
Min.
Typ.
Max.
Unit
+150
°C
+150
°C
+300
°C
FMS6408 — Triple Video Filter Driver for RGB and YUV Signals
Absolute Maximum Ratings
Reliability Information
Symbol
TJ
TSTG
Parameter
Junction Temperature
Storage Range Temperature
-65
TL
Lead Temperature (Soldering, 10 Seconds)
ΘJA
Thermal Resistance; JEDEC Standard Multi-layer
Test Boards, in Still Air
© 2004 Fairchild Semiconductor Corporation
FMS6408 Rev. 3.0.0
90
°C/W
www.fairchildsemi.com
4
TC = 25˚C, VI = 1VPP, VCC = 5.0V; all inputs AC coupled with 0.1µF; all outputs AC coupled with 220µF into 150Ω,
referenced to 400kHz, 0dB peaking option; unless otherwise noted.
Symbol
Parameter
ICC
Supply Current
VI
Input Voltage Maximum
VIL
Digital Input Low(3)
VIH
Conditions
(3)
Min.
VCC no load
Digital Input High
Bypass, A_NB
0
Bypass, A_NB
2.0
YUV/RGB/CV Inputs
Clamp Voltage(4)
PSRR
Power Supply Rejection Ratio
Max.
Units
52
86
mA
1.4
(3)
VCLAMP
Typ.
PbPr/C Inputs
DC
VPP
0.8
VCC
V
V
250
mV
1.125
V
-40
dB
Notes:
3. 100% tested at 25°C.
4. Mode selection for YUV/RGB vs. PbPr/YC vs. YC CV operation based on factory programming.
AC Electrical Characteristics
TC = 25˚C, VI = 1VPP, VCC = 5.0V; all inputs AC coupled with 0.1µF; all outputs AC coupled with 220µF into 150Ω,
referenced to 400kHz, 0dB peaking option; unless otherwise noted.
Symbol
APB
AVLF
∆AVHF
fC
Parameter
Conditions
(5)
Passband Response
Low Frequency Gain (All Channels)
(5)
Delta High Frequency at 5MHz
(All Channels)(6)
Min.
Typ.
4.2MHz
-0.5
0
at 400kHz
5.6
Units
dB
6.2
dB
0dB Peaking Option
0.3
dB
0.4dB Peaking Option
0.7
dB
0.9dB Peaking Option
1.2
dB
1.3dB Peaking Option
1.6
dB
7.6
MHz
52
dB
0.2
%
-3dB Bandwidth
All Channels
fSBh
Stopband Rejection (All Channels)(5)
at 27MHz
dG
Differential Gain
All Channels
dθ
5.9
Max.
48
Differential Phase
All Channels
0.5
°
THD
Total Harmonic Distortion
at 3.58MHz
0.2
%
SNR
SNR All Channels (NTC7 Weighted)
4.2MHz Lowpass, 100kHz
Highpass
75
dB
HDIST
Line-Time Distortion
18µs, 100 IRE Bar
TBD
%
Field-Time Distortion
130 Lines, 18µs, 100 IRE
Bar
TBD
%
tpd
Propagation Delay (All Channels)
400kHz
65
ns
GD
Group Delay (All Channels)
to 3.58MHz (NTSC)
14
ns
VDIST
tpdSkew Between Any 2 Channels
at 400kHz
2
AV(match)
tSKEW
Channel Gain Matching(5)
400kHz
0
TCLAMP
Clamp Response Time (All Channels)
Settled to 10mV, Initial
Condition 0V
5
XTALK
Crosstalk (Channel-to-Channel)
at 1.0MHz
-65
dB
Input MUX Isolation
at 1.0MHz
-85
dB
Bypass Mode -1dB Bandwidth
1.4Vpp Output All Channels
25
MHz
INMUXISO
f1dBWB
FMS6408 — Triple Video Filter Driver for RGB and YUV Signals
Electrical Characteristics
ns
5
%
ms
Notes:
5. 100% tested at 25°C.
6. Peaking Options boost gain by 0dB, 0.4dB, 0.9dB, or 1.3dB from 4.2MHz to 5MHz based on factory
programming.
© 2004 Fairchild Semiconductor Corporation
FMS6408 Rev. 3.0.0
www.fairchildsemi.com
5
TC = 25˚C, VI = 1Vpp, VCC = 5.0V; all inputs AC coupled with 0.1µF; all outputs AC coupled with 220µF into 150Ω,
referenced to 400kHz, 0dB peaking option; unless otherwise noted.
10
1
40
-10
-20
Mkr
Freq.
Gain
Ref 400kHz
-30
-40
6dB
1
6.91MHz -1dB BW
2
7.8MHz
-3dB BW
3
27MHz
-43.24dB
5
10
0
-20
-40
fSBSD = Gain(ref) – Gain(3) = 49.24dB
-50
400kH
1
20
Delay (ns)
0
Gain (10dB/div)
60
2
15
3
20
25
1 = 7.6MHz (31.88ns)
-60
400kHz
30
5
10
Frequency (MHz)
Figure 3. SD Frequency Response
0.2
Differential Gain (%)
-60
Noise (dB)
-70
-80
-90
-100
1.0
2.0
3.0
30
4.0
5.0
NTSC
-0.2
-0.4
Min = -0.61
Max = 0.00
ppMax = 0.61
-0.8
6.0
1st
Frequency (MHz)
Figure 5. SD Noise vs. Frequency
2nd
3rd
4th
5th
6th
Figure 6. SD Differential Gain
7
0.05
VO = 1.4pp
6
0
Gain (1dB/div)
Differential Phase (deg)
25
0
-0.6
-110
0
20
Figure 4. SD Group vs. Frequency
-50
-120
15
Frequency (MHz)
FMS6408 — Triple Video Filter Driver for RGB and YUV Signals
Typical Performance Characteristics
-0.05
-0.10
-0.15
-0.20
2nd
1
4
2
3
2
Mkr Frequency
Ref 400kHz
Min = -0.13
Max = 0.00
ppMax = 0.13
1st
5
1
3rd
4th
5th
1
28.75MHz
-1dB BW
2
36.94MHz
-3dB BW
10
20
0
400kHz 5
6th
Gain
6dB
15
25
30
35
40
Frequency (MHz)
Figure 7. SD Differential Phase
Figure 8. Bypass Mode Frequency Response
16
14
Delay (ns)
12
10
8
1
6
4
2
1 = 25MHz (8.99ns)
0
400kHz 5
10
15
20
25
30
35
40 45
Frequency (MHz)
Figure 9. Bypass Mode Group Delay vs. Frequency
© 2004 Fairchild Semiconductor Corporation
FMS6408 Rev. 3.0.0
www.fairchildsemi.com
6
Introduction
Inputs
This product is a three-channel monolithic continuous
time video filter designed for reconstructing YUV, YC
CV, or RGB signals from a video D/A source. Inputs
should be AC coupled while outputs can be either AC or
DC coupled. The reconstruction filters approximate a
th
5 -order Butterworth response, optimized for minimum
overshoot and flat group delay. This provides a
maximally flat response in terms of delay and
amplitude. Each of the three outputs is capable of
driving 2VPP into 75Ω loads.
The inputs are typically be driven by either a lowimpedance source of 1Vpp or the output of a 75Ω
terminated line driven by the output of a current DAC. In
either case, the inputs must be capacitively coupled to
allow the sync-detect and DC-restore circuitry to
operate properly.
Outputs
The outputs are low-impedance voltage drivers that can
handle either a single or dual load. A single load
consists of a 75Ω-series termination resistor feeding a
75Ω-terminated line for a total load at the part of 150Ω.
Even when two loads are present (75Ω) the driver
produces a full 2VPP signal at its output pin. The driver
can also be used to drive an AC coupled single or dual
load. When driving a dual load, either output functions if
the other output connection is inadvertently shorted,
providing these loads are AC coupled.
All channels are clamped during the sync interval to set
the appropriate DC output level. Sync tip clamping
greatly reduces the effective input time constant,
allowing the use of small, low-cost input coupling
capacitors. The input settles to 10mV in 2ms for typical
DC shifts present in the video signal.
In most applications, the input coupling capacitors are
0.1µF. The inputs typically sink 1µA of current during
active video. For YUV signals, this translates into a 2mV
tilt in a horizontal line at the Y output. During sync, the
clamp restores this leakage current by sourcing an
average of 20µA over the clamp interval. Any change in
the coupling capacitor values affects the amount of tilt
per line. Any reduction in tilt comes with an increase in
settling time.
© 2004 Fairchild Semiconductor Corporation
FMS6408 Rev. 3.0.0
FMS6408 — Triple Video Filter Driver for RGB and YUV Signals
Functional Description
www.fairchildsemi.com
7
+5V
0.1µF
0.1µF
1.0 µF
1
YINA
14
YINA
0.1µF
VCC
2
UINA
UINA
220µF
75Ω
13
75Ω Video Cables
YOUT
75Ω
0.1µF
3
VINA
4
BYPASS
GND
U
220µF
75Ω
11
OUT
75Ω
300k
0.1µF
5
10
Y
YINB
0.1µF
GND
INB
6
220µF
75Ω
9
UINB
UINB
VOUT
75Ω
10k
0.1µF
V
12
VINA
7
INB
V
IN
INB
MUX
Figure 10.
(A/B)
8
AC-Couples YUV Line Driver with Single Video Loads
FMS6408 — Triple Video Filter Driver for RGB and YUV Signals
Typical Application Diagrams
+5V
0.1µF
0.1µF
1.0 µF
1
YINA
YINA
14
75Ω
13
75Ω
12
75Ω
11
75Ω
75Ω Video Cables
V CC
75Ω
0.1µF
2
UINA
UINA
YOUT
75Ω
0.1µF
3
VINA
VINA
BYPASS
75Ω
4
GND
UOUT
300kΩ
0.1µF
5
Y
YINB
75Ω
75Ω
10
INB
GND
75Ω
0.1µF
6
UINB
75Ω
9
UINB
VOUT
75Ω
0.1µF
10kΩ
7
VINB
8
VINB
Figure 11.
© 2004 Fairchild Semiconductor Corporation
FMS6408 Rev. 3.0.0
IN MUX (A/B)
DC-Couples YUV Line Driver with Dual Video Loads
www.fairchildsemi.com
8
Introduction
The average DC level for the U and V channels is set
by the clamp circuit to 1.125V. The signal is
symmetrical about this voltage, therefore:
The FMS6408 can drive dual 75Ω loads, where each
load consists of a 75Ω resistor in series with a 75Ω
termination resistor in the driven device. This
presents a 150Ω load to the output, so two similar
loads in parallel look like 75Ω from the output to
ground. In some cases, it may be desirable to drive a
single load on one or more outputs with a dual load
on the remaining outputs. This is an acceptable
loading condition, but can cause a slight degradation
in gain matching.
ILOAD (U) = 1.125 V / 75Ω = 15mA
(3)
The device dissipation due to this load is the internal
voltage drop multiplied by the load current:
PD (U) = (5V − 1.125V ) • 15mA = 58.125mW
(4)
Since the U and the V power dissipation are
approximately the same, the total dissipation due to
load can be estimated by:
Device Power Dissipation
The FMS6408 specifications provide a quiescent noload supply current of 52mA (typical). With a nominal
5V supply, this results in a power dissipation of
260mW. The overall power dissipation can be
significantly affected by the applied load, particularly
in DC-coupled applications. To calculate the total
power dissipation the typical output voltages and the
loading must be known.
PD (load) = P( Y ) + 2 • P(U) =
71mW + 2 • 58.125mW = 187.55mW
(5)
Assume a video signal on the Y channel that
averages 50% luminance with an output voltage of
1.55V, then calculate the load current:
This brings the typical total device power
dissipation to 260mW (quiescent power) +
187.55mW (load power) or 447.55mW. It is
advisable to calculate the highest possible power
dissipation using worst-case quiescent supply
current and the maximum allowable power supply
voltage. This result should be used when
calculating the die temperature rise with the
supplied θJA, thermal resistance value.
ILOAD ( Y ) = 1.55 V / 75Ω = 20.6mA
Field Time Distortion
The highest power dissipation occurs for YUV video
signals DC-coupled into dual video loads (refer to
Figure 3).
(1)
In applications with AC-coupled outputs, the ACcoupling capacitors dominate the field time distortion.
Performance is specified with 220µF coupling
capacitors; if better performance is desired, the
capacitors may be increased or the outputs may be
DC-coupled.
The device dissipation due to this load is the
internal voltage drop multiplied by the load current:
PD ( Y ) = (5 V − 1.55 V ) • 20.6mA = 71mW
(2)
FMS6408 — Triple Video Filter Driver for RGB and YUV Signals
Application Notes
+5V
VCC
75Ω
2.25V
1.55V
IY
Driver
YOUT
75Ω
0.85V
0.25V
75Ω
1.825V
75Ω
75Ω
+ VI Y -
1.125V
IU
Driver
75Ω
0.425V
75Ω
Ω
UOUT
75Ω
+ VIU 75Ω
1.825V
1.825V
1.125V
IV
Driver
75Ω
0.425V
75Ω
VOUT
75Ω
+ VI V -
Figure 12.
© 2004 Fairchild Semiconductor Corporation
FMS6408 Rev. 3.0.0
75Ω Video Cables
YUV Video Signals that are DC-Coupled into Dual Video Loads
www.fairchildsemi.com
9
FMS6408 — Triple Video Filter Driver for RGB and YUV Signals
Package Dimensions
Figure 13.
© 2004 Fairchild Semiconductor Corporation
FMS6408 Rev. 3.0.0
14-Lead, Thin Shrink Small Outline Package (TSSOP)
www.fairchildsemi.com
10
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FMS6408 — Triple Video Filter Driver for RGB and YUV Signals
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I31
© 2004 Fairchild Semiconductor Corporation
FMS6408 Rev. 3.0.0
www.fairchildsemi.com
11
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