Lattice ISPLSI1032EA-125LT100 In-system programmable high density pld Datasheet

ispLSI 1032EA
®
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally and Pinout Compatible with
ispLSI 1032E
• NEW FEATURES
— 100% IEEE 1149.1 Boundary Scan Testable
— ispJTAG™ In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User Selectable 3.3V or 5V I/O Supports MixedVoltage Systems (VCCIO Pin)
— Open-Drain Output Option
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0
C7
C6
A2
C5
D Q
Logic
Array
A3
D Q
GLB
A4
C4
C3
D Q
A5
A6
A7
Output Routing Pool
Output Routing Pool
D Q
A1
C2
C1
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7
C0
CLK
Output Routing Pool
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 200 MHz Maximum Operating Frequency
— tpd = 4.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
0139A(A1)-isp
Description
The ispLSI 1032EA is a High Density Programmable
Logic Device containing 192 Registers, 64 Universal I/O
pins, four Dedicated Input pins, four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1032EA features 5V in-system
programmability (ISP™) and in-system diagnostic capabilities via IEEE 1149.1 Test Access Port. The ispLSI
1032EA device offers non-volatile reprogrammability of
the logic, as well as the interconnects to provide truly
reconfigurable systems. A functional superset of the
ispLSI 1032 architecture, the ispLSI 1032EA device adds
user selectable 3.3V or 5V I/O and open-drain output
options.
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on the ispLSI 1032EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…D7 (Figure 1). There are a total of 32 GLBs in the
ispLSI 1032EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8037; http://www.latticesemi.com
1032ea_02
1
January 2000
Specifications ispLSI 1032EA
Functional Block Diagram
IN 3
IN 2
I/O 51
I/O 50
I/O 49
I/O 48
I/O 55
I/O 54
I/O 53
I/O 52
I/O 59
I/O 58
I/O 57
I/O 56
I/O 63
I/O 62
I/O 61
I/O 60
Figure 1. ispLSI 1032EA Functional Block Diagram
RESET
Input Bus
Generic
Logic Blocks
(GLBs)
Output Routing Pool (ORP)
D7
D6
D5
D4
D3
D2
D1
GOE 1/IN 1
GOE 0/IN 0
D0
I/O 47
I/O 46
I/O 45
I/O 44
C7
C5
A2
C4
Global
Routing
Pool
(GRP)
A3
A4
C3
C2
A5
lnput Bus
Output Routing Pool (ORP)
I/O 8
I/O 9
I/O 10
I/O 11
C6
A1
lnput Bus
I/O 4
I/O 5
I/O 6
I/O 7
A0
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
C1
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
A6
I/O 12
I/O 13
I/O 14
I/O 15
I/O 43
I/O 42
I/O 41
I/O 40
C0
A7
TDI
TMS
B0
B1
B2
B3
B4
B5
B6
B7
Clock
Distribution
Network
Output Routing Pool (ORP)
Megablock
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Input Bus
Y0
Y1
Y2
Y3
I/O 28
I/O 29
I/O 30
I/O 31
I/O 24
I/O 25
I/O 26
I/O 27
I/O 20
I/O 21
I/O 22
I/O 23
I/O 16
I/O 17
I/O 18
I/O 19
TDO
TCK
VCCIO
The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered input, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the
VCCIO pin to a common 5V or 3.3V power supply, I/O
output levels can be matched to 5V or 3.3V-compatible
voltages.
Clocks in the ispLSI 1032EA device are selected using
the Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (C0 on the ispLSI
1032EA device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.
Eight GLBs, 16 I/O cells, dedicated inputs (if available)
and one ORP are connected together to make a
Megablock (Figure 1). The outputs of the eight GLBs are
connected to a set of 16 universal I/O cells by the ORP.
Each ispLSI 1032EA device contains four Megablocks.
In addition to the standard output configuration, the
outputs of the ispLSI 1032EA are individually programmable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
Programmable Open-Drain Outputs
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
2
Specifications ispLSI 1032EA
Boundary Scan
Figure 2. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
Tbtsu
Tbtch
Tbth
Tbtcl
Tbtcp
TCK
Tbtvo
Tbtco
TDO
Valid Data
Tbtcpsu
Data to be
captured
Tbtoz
Valid Data
Tbtcph
Data Captured
Tbtuov
Tbtuco
Data to be
driven out
Symbol
Valid Data
Parameter
Tbtuoz
Valid Data
Min
Max
Units
tbtcp
TCK [BSCAN test] clock pulse width
100
–
ns
tbtch
TCK [BSCAN test] pulse width high
50
–
ns
tbtcl
TCK [BSCAN test] pulse width low
50
–
ns
tbtsu
TCK [BSCAN test] setup time
20
–
ns
tbth
TCK [BSCAN test] hold time
25
–
ns
trf
TCK [BSCAN test] rise and fall time
50
–
mV/ns
tbtco
TAP controller falling edge of clock to valid output
–
25
ns
tbtoz
TAP controller falling edge of clock to data output disable
–
25
ns
tbtvo
TAP controller falling edge of clock to data output enable
–
25
ns
tbtcpsu
BSCAN test Capture register setup time
40
–
ns
tbtcph
BSCAN test Capture register hold time
25
–
ns
tbtuco
BSCAN test Update reg, falling edge of clock to valid output
–
50
ns
tbtuoz
BSCAN test Update reg, falling edge of clock to output disable
–
50
ns
tbtuov
BSCAN test Update reg, falling edge of clock to output enable
–
50
ns
3
Specifications ispLSI 1032EA
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
PARAMETER
SYMBOL
VCC
Supply Voltage
MIN.
MAX.
UNITS
4.75
5.25
V
5V
4.75
5.25
V
3.3V
3.0
3.6
V
0.8
V
Vcc+1
V
Commercial
TA = 0°C to + 70°C
VCCIO
Supply Voltage: Output Drivers
VIL
VIH
Input Low Voltage
0
Input High Voltage
2.0
Table 2-0005/1032EA
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
C1
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
(Commercial/Industrial)
8
pf
VCC = 5.0V, VPIN = 2.0V
C2
Y0 Clock Capacitance
10
pf
VCC = 5.0V, VPIN = 2.0V
Table 2-0006/1032EA
Erase/Reprogram Specifications
PARAMETER
MINIMUM
MAXIMUM
UNITS
10000
–
Cycles
Erase/Reprogram Cycles
Table 2-0008/1032EA
4
Specifications ispLSI 1032EA
Switching Test Conditions
Input Pulse Levels
Figure 3. Test Load
GND to 3.0V
Input Rise and Fall Time 10% to 90%
1.5ns
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
+ 5V
1.5V
Output Load
R1
See Figure 3
Device
Output
Table 2-0003/1032EA
3-state levels are measured 0.5V from
steady-state active level.
Test
Point
CL*
R2
Output Load Conditions (see Figure 3)
TEST CONDITION
R1
R2
CL
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
A
B
C
*CL includes Test Fixture and Probe Capacitance.
0213a
Table 2-0004/1032EA
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.3
MAX. UNITS
VOL
VOH
IIL
Output Low Voltage
IOL = 8 mA
—
—
Output High Voltage
IOH = -4 mA
2.4
—
—
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
—
—
-10
µA
IIH
Input or I/O High Leakage Current
(VCCIO - 0.2)V ≤ VIN ≤ VCCIO
—
—
10
µA
VCCIO ≤ VIN ≤ 5.25V
—
—
10
µA
IIL-PU
IOS1
I/O Active Pull-Up Current
0V ≤ VIN ≤ 2.0V
-10
—
-250
µA
Output Short Circuit Current
VCCIO = 5.0V or 3.3V, VOUT = 0.5V
—
—
-240
mA
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
fTOGGLE = 1 MHz
—
153
—
mA
ICC2, 4, 5
0.4
V
Table 2-0007/1032EA
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Meaured using eight 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25°C.
4. Unused inputs held at 0.0V.
5. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book CD-ROM to estimate maximum ICC.
5
Specifications ispLSI 1032EA
External Timing Parameters
Over Recommended Operating Conditions
4
PARAMETER
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
tsu3
th3
1.
2.
3.
4.
-200
-170
TEST
COND.
#
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
—
4.0
—
5.0
ns
A
2
Data Propagation Delay, Worst Case Path
—
5.5
—
7.0
ns
200
—
170
—
MHz
167
—
125
—
MHz
250
—
222
—
MHz
3.0
—
3.5
—
ns
A
1
2
3
DESCRIPTION
Clock Frequency with Internal Feedback
MIN. MAX. MIN. MAX.
3
1
tsu2 + tco1
)
UNITS
—
4
Clock Frequency with External Feedback (
—
5
Clock Frequency, Max. Toggle
—
6
GLB Reg. Setup Time before Clock,4 PT Bypass
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
—
2.5
—
3.5
ns
—
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
—
0.0
—
ns
—
9
GLB Reg. Setup Time before Clock
3.5
—
4.5
—
ns
—
10 GLB Reg. Clock to Output Delay
—
3.0
—
4.5
ns
—
11 GLB Reg. Hold Time after Clock
0.0
—
0.0
—
ns
A
12 Ext. Reset Pin to Output Delay
—
13 Ext. Reset Pulse Duration
B
( twh 1+ twl )
—
5.5
—
7.0
ns
3.5
—
4.0
—
ns
14 Input to Output Enable
—
7.0
—
9.0
ns
C
15 Input to Output Disable
—
7.0
—
9.0
ns
B
16 Global OE Output Enable
—
4.5
—
6.5
ns
C
17 Global OE Output Disable
—
4.5
—
6.5
ns
—
18 External Synchronous Clock Pulse Duration, High
2.0
—
2.25
—
ns
—
19 External Synchronous Clock Pulse Duration, Low
2.0
—
2.25
—
ns
—
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
3.0
—
3.0
—
ns
—
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
0.0
—
0.0
—
ns
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
6
Table 2-0030A/1032EA
Specifications ispLSI 1032EA
External Timing Parameters
Over Recommended Operating Conditions
4
PARAMETER
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
tsu3
th3
1.
2.
3.
4.
-125
TEST
COND.
#
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
A
2
A
3
–
4
Clock Frequency with External Feedback ( tsu2 + tco1)
1
2
DESCRIPTION
-100
MIN. MAX. MIN. MAX.
–
7.5
Data Propagation Delay, Worst Case Path
–
Clock Frequency with Internal Feedback 3
125
1
(
1
twh + twl
)
UNITS
–
10.0
ns
10.0
–
12.5
ns
–
100
–
MHz
100
–
77
–
MHz
167
–
125
–
MHz
4.5
–
6.0
–
ns
–
5
Clock Frequency, Max. Toggle
–
6
GLB Reg. Setup Time before Clock,4 PT Bypass
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
4.5
–
6.0
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
0.0
–
ns
–
9
GLB Reg. Setup Time before Clock
5.5
–
7.0
–
ns
–
10 GLB Reg. Clock to Output Delay
–
5.5
–
7.0
ns
–
11 GLB Reg. Hold Time after Clock
0.0
–
0.0
–
ns
A
12 Ext. Reset Pin to Output Delay
–
10.0
–
13.5
ns
–
13 Ext. Reset Pulse Duration
5.0
–
6.5
–
ns
B
14 Input to Output Enable
–
12.0
–
15.0
ns
C
15 Input to Output Disable
–
12.0
–
15.0
ns
B
16 Global OE Output Enable
–
7.0
–
9.0
ns
C
17 Global OE Output Disable
–
7.0
–
9.0
ns
–
18 External Synchronous Clock Pulse Duration, High
3.0
–
4.0
–
ns
–
19 External Synchronous Clock Pulse Duration, Low
3.0
–
4.0
–
ns
–
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
3.0
–
3.5
–
ns
–
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
0.0
–
0.0
–
ns
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
7
Table 2-0030B/1032EA
Specifications ispLSI 1032EA
Internal Timing Parameters1
PARAM. #
2
-200
DESCRIPTION
-170
MIN. MAX. MIN. MAX.
UNITS
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
22 I/O Register Bypass
—
0.3
—
0.3
ns
23 I/O Latch Delay
—
4.0
—
4.0
ns
24 I/O Register Setup Time before Clock
3.0
—
3.0
—
ns
25 I/O Register Hold Time after Clock
0.0
—
0.0
—
ns
26 I/O Register Clock to Out Delay
—
4.0
—
4.6
ns
27 I/O Register Reset to Out Delay
—
4.0
—
4.6
ns
28 Dedicated Input Delay
—
1.1
—
1.8
ns
29 GRP Delay, 1 GLB Load
—
1.3
—
1.4
ns
30 GRP Delay, 4 GLB Loads
—
1.5
—
1.6
ns
31 GRP Delay, 8 GLB Loads
—
1.7
—
1.8
ns
GRP
tgrp1
tgrp4
tgrp8
tgrp16
tgrp32
32 GRP Delay, 16 GLB Loads
—
2.1
—
2.2
ns
33 GRP Delay, 32 GLB Loads
—
2.9
—
3.0
ns
34 4 ProductTerm Bypass Path Delay (Combinatorial)
—
1.4
—
2.1
ns
35 4 Product Term Bypass Path Delay (Registered)
—
1.5
—
2.0
ns
36 1 ProductTerm/XOR Path Delay
—
1.6
—
2.3
ns
37 20 Product Term/XOR Path Delay
—
1.6
—
2.2
ns
38 XOR Adjacent Path Delay 3
—
1.6
—
2.2
ns
39 GLB Register Bypass Delay
—
0.8
—
1.0
ns
40 GLB Register Setup Time before Clock
0.3
—
0.3
—
ns
41 GLB Register Hold Time after Clock
1.0
—
2.0
—
ns
42 GLB Register Clock to Output Delay
—
1.1
—
1.4
ns
43 GLB Register Reset to Output Delay
—
4.2
—
4.7
ns
44 GLB Product Term Reset to Register Delay
—
2.2
—
2.7
ns
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
tgfb
45 GLB Product Term Output Enable to I/O Cell Delay
—
2.3
—
3.6
ns
1.2
2.2
1.7
2.7
ns
47 GLB Feedback Delay
—
0.1
—
0.1
ns
48 ORP Delay
—
0.6
—
1.0
ns
—
0.1
—
0.1
ns
46 GLB Product Term Clock Delay
ORP
torp
torpbp
49 ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
Table 2-0036A/1032EA
Specifications ispLSI 1032EA
Internal Timing Parameters1
PARAM.
#
DESCRIPTION
-200
-170
MIN. MAX. MIN. MAX.
UNITS
Outputs
tob
tsl
toen
todis
tgoe
50 Output Buffer Delay
—
0.7
51 Output Buffer Delay, Slew Limited Adder
—
52 I/O Cell OE to Output Enabled
—
53 I/O Cell OE to Output Disabled
54 Global OE
—
0.9
ns
5.0
—
5.0
ns
2.9
—
3.3
ns
—
2.9
—
3.3
ns
—
1.6
—
2.6
ns
55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk)
0.6
0.6
0.9
0.9
ns
56 Clock Delay, Y1 or Y2 to Global GLB Clock Line
0.9
0.9
0.9
0.9
ns
57 Clock Delay, Clock GLB to Global GLB Clock Line
0.8
1.8
0.8
1.8
ns
58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
0.0
0.0
0.0
0.0
ns
0.8
2.8
0.8
2.8
ns
—
0.0
—
0.4
ns
Clocks
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
59 Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset
tgr
60 Global Reset to GLB and I/O Registers
1. Internal Timing Parameters are not tested and are for reference only.
9
Table 2-0037A/1032EA
Specifications ispLSI 1032EA
Internal Timing Parameters1
PARAM. #
2
-125
DESCRIPTION
-100
MIN. MAX. MIN. MAX.
UNITS
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
22 I/O Register Bypass
–
0.3
–
0.4
ns
23 I/O Latch Delay
–
4.0
–
4.0
ns
24 I/O Register Setup Time before Clock
3.0
–
3.4
–
ns
25 I/O Register Hold Time after Clock
0.0
–
0.0
–
ns
26 I/O Register Clock to Out Delay
–
4.6
–
5.0
ns
27 I/O Register Reset to Out Delay
–
4.6
–
5.0
ns
28 Dedicated Input Delay
–
1.9
–
2.2
ns
29 GRP Delay, 1 GLB Load
–
1.7
–
2.1
ns
30 GRP Delay, 4 GLB Loads
–
1.9
–
2.3
ns
31 GRP Delay, 8 GLB Loads
–
2.1
–
2.5
ns
32 GRP Delay, 16 GLB Loads
–
2.5
–
2.9
ns
33 GRP Delay, 32 GLB Loads
–
3.3
–
3.7
ns
34 4 Product Term Bypass Path Delay (Combinatorial)
–
3.4
–
4.9
ns
35 4 Product Term Bypass Path Delay (Registered)
–
3.1
–
4.9
ns
36 1 Product Term/XOR Path Delay
–
3.6
–
4.3
ns
37 20 Prod. Term/XOR Path Delay
–
3.6
–
4.3
ns
38 XOR Adjacent Path Delay 3
–
3.6
–
4.3
ns
39 GLB Register Bypass Delay
–
1.2
–
2.1
ns
40 GLB Register Setup Time before Clock
0.3
–
0.3
–
ns
41 GLB Register Hold Time after Clock
3.5
–
4.8
–
ns
42 GLB Register Clock to Output Delay
–
1.4
–
1.7
ns
43 GLB Register Reset to Output Delay
–
4.9
–
5.0
ns
44 GLB Product Term Reset to Register Delay
–
3.8
–
4.5
ns
GRP
tgrp1
tgrp4
tgrp8
tgrp16
tgrp32
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
tgfb
45 GLB Product Term Output Enable to I/O Cell Delay
–
5.2
–
7.2
ns
2.8
3.9
3.5
4.7
ns
47 GLB Feedback Delay
–
0.6
–
1.4
ns
48 ORP Delay
–
1.3
–
1.4
ns
49 ORP Bypass Delay
–
0.2
–
0.4
ns
46 GLB Product Term Clock Delay
ORP
torp
torpbp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
10
Table 2-0036B/1032EA
Specifications ispLSI 1032EA
Internal Timing Parameters1
PARAM.
#
-125
DESCRIPTION
-100
MIN. MAX. MIN. MAX.
UNITS
Outputs
tob
tsl
toen
todis
tgoe
50 Output Buffer Delay
—
1.7
—
2.0
ns
51 Output Buffer Delay, Slew Limited Adder
—
5.0
—
5.0
ns
52 I/O Cell OE to Output Enabled
—
4.0
—
5.1
ns
53 I/O Cell OE to Output Disabled
—
4.0
—
5.1
ns
54 Global OE
—
3.0
—
3.9
ns
55 Clock Delay, Y0 to Global GLB Clk Line (Ref. Clock)
1.1
1.1
1.9
1.9
ns
56 Clock Delay, Y1 or Y2 to Global GLB Clock Line
0.9
0.9
1.5
1.5
ns
57 Clock Delay, Clock GLB to Global GLB Clock Line
0.8
1.8
0.8
1.8
ns
58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
0.0
0.0
0.0
0.0
ns
59 Clock Delay, Clock GLB to I/O Cell Global Clock Line
0.8
2.8
0.8
2.8
ns
—
2.1
—
5.1
ns
Clocks
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
Global Reset
tgr
60 Global Reset to GLB and I/O Registers
1. Internal Timing Parameters are not tested and are for reference only.
11
Table 2-0037B/1032EA
Specifications ispLSI 1032EA
ispLSI 1032EA Timing Model
I/O Cell
GRP
GLB
#47
Ded. In
I/O Pin
(Input)
#60
Comb 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#22
#30
#35
#39
#49
Input
D Register Q
RST
#23 - 27
GRP Loading
Delay
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
#29, 31 - 33
#36 - 38
I/O Reg Bypass
GRP4
I/O Cell
Feedback
#34
#28
ORP
Reg 4 PT Bypass
D
Q
#50, 51
#52, 53
#48
RST
#60
Reset
Clock
Distribution
Y1,2,3
#56 - 59
#40 - 43
Control RE
PTs
OE
#44 - 46 CK
0491/1032EA
#54
Y0
#53
GOE 0,1
Derivations of tsu, th and tco from the Product Term Clock 1
tsu
=
=
=
0.7 =
Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))
(#22 + #30 + #37) + (#40) - (#22 + #30 + #46)
(0.3 + 1.5 + 1.6) + (0.3) - (0.3 + 1.5 + 1.2)
th
=
=
=
1.6 =
Clock (max) + Reg h - Logic
(tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 1.5 + 2.2) + (1.0) - (0.3 + 1.5 + 1.6)
tco
=
=
=
6.7 =
Clock (max) + Reg co + Output
(tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
(#22 + #30 + #46) + (#42) + (#48 + #50)
(0.3 + 1.5 + 2.2) + (1.4) + (0.6 + 0.7)
Derivations of tsu, th and tco from the Clock GLB 1
tsu
=
=
=
0.9 =
Logic + Reg (setup) - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))
(#22 + #30 + #37) + (#40) - (#55 + #42 + #57)
(0.3 + 1.5 + 1.6) + (0.3) - (0.6 + 1.4 + 0.8)
th
=
=
=
1.1 =
Clock (max) + Reg (hold) - Logic
(tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#55 + #42 + #57) + (#41) - (#22 + #30 + #37)
(0.6 + 1.1 + 1.8) + (1.0) - (0.3 + 1.5 + 1.6)
tco
=
=
=
5.9 =
Clock (max) + Reg (clock-to-out) + Output
(tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
(#55 + #42 + #57) + (#42) + (#48 + #50)
(0.6 + 1.1 + 1.8) + (1.1) + (0.6 + 0.7)
1. Calculations are based upon timing specifications for the ispLSI 1032EA-200.
Table 2-0042a/1032EA
12
I/O Pin
(Output)
Specifications ispLSI 1032EA
Maximum GRP Delay vs GLB Loads
6
GRP Delay (ns)
5
4
ispLSI 1032EA-100
ispLSI 1032EA-125
ispLSI 1032EA-170
ispLSI 1032EA-200
3
2
1
1
4
8
16
32
GLB Load
GRP/GLB/1032EA
Power Consumption
Power consumption in the ispLSI 1032EA device depends on two primary factors: the speed at which the
device is operating, and the number of product terms
used. Figure 4 shows the relationship between power
and operating speed.
Figure 4. Typical Device Power Consumption vs fmax
260
ispLSI 1032EA
240
ICC (mA)
220
200
180
160
140
120
100
0
50
100
150
fmax (MHz)
200
250
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25°C
Icc can be estimated for the ispLSI 1032EA using the following equation:
Icc = 20mA + (# of PTs * .52) + (# of nets * Max Freq * .003)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of Icc is sensitive to operating
conditions and the program in the device, the actual Icc should be verified.
0127/1032EA
13
Specifications ispLSI 1032EA
Pin Description
NAME
TQFP PIN
NUMBERS
18,
22,
30,
34,
41,
45,
53,
57,
68,
72,
80,
84,
91,
95,
3,
7,
19,
23,
31,
35,
42,
46,
54,
58,
69,
73,
81,
85,
92,
96,
4,
8,
DESCRIPTION
20, Input/Output Pins - These are the general purpose I/O pins used by the logic array.
28,
32,
36,
43,
47,
55,
59,
70,
78,
82,
86,
93,
97,
5,
9
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
17,
21,
29,
33,
40,
44,
48,
56,
67,
71,
79,
83,
90,
94,
98,
6,
GOE 0/IN 02
66
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
GOE 1/IN 12
87
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
IN 2, IN 3
89,
TDI
16
Input - Functions as an input pin to load programming data into the device and also used as one of
the two control pins for the ispJTAG state machine.
TMS
37
Input - Controls the operation of the ISP state machine.
TDO
39
Output - Functions as an output pin to read serial shift register data.
TCK
60
Input - Functions as a clock pin for the Serial Shift Register.
RESET
15
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
Y0
11
Y1
65
Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on
the device.
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB on the device.
Y2
62
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB and/or any I/O cell on the device.
Y3
61
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any I/O cell on the device.
GND
VCC
13, 38, 63, 88
12, 64
Ground (GND)
VCCIO
14
Supply voltage for output drivers, 5V or 3.3V.
NC1
1,
26,
51,
76,
Dedicated input pins to the device.
10
2,
27,
52,
77,
24,
49,
74,
99,
Vcc
25, No connect.
50,
75,
100
1. NC pins are not to be connected to any active signals, Vcc or GND.
2. Pins have dual function capability which is software selectable.
14
Table 2-0002A/1032EA
Specifications ispLSI 1032EA
Pin Configurations
2NC
2NC
ispLSI 1032EA
Top View
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC2
NC2
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
GOE 0/IN 01
Y1
VCC
GND
Y2
Y3
TCK
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
NC2
NC2
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
TMS
GND
TDO
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
2NC
2NC
2NC
2NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
IN 3
Y0
VCC
GND
VCCIO
RESET
TDI
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
2NC
2NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NC2
NC2
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 2
GND
GOE 1/IN 11
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
NC2
NC2
ispLSI 1032EA 100-Pin TQFP Pinout Diagram
1. Pins have dual function capability which is software selectable.
2. NC pins are not to be connected to any active signal, VCC or GND.
100-TQFP/1032EA
15
Specifications ispLSI 1032EA
Part Number Description
ispLSI 1032EA - XXX
X
XXXX X
Device Family
Grade
Blank = Commercial
Package
T100 = 100-Pin TQFP
Device Number
Power
L = Low
Speed
200 = 200 MHz fmax
170 = 170 MHz fmax
125 = 125 MHz fmax
100 = 100 MHz fmax
0212/1032EA
ispLSI 1032EA Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
200
4.0
ispLSI 1032EA-200LT100
100-Pin TQFP
170
5.0
ispLSI 1032EA-170LT100
100-Pin TQFP
125
7.5
ispLSI 1032EA-125LT100
100-Pin TQFP
100
10
ispLSI 1032EA-100LT100
100-Pin TQFP
Table 2-0041A/1032EA
16
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