BSI BS62UV2001STI Ultra low power/voltage cmos sram 256k x 8 bit Datasheet

Ultra Low Power/Voltage CMOS SRAM
256K X 8 bit
BSI
BS62UV2001
„ DESCRIPTION
„ FEATURES
• Wide Vcc operation voltage : 1.8V ~ 3.6V
• Ultra low power consumption :
Vcc = 2.0V C-grade : 15mA (Max.) operating current
I- grade : 20mA (Max.) operating current
0.08uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns(Max.) at Vcc = 2.0V
-10
100ns(Max.) at Vcc = 2.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
The BS62UV2001 is a high performance, Ultra low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA and maximum access time of 70ns in 3.0V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62UV2001 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62UV2001 is available in the JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.
„ PRODUCT FAMILY
PRODUCT
FAMILY
BS62UV2001TC
BS62UV2001STC
BS62UV2001SC
BS62UV2001TI
BS62UV2001STI
BS62UV2001SI
OPERATING
TEMPERATURE
•
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
BS62UV2001TC
BS62UV2001STC
BS62UV2001TI
BS62UV2001STI
1
2
3
4
5
6
7 BS62UV2001SC
8 BS62UV2001SI
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Operating
(I CCSB1 , Max)
Vcc=2V
Vcc=3V
PKG TYPE
(ICC , Max)
Vcc=2V Vcc=3V Vcc=2V
70 / 100
0.7uA
0.5uA
20mA
15mA
O
1.8~3.6V
70 / 100
1.5uA
1uA
25mA
20mA
-40 C to +85 C
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
POWER DISSIPATION
STANDBY
1.8~3.6V
TSOP - 32
STSOP - 32
SOP - 32
TSOP - 32
STSOP - 32
SOP - 32
„ BLOCK DIAGRAM
„ PIN CONFIGURATIONS
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
SPEED
(ns)
O
+0OC to +70 C
O
Vcc
RANGE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A13
A17
A15
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
20
Row
1024
Memory Array
1024 x 2048
Decoder
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
CE1
CE2
WE
OE
Vdd
Gnd
8
8
Data
Input
Buffer
Data
Output
Buffer
Column I/O
8
8
Write Driver
Sense Amp
256
Column Decoder
16
Control
Address Input Buffer
A11 A9 A8 A3 A2 A1 A0 A10
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62UV2001
1
Revision 2.4
April 2002
BSI
BS62UV2001
„ PIN DESCRIPTIONS
Name
Function
A0-A17 Address Input
These 18 address inputs select one of the 262,144 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
„ TRUTH TABLE
MODE
WE
CE1
CE2
OE
Not selected
(Power Down)
X
H
X
X
X
X
L
X
Output Disabled
H
L
H
Read
H
L
H
Write
L
L
H
PARAMETER
I CCSB, I CCSB1
H
High Z
I CC
L
D OUT
I CC
X
D IN
I CC
„ OPERATING RANGE
RATING
UNITS
-0.5 to
Vcc+0.5
V
VTERM
Terminal Voltage with
Respect to GND
TBIAS
Temperature Under Bias
-40 to +125
O
TSTG
Storage Temperature
-60 to +150
O
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
C
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0 O C to +70 O C
1.8V ~ 3.6V
Industrial
O
O
-40 C to +85 C
1.8V ~ 3.6V
C
„ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
R0201-BS62UV2001
Vcc CURRENT
High Z
„ ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
I/O OPERATION
2
CIN
CDQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V
6
pF
VI/O=0V
8
pF
1. This parameter is guaranteed and not tested.
Revision 2.4
April 2002
BSI
BS62UV2001
„ DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER
NAME
V IL
V IH
IIL
PARAMETER
TEST CONDITIONS
Guaranteed Input Low
Voltage (2)
Guaranteed Input High
Voltage (2)
MIN.
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Input Leakage Current
Vcc = Max, V IN = 0V to Vcc
IOL
Output Leakage Current
Vcc = Max, CE1 = V IH or CE2=V IL
or OE = V IH, V I/O = 0V to Vcc
V OL
Output Low Voltage
Vcc = Max, IOL = 1mA
TYP. (1)
MAX.
UNITS
-0.5
-0.5
1.4
2.0
--
------
0.6
0.8
Vcc+0.2
Vcc+0.2
1
uA
--
--
1
uA
------
0.4
0.4
--15
V OH
Output High Voltage
Vcc = Min, IOH = -0.5mA
Operating Power Supply
Current
Vcc = Max, CE1= V IL, CE2=V IH
IDQ = 0mA, F = Fmax(3)
Vcc=2.0V
ICC
--1.6
2.4
--
Vcc=3.0V
--
--
20
Standby Current-TTL
Vcc = Max, CE1 = V IH or CE2=V IL
IDQ = 0mA
Vcc=2.0V
ICCSB
--
--
0.6
Vcc=3.0V
--
--
1
--
0.08
0.5
Standby Current-CMOS
Vcc = Max, CE1ЊVcc-0.2V or
CE2Љ0.2V ;V INЊ Vcc - 0.2V or
V INЉ0.2V
Vcc=2.0V
ICCSB1
Vcc=3.0V
--
0.1
0.7
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
V
V
V
V
mA
mA
uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
„ DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
VDR
Vcc for Data Retention
CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
1.5
--
--
V
ICCDR
Data Retention Current
CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
--
0.01
0.5
uA
tCDR
Chip Deselect to Data
Retention Time
--
--
ns
--
--
ns
tR
See Retention Waveform
Operation Recovery Time
0
TRC
(2)
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
„ LOW VCC DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
Data Retention Mode
Vcc
VDR ≥ 1.5V
Vcc
CE1
Vcc
tR
t CDR
CE1 ≥ Vcc - 0.2V
VIH
„ LOW VCC DATA RETENTION WAVEFORM (2)
VIH
( CE2 Controlled )
Data Retention Mode
Vcc
VDR Њ 1.5V
Vcc
CE2
R0201-BS62UV2001
VIL
Vcc
tR
t CDR
CE2 Љ 0.2V
3
VIL
Revision 2.4
April 2002
BSI
BS62UV2001
„ KEY TO SWITCHING WAVEFORMS
„ AC TEST CONDITIONS
Vcc/0V
5ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
1333 Ω
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
5PF
DON T CARE:
ANY CHANGE
PERMITTED
CHANGE :
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
0.5Vcc
„ AC TEST LOADS AND WAVEFORMS
1333 Ω
2V
2V
OUTPUT
,
OUTPUT
100PF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
2000 Ω
2000 Ω
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
800 Ω
OUTPUT
1.2V
ALL INPUT PULSES
Vcc
GND
90% 90%
10%
→
←
→
10%
← 5ns
FIGURE 2
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 2.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
tAVAX
tAVQV
t E1LQV
t E2HOV
tGLQV
t E1LQX
t E2HOX
tGLQX
t E1HQZ
tE2HQZ
tGHQZ
tRC
tAA
t ACS1
t ACS2
tOE
t CLZ1
t CLZ2
tOLZ
t CHZ1
t CHZ2
tOHZ
tAXOX
tOH
R0201-BS62UV2001
BS62UV2001-70
MIN. TYP. MAX.
DESCRIPTION
Read Cycle Time
BS62UV2001-10
MIN. TYP. MAX.
UNIT
70
--
--
100
--
--
ns
--
--
70
--
--
100
ns
Chip Select Access Time
(CE1)
--
--
70
--
--
100
ns
Chip Select Access Time
(CE2)
--
--
70
--
--
100
ns
--
--
35
--
--
50
ns
Address Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
(CE1)
10
--
--
15
--
--
ns
Chip Select to Output Low Z
(CE2)
10
--
--
15
--
--
ns
10
--
--
15
--
--
ns
Chip Deselect to Output in High Z
(CE1)
0
--
35
0
--
40
ns
Chip Deselect to Output in High Z
(CE2)
0
--
35
0
--
40
ns
0
--
30
0
--
35
ns
10
--
--
15
--
--
ns
Output Enable to Output in Low Z
Output Disable to Output in High Z
Output Disable to Output Address Change
4
Revision 2.4
April 2002
BSI
BS62UV2001
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t RC
ADDRESS
t
t
t OH
AA
OH
D OUT
READ CYCLE2 (1,3,4)
CE1
CE2
t
t
ACS1
t
ACS2
t
(5)
(5)
CHZ1,
t
CHZ2
CLZ
D OUT
READ CYCLE3 (1,4)
t RC
ADDRESS
t
AA
OE
t
t
CE1
t
CE2
(5)
t
OH
OLZ
t ACS1
CLZ1
t
t
OE
t OHZ (5)
(1,5)
t CHZ1
ACS2
t
(5)
(2,5)
CHZ2
CLZ2
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS62UV2001
5
Revision 2.4
April 2002
BSI
BS62UV2001
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 2.0V )
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
BS62UV2001-70
MIN. TYP. MAX.
DESCRIPTION
BS62UV2001-10
MIN. TYP. MAX.
UNIT
tAVAX
tWC
Write Cycle Time
70
--
--
100
--
--
ns
t E1LWH
tCW
Chip Select to End of Write
70
--
--
100
--
--
ns
tAVWL
tAS
Address Set up Time
0
--
--
0
--
--
ns
tAVWH
tAW
Address Valid to End of Write
70
--
--
100
--
--
ns
tWLWH
tWP
Write Pulse Width
35
--
--
50
--
--
ns
tWHAX
t WR1
Write Recovery Time
(CE1 , WE)
0
--
--
0
--
--
ns
t E2LAX
t WR2
Write Recovery Time
(CE2)
0
--
--
0
--
--
ns
tWLOZ
tWHZ
Write to Output in High Z
0
--
30
0
--
40
ns
tDVWH
tDW
Data to Write Time Overlap
30
--
--
40
--
--
ns
tWHDX
tDH
Data Hold from Write Time
0
--
--
0
--
--
ns
tGHOZ
tOHZ
Output Disable to Output in High Z
0
--
30
0
--
40
ns
tWHQX
tOW
End of Write to Output Active
5
--
--
10
--
--
ns
„ SWITCHING WAVEFORMS (WRITE CYCLE)
t WC
WRITE CYCLE1 (1)
ADDRESS
t
(3)
WR1
OE
(11)
t CW
(5)
CE1
(5)
CE2
t CW
t
WE
(11)
t WR2
AW
t
t AS
(3)
WP
(2)
(4,10)
t OHZ
D OUT
t DH
t DW
D IN
R0201-BS62UV2001
6
Revision 2.4
April 2002
BSI
BS62UV2001
WRITE CYCLE2 (1,6)
t WC
ADDRESS
(11)
t
(5)
CW
CE1
CE2
(5)
(11)
t
t CW
AW
t WR2
t WP
(3)
(2)
WE
t
t AS
DH
(4,10)
t WHZ
D OUT
(7)
(8)
t DW
t
DH
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BS62UV2001
7
Revision 2.4
April 2002
BSI
BS62UV2001
„ ORDERING INFORMATION
BS62UV2001
X X
ˀˀ Y Y
SPEED
70: 70ns
10: 100ns
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
S: SOP
„ PACKAGE DIMENSIONS
STSOP - 32
R0201-BS62UV2001
8
Revision 2.4
April 2002
BSI
BS62UV2001
„ PACKAGE DIMENSIONS (continued)
TSOP - 32
WITH PLATING
b
c c1
BASE METAL
b1
SECTION A-A
SOP -32
R0201-BS62UV2001
9
Revision 2.4
April 2002
BSI
BS62UV2001
REVISION HISTORY
Revision
Description
Date
2.2
2001 Data Sheet release
Apr. 15, 2001
2.3
Modify Standby Current (Typ.
and Max.)
Jun. 29, 2001
2.4
Modify some AC parameters
April,11,2002
R0201-BS62UV2001
10
Note
Revision 2.4
April 2002
Similar pages