IDT IDT82V2058BB Octal e1 short haul line interface unit Datasheet

OCTAL E1 SHORT HAUL
LINE INTERFACE UNIT
FEATURES
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Fully integrated octal E1 short haul line interface which
supports 120Ω E1 twisted pair and 75Ω E1 coaxial applications
Selectable single rail or dual rail mode and AMI or HDB3
line encoder/decoder
Built-in transmit pre-equalization meets G.703
Selectable transmit/receive jitter attenuator meets ETSI
CTR12/13, ITU G.736, G.742 and G.823 specifications
SONET/SDH optimized jitter attenuator meets ITU G.783
mapping jitter specification
Digital/analog LOS detector meets ITU G.775 and ETS 300
233
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IDT82V2058
ITU G.772 non-intrusive monitoring for in-service testing
for any one of channel1 to channel7
Low impedance transmit drivers with tri-state
Selectable hardware and parallel/serial host interface
Local and remote loopback test functions
Hitless Protection Switching (HPS) for 1 to 1 protection
without relays
JTAG boundary scan for board test
3.3V supply with 5V tolerant I/O
Low power consumption
Operating temperature range: -40°C to +85°C
Available in 144-pin Thin Quad Flat Pack (TQFP_144_DA)
and 160-pin Plastic Ball Grid Array (PBGA) packages
FUNCTIONAL BLOCK DIAGRAM
One of Eight Identical Channels
LOS
Detector
RTIPn
CLK&Data
Recovery
(DPLL)
Slicer
RRINGn
Analog
Loopback
Line
Driver
TRINGn
Jitter
Attenuator
Digital
Loopback
Peak
Detector
TTIPn
LOSn
Waveform
Shaper
Remote
Loopback
Jitter
Attenuator
RCLKn
RDn/RDPn
CVn/RDNn
HDB3/AMI
Decoder
AIS
Detector
TCLKn
TDn/TDPn
BPVIn/TDNn
HDB3/AMI
Encoder
Transmit
All Ones
JTAG TAP
VDD IO
VDDT
VDDD
VDDA
TRST
TCK
TMS
TDI
TDO
Control Interface
OE
CLKE
MODE[2:0]
CS/JAS
SCLK/ALE/AS
RD/R/W
SDI/WR/DS
SD0/RDY/ACK
INT
LP/D/AD[7:0]
MC/A[4:0]
Register
File
Clock
Generator
MCLK
G.772
Monitor
Figure - 1. Block Diagram
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
JANUARY 2003
INDUSTRIAL TEMPERATURE RANGES
1
 2002 Integrated Device Technology, Inc.
DSC-6038/9
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
DESCRIPTION:
tenuation performance meets ETSI CTR12/13, ITU G.736, G.742, and
G.823 specifications.
The IDT82V2058 offers hardware control mode and software control mode. Software control mode works with either serial host interface
or parallel host interface. The latter works via an Intel/Motorola compatible 8-bit parallel interface for both multiplexed or nonmultiplexed applications. Hardware control mode uses
multiplexed pins to select different operation mode when host interface is not available to the device.
The IDT82V2058 also provides loopback testing functions and
JTAG boundary scan testing functions. As the monitoring function is
integrated, IDT82V2058 can be configured as a 7-channel transceiver
with non-intrusive protected monitoring points.
The IDT82V2058 can be used for SDH/SONET multiplexers, central office or PBX, digital access cross connects, digital radio base stations, remote wireless modules and microwave transmission systems.
The IDT82V2058 is a single chip, 8-channel E1 short haul PCM
transceiver with a reference clock of 2.048MHz. It contains 8 transmitters and 8 receivers.
Both receivers and transmitters can be programmed to work either
in single rail mode or dual rail mode. AMI or HDB3 encoder/decoder
is selectable in single rail mode. Pre-encoded transmit data in NRZ
format can be accepted when the device is configured in dual rail
mode. The receivers perform clock and data recovery by using
integrated digital phase-locked loop. As an option, the raw sliced data
(no retiming) can be output on the receive data pins. Transmit
equalization is implemented with low-impedance output drivers that
provide shaped waveforms to the transformer, guaranteeing template
conformance.
A jitter attenuator is integrated in the IDT82V2058 and can be
switched into either the transmit path or the receive path. The jitter at-
IDT
82V2058DA
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
TD7/TDP7
TCLK7
LOS6
CV6/RDN6
RD6/RDP6
RCLK6
BPVI6/TDN6
TD6/TDP6
TCLK6
MCLK
MODE2
A4
MC3/A3
MC2/A2
MC1/A1
MC0/A0
VDDIO
GNDIO
VDDD
GNDD
LP0/D0/AD0
LP1/D1/AD1
LP2/D2/AD2
LP3/D3/AD3
LP4/D4/AD4
LP5/D5/AD5
LP6/D6/AD6
LP7/D7/AD7
TCLK1
TD1/TDP1
BPVI1/TDN1
RCLK1
RD1/RDP1
CV1/RDN1
LOS1
TCLK0
BPVI4/TDN4
RCLK4
RD4/RDP4
CV4/RDN4
LOS4
OE
CLKE
VDDT4
TTIP4
TRING4
GNDT4
RTIP4
RRING4
GNDT5
TRING5
TTIP5
VDDT5
RRING5
RTIP5
VDDT6
TTIP6
TRING6
GNDT6
RTIP6
RRING6
GNDT7
TRING7
TTIP7
VDDT7
RRING7
RTIP7
LOS7
CV7/RDN7
RD7/RDP7
RCLK7
BPVI7/TDN7
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TD4/TDP4
TCLK4
LOS5
CV5/RDN5
RD5/RDP5
RCLK5
BPVI5/TDN5
TD5/TDP5
TCLK5
TDI
TDO
TCK
TMS
TRST
IC
IC
VDDIO
GNDIO
VDDA
GNDA
MODE0/CODE
CS/JAS
SCLK/ALE/AS
RD/R/W
SDI/WR/DS
SDO/RDY/ACK
INT
TCLK2
TD2/TDP2
BPVI2/TDN2
RCLK2
RD2/RDP2
CV2/RDN2
LOS2
TCLK3
TD3/TDP3
PIN CONFIGURATIONS
Figure - 2. TQFP144 Package Pin Assignment
2
BPVI3/TDN3
RCLK3
RD3/RDP3
CV3/RDN3
LOS3
RTIP3
RRING3
VDDT3
TTIP3
TRING3
GNDT3
RRING2
RTIP2
GNDT2
TRING2
TTIP2
VDDT2
RTIP1
RRING1
VDDT1
TTIP1
TRING1
GNDT1
RRING0
RTIP0
GNDT0
TRING0
TTIP0
VDDT0
MODE1
LOS0
CV0/RDN0
RD0/RDP0
RCLK0
BPVI0/TDN0
TD0/TDP0
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONTINUED)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1
RCLK
7
TCLK
7
RCLK
6
TCLK
6
MCLK
MC
1
LP
6
LP
7
TCLK
1
RCLK
1
TCLK
0
RCLK
0
1
2
RDP
7
TDP
7
RDP
6
TDP
6
MODE
2
MC
2
LP
0
LP
2
LP
5
MODE
1
TDP
1
RDP
1
TDP
0
RDP
0
2
3
RDN
7
TDN
7
RDN
6
TDN
6
LOS
6
MC
3
MC
0
LP
1
LP
4
LOS
1
TDN
1
RDN
1
TDN
0
RDN
0
3
4
VDDT
7
VDDT
7
VDDT
6
VDDT
6
LOS
7
A4
LP
3
LOS
0
VDDT VDDT VDDT
1
1
0
VDDT
0
4
5
TRING
7
TTIP
7
TRING
6
TTIP
6
TTIP
1
TRING
0
5
6
GNDT GNDT GNDT GNDT
7
7
6
6
GNDT GNDT GNDT GNDT
1
1
0
0
6
7
RTIP RRING
7
7
RTIP
6
RRING
6
RRING RTIP
1
1
RRING
0
RTIP
0
7
8
RTIP RRING
4
4
RTIP
5
RRING
5
RRING RTIP
2
2
RRING
3
RTIP
3
8
9
GNDT GNDT GNDT GNDT
4
4
5
5
GNDT GNDT GNDT GNDT
2
2
3
3
9
10
TRING
4
TTIP
4
TRING
5
TTIP
5
TTIP
2
11
VDDT
4
VDDT
4
VDDT
5
VDDT
5
LOS
4
TMS
12
RDN
4
TDN
4
RDN
5
TDN
5
LOS
5
TDI
TRST
13
RDP
4
TDP
4
RDP
5
TDP
5
CLKE
TDO
IC
14
RCLK
4
TCLK
4
RCLK
5
TCLK
5
OE
TCK
A
B
C
D
E
F
VDDIO VDDD
GNDIO GNDD
IDT82V2058
Bottom View
GNDIO GNDA
CS
MODE
SCLK
0
IC
VDDIO VDDA
G
H
LOS
3
TRING
2
TTIP
0
TTIP
3
TRING
3
10
VDDT VDDT VDDT
2
2
3
VDDT
3
11
LOS
2
TDN
2
RDN
2
TDN
3
RDN
3
12
RD
INT
TDP
2
RDP
2
TDP
3
RDP
3
13
SDI
SDO
TCLK
2
RCLK
2
TCLK
3
RCLK
3
14
J
K
L
M
N
P
Figure - 2b. PBGA160 Package Pin Assignment
3
TRING
1
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION
Name
TTIP0
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7
TRING0
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
RTIP0
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7
RRING0
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
1
Type
Analog
Output
Analog
Input
Pin No.
QFP144 BGA160
45
52
57
64
117
124
129
136
N5
L5
L10
N10
B10
D10
D5
B5
46
51
58
63
118
123
130
135
48
55
60
67
120
127
132
139
P5
M5
M10
P10
A10
C10
C5
A5
P7
M7
M8
P8
A8
C8
C7
A7
49
54
61
66
121
126
133
138
N7
L7
L8
N8
B8
D8
D7
B7
Description
Transmit and Receive Line Interface
TTIPn/TRINGn: Transmit Bipolar Tip/Ring for Channel 0~7
These pins are the differential line driver outputs. They will be in high impedance state if pin OE
is low or the corresponding pin TCLKn is low (pin OE is globe control, while pin TCLKn is perchannel control). In host mode, each pin can be in high impedance state by programming a “1” to
the corresponding bit in Register OE1.
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 0~7
These pins are the differential line receiver inputs.
Register name is indicated by bold capital letter. OE: Output Enable Register.
4
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name
Type
TD0/TDP0
TD1/TDP1
TD2/TDP2
TD3/TDP3
TD4/TDP4
TD5/TDP5
TD6/TDP6
TD7/TDP7
Pin No.
QFP144 BGA160
N2
37
L2
30
L13
80
N13
73
B13
108
D13
101
D2
8
B2
1
I
38
31
79
72
109
102
7
144
BPVI0/TDN0
BPVI1/TDN1
BPVI2/TDN2
BPVI3/TDN3
BPVI4/TDN4
BPVI5/TDN5
BPVI6/TDN6
BPVI7/TDN7
TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
I
36
29
81
74
107
100
9
2
N3
L3
L12
N12
B12
D12
D3
B3
N1
L1
L14
N14
B14
D14
D1
B1
Description
TDn: Transmit Data for Channel 0~7
When the device is in Single Rail mode, the NRZ data to be transmitted is input on this pin. Data
on TDn is sampled into the device on falling edges of TCLKn, and encoded by AMI or HDB3 line
code rules before being transmitted to the line.
BPVIn: Bipolar Violation Insertion for Channel 0~7
Bipolar violation insertion is available in Signal Rail mode 2 (see table-1) with AMI enabled. A lowto-high transition on this pin will make the next logic one to be transmitted on TDn pin the same
polarity as the previous pulse, and violate the AMI rule. This is for testing.
TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7
When the device is in Dual Rail mode, the NRZ data to be transmitted for positive/negative pulse
is input on this pin. Data on TDPn/TDNn are active high and sampled into the device on falling
edges of TCLKn. The line code in Dual Rail mode is as the follows :
TDPn TDNn Output Pulse
0
0
Space
0
1
Negative Pulse
1
0
Positive Pulse
1
1
Space
Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the
corresponding channel into Single Rail mode 1 (see table-1 on Page13).
TCLKn: Transmit Clock for Channel 0~7
The clock of 2.048 MHz to be transmitted is input on this pin. The transmit data at TDn/TDPn or
TDNn is sampled into the device on falling edges of TCLKn.
Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in
Transmit All One (TAO) state (when MCLK is clocked). In TAO state, the TAO generator adopts
MCLK as the time reference.
If TCLKn is Low, the corresponding transmit channel is set into power down state, while driver
output ports become high impedance.
The different operating modes of TCLKn are summarized as follows:
MCLK
TCLKn
Transmitter Mode
Clocked
Clocked
Normal operation
Clocked
High (≥ 16 MCLK) Transmit All One (TAO) signals to line side in the
corresponding transmit channel.
Clocked
Low (≥ 64 MCLK) Corresponding transmit channel is set into power down state.
High/Low
TCLK1 is clocked TCLKn is clocked Normal operation
TCLKn is high
Transmit All One (TAO) signals to the line
side in the corresponding transmit channel.
(≥ 16 TCLK1)
TCLKn is low
Corresponding transmit channel is set into
power down state.
(≥ 64 TCLK1)
The receive path is not affected by the status of TCLK1.
When MCLK is high, all receive paths just slice the incoming
data stream. When MCLK is low, all the receive paths are
powered down.
High/Low
TCLK1 is not
All eight transmitters (TTIPn & TRINGn) will be in high
available
impedance state.
(High/Low)
5
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Pin No.
QFP144 BGA160
P2
RD0/RDP0
O
40
M2
33
RD1/RDP1
M13
77
RD2/RDP2 Tri-state
P13
70
RD3/RDP3
A13
111
RD4/RDP4
C13
104
RD5/RDP5
C2
5
RD6/RDP6
A2
142
RD7/RDP7
Name
Type
CV0/RDN0
CV1/RDN1
CV2/RDN2
CV3/RDN3
CV4/RDN4
CV5/RDN5
CV6/RDN6
CV7/RDN7
RCLK0
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
MCLK
LOS0
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
O
Tri-state
I
O
41
34
76
69
112
105
4
141
P3
M3
M12
P12
A12
C12
C3
A3
39
32
78
71
110
103
6
143
10
P1
M1
M14
P14
A14
C14
C1
A1
E1
42
35
75
68
113
106
3
140
K4
K3
K12
K11
E11
E12
E3
E4
Description
RDn: Receive Data for Channel 0~7
In Single Rail mode, the received NRZ data is output on this pin. The data is decoded by AMI or HDB3
line code rule.
CVn: Code Violation for Channel 0~7
In Single Rail mode, the bipolar violation, code violation and excessive zeros will be reported by driving
pin CVn to high level for a full clock cycle. However, only bipolar violation is indicated when AMI
decoder is selected.
RDPn/RDNn: Positive/Negative Receive Data for Channel 0~7
In Dual Rail mode with clock recovery, these pins output the NRZ data. A high signal on RDPn
indicates the receipt of a positive pulse on RTIPn/RRINGn while a high signal on RDNn indicates the
receipt of a negative pulse on RTIPn/RRINGn.
The output data at RDn or RDPn/RDNn are valid on the falling edges of RCLK when the CLKE input is
in High level, or valid on the rising edges of RCLK when CLKE is Low.
In Dual Rail mode without clock recovery, these pins output the raw RZ sliced data. In this data
recovery mode, the active polarity of RDPn/RDNn is determined by pin CLKE. When pin CLKE is Low,
RDPn/RDNn is active low. When pin CLKE is High, RDPn/RDNn is active high.
In hardware mode, RDn or RDPn/RDNn will remain active during LOS. In host mode, these pins will
either remain active or insert alarm indication signal (AIS) into the receive path, determined by bit AISE
in register GCF (Global Configuration register).
RDn or RDPn/RDNn is set into high impedance when the corresponding receiver is power down.
RCLKn: Receive Clock for Channel 0~7
In clock recovery mode, this pin outputs the recovered clock from signal received on RTIPn/RRINGn.
The received data are clocked out of the device on rising edges of RCLKn if pin CLKE is low, or on
falling edges of RCLKn if pin CLKE is high.
In data recovery mode, RCLKn is the output of an internal exclusive OR (XOR) which is connected with
RDPn and RDNn. The clock is recovered from the signal on RCLKn externally.
If receiver n is power down, the corresponding RCLKn is in high impedance.
MCLK: Master Clock
This is the independent, free running reference clock. A clock of 2.048 MHz is supplied to this pin as
the clock reference of the device for normal operation.
In receive path, when MCLK is high, the device slices the incoming bipolar line signal into RZ pulse
(Data Recovery mode). When MCLK is low, all the receivers are power down, and the output pins
RCLKn, RDPn and RDNn are switched to high impedance.
In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (see TCLKn
pin description for detail).
Note that wait state generation via RDY/ACK is not available if MCLK is not provided.
LOSn: Loss of Signal Output for Channel 0~7
A high level on this pin indicates the loss of signal when there is no transition over a specified period of
time or hasn’t enough ones density in the received signal. The transition will return to low automatically
when there is enough transitions over a specified period of time with a certain ones density in the
received signal. The LOS assertion and desertion criteria are described in the Functional Description.
6
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name
Type
MODE2
I
Pin No.
QFP144 BGA160
11
E2
(Pulled
to
VDDIO
/2)
MODE1
I
43
K2
MODE0
/CODE
I
88
H12
Description
Hardware/Host Control Mode
MODE2: Control Mode Select 2
The signal on this pin determines which control mode is selected to control the device:
MODE2
Control Interface
Low
Control by Hardware mode
VDDIO/2
Control by Serial Host Interface
High
Control by Parallel Host Interface
Hardware control pins include MODE[2:0], TS[2:0], LOOP[7:0], CODE, CLKE, JAS and OE.
Serial host Interface pins include CS, SCLK, SDI, SDO and INT.
Parallel host Interface pins include CS, A[4:0], D[7:0], WR/DS, RD/R/W, ALE/AS, INT and RDY/ACK. The
device supports multiple parallel host interface as follows (refer to MODE1 and MODE0 pin descriptions
below for details):
MODE[2:0]
Host Interface
100
Non-multiplexed Motorola mode interface.
101
Non-multiplexed Intel mode interface.
110
Multiplexed Motorola mode interface.
111
Multiplexed Intel mode interface.
MODE1: Control Mode Select 1
In parallel host mode, the parallel interface operates with separate address bus and data bus when this
pin is Low, and operates with multiplexed address and data bus when this pin is High.
In serial host mode and hardware mode, this pin should be grounded.
MODE0: Control Mode Select 0
In host mode, the parallel host interface is configured for Motorola compatible hosts when this pin is Low,
or for Intel compatible hosts when this pin is High.
CODE: Line Code Rule Select
In hardware control mode, the HDB3 encoder/decoder is enabled when this pin is Low, and AMI
encoder/decoder is enabled when this pin is High. The selections affect all the channels.
CS/JAS
I
(Pulled
to
VDDIO
/2)
87
J11
In serial host mode, this pin should be grounded.
CS: Chip Select (Active Low)
In host mode, this pin is asserted low by the host to enable host interface. A transition from High to Low
must occur on this pin for each Read/Write operation and the level must not return to High until the
operation is over.
JAS: Jitter Attenuator Select
In hardware control mode, this pin globally determines the Jitter Attenuator position:
JAS
Jitter Attenuator (JA) Configuration
Low
JA in transmit path
VDDIO/2
JA not used
High
JA in receive path
7
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name
Type
SCLK
/ALE
/AS
I
Pin No.
Description
QFP144 BGA160
86
J12 SCLK: Shift Clock
In serial host mode, the signal on this pin is the shift clock for the serial interface. Data on pin SDO is
clocked out on falling edges of SCLK if pin CLKE is Low, or on rising edges of SCLK if pin CLKE is
High. Data on pin SDI is always sampled on rising edges of SCLK.
ALE: Address Latch Enable
In parallel Intel multiplexed host mode, the address on AD[4:0] is sampled into the device on falling
edges of ALE (Signals on AD[7:5] are ignored). In non-multiplexed host mode, ALE should be pulled
High.
AS: Address Strobe (Active Low)
In parallel Motorola multiplexed host mode, the address on AD[4:0] is latched into the device on falling
edges of AS (Signals on AD[7:5] are ignored). In non-multiplexed host mode, AS should be pulled
High.
RD/R/ W
I
85
J13
(Note: This pin is ignored in hardware control mode.)
RD: Read Strobe (Active Low)
In parallel Intel multiplexed or non-multiplexed host mode, this pin is active low for read operation.
R/W: Read/Write Select
In parallel Motorola multiplexed or non-multiplexed host mode, the pin is active low for write operation
and high for read operation.
SDI
/WR
/DS
I
84
J14
(Note: This pin is ignored in hardware control mode)
SDI: Serial Data Input
In serial host mode, this pin input the data to the serial interface. Data on this pin is sampled on rising
edges of SCLK.
WR: Write Strobe (Active Low)
In parallel Intel host mode, this pin is active low during write operation. The data on D[7:0] (in nonmultiplexed mode) or AD[7:0] (in multiplexed mode) is sampled into the device on rising edges of WR.
DS: Data Strobe (Active Low)
In parallel Motorola host mode, this pin is active low. During a write operation (R/ W = 0), the data on
D[7:0] (in non-multiplexed mode) or AD[7:0] (in multiplexed mode) is sampled into the device on rising
edges of DS. During a read operation (R/W=1), the data is driven to D[7:0] (in non-multiplexed mode)
or AD[7:0] (in multiplexed mode) by the device on rising edges of DS.
In parallel Motorola non-multiplexed host mode, the address information on the 5 bits of address bus
A[4:0] are latched into the device on the falling edge of DS.
SDO
/RDY
/ACK
O
83
K14
(Note: This pin is ignored in hardware control mode)
SDO: Serial Data Output
In serial host mode, the data is output on this pin. In serial write operation, SDO is always in High
impedance. In serial read operation, SDO is in High impedance only when SDI is in
address/command byte. Data on pin SDO is clocked out of the device on falling edges of SCLK if pin
CLKE is Low, or on rising edges of SCLK if pin CLKE is High.
RDY: Ready Output
In parallel Intel host mode, the high level of this pin reports to the host that bus cycle can be
completed, while low reports the host must insert wait states.
ACK : Acknowledge Output (Active Low)
In parallel Motorola host mode, the low level of this pin indicates that valid information on the data bus
is ready for a read operation or acknowledges the acceptance of the written data during a write
operation.
8
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name
Type
INT
O
Open
Drain
I/O
LP7/D7/AD7
LP6/D6/AD6
LP5/D5/AD5 Tri-State
LP4/D4/AD4
LP3/D3/AD3
LP2/D2/AD2
LP1/D1/AD1
LP0/D0/AD0
Pin No.
Description
QFP144 BGA160
82
K13
INT: Interrupt (Active Low)
This is the open drain, active low interrupt output. Four sources may cause the interrupt (refer
to Interrupt Handling of Functional Description for details).
28
K1
LPn: Loopback Select 7~0
27
J1
In hardware control mode, pin LPn configures the corresponding channel in different loopback
26
J2
mode, as follows:
25
J3
LPn
Loopback Configuration
24
J4
Low
Remote Loopback
23
H2
VDDIO/2
No Loopback
22
H3
High
Analog Loopback
21
G2
Refer to Loopback Configuration of Functional Description for details.
Dn: Data Bus 7~0
In non-multiplexed host mode, these pins are the bi-directional data bus.
ADn: Address/Data Bus 7~0
In multiplexed host mode, these pins are the multiplexed bi-directional address/data bus.
A4
MC3/A3
MC2/A2
MC1/A1
MC0/A0
I
12
13
14
15
16
F4
F3
F2
F1
G3
In serial host mode, these pins should be grounded.
MCn: Performance Monitor Configuration 4~0
In hardware control mode, A4 must be connected to GND. MC[3:0] are used to select one
transmitter or receiver of the channel 1 to 7 for non-intrusive monitoring. Channel 0 is used as
the monitoring channel. If a transmitter is monitored, signals on the corresponding pins TTIPn
and TRINGn are internally transmitted to RTIP0 and RRING0. If a receiver is monitored, signals
on the corresponding pins RTIPn and RRINGn are internally transmitted to RTIP0 and RRING0.
The clock and data recovery circuit in receiver 0 can then output the monitored clock to pin
RCLK0 as well as the monitored data to RDP0 and RDN0 pins. The signals monitored by channel 0 can be routed to TTIP0/TRING0 by activating the remote loopback in this channel.
Performance Monitor Configuration determined by MC[3:0] is shown below. Note that if MC[2:0]
= 000, the device is in normal operation of all the channels.
MC[3:0]
Monitoring Configuration
0000
Normal operation without monitoring
0001
Monitoring receiver 1
0010
Monitoring receiver 2
0011
Monitoring receiver 3
0100
Monitoring receiver 4
0101
Monitoring receiver 5
0110
Monitoring receiver 6
0111
Monitoring receiver 7
1000
Normal operation without monitoring
1001
Monitoring transmitter 1
1010
Monitoring transmitter 2
1011
Monitoring transmitter 3
1100
Monitoring transmitter 4
1101
Monitoring transmitter 5
1110
Monitoring transmitter 6
1111
Monitoring transmitter 7
An: Address Bus 4~0
When pin MODE1 is low, the parallel host interface operates with separate address and data
bus. In this mode, the signal on this pin is the address bus of the host interface.
9
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name
Type
OE
I
CLKE
I
TRST
I
Pull up
TMS
I
Pull up
TCK
I
TDO
O
Tri-state
TDI
I
Pull up
IC
-
IC
-
VDDIO
-
GNDIO
-
VDDT0
VDDT1
VDDT2
VDDT3
VDDT4
VDDT5
VDDT6
VDDT7
GNDT0
GNDT1
GNDT2
GNDT3
GNDT4
GNDT5
GNDT6
GNDT7
VDDD
VDDA
GNDD
GNDA
-
-
-
Pin No.
Description
QFP144 BGA160
114
E14 OE: Output Driver Enable
Pulling this pin to low can make all driver output into high impedance state immediately for redundancy
application without external mechanical relays. In this condition, all the other internal circuits remain
active.
115
E13 CLKE: Clock Edge Select
The signal on this pin determins the active edge of RCLKn and SCLK in clock recovery mode, or
determines the active level of RDPn and RDNn in the data recovery mode. (Refer to Functional
Description and Table-2).
JTAG Signals
95
G12 TRST : JTAG Test Port Reset (Active Low)
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pullup resistor
and it can be left disconnected.
96
F11 TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is clocked into the device on rising edges
of TCK. This pin has an internal pullup resistor and it can be left disconnected.
97
F14 TCK: JTAG Test Clock
This pin input the clock of the JTAG Test. The data on TDI and TMS are clocked into the device on rising
edges of TCK, while the data on TDO is clocked out of the device on falling edges of TCK.
98
F13 TDO: JTAG Test Data Output
This pin output the serial data of the JTAG Test. The data on TDO is clocked out of the device on falling
edges of TCK. TDO is a Tri-state output signal. It is active only when scanning of data is out.
99
F12 TDI: JTAG Test Data Input
This pin input the serial data of the JTAG Test. The data on TDI is clocked into the device on rising edges
of TCK. This pin has an internal pullup resistor and it can be left disconnected.
93
G13 IC: Internal Connected
(Leave it open for normal operation.)
94
H13 IC: Internal Connected
(Leave it open for normal operation.)
Supplies and Grounds
17
G1
3.3V I/O Power Supply
92
G14
18
G4
I/O GND
91
G11
44
N4,P4 3.3V / 5V Power Supply for Transmitter Driver
53
L4,M4 All VDDT pins must be connected to either 3.3V or 5V. It is not allowed to leave any of the VDDT pins
56
L11,M11 open (not-connected) even if the channel is not used.
65
N11,P11
116
A11,B11
125
C11,D11
128
C4,D4
137
A4,B4
47
N6,P6 Analog GND for Transmitter Driver
50
L6,M6
59
L9,M9
62
N9,P9
119
A9,B9
122
C9,D9
131
C6,D6
134
A6,B6
19
H1
3.3V Digital / Analog Core Power Supply
90
H14
20
H4
Digital / Analog Core GND
89
H11
10
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
are raw RZ slice output and internally connected to an EXOR which is
fed to the RCLKn output for external clock recovery applications.
In Single Rail mode, data transmitted from TDn appears on TTIPn
and TRINGn at the line interface. Data received from the RTIPn and
RRINGn at the line interface appears on RDn while the recovered
clock extracting from the received data stream outputs on RCLKn.
When the device is in Single Rail interface, the selectable AMI or
HDB3 line encoder/decoder is available and any code violation in the
received data will be indicated at the CVn pin. The Single Rail mode
can be divided into 2 sub-modes. Single Rail mode1, whose interface
is composed of TDn, TCLKn, RDn, CVn and RCLKn, is realized by
pulling pin TDNn to high for more than 16 consecutive TCLK cycles.
Single Rail mode 2, whose interface is composed of TDn, TCLKn,
RDn, CVn, RCLKn and BPVIn, is realized by setting bit CRS in eCRS2 and bit SING in e-SING. The difference between them is that, in
the latter mode bipolar violation can be inserted via pin BPVIn if AMI
line code is selected.
The configuration of different system interface is summarized in
Table-1.
OVERVIEW
The IDT82V2058 is a fully integrated octal short-haul line interface
unit, which contains eight transmit and receive channels for use in E1
applications. The receiver performs clock and data recovery. As an
option, the raw sliced data (no retiming) can be output to the system.
Transmit equalization is implemented with low-impedance output drivers that provide shaped waveforms to the transformer, guaranteeing
template conformance. A selectable jitter attenuation may be placed in
the receive path or the transmit path. Moreover, multiple testing functions, such as error detection, loopback and JTAG boundary scan are
also provided. The device is optimized for flexible software control
through a serial or parallel host mode interface. Hardware control is
also available. Figure-1 shows One of the Eight Identical Channels
operation.
SYSTEM INTERFACE
The system interface of each channel can be configured to
operate in different modes:
1. Single Rail interface with clock recovery.
2. Dual Rail interface with clock recovery.
3. Dual Rail interface with data recovery (that is, with raw data slicing only and without clock recovery).
Therefore, each signal pin on system side has multiple functions
depending on which operation mode the device is in.
Dual Rail interface consists of TDPn 1, TDNn, TCLKn, RDPn, RDNn
and RCLKn. Data transmitted from TDPn and TDNn appears on
TTIPn and TRINGn at the line interface; data received from the RTIPn
and RRINGn at the line interface are transferred to RDPn and RDNn
while the recovered clock extracting from the received data stream
outputs on RCLKn. In Dual Rail operation, the clock/data recovery
mode is selectable. Dual Rail interface with clock recovery shown in
Figure-3 is a default configuration mode. Dual Rail interface with data
recovery is shown in Figure-4. Pin RDPn and RDNn, in this condition,
CLOCK EDGES
The active edge of RCLK and SCLK(serial interface clock) are also
selectable. If pin CLKE is Low, the active edge of RCLK is the rising
edge, as for SCLK, that is falling edge. On the contrary, if CLKE is
High, the active edge of RCLK is the falling edge and that of SCLK is
rising edge. Pins RDn/RDPn, CVn/RDNn and SDO are always active
high, and those output signals are valid on the active edge of RCLK
and SCLK respectively. See Table-2 for details. However, in dual rail
mode without clock recovery, pin CLKE is used to set the active level
for RDPn/RDNn raw slicing output: High for active high polarity and
Low for active low. It should be noted that data on pin SDI are always
active high and is sampled on the rising edge of SCLK. The data on
pin TD/TDP or BPVI/TDN are also always active high but is sampled
on the falling edge of TCLK, despite the level on CLKE.
One of Eight Identical Channels
LOS
Detector
RTIPn
Slicer
RRINGn
LOSn
CLK&Data
Recovery
(DPLL)
Jitter
Attenuator
HDB3/
AMI
Decoder
RCLKn
RDPn
RDNn
Waveform
Shaper
Jitter
Attenuator
HDB3/
AMI
Encoder
TCLKn
TDPn
TDNn
Peak
Detector
TTIPn
TRINGn
Line
Driver
Transmit
All Ones
Figure - 3. Dual Rail Interface with Clock Recovery 3
NOTE:
1. The footprint ‘n’ (n = 0 - 7) indicates one of the eight channels
2. The first letter “e-”indicates expanded register.
3. The grey blocks are bypassed and the dotted blocks are selectable
11
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
LOS
Detector
RTIPn
Slicer
RRINGn
One of Eight Identical Channels
LOSn
CLK&Data
Recovery
(DPLL)
Jitter
Attenuator
HDB3/
AMI
Decoder
Waveform
Shaper
Jitter
Attenuator
HDB3/
AMI
Encoder
RCLKn
(RDP RDN)
RDPn
RDNn
Peak
Detector
TTIPn
Line
Driver
TRINGn
TCLKn
TDPn
TDNn
Transmit
All Ones
Figure - 4. Dual Rail Interface with Data Recovery
LOS
Detector
RTIPn
Slicer
RRINGn
One of Eight Identical Channels
LOSn
CLK&Data
Recovery
(DPLL)
Jitter
Attenuator
HDB3/
AMI
Decoder
Waveform
Shaper
Jitter
Attenuator
HDB3/
AMI
Encoder
RCLKn
RDn
CVn
Peak
Detector
TTIPn
TRINGn
Line
Driver
TCLKn
TDn
TDNn/BPVIn
Transmit
All Ones
Figure - 6. Single Rail Mode
TABLE - 1a. SYSTEM INTERFACE CONFIGURATION (Host Mode)
MCLK
clocked
clocked
clocked
clocked
H
TDNn
H
pulse
pulse
pulse
pulse
CRSn in e-CRS
0
0
0
1
-
L
pulse
-
Host Mode
SINGn in e-SING
0
1
0
0
-
12
Interface
Single Rail mode 1
Single Rail mode 2
Dual Rail with Clock Recovery
Dual Rail with Data Recovery
Receive just slice the incoming data.
Transmit is determined by the status of TCLKn.
Receive is power down.
Transmit is determined by the status of TCLKn.
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 1b. SYSTEM INTERFACE CONFIGURATION (Hardware Mode)
Hardware Mode
MCLK
clocked
clocked
H
L
TDNn
H ( 16 MCLK)
pulse
pulse
pulse
Interface
Single Rail mode 1
Dual Rail with Clock Recovery
Receive just slice the incoming data. Transmit is determined by the status of TCLKn.
Receive is power down. Transmit is determined by the status of TCLKn.
TABLE - 2. ACTIVE CLOCK EDGE AND ACTIVE LEVEL
Pin CLKE
RD/RDP and CV/RDN
Clock recovery
Slicer output
Low
RCLK
Active High
Active Low
High
RCLK
Active High
Active High
SDO
SCLK
SCLK
Active High
Active High
RECEIVER
In receive path, the line signals couple into RRINGn and RTIPn via
a transformer and are converted into RZ digital pulses by a data
slicer. Adaptation for attenuation is achieved using an integral peak
detector that sets the slicing levels. Clock and data are recovered
from the received RZ digital pulses by a digital phase-locked loop that
provides excellent jitter accommodation. After passing through the
selectable jitter attenuator, the recovered data are decoded using
HDB3 or AMI line code rules and clocked out of pin RDn in single rail
mode, or presented on RDPn/RDNn in an undecoded dual rail NRZ
format. Loss of signal, alarm indication signal, line code violations and
excessive zero are detected. These various changes in status may
be enabled to generate interrupts.
The clock recovery and data recovery mode can be selected on
per channel basis by setting the bit CRSn in e-CRS. When bit CRSn is
defaulted to ‘0’, the corresponding channel operates in data and clock
recovery mode. The recovered clock is output on pin RCLKn and retimed NRZ data are output on pin RDPn/RDNn in dual rail mode or on
RDn in single rail mode. When CRSn is ‘1’, dual rail with data
recovery mode is enabled in the corresponding channel and the clock
recovery function is bypassed. In this condition, the analog line signal
are converted to RZ digital bit streams on the RDPn/RDNn pins and
internally connected to an EXOR which is fed to the RCLKn output for
external clock recovery applications.
Moreover, Pulling MCLK to H level, all the receivers will enter the
dual rail with data recovery mode. In this case, e-CRS is ignored.
Peak Detector and Slicer
The slicer determines the presence and polarity of the received
pulses. In data recovery mode, the raw positive slicer output appears
on RDPn while the negative slicer output appears on RDNn. In clock
and data recovery mode, the slicer output is sent to Clock and Data
Recovery circuit for abstracting retimed data and optional decoding.
The slicer circuit has a built-in peak detector from which the slicing
threshold is derived. The slicing threshold is default to 50% (typical) of
the peak value.
Signals with an attenuation of up to 12 dB (from 2.4V) can be recovered accurately by the receiver. To provide immunity from impulsive noise, the peak detectors are held above a minimum level of
0.150 V typically, despite the received signal level.
HDB3/AMI Line Code Rule
Selectable HDB3 or AMI line coding/decoding is provided when the
device is configured in single rail mode. HDB3 rules is enabled by setting bit CODE in register GCF (global control configuration) to ‘0’ or
pulling pin CODE to Low. AMI rule is enabled by setting bit CODE in
GCF to ‘1’ or pulling pin CODE to High. All the setting above are effected to eight channels.
Individual line code rule selection for each channel, if need, is
available by setting bit SINGn in e-SING to ‘1’ (to activate bit CODEn in
e-CODE) and programming bit CODEn to select line code rules in the
corresponding channel: ‘0’ for HDB3, while ‘1’ for AMI. In this case, the
value in bit CODE in GCF or pin CODE for global control is unaffected
in the corresponding channel and only affect in other channels.
In dual rail mode, the decoder/encoder are bypassed. Bit CODE in
GCF, bit CODEn in e-CODE and pin CODE are ignored.
The configuration of the Line Code Rule is summarized in Table-3.
Clock and Data Recovery
The function of Clock and Data Recovery is accomplished by
Digital Phase Locked Loop (DPLL). The DPLL is clocked 16 times of
the received clock rate, i.e. 32.768 MHz in E1 mode. The recovered
data and clock from DPLL is then sent to the selectable Jitter
Attenuator or decoder circuit for further processing.
13
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 3. CONFIGURATION OF THE LINE CODE RULE
Hardware Mode
CODE
Line Code Rule
L
All channels in HDB3
H
All channels in AMI
Host Mode
CODE in GCF CODEn in e-CODE SINGn in e-SINGn
0
0/1
0
0
0
1
1
0/1
0
1
1
1
0
1
1
1
0
1
Line Code Rule
All channels in HDB3
All channels in AMI
CHn in AMI
CHn in HDB3
TABLE - 4. LOS CONDITION IN CLOCK RECOVERY MODE
STANDARD
LOS
Continuous Intervals
Detected
Amplitude
LOS
Density
Cleared
Amplitude
G.775 for E1
32
below typ. 310mV (Vpp)
12.5% (4 marks in a sliding 32-bit period)
with no more that 15 continuous zeros
exceed typ. 540mV (Vpp)
Loss of Signal (LOS) Detection
The Loss of Signal Detector monitors the amplitude and density of
the received signal on Receiver line before the transformer
(measured on port A, B in Figure 12). The loss condition is reported
by pulling pin LOSn to high. In the same time, LOS alarm registers
track LOS condition. When LOS detected or cleared, an interrupt will
generate if not masked. In host mode, the detection supports the ITUG.775 and ETSI 300233. In hardware mode, it only supports the ITUG.775 specification.
Table-4 summarizes the conditions of LOS in clock recovery
mode.
In data recovery mode, the LOS condition is cleared upon
detecting the signal level exceeds 540mV.
During LOS, the RDPn/RDNn output the sliced data when bit
ETSI 300233 for E1
2048 (1 ms)
below typ. 310mV (Vpp)
12.5% (4 marks in a sliding 32-bit period)
with no more than 15 continuous zeros
exceed typ. 540mV (Vpp)
Signal on
pin LOSn
H
L
AISE(Alam Indication Signal Enable) in register GCF is 0 or output all
ones as AIS (Alarm Indication Signal) when bit AISE is set to 1; The
RCLKn is replaced by MCLK only if the AISE is set.
Alarm Indication Signal Detection (AIS)
Alarm Indication Signal is available only in host mode with clock
recovery, as Table-5 shows.
Error Detection
The device can detects excessive zero, bipolar violations and
HDB3 code violations, refer to figure-7, 8, 9. All the three kinds of errors are reported in both host mode and hardware mode with HDB3
line code rule is used. Moreover, in host mode, the expanded registers e-CZER and e-CODV are used to determine whether the exces-
TABLE - 5. AIS CONDITION
AIS Detected
AIS Cleared
ITU G.755 for E1 (register LAC defaulted to 0)
Less than 3 zeros contained in each of two consecutive
512-bit stream are received
3 or more zeros contained in each of two consecutive
512-bit stream are received
ETSI 300233 for E1 (register LAC is 1)
Less than 3 zeros contained in a 512-bit stream
are received
3 or more zeros contained in a 512-bit stream
are received
TABLE - 6. ERROR DETECTION
Hardware Mode
Line Code Pin CVn Reports
AMI
Bipolar Violation
HDB3
Bipolar Violation
+ Code Violation
+ Excessive Zero
Host Mode
Line Code CODVn in e-CODV CZERn in e-CZER
Pin CVn Reports
AMI
Bipolar Violation
0
0
Bipolar Violation + Code Violation
0
1
Bipolar
Violation
+ Code Violation + Excessive Zero
HDB3
1
0
Bipolar Violation
1
1
Bipolar Violation + Excessive Zero
14
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
CLK
RTIP
1
RRING
3
2
5
V
7
4
RD
1
6
2
3
4
5
V
6
CV
Bipolar violation
Bipolar Violation detected
Figure - 7. AMI Bipolar Violation
Code violation
CLK
RTIP
1
3
5
4 consecutive zeros
RRING
RD
2
4
1
V
2
3
V
6
4
5
6
CV
Excessive zero detected
Code violation detected
Figure - 8. HDB3 Code Violation & Excessive Zero
1.20
sive zero and code violation are reported respectively. When
configured in AMI decoding mode, only bipolar violation can be reported.
The error detection is available only in single rail mode where the
pin RDNn/CVn is used as error report output (CVn pin).
The configuration and report status of error detection are summarized in Table-6.
1.00
Normalized Amplitude
0.80
0.60
0.40
0.20
TRANSMITTER
In transmit path, data in NRZ (non return to zero) format are
clocked into the device on TDn and encoded by AMI or HDB3 line
code rules when single rail mode is configured or pre-encoded data
in NRZ format are input on TDPn and TDNn when dual rail mode is
configured. The data are sampled into the device on falling edges of
TCLKn. Jitter attenuator, if enabled, is provided with a FIFO which the
data to be transmitted are passing through. A low jitter clock is
generated by an integral digital phase-locked loop and is used to
read data from the FIFO. The shape of the pulses should meet the
E1 pulse template after the signal is passed through different cable
types. Bipolar violation, for diagnosing, can be inserted on pin BPVIn
if AMI line code rule is enabled.
0.00
-0.20
-300
-200
-100
0
Time (ns)
100
200
300
Figure - 9. CEPT Waveform Template
Waveform Shaper
E1 pulse template, specified in ITU-T G.703, is shown in Figure-9.
The device has built-in transmit waveform templates for cable of 75Ω
or 120Ω.
The built-in waveform shaper use an internal high frequency clock
which is 16XMCLK as clock reference. This function will be bypassed
when MCLK is unavailable.
15
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
attenuator in the corresponding transmit or receive path. The constant
delay feature is crucial for the applications requiring “hitless” switching.
In host mode, bit JABW in GCF determines the jitter attenuator 3dB
corner frequency (fc). In hardware mode, the fc is fixed to 1.7Hz.
Generally, the lower the fc is, the higher the attenuation. However,
lower fc comes at the expense of increased acquisition time.
Therefore, the optimum fc is to optimize both the attenuation and the
acquisition time. In addition, the longer FIFO length results in an
increased throughput delay and also influences the 3dB corner
frequency. Generally, it’s recommended to use the lower corner
frequency and the shortest FIFO length that can still meet jitter
attenuation requirements.
The output jitter specifications include: ITU-T G.736, ITU-T G.742,
ITU-T G.783 and ETSI CTR 12/13.
Bipolar Violation Insertion
When configured in single rail mode 2 with AMI line code enabled,
pin TDNn/BPVIn is used as BPVI input. A low-to-high transition on this
pin inserts a bipolar violation on the next available mark in the transmit data stream. Sampling occurs on the falling edge of TCLK. But in
TAOS with analog loopback mode and remote loopback mode, the
BPVI is disabled. In TAOS with digital loopback mode, the BPVI is
looped back to system side, so the data to be transmitted on TTINGn
and TRINGn are all ones with no bipolar violation.
JITTER ATTENUATOR
The jitter attenuator is provided for narrow-band width jitter transfer
and can be selected to work either in transmit path or in receive path
or not used. The selection is accomplished by setting pin JAS in hardware mode or configuring bits JACF1 and JACF0 in register GCF in
host mode which are both effected to all the channels.
For applications which require line synchronization, the line clock
is need to be extracted for the internal synchronization, the jitter
attenuator is set in the receive path. Another use of the jitter attenuator
is to provide clock smoothing in the transmit path for applications such
as synchronous/asynchronous demultiplexing applications. In these
applications, TCLK will have an instantaneous frequency that is higher
than the nominal E1 data rate and in order to set the average longterm TCLK frequency within the transmit line rate specifications, periods of TCLK are suppressed (gapped).
The jitter attenuator integrates a FIFO which can accommodate a
gapped TCLK. In host mode, the FIFO length can be 32 X 2 or 64 X 2
bits by programming bit JADP in GCF. In hardware mode, it is fixed to
64 X 2 bits. The FIFO length determines the maximum permissible
gap width (see table-7), exceeding these values will cause FIFO overflow or underflow. The data is 16 or 32 bits’ delay through the jitter
•
0.22µF
•
•
B
1
2:1
• •
1kΩ
Component
RT
RR
Cp
D1 – D4
75Ω Coax
9.5 Ω ± 1%
9.31 Ω ± 1%
120Ω Twisted Pair
9.5Ω ± 1%
15Ω ± 1%
2200pf
Nihon Inter Electronics - EP05Q03L, 11EQS03L,
EC10QS04, EC10QS03L
Motorola – MBR0540T1
RTIPn
RR
RR
1kΩ
RT
VDDT
D4
D3
TX Line
Max. Gap Width
56 UI
28 UI
TABLE - 8. EXTERNAL COMPONENTS VALUES
Cp
RRINGn
·
TTIPn
IDT82V2058
2:1
• •
RX Line
FIFO Length
64 bit
32 bit
One of Eight Identical Channels
1
A
TABLE - 7. GAP WIDTH LIMITATION
VDDDn
2
VDDT
D2
RT
D1
VDDT
•
0.1µF
GNDTn
·
68µF 3
•
TRINGn
NOTE:
1. Pulse T1124 transformer is recommended to use in Standard (STD) operating temperature range (0° to 70°C), while Pulse T1114 transformer is recommended to use in Extended (EXT)
operating temperature range is -40° to +85°C. See Transformer Specifications Table for details.
2. Typical value. Adjust for actual board parasitics to obtain optimum return loss.
3. Common decoupling capacitor for all VDDT and GNDT pins.
Figure - 10. External Transmit/Receive Line Circuitry
16
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 9. TRANSFORMER SPECIFICATIONS
Part No.
STD Temp. EXT Temp.
T1124
T1114
Electrical Specification @ 25 °C
Turns Ratio (Pri: sec±2%) OCL @ 25°C (mH MIN)
LL (µH MAX)
Transmit
Receive
Transmit
Receive Transmit Receive
1:2CT
1CT:2
1.2
1.2
.6
.6
cally.
CW/W (pF MAX)
Transmit Receive
35
35
Package/
Schematic
TOU/3
LINE INTERFACE CIRCUITRY
The transmit and receive interface RTIP/RRING and TTIP/TRING
connections provide a matched interface to the cable. Figure-12
shows the appropriate external components to connect with the cable
for one transmit/receive channel. Table-8 summarizes the
component values based on the specific application.
HITLESS PROTECTION SWITCHING (HPS)
The IDT82V2048 tranceivers include an output driver tristatability
feature for T1/E1 redundancy applications. This feature greatly reduces the cost of implementing redundancy protection by eliminating
external relays. Details of HPS will be described in relative Application
Note.
TRANSMIT DRIVER POWER SUPPLY
The nominal transmit driver power supply must be 5.0V or 3.3V.
Despite of the power supply voltage, the 75Ω/120Ω lines are
driven through 9.5Ω series resistors and a 1:2 transformer.
However, in harsh cable environment, series resistors are required to improve the transmit return loss performance and protect
the device from surges coupling into the device.
RESET
Writing register RS can cause software reset by initiating about 1µs
reset cycle. This operation set all the registers to their default value.
SHORT CIRCUIT MONITOR
An internal Short Circuit Monitor (SCM), parallelly connected with
TTIPn and TRINGn, can detect short circuit in the transmit line side.
Bit SCPB in Register GCF decides whether the output driver shortcircuit protection is enabled. (Refer to Programming Information).
When it is enabled, the max driver’s output current is limited to
150mA.
POWER DOWN
Each transmitter channel will power down by pulling pin TCLKn to
low for more than 64 MCLK cycles (if MCLK is available) or about
30us (when MCLK is not availabe). Each transmitter channel will also
power down by setting bit TPDNn in e-TPDN to 1.
All the receivers will power down when MCLK is Low. When MCLK
is clocked or High, setting bit RPDNn in e-RPDN to ‘1’ will configure the
corresponding receiver to power down.
LINE PROTECTION
In transmit side, the Schottky diodes D1~D4 are required to protect
the line driver and improve the design robustness. In receive side,
the series resistors of 1kΩ are used to protect the receiver against
current surges coupled in the device. It does not affect the receiver
sensitivity, since the receiver impedance is as high as 120kΩ typi-
INTERFACE WITH 5V LOGIC
The IDT82V2048 can interface directly with 5V TTL family devices.
The internal input pads are tolerant to 5V output from TTL and CMOS
family devices.
POWER UP
During power up, an internal reset signal sets all the registers to
default values. This procedure takes at least 2 machine cycles.
One of Eight Identical Channels
LOS
Detector
RTIPn
Slicer
RRINGn
CLK&Data
Recovery
(DPLL)
TRINGn
Jitter
Attenuator
HDB3/AMI
Decoder
RCLKn
RDn/RDPn
CVn/RDNn
Jitter
Attenuator
HDB3/AMI
Encoder
TCLKn
TDn/TDPn
BPVIn/TDNn
Digital
Loopback
Peak
Detector
TTIPn
LOSn
Line
Driver
Waveform
Shaper
Transmit
All Ones
Figure - 11. Digital Loopback
17
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
LOOPBACK MODE
The device provides four different diagnostic loopback configurations: Digital Loopback, Analog Loopback, Remote Loopback and
Dual Loopback. In host mode, these functions are implemented by
programming the registers DLB, ALB or RLB. In hardware mode,
only analog loopback and remote loopback can be selected by pulling pin LPn to High and Low respectively.
Remote Loopback
By programming the bits of RLB register or pulling pin LPn to Low,
each channel of the device can be set in Remote Loopback. In this
configuration, the data and clock recovered by the Clock and Data
Recovery circuits are looped to waveform shaper and output on
TTIPn and TRINGn. The jitter attenuator is also included in loopback
when enabled in the transmit or receive path. The received data and
clock are still output on RCLKn, RDn/RDPn and CVn/RDNn while the
data to be transmitted on TCLKn, TDn/TDPn and BPVIn/TDNn are
ignored. The Loss Detector is still in use. Figure-13 shows the
process.
Digital Loopback
By programming the bits of register DLB, each channel of the device can be set in Local Digital Loopback. In this configuration, the
data and clock to be transmitted, after passing the encoder, is looped
back to jitter attenuator (if enabled) and decoder in the receive path,
then output on RCLKn, RDn/RDPn and CVn/RDNn. The data to be
transmitted are still output on TTIPn and TRINGn while the data received on RTIPn and RRINGn are ignored. The Loss Detector is still
in use. Figure-11 shows the process.
Dual Loopback
Dual Loopback mode is set by setting both bit DLBn in register
DLB and bit RLBn in register RLB to ‘1’. In this configuration, after
passing the encoder, the data and clock to be transmitted are looped
back to decoder directly and output on RCLKn, RDn/RDPn and CVn/
RDNn. The recovered data from RTIPn and RRINGn are looped back
to waveform shaper through JA (if selected) and output on TTIPn and
TRINGn. The Loss Detector is still in use. Figure-14 shows the process.
Analog Loopback
By programming the bits of ALB register or pulling pin LPn to
High, each channel of the device can be set in Analog Loopback. In
this configuration, the data to be transmitted output from the line driver
are internally looped back to the slicer and peak detector in the
receive path and output on RCLKn, RDn/RDPn and CVn/RDNn. The
data to be transmitted are still output on TTIPn and TRINGn while the
data received on RTIPn and RRINGn are ignored. The Loss Detector
is still in use. Figure-12 shows the process.
The TTIPn and RTIPn, TRINGn and RRINGn cannot be connected
directly to do the external analog loopback test. Line impedance
loading is required to conduct the external analog loopback test.
Transmit All Ones
In hardware mode, the TAOS mode is set by pulling TCLKn High
for more than 16 MCLK cycles. In host mode, TAOS mode is set by
programming register TAO. In addition, automatic TAO signals are inserted by setting register ATAO when Loss of Signal occurs. Note that
the TAOS generator adopts MCLK as a timing reference. In order to
assure that the output frequency is within specification limits, MCLK
must have the applicable stability.
This TAOS mode and Digital Loopback or Analog Loopback can
be configured simultaneously. Figure-15 shows their process.
LOS
Detector
RTIPn
Slicer
RRINGn
Analog
Loopback
TTIPn
TRINGn
CLK&Data
Recovery
(DPLL)
One of Eight Identical Channels
LOSn
Jitter
Attenuator
HDB3/AMI
Decoder
RCLKn
RDn/RDPn
CVn/RDNn
HDB3/AMI
Encoder
TCLKn
TDn/TDPn
BPVIn/TDNn
Peak
Detector
Line
Driver
Waveform
Shaper
Jitter
Attenuator
Transmit
All Ones
Figure - 12. Analog Loopback
18
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
One of Eight Identical Channels
LOS
Detector
RTIPn
CLK&Data
Recovery
(DPLL)
Slicer
RRINGn
LOSn
Jitter
Attenuator
Peak
Detector
TTIPn
RCLKn
RDn/RDPn
CVn/RDNn
HDB3/AMI
Encoder
TCLKn
TDn/TDPn
BPVIn/TDNn
Remote
Loopback
Line
Driver
TRINGn
HDB3/AMI
Decoder
Waveform
Shaper
Jitter
Attenuator
Transmit
All Ones
Figure - 13. Remote Loopback
One of Eight Identical Channels
LOS
Detector
RTIPn
Slicer
RRINGn
LOSn
CLK&Data
Recovery
(DPLL)
Jitter
Attenuator
HDB3/AMI
Decoder
RCLKn
RDn/RDPn
CVn/RDNn
HDB3/AMI
Encoder
TCLKn
TDn/TDPn
BPVIn/TDNn
Peak
Detector
TTIPn
TRINGn
Line
Driver
Jitter
Attenuator
Waveform
Shaper
Transmit
All Ones
Figure - 14. Dual Loopback
LOS
Detector
RTIPn
Slicer
RRINGn
CLK&Data
Recovery
(DPLL)
One of Eight Identical Channels
LOSn
Jitter
Attenuator
HDB3/AMI
Decoder
RCLKn
RDn/RDPn
CVn/RDNn
Peak
Detector
TTIPn
TRINGn
Line
Driver
Waveform
Shaper
Jitter
Attenuator
Transmit
All Ones
Figure - 15a. TAOS Data Path
19
HDB3/AMI
Encoder
TCLKn
TDn/TDPn
BPVIn/TDNn
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
One of Eight Identical Channels
LOS
Detector
RTIPn
CLK&Data
Recovery
(DPLL)
Slicer
RRINGn
LOSn
Jitter
Attenuator
HDB3/AMI
Decoder
RCLKn
RDn/RDPn
CVn/RDNn
Jitter
Attenuator
HDB3/AMI
Encoder
TCLKn
TDn/TDPn
BPVIn/TDNn
Peak
Detector
TTIPn
TRINGn
Line
Driver
Waveform
Shaper
Transmit
All Ones
Figure - 15b. TAOS with Digital Loopback
One of Eight Identical Channels
LOS
Detector
RTIPn
Slicer
RRINGn
LOSn
CLK&Data
Recovery
(DPLL)
Jitter
Attenuator
HDB3/AMI
Decoder
RCLKn
RDn/RDPn
CVn/RDNn
Peak
Detector
TTIPn
TRINGn
Line
Driver
Waveform
Shaper
HDB3/AMI
Encoder
TCLKn
TDn/TDPn
BPVIn/TDNn
Transmit
All Ones
Figure - 15c. TAOS with Analog Loopback
HOST INTERFACES
The host interface provides access to read and write the registers
in the device. The interface consists of serial host interface and
parallel host interface. By pulling pin MODE2 to VDDIO/2 or to High,
the device can be set to work in serial mode and in parallel mode
respectively.
Parallel Host Interface
The interface is compatible with Motorola or Intel host. Pins
MODE1 and MODE0 are used to select the operating mode of the
parallel host interface. When pin MODE1 is pulled to Low, the host
uses separate address bus and data bus. When High, multiplexed
address/data bus is used. When pin MODE0 is pulled to Low, the parallel host interface is configured for Motorola compatible hosts. When
High, for Intel compatible hosts. This is well described in the Pin Description. The host interface pins in each operation mode is tabulated in Table-10.
Serial Host Interface
By pulling pin MODE2 to VDDIO/2, the device operates in the serial
host Mode. In this mode, the registers are accessible through a 16-bit
word which contains an 8-bit command/address byte (bit R/W and 5-address-bit A1~A5, A6 and A7 are ignored) and a subsequent 8-bit data
byte (D0~D7). When bit R/W is 1, data is read out at pin SDO. When bit
R/W is 0, data is written into pin SDI to the register which is indicated by
address bits A5~A1.
INTERRUPT HANDLING
Interrupt Sources
There are three kinds of interrupt sources:
1. Status change in the LOS (Loss of Signal) Status Register(04H).
The analog/digital loss of signal detector continuously monitors the received signal to update the specific bit in LOS which indicates presence
or absence of a LOS condition.
20
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 10. PARALLEL HOST INTERFACE PINS
MODE[2:0]
100
101
110
111
Host interface
Non-multiplexed Motorola interface
Non-multiplexed Intel interface
Multiplexed Motorola interface
Multiplexed Intel interface
Generic control, data, and output pin name
CS, ACK, DS, R/W, AS, A[4:0], D[7:0], INT
CS, RDY, WR, RD, ALE, A[4:0], D[7:0], INT
CS, ACK, DS, R/W, AS, AD[7:0], INT
CS, RDY, WR, RD, ALE, AD[7:0], INT
CS
SCLK
SDI
2
2
1
R/W A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7
Address/Command Byte
SDO
Input Data Byte
D0 D1 D2 D3 D4 D5 D6 D7
High Impedance
Driven while R/W=1
NOTE:
1. While R/W=1, read from IDT82V2058; While R/W=0, write to IDT82V2058.
2. Ignored.
Figure - 16. Serial Host Mode Timing
2. Status change in the SC (Short Circuit) Status Register(05H).
The automatic power driver circuit continuously monitors the output
drivers signal to update the specific bit in SCM which indicates presence or absence of the transmit line side short circuit condition.
3. Status change in the AIS (Alarm Indication Signal) Status
Register(13H). The AIS detector monitors the received signal to update the specific bit in AIS which indicates presence or absence of a
AIS condition.
Interrupt Allowed
No
Interrupt Enable
The IDT82V2058 provides a latched interrupt output (INT) and the
three kinds of interrupts are all reported by this pin. When the Interrupt
Mask register (LOSM , SCM and AISM ) is set to ‘1’, the Interrupt Status register (LOSI, SCI and AISI) is enabled respectively. Whenever
there is a transition (‘0’ to ‘1’ or ‘1’ to ‘0’) in the corresponding Status
register, the Interrupt Status register will change into ‘1’, which means
an interrupt occurs, and there will be a transition from high to low on
INT. An external pull-up resistor of approximately 10kΩ is required to
support the wire-OR operation of INT. When any of the three Interrupt
Mask registers is set to ‘0’ (the power-on default value is ‘0’), the corresponding Interrupt Status register is disabled and the transition on
status register is ignored.
Interrupt Condition
Exist?
Yes
Read Interrupt Status Register
Read Corresponding Status
Register
Interrupt Clearing
When an interrupt occurs, the Interrupt Status registers (LOSI, SCI
and AISI) are read to identify the interrupt source. And these registers
will be cleared to ‘0’ after the corresponding Status register (LOS, SC
and AIS) being read. The Status registers will be cleared once the
corresponding conditions are met.
Pin INT is pulled High when there are no pending interrupt left.
The interrupt handling in the interrupt service routine is showed Figure-17.
Service the Interrupt
Figure - 17. Interrupt Service Routine
21
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
G.772 MONITORING
The eight channels of IDT82V2058 can all be configured to work as
regular transceivers. In applications using only seven channels
(channels 1 to 7), channel 0 is configured to non-intrusively monitor
any of the other channels’ inputs or outputs on the line side. The
monitoring is non-intrusive per ITU-T G.772. Figure-17 shows the
Monitoring Principle. The receiver or transmitter path to be monitored
is configured by pin MC[0:3] in hardware mode or by PMON in host
mode (refer to Programming Information for details).
The signal which is monitored goes through the clock and data
recovery circuit of channel 0. The monitored clock can output on
RCLK0 which can be used as a timing interfaces derived from E1
signal. The monitored data can be observed digitally at the output pin
RCLK0, RD0/RDP0 and RDN0. LOS detector is still in use in channel
0 for the monitored signal.
In monitoring mode, channel 0 can be configured to the Remote
Loopback. The signal which is being monitored will output on TTIP0
and TRING0. The output signal can then be connected to a standard
test equipment with an E1 electrical interface for non-intrusive
monitoring.
Channel N ( 7 > N > 1 )
LOS
Detector
RTIPn
Slicer
RRINGn
LOSn
CLK&Data
Recovery
(DPLL)
Jitter
Attenuator
HDB3/
AMI
Decoder
RCLKn
RDn/RDPn
CVn/RDNn
Waveform
Shaper
Jitter
Attenuator
HDB3/
AMI
Encoder
TCLKn
TDn/TDPn
BPVIn/TDNn
Peak
Detector
TTIPn
Line
Driver
TRINGn
Transmit
All Ones
Channel 0
G.772
Monitor
LOS
Detector
RTIP0
Slicer
RRING0
CLK&Data
Recovery
(DPLL)
LOS0
Jitter
Attenuator
TRING0
Line
Driver
RCLK0
RD0/RDP0
CV0/RDN0
Remote
Loopback
Peak
Detector
TTIP0
HDB3/
AMI
Decoder
Waveform
Shaper
Jitter
Attenuator
Transmit
All Ones
Figure - 17. Monitoring Principle
22
HDB3/
AMI
Encoder
TCLK0
TD0/TDP0
BPVI0/TDN0
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PROGRAMMING INFORMATION
carries the address information. In serial interface mode, A[5:1] are used
to address the register.
The Address Pointer Control Register (ADDP), addressed as 11111
or 1F Hex, switches between primary registers bank and expanded registers bank.
By setting the content of ADDP to AAH, the 5 address bits point to the
expanded register bank, that is, 16 expanded registers are then available to access. By clearing ADDP, the primary registers are accessible
again.
REGISTER LIST AND MAP
There are 21 primary registers (including an Address Pointer Control Register), including 8 expanded registers in the device.
Whatever the control interface is, 5 address bits are used to set the
registers. In non-multiplexed parallel interface mode, the five dedicated
address bits are A[4:0]. In multiplexed parallel interface mode, AD[4:0]
TABLE - 11. PRIMARY REGISTER LIST
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
Address
serial
parallel
interface
interface
A7-A1
A7-A0
XX00000 XXX00000
XX00001 XXX00001
XX00010 XXX00010
XX00011 XXX00011
XX00100 XXX00100
XX00101 XXX00101
XX00110 XXX00110
XX00111 XXX00111
XX01000 XXX01000
XX01001 XXX01001
XX01010 XXX01010
XX01011 XXX01011
XX01100 XXX01100
XX01101 XXX01101
XX01110 XXX01110
XX01111 XXX01111
XX10000 XXX10000
XX10001 XXX10001
XX10010 XXX10010
XX10011 XXX10011
XX10100 XXX10100
XX10101 XXX10101
XX10110 XXX10110
XX10111 XXX10111
XX11000 XXX11000
XX11001 XXX11001
XX11010 XXX11010
XX11011 XXX11011
XX11100 XXX11100
XX11101 XXX11101
XX11110 XXX11110
1F
XX11111
Hex
Register
ID
ALB
RLB
TAO
LOS
SC
LOSM
SCM
LOSI
SCI
RS
PMON
DLB
LAC
ATAO
GCF
R/W
R
R/W
R/W
R/W
R
R
R/W
R/W
R
R
W
R/W
R/W
R/W
R/W
R/W
Explanation
Device ID Register
Analog Loopback Configuration Register
Remote Loopback Configuration Register
Transmit All One Code Configuration Register
Loss of Signal Status Register
Short Circuit Status Register
LOS Interrupt Mask Register
Short Circuit Interrupt Mask Register
LOS Interrupt Status Register
Short Circuit Interrupt Status Register
Software Reset Register
Performance Monitor Configuration Register
Digital Loopback Configuration Register
LOS/AIS Criteria Configuration Register
Automatic TAO Configuration Register
Global Configuration Register
Reserved
OE
AIS
AISM
AISI
XXX11111 ADDP
R/W
R
R/W
R
Output Enable Configuration Register
AIS Status Register
AIS Interrupt Mask Register
AIS Interrupt Status Register
Reserved
R/W
Address pointer control Register for switching between
primary register bank and expanded register bank
23
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 12. EXPANDED (INDIRECT ADDRESS MODE) REGISTER LIST
Address
serial
Hex interface
A7-A1
00 XX00000
01 XX00001
02 XX00010
03 XX00011
04 XX00100
05 XX00101
06 XX00110
07 XX00111
08 XX01000
09 XX01001
0A XX01010
0B XX01011
0C XX01100
0D XX01101
0E XX01110
0F XX01111
10 XX10000
11 XX10001
12 XX10010
13 XX10011
14 XX10100
15 XX10101
16 XX10110
17 XX10111
18 XX11000
19 XX11001
1A XX11010
1B XX11011
1C XX11100
1D XX11101
1E XX11110
parallel
interface
A7-A0
XXX00000
XXX00001
XXX00010
XXX00011
XXX00100
XXX00101
XXX00110
XXX00111
XXX01000
XXX01001
XXX01010
XXX01011
XXX01100
XXX01101
XXX01110
XXX01111
XXX10000
XXX10001
XXX10010
XXX10011
XXX10100
XXX10101
XXX10110
XXX10111
XXX11000
XXX11001
XXX11010
XXX11011
XXX11100
XXX11101
XXX11110
1F
XXX11111
XX11111
Register
e-SING
e-CODE
e-CRS
e-RPDN
e-TPDN
e-CZER
e-CODV
e-EQUA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Explanation
Single Rail Mode Setting Register
Encoder/Decoder Selection Register
Clock Recovery Enable/Disable Register
Receiver n Powerdown Enable/Disable Register
Transmitter n Powerdown Enable/Disable Register
Consecutive Zero Detect Enable/Disable Register
Code Violation Detect Enable/Disable Register
Enable Equalizer Enable/Disable Register
Test
ADDP
R/W
Address pointer control register for switching between primary
register bank and expanded register bank
24
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 13. PRIMARY REGISTER MAP
Register
ID
ALB
RLB
TAO
LOS
SC
LOSM
SCM
LOSI
SCI
RS
PMON
DLB
LAC
ATAO
GCF
Address
R/W
b7
Default
00 Hex
ID 7
R/W
R
Default
0
01 Hex
ALB 7
R/W
R/W
0
Default
02 Hex
RLB 7
R/W
R/W
Default
0
03 Hex
TAO 7
R/W
R/W
Default
0
04 Hex
LOS 7
R/W
R
0
Default
05 Hex
SC 7
R/W
R
0
Default
06 Hex
LOSM 7
R/W
R/W
Default
0
07 Hex
SCM 7
R/W
R/W
0
Default
08 Hex
LOSI 7
R
R/W
0
Default
09 Hex
SCI 7
R
R/W
0
Default
0A Hex
RS 7
W
W
Default
1
0B Hex
R/W
R/W
Default
0
0C Hex
DLB 7
R/W
R/W
Default
0
0D Hex
LAC 7
R/W
R/W
Default
0
0E Hex
ATAO 7
R/W
R/W
Default
0
0F Hex
R/W
R/W
Default
0
b6
b5
b4
b3
b2
b1
b0
ID 6
R
0
ALB 6
R/W
0
RLB 6
R/W
0
TAO 6
R/W
0
LOS 6
R
0
SC 6
R
0
LOSM 6
R/W
0
SCM 6
R/W
0
LOSI 6
R
0
SCI 6
R
0
RS 6
W
1
R/W
0
DLB 6
R/W
0
LAC 6
R/W
0
ATAO 6
R/W
0
AISE
R/W
0
ID 5
R
0
ALB 5
R/W
0
RLB 5
R/W
0
TAO 5
R/W
0
LOS 5
R
0
SC 5
R
0
LOSM 5
R/W
0
SCM 5
R/W
0
LOSI 5
R
0
SCI 5
R
0
RS 5
W
1
R/W
0
DLB 5
R/W
0
LAC 5
R/W
0
ATAO 5
R/W
0
SCPB
R/W
0
ID 4
R
1
ALB 4
R/W
0
RLB 4
R/W
0
TAO 4
R/W
0
LOS 4
R
0
SC 4
R
0
LOSM 4
R/W
0
SCM 4
R/W
0
LOSI 4
R
0
SCI 4
R
0
RS 4
W
1
R/W
0
DLB 4
R/W
0
LAC 4
R/W
0
ATAO 4
R/W
0
CODE
R/W
0
ID 3
R
0
ALB 3
R/W
0
RLB 3
R/W
0
TAO 3
R/W
0
LOS 3
R
0
SC 3
R
0
LOSM 3
R/W
0
SCM 3
R/W
0
LOSI 3
R
0
SCI 3
R
0
RS 3
W
1
MC 3
R/W
0
DLB 3
R/W
0
LAC 3
R/W
0
ATAO 3
R/W
0
JADP
R/W
0
ID 2
R
0
ALB 2
R/W
0
RLB 2
R/W
0
TAO 2
R/W
0
LOS 2
R
0
SC 2
R
0
LOSM 2
R/W
0
SCM 2
R/W
0
LOSI 2
R
0
SCI 2
R
0
RS 2
W
1
MC 2
R/W
0
DLB 2
R/W
0
LAC 2
R/W
0
ATAO 2
R/W
0
JABW
R/W
0
ID 1
R
0
ALB 1
R/W
0
RLB 1
R/W
0
TAO 1
R/W
0
LOS 1
R
0
SC 1
R
0
LOSM 1
R/W
0
SCM 1
R/W
0
LOSI 1
R
0
SCI 1
R
0
RS 1
W
1
MC 1
R/W
0
DLB 1
R/W
0
LAC 1
R/W
0
ATAO 1
R/W
0
JACF 1
R/W
0
ID 0
R
0
ALB 0
R/W
0
RLB 0
R/W
0
TAO 0
R/W
0
LOS 0
R
0
SC 0
R
0
LOSM 0
R/W
0
SCM 0
R/W
0
LOSI 0
R
0
SCI 0
R
0
RS 0
W
1
MC 0
R/W
0
DLB 0
R/W
0
LAC 0
R/W
0
ATAO 0
R/W
0
JACF 0
R/W
0
25
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 13. PRIMARY REGISTER MAP (CONTINUED)
Register
OE
AIS
AISM
AISI
ADDP
Address
R/W
b7
Default
OE 7
12 Hex
R/W
R/W
0
Default
13 Hex
AIS 7
R/W
R
Default
0
14 Hex
AISM 7
R/W
R/W
Default
0
15 Hex
AISI 7
R/W
R
0
Default
1F Hex
ADDP 7
R/W
R/W
Default
0
b6
b5
b4
b3
b2
b1
b0
OE 6
R/W
0
AIS 6
R
0
AISM 6
R/W
0
AISI 6
R
0
ADDP 6
R/W
0
OE 5
R/W
0
AIS 5
R
0
AISM 5
R/W
0
AISI 5
R
0
ADDP 5
R/W
0
OE 4
R/W
0
AIS 4
R
0
AISM 4
R/W
0
AISI 4
R
0
ADDP 4
R/W
0
OE 3
R/W
0
AIS 3
R
0
AISM 3
R/W
0
AISI 3
R
0
ADDP 3
R/W
0
OE 2
R/W
0
AIS 2
R
0
AISM 2
R/W
0
AISI 2
R
0
ADDP 2
R/W
0
OE 1
R/W
0
AIS 1
R
0
AISM 1
R/W
0
AISI 1
R
0
ADDP 1
R/W
0
OE 0
R/W
0
AIS 0
R
0
AISM 0
R/W
0
AISI 0
R
0
ADDP 0
R/W
0
TABLE - 14. EXPANDED (INDIRECT ADDRESS MODE) REGISTER MAP
Register
e-SING
e-CODE
e-CRS
e-RPDN
e-TPDN
e-CZER
e-CODV
e-EQUA
ADDP
Address
R/W
Default
00 Hex
R/W
Default
01 Hex
R/W
Default
02 Hex
R/W
Default
03 Hex
R/W
Default
04 Hex
R/W
Default
05 Hex
R/W
Default
06 Hex
R/W
Default
07 Hex
R/W
Default
1F Hex
R/W
Default
b7
b6
b5
b4
b3
b2
b1
b0
SING 7
R/W
0
CODE 7
R/W
0
CRS 7
R/W
0
RPDN 7
R/W
0
TPDN 7
R/W
0
CZER 7
R/W
0
CODV 7
R/W
0
EQUA 7
R/W
0
ADDP 7
R/W
0
SING 6
R/W
0
CODE 6
R/W
0
CRS 6
R/W
0
RPDN 6
R/W
0
TPDN 6
R/W
0
CZER 6
R/W
0
CODV 6
R/W
0
EQUA 6
R/W
0
ADDP 6
R/W
0
SING 5
R/W
0
CODE 5
R/W
0
CRS 5
R/W
0
RPDN 5
R/W
0
TPDN 5
R/W
0
CZER 5
R/W
0
CODV 5
R/W
0
EQUA 5
R/W
0
ADDP 5
R/W
0
SING 4
R/W
0
CODE 4
R/W
0
CRS 4
R/W
0
RPDN 4
R/W
0
TPDN 4
R/W
0
CZER 4
R/W
0
CODV 4
R/W
0
EQUA 4
R/W
0
ADDP 4
R/W
0
SING 3
R/W
0
CODE 3
R/W
0
CRS 3
R/W
0
RPDN 3
R/W
0
TPDN 3
R/W
0
CZER 3
R/W
0
CODV 3
R/W
0
EQUA 3
R/W
0
ADDP 3
R/W
0
SING 2
R/W
0
CODE 2
R/W
0
CRS 2
R/W
0
RPDN 2
R/W
0
TPDN 2
R/W
0
CZER 2
R/W
0
CODV 2
R/W
0
EQUA 2
R/W
0
ADDP 2
R/W
0
SING 1
R/W
0
CODE 1
R/W
0
CRS 1
R/W
0
RPDN 1
R/W
0
TPDN 1
R/W
0
CZER 1
R/W
0
CODV 1
R/W
0
EQUA 1
R/W
0
ADDP 1
R/W
0
SING 0
R/W
0
CODE 0
R/W
0
CRS 0
R/W
0
RPDN 0
R/W
0
TPDN 0
R/W
0
CZER 0
R/W
0
CODV 0
R/W
0
EQUA 0
R/W
0
ADDP 0
R/W
0
26
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
REGISTER DESCRIPTION
Primary Register Description
ID: Device ID Register (R, Address = 00 Hex)
Symbol
Position
Default
ID[7:0]
ID.7-0
10 H
Description
An 8-bit word is pre-set into the device as the identification and revision number. This number is
different with the functional changes and is mask programmed.
ALB: Analog Loopback Configuration Register (R/W, Address = 01 Hex)
Symbol
ALB[7:0]
Position
ALB.7-0
Default
Description
0 = Normal operation. (Default)
1 = Analog Loopback enabled.
00 H
RLB: Remote Loopback Configuration Register (R/W, Address = 02 Hex)
Symbol
RLB[7:0]
Position
RLB.7-0
Default
Description
0 = Normal operation. (Default)
1 = Remote Loopback enabled.
00 H
TAO: Transmit All One Code Configuration Register (R/W, Address = 03 Hex)
Symbol
TAO[7:0]
Position
Default
TAO.7-0
Description
0 = Normal operation. (Default)
1 = Transmit all one code.
00 H
LOS: Loss of Signal Status Register (R, Address = 04 Hex)
Symbol
LOS[7:0]
Position
Default
LOS.7-0
Description
0 = Normal operation. (Default)
1 = Loss of signal detected.
00 H
SC: Short Circuit Status Register (R, Address = 05 Hex)
Symbol
Position
Default
SC[7:0]
SC.7-0
00 H
Description
0 = Normal operation. (Default)
1 = Short circuit detected.
LOSM : Loss of Signal Interrupt Mask Register (R/W, Address = 06 Hex)
Symbol
Position
Default
LOSM[7:0]
LOSM.7-0
00 H
Description
0 = LOS interrupt is not allowed. (Default)
1 = LOS interrupt is allowed.
SCM: Short Circuit Interrupt Mask Register (R/W, Address = 07 Hex)
Symbol
Position
Default
SCM[7:0]
SCM.7-0
00 H
Description
0 = Short circuit interrupt is not allowed. (Default)
1 = Short circuit interrupt is allowed.
LOSI: Loss of Signal Interrupt Status Register (R, Address = 08 Hex)
Symbol
Position
Default
LOSI[7:0]
LOSI.7-0
00 H
Description
0 = (Default). Or after a LOS read operation.
1 = Any transition on LOSn (Corresponding LOSMn is set to 1).
27
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
SCI: Short Circuit Interrupt Status Register (R, Address = 09 Hex)
Symbol
Position
Default
SCI[7:0]
SCI.7-0
00 H
Description
0 = (Default). Or after an SC read operation.
1 = Any transition on SCn (Corresponding SCMn is set to 1).
RS: Software Reset Register (W, Address = 0A Hex)
Symbol
Position
Default
RS[7:0]
RS.7-0
FF H
Description
Writing to this register will not change the content in this register but initiate a 1µs reset cycle,
which means all the registers in the device are set to their default values.
PMON: Performance Monitor Configuration Register (R/W, Address = 0B Hex)
Symbol
-
MC[3:0]
Position
PMON.7-4
PMON.3-0
Default
Description
0 = Normal operation. (Default)
1 = Reserved.
MC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0000
Monitoring Configuration
Normal operation without monitoring.
Monitoring receiver 1.
Monitoring receiver 2.
Monitoring receiver 3.
Monitoring receiver 4.
Monitoring receiver 5.
Monitoring receiver 6.
Monitoring receiver 7.
Normal operation without monitoring.
Monitoring transmitter 1.
Monitoring transmitter 2.
Monitoring transmitter 3.
Monitoring transmitter 4.
Monitoring transmitter 5.
Monitoring transmitter 6.
Monitoring transmitter 7.
DLB: Digital Loopback Configuration Register (R/W, Address = 0C Hex)
Symbol
DLB[7:0]
Position
DLB.7-0
Default
00 H
Description
0 = Normal operation. (Default)
1 = Digital Loopback enabled.
LAC: LOS/AIS Criteria Configuration Register (R/W, Address = 0D Hex)
Symbol
LAC[7:0]
Position
LAC.7-0
Default
00 H
Description
0 = G.775 mode. (Default)
1 = ETSI 300233 mode.
ATAO: Automatic TAO Configuration Register (R/W, Address = 0E Hex)
Symbol
Position
Default
ATAO[7:0]
ATAO.7-0
00 H
Description
0 = No automatic TAO. (Default)
1 = Automatic transmit all ones to the line side on LOS.
28
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
GCF: Global Configuration Register (R/W, Address = 0F Hex)
Symbol
Position
Default
-
GCF.7
0
AISE
GCF.6
0
SCPB
GCF.5
0
CODE
GCF.4
0
JADP
GCF.3
0
JABW
GCF.2
0
JACF[1:0]
GCF.1-0
00
Description
0 = Normal operation. (Default)
1 = Reserved.
AIS Enable During LOS.
0 = AIS insertion to the system side disabled on LOS. (Default)
1 = AIS insertion to the system side enabled on LOS.
Short Circuit Protection Enable.
0 = Short circuit protection is enabled. (Default)
1 = Short circuit protection is disabled.
Line Code Enable.
0 = B8ZS/HDB3 encoder/decoder enabled. (Default)
1 = AMI encoder/decoder enabled.
Jitter Attenuator Depth Select.
0 = 32-bit FIFO. (Default)
1 = 64-bit FIFO.
Jitter Transfer Function Bandwidth Select.
0 = 1.7Hz. (Default)
1 = 6.6Hz.
Jitter Attenuator Configuration.
00 = JA not used. (Default)
01 = JA in transmit path.
10 = JA not used.
11 = JA in receive path.
OE: Output Enable Configuration Register (R/W, Address = 12 Hex)
Symbol
Position
Default
OE[7:0]
OE.7-0
00 H
Description
0 = Transmit drivers enabled. (Default)
1 = Transmit drivers placed in high impedance state.
AIS: Alarm Indication Signal Status Register (R, Address = 13 Hex)
Symbol
Position
AIS[7:0]
Default
AIS.7-0
00 H
Description
0 = Normal operation. (Default)
1 = AIS detected.
AISM : Alarm Indication Signal Interrupt Mask Register (R/W, Address = 14 Hex)
Symbol
Position
Default
AISM[7:0]
AISM.7-0
00 H
Description
0 = AIS interrupt is not allowed. (Default)
1 = AIS interrupt is allowed.
AISI: Alarm Indication Signal Interrupt Status Register (R, Address = 15 Hex)
Symbol
Position
Default
AISI[7:0]
AISI.7-0
00 H
Description
0 = (Default), or after an AIS read operation
1 = Any transition on AISn. (Corresponding AISMn is set to 1.)
ADDP: Address Pointer Control Register (R/W, Address = 1F Hex)
Symbol
Position
ADDP[7:0] ADDP.7-0
Default
00 H
Description
Two kinds of configuration in this register can be set to switch between primary register bank and expanded
register bank. When power up, the address pointer will point to the top address of primary register bank
automatically.
00H = The address pointer points to the top address of primary register bank (default).
AAH = The address pointer points to the top address of expanded register bank.
29
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Expanded Register Description
e-SING: Single Rail Mode Setting Register (R/W, Expanded Address = 00 Hex)
Symbol
Position
Default
SING[7:0]
SING.7-0
00 H
Description
0 = Pin TDNn selects single rail mode or dual rail mode. (Default)
1 = Single rail mode enabled (with CRSn=0)
e-CODE: Encoder/Decoder Selection Register (R/W, Expanded Address = 01 Hex)
Symbol
Position
Default
CODE[7:0]
CODE.7-0
00 H
Description
Line Code Selection.
CODEn selects AMI or B8ZS/HDB3 encoder/decoder on per-channel basis with SINGn = 1 and
CRSn = 0.
0 = B8ZS/HDB3 encoder/decoder enabled. (Default)
1 = AMI encoder/decoder enabled.
e-CRS: Clock Recovery Enable/Disable Selection Register (R/W, Expanded Address = 02 Hex)
Symbol
CRS[7:0]
Position
Default
CRS.7-0
00 H
Description
0 = Clock recovery enabled. (Default)
1 = Clock recovery disabled.
e-RPDN: Receiver n Powerdown Register (R/W, Expanded Address = 03 Hex)
Symbol
RPDN[7:0]
Position
Default
RPDN.7-0
00 H
Description
0 = Normal operation. (Default)
1 = Power down in receiver n.
e-TPDN: Transmitter n Powerdown Register (R/W, Expanded Address = 04 Hex)
Symbol
Position
Default
TPDN[7:0]
TPDN.7-0
00 H
Description
0 = Normal operation. (Default)
1 = Power down in Transmitter n (the corresponding transmit output driver enters a low power high
impedance mode).
Note that transmitter n is power down when either pin TCLKn is pulled to low or TPDNn is set to 1.
e-CZER: Consecutive Zero Detect Enable/Disable Register (R/W, Expanded Address = 05 Hex)
Symbol
Position
Default
CZER[7:0]
CZER.7-0
00 H
Description
0 = Excessive zero detect disabled. (Default)
1 = Excessive zero detect enabled for B8ZS/HDB3 decoder in single rail mode.
e-CODV: Code Violation Detect Enable/Disable Register (R/W, Expanded Address = 06 Hex)
Symbol
Position
Default
CODV[7:0]
CODV.7-0
00 H
Description
0 = Code Violation Detect enable for HDB3 decoder in single rail mode. (Default)
1 = Code Violation Detect disable.
30
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
e-EQUA: Receive Equalizer Enable/Disable Register (R/W, Expanded Address = 07 Hex)
Symbol
Position
Default
EQUA[7:0]
EQUA.7-0
00 H
Description
0 = Normal operation. (Default)
1 = Equalizer in Receiver n enabled, which can improved the receive performance when transmission
length is more than 200 m.
Reserved Registers: Primary Registers 10, 11, 16 - 1E are reservered.
Test Registers: Expand Registers 08 - 1E are test registers. They must be set to 0.
31
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
IEEE STD 1149.1 JTAG TEST ACCESS
PORT
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR)
The IR (Instruction Register) with instruction decode block is used to
select the test to be executed or the data register to be accessed or both.
The instructions are shifted in LSB first to this 3-bit register. See Table15 for details of the codes and the instructions related.
The IDT82V2048 supports the digital Boundary Scan Specification
as described in the IEEE 1149.1 standards.
The boundary scan architecture consists of data and instruction
registers plus a Test Access Port (TAP) controller. Control of the TAP is
achieved through signals applied to the Test Mode Select (TMS) and
Test Clock (TCK) input pins. Data is shifted into the registers via the
Test Data Input (TDI) pin, and shifted out of the registers via the Test
Data Output (TDO) pin. Both TDI and TDO are clocked at a rate determined by TCK.
The JTAG boundary scan registers includes BSR (Boundary
Scan Register), IDR (Device Identification Register), BR (Bypass
Register) and IR (Instruction Register). These will be described in the
following pages. Refer to Figure-18 for architecture.
Digital output pins
JTAG DATA REGISTER
Device Identification Register (IDR)
The IDR can be set to define the producer number, part number and
the device revision, which can be used to verify the proper version or
revision number that has been used in the system under test. The IDR
is 32 bits long and is partitioned as in Table-16. Data from the IDR is
shifted out to TDO LSB first.
Digital input pins
parallel latched output
BSR (Boundary Scan Register)
MUX
IDR (Device Identification Register)
TDI
MUX
BR (Bypass Register)
IR (Instruction Register)
Control<6:0>
TMS
TRST
TAP
(Test Access Port)
Controller
Select
Tristate Enable
TCK
Figure - 18. JTAG Architecture
32
TDO
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 15. INSTRUCTION REGISTER DESCRIPTION
IR CODE
INSTRUCTION
000
Extest
100
Sample / Preload
110
Idcode
111
Bypass
COMMENTS
The external test instruction allows testing of the interconnection to other devices. When the current
instruction is the EXTEST instruction, the boundary scan register is placed between TDI and TDO.
The signal on the input pins can be sampled by loading the boundary scan register using the CaptureDR state. The sampled values can then be viewed by shifting the boundary scan register using the
Shift-DR state. The signal on the output pins can be controlled by loading patterns shifted in through
input TDI into the boundary scan register using the Update-DR state.
The sample instruction samples all the device inputs and outputs. For this instruction, the boundary
scan register is placed between TDI and TDO. The normal path between the IDT82V2058 logic and
the I/O pins is maintained. Primary device inputs and outputs can be sampled by loading the boundary
scan register using the Capture-DR state. The sampled values can then be viewed by shifting the
boundary scan register using the Shift-DR state.
The identification instruction is used to connect the identification register between TDI and TDO. The
device's identification code can then be shifted out using the Shift-DR state.
The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The
instruction is used to bypass the device.
TABLE - 16. DEVICE IDENTIFICATION REGISTER DESCRIPTION
BIT No.
0
1~11
12~27
28~31
Boundary Scan Register (BSR)
The BSR can apply and read test patterns in parallel to or from all
the digital I/O pins. The BSR is a 98 bits long shift register and is initialized
and read using the instruction EXTEST or SAMPLE/PRELOAD. Each
pin is related to one or more bits in the BSR. Please refer to Table-17
for details of BSR bits and their functions.
COMMENTS
Set to “1”
Producer Number
Part Number
Device Revision
TEST ACCESS PORT CONTROLLER
The TAP controller is a 16-state synchronous state machine. Figure19 shows its state diagram. A description of each state follows. Note that
the figure contains two main branches to access either the data or
instruction registers. The value shown next to each state transition in
this figure states the value present at TMS at each rising edge of TCK.
Please refer to Table-18 for details of the state description.
Bypass Register (BR)
The BR consists of a single bit. It can provide a serial path between
the TDI input and TDO output, bypassing the BSR to reduce test access
times.
TABLE - 17. BOUNDARY SCAN REGISTER DESCRIPTION
BIT No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BIT SYMBOL
POUT0
PIN0
POUT1
PIN1
POUT2
PIN2
POUT3
PIN3
POUT4
PIN4
POUT5
PIN5
POUT6
PIN6
POUT7
PIN7
PIN SIGNAL
LP0
LP0
LP1
LP1
LP2
LP2
LP3
LP3
LP4
LP4
LP5
LP5
LP6
LP6
LP7
LP7
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
COMMENTS
33
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 17. BOUNDARY SCAN REGISTER DESCRIPTION (CONTINUED)
BIT No.
16
BIT SYMBOL
PIOS
PIN SIGNAL
N/A
TYPE
-
17
18
19
20
21
22
23
TCLK1
TDP1
TDN1
RCLK1
RDP1
RDN1
HZEN1
TCLK1
TDP1
TDN1
RCLK1
RDP1
RDN1
N/A
I
I
I
O
O
O
-
24
25
26
27
28
29
30
31
LOS1
TCLK0
TDP0
TDN0
RCLK0
RDP0
RDN0
HZEN0
LOS1
TCLK0
TDP0
TDN0
RCLK0
RDP0
RDN0
N/A
O
I
I
I
O
O
O
-
32
33
34
35
36
37
LOS0
MODE1
LOS3
RDN3
RDP3
HZEN3
LOS0
MODE1
LOS3
RDN3
RDP3
N/A
O
I
O
O
O
-
38
39
40
41
42
43
44
45
RCLK3
TDN3
TDP3
TCLK3
LOS2
RDN2
RDP2
HZEN2
RCLK3
TDN3
TDP3
TCLK3
LOS2
RDN2
RDP2
N/A
O
I
I
I
O
O
O
-
46
47
48
49
50
51
52
RCLK2
TDN2
TDP2
TCLK2
INT
ACK
SDORDYS
RCLK2
TDN2
TDP2
TCLK2
INT
ACK
N/A
O
I
I
I
O
O
-
53
54
55
WRB
RDB
ALE
DS
R/W
ALE
I
I
I
COMMENTS
Controls pin LP7~0.
When “0”, the pins are configured as outputs. The output values to the
pins are set in POUT7~0.
When “1”, the pins are tristated. The input values to the pins are read in
PIN7~0.
Controls pin RDP1, RDN1 and RCLK1.
When “0”, the outputs are enabled on the pins.
When “1”, the pins are tristated.
Controls pin RDP0, RDN0 and RCLK0.
When “0”, the outputs are enabled on the pins.
When “1”, the pins are tristated.
Controls pin RDP3, RDN3 and RCLK3.
When “0”, the outputs are enabled on the pins.
When “1”, the pins are tristated.
Controls pin RDP2, RDN2 and RCLK2.
When “0”, the outputs are enabled on the pins.
When “1”, the pins are tristated.
Control pin ACK.
When “0”, the output is enabled on pin ACK.
When “1”, the pin is tristated.
34
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 17. BOUNDARY SCAN REGISTER DESCRIPTION (CONTINUED)
BIT No.
56
57
58
59
60
61
62
63
64
BIT SYMBOL
CSB
MODE0
TCLK5
TDP5
TDN5
RCLK5
RDP5
RDN5
HZEN5
PIN SIGNAL
CS
MODE0
TCLK5
TDP5
TDN5
RCLK5
RDP5
RDN5
N/A
TYPE
I
I
I
I
I
O
O
O
-
65
66
67
68
69
70
71
72
LOS5
TCLK4
TDP4
TDN4
RCLK4
RDP4
RDN4
HZEN4
LOS5
TCLK4
TDP4
TDN4
RCLK4
RDP4
RDN4
N/A
O
I
I
I
O
O
O
-
73
74
75
76
77
78
79
LOS4
OE
CLKE
LOS7
RDN7
RDP7
HZEN7
LOS4
OE
CLKE
LOS7
RDN7
RDP7
N/A
O
I
I
O
O
O
-
80
81
82
83
84
85
86
87
RCLK7
TDN7
TDP7
TCLK7
LOS6
RDN6
RDP6
HZEN6
RCLK7
TDN7
TDP7
TCLK7
LOS6
RDN6
RDP6
N/A
O
I
I
I
O
O
O
-
88
89
90
91
92
93
94
95
96
97
98
RCLK6
TDN6
TDP6
TCLK6
MCLK
MODE2
A4
A3
A2
A1
A0
RCLK6
TDN6
TDP6
TCLK6
MCLK
MODE2
A4
A3
A2
A1
A0
O
I
I
I
I
I
I
I
I
I
I
COMMENTS
Controls pin RDP5, RDN5 and RCLK5.
When “0”, the outputs are enabled on the pins.
When “1”, the pins are tristated.
Controls pin RDP4, RDN4 and RCLK4.
When “0”, the outputs are enabled on the pins.
When “1”, the pins are tristated.
Controls pin RDP7, RDN7 and RCLK7.
When “0”, the outputs are enabled on the pins.
When “1”, the pins are tristated.
Controls pin RDP6, RDN6 and RCLK6.
When “0”, the outputs are enabled on the pins.
When “1”, the pins are tristated.
35
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 18. TAP CONTROLLER STATE DESCRIPTION
STATE
Test Logic
Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-Scan
Capture-IR
Shift-IR
DESCRIPTION
In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device
initializes the instruction register with the IDCODE instruction.
Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input
is held high for at least 5 rising edges of TCK. The controller remains in this state while TMS is high. The device
processor automatically enters this state at power-up.
This is a controller state between scan operations. Once in this state, the controller remains in the state as long as
TMS is held low. The instruction register and all test data registers retain their previous state. When TMS is high and a
rising edge is applied to TCK, the controller moves to the Select-DR state.
This is a temporary controller state and the instruction does not change in this state. The test data register selected
by the current instruction retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this
state, the controller moves into the Capture-DR state and a scan sequence for the selected test data register is initiated.
If TMS is held high and a rising edge applied to TCK, the controller moves to the Select-IR-Scan state.
In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or
SAMPLE/PRELOAD. The instruction does not change in this state. The other test data registers, which do not have
parallel input, are not changed. When the TAP controller is in this state and a rising edge is applied to TCK, the
controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
In this controller state, the test data register connected between TDI and TDO as a result of the current instruction
shifts data on stage toward its serial output on each rising edge of TCK. The instruction does not change in this state.
When the TAP controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if
TMS is high or remains in the Shift-DR state if TMS is low.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller
to enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to
TCK, the controller enters the Pause-DR state. The test data register selected by the current instruction retains its
previous value and the instruction does not change during this state.
The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the
serial path between TDI and TDO. For example, this state could be used to allow the tester to reload its pin memory
from disk during application of a long test sequence. The test data register selected by the current instruction retains its
previous value and the instruction does not change during this state. The controller remains in this state as long as TMS
is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-DR state.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller
to enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to
TCK, the controller enters the Shift-DR state. The test data register selected by the current instruction retains its
previous value and the instruction does not change during this state.
The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in
response to the EXTEST and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the
Boundary Scan Register is selected, data is latched into the parallel output of this register from the shift-register path on
the falling edge of TCK. The data held at the latched parallel output changes only in this state. All shift-register stages in
the test data register selected by the current instruction retain their previous value and the instruction does not change
during this state.
This is a temporary controller state. The test data register selected by the current instruction retains its previous
state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-IR
state, and a scan sequence for the instruction register is initiated. If TMS is held high and a rising edge is applied to
TCK, the controller moves to the Test-Logic-Reset state. The instruction does not change during this state.
In this controller state, the shift register contained in the instruction register loads a fixed value of ‘100’ on the rising
edge of TCK. This supports fault-isolation of the board-level serial test data path. Data registers selected by the current
instruction retain their value and the instruction does not change during this state. When the controller is in this state
and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or the Shift-IR state if
TMS is held low.
In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data
one stage towards its serial output on each rising edge of TCK. The test data register selected by the current instruction
retains its previous value and the instruction does not change during this state. When the controller is in this state and a
rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or remains in the Shift-IR state
if TMS is held low.
36
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TABLE - 19. TAP CONTROLLER STATE DESCRIPTION (CONTINUED)
STATE
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
DESCRIPTION
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to
enter the Update-IR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the
controller enters the Pause-IR state. The test data register selected by the current instruction retains its previous value and
the instruction does not change during this state.
The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test
data register selected by the current instruction retains its previous value and the instruction does not change during this
state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK,
the controller moves to the Exit2-IR state.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to
enter the Update-IR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the
controller enters the Shift-IR state. The test data register selected by the current instruction retains its previous value and the
instruction does not change during this state.
The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling
edge of TCK. When the new instruction has been latched, it becomes the current instruction. The test data registers selected
by the current instruction retain their previous value.
1
Test-logic Reset
0
0
Run Test/Idle
1
Select-DR
1
Select-IR
0
1
0
1
Capture-DR
Capture-IR
0
0
0
0
Shift-DR
Shift-IR
1
1
1
Exit1-DR
1
Exit1-IR
0
0
0
0
Pause-DR
Pause-IR
1
0
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
0
1
Figure - 19. JTAG State Diagram
37
1
Update-IR
1
0
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING
Symbol
VDDA,VDDD
VDDIO0,VDDIO1
VDDT0-7
Parameter
Core Power Supply
I/O Power Supply
Transmit Power Supply
Input Voltage, Any Digital Pin
Min
-0.5
-0.5
-0.5
GND-0.5
Vin
Input Voltage, Any RTIP and RRING pin (1)
GND-0.5
Max
4.0
4.0
7.0
5.5
VDDA+0.5
VDDD+0.5
Unit
V
V
V
V
V
ESD Voltage, any pin (2)
2000
V
Transient latch-up current, any pin
100
mA
Input current, any digital pin (3)
-10
10
mA
Iin
(3)
±
DC Input current, any analog pin
100
mA
Pd
Maximum power dissipation in package
1.6
W
°C
Tc
Case Temperature
120
°C
Ts
Storage Temperature
-65
+150
CAUTION
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTE:
1. Referenced to ground
2. Human body model
3. Constant input current
RECOMMENDED OPERATING CONDITIONS
Symbol
VDDA,VDDD
VDDIO
VDDT
TA
RL
IVDD
IVDDIO
IVDDT
Parameter
Core Power Supply
I/O Power Supply
Transmitter Supply
3.3V
5V
Ambient operating temperature
Output load at TTIP and TRING
Average core power supply current (1)
IO power supply current (3)
Average transmitter power supply current, E1
mode (1, 2)
75Ω
50% ones density data:
100% ones density data:
120 Ω
50% ones density data:
100% ones density data:
Min
3.13
3.13
Typ
3.3
3.3
Max
3.47
3.47
Unit
V
V
3.13
4.75
-40
25
3.3
5.0
25
3.47
5.25
85
40
15
60
25
V
V
°C
Ω
mA
mA
NOTE:
1. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels.
2. Power consumption includes power absorbed by line load and external transmitter components.
3. Digital output is driving 50pF load, digital input is within 10% of the supply rails.
38
125
220
100
200
mA
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
POWER CONSUMPTION
Symbol
Parameter
E1, 3.3V, 75 Ω Load
50% ones density data:
100% ones density data:
E1, 3.3V, 120 Ω Load
50% ones density data:
100% ones density data:
E1, 5.0V, 75 Ω Load
50% ones density data:
100% ones density data:
E1, 5.0V, 120 Ω Load
50% ones density data:
100% ones density data:
LEN
Min
Typ
Max(1, 2)
Unit
000
000
-
612
1050
1125
mW
000
000
-
526
880
940
mW
000
000
-
835
1510
1610
mW
000
000
-
710
1240
1330
mW
Max
Unit
1
3 VDDIO-0.2
0.8
V
2
VDDIO-0.2
3
V
NOTE:
1. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels.
2. Power consumption includes power absorbed by line load and external transmitter components.
3. T1 maximum values measured with maximum cable length (LEN = 111). Typical values measured with typical cable length (LEN = 101).
DC CHARACTERISTICS
Symbol
VIL
Parameter
Input Low Level Voltage
Min
Typ
MODE2, JAS, LPn pins
VIM
All other digital inputs pins
Input Mid Level Voltage
1
VDDIO+0.2
3
MODE2, JAS, LPn pins
VIH
Input High Voltage
MODE2, JAS, LPn pins
VOL
VOH
VMA
IH
IL
II
IZL
Z OH
1
2 VDDIO
All other digital inputs pins
Output Low level Voltage (1)
(Iout=1.6mA)
Output High level Voltage (1)
(Iout=400µA)
Analog Input Quiescent Voltage
(RTIP, RRING pin while floating)
Input High Level Current
(MODE2, JAS, LPn pin)
Input Low Level Current
(MODE2, JAS, LPn pin)
Input Leakage Current
TMS, TDI, TRST
All other digital input pins
Tri-state Leakage Current
Output High Impedance on (TTIP, TRING Pins)
NOTE:
1. Output drivers will output CMOS logic levels into CMOS loads.
39
2
3 VDDIO+ 0.2
2.0
V
2.4
1.33
-10
-10
150
1.4
0.4
V
VDDIO
V
1.47
V
50
µA
50
µA
50
10
10
µA
µA
µA
KΩ
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TRANSMITTER CHARACTERISTICS
Symbol
Parameter
V0-p
Output pulse amplitudes (1)
E1, 75 Ω load
E1,120Ω load
VO-S
Zero (space) level
E1, 75 Ω load
E1,120 Ω load
Transmit amplitude variation with supply
Difference between pulse sequences for 17 consecutive pulses
T PW
Output Pulse Width at 50% of nominal amplitude:
Ratio of the amplitudes of Positive and Negative Pulses at the
center of the pulse interval
RTX
Transmit Return Loss (2)
51 KHz – 102 KHz
E1,75 Ω
102 KHz - 2.048 MHz
2.048 MHz – 3.072 MHz
51 KHz – 102 KHz
E1,120Ω
102 KHz - 2.048 MHz
2.048 MHz – 3.072 MHz
JTXP-P
Intrinsic Transmit Jitter (TCLK is jitter free, JA enable)
E1: 20 HZ – 100 KHz
Td
Transmit path delay
(JA is disabled)
Single rail
Dual rail
ISC
Line short circuit current (3)
NOTE:
1. E1:measured at the line output ports
2. Test at IDT82V2058 evaluation board
3. Measured at 2x9.5Ω series resistors and 1:2 transformer
40
Min
Typ
Max
Unit
2.14
2.7
2.37
3.0
2.6
3.3
V
V
-0.237
-0.3
0.237
0.3
V
V
-1
+1
200
256
%
mV
ns
232
244
0.95
1.05
15
15
15
15
15
15
dB
dB
dB
dB
dB
dB
0.050
U.I.
8
3
U.I.
U.I.
mA
Ip-p
150
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
RECEIVER CHARACTERISTICS
Symbol
ATT
IA
SIR
SRE
JRX p-p
JTRX
ZDM
ZCM
RRX
Parameter
Permissible Cable Attenuation (@1024kHz)
Input Amplitude
Signal to Interference Ratio Margin (1)
Data decision threshold (reference to peak input voltage)
Data slicer threshold
Analog loss of signal (2)
Threshold:
Hysteresis:
Allowable consecutive zeros before LOS
E1, G.775:
E1, ETSI300233:
LOS reset
Clock recovery mode
Peak to Peak Intrinsic Receive Jitter (JA disabled)
Jitter Tolerance
1 Hz – 20 Hz
20 Hz – 2.4 KHz
18 KHz – 100 KHz
Receiver Differential Input Impedance
Receiver Common Mode Input Impedance to GND
Receive Return Loss
51 KHz – 102 KHz
102 KHz - 2.048 MHz
2.048 MHz – 3.072 MHz
Receive path delay
Dual rail
Single rail
Min
Typ
50
150
Unit
dB
Vp
dB
%
mV
310
230
mV
mV
0.1
-14
Max
15
0.8
32
2048
12.5
0.0625
18.0
1.5
0.2
% ones
U.I.
10
U.I.
U.I.
U.I.
KΩ
KΩ
20
20
20
db
dB
dB
120
3
8
U.I.
U.I.
NOTE:
1. E1: per G.703, O.151 @6dB cable attenuation.
2. The test circuit for this parameter is shown in Figure 12. The analog signal is measured on the Receiver line before the transformer (port A and port B in Figure 12). And
the receive line is a T1/E1 cable simulator.
JITTER ATTENUATOR CHARACTERISTICS
Symbol
Parameter
f-3dB
Jitter Transfer Function Corner (–3dB) Frequency
Host mode:
32/64 bit FIFO
JABW = 0:
JABW = 1:
Hardware mode
Jitter Attenuator (1)
@ 3 Hz
@ 40 Hz
@ 400 Hz
@ 100kHz
td
Jitter Attenuator Latency Delay
32bit FIFO:
64bit FIFO:
Input jitter tolerance before FIFO overflow or underflow
32bit FIFO:
64bit FIFO:
Output jitter in remote loopback (2)
NOTE:
1. Per G.736, see Fig-35.
2. Per ETSI CTR12/13 Output jitter.
41
Min
Typ
Max
1.7
6.6
1.7
Unit
Hz
Hz
Hz
-0.5
-0.5
+19.5
+19.5
dB
16
32
U.I.
U.I.
28
56
U.I.
U.I.
U.I.
0.11
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TRANSCEIVER TIMING CHARACTERISTICS
Symbol
Parameter
Min
MCLK frequency
MCLK tolerance
MCLK duty cycle
Typ
2.048
-100
40
Max
100
60
Unit
MHz
ppm
%
Transmit path
t1
t2
TCLK frequency
TCLK tolerance
TCLK Duty Cycle
Transmit Data Setup Time
Transmit Data Hold Time
Delay time of OE low to driver High Z
Delay time of TCLK low to driver High Z
2.048
-50
10
40
40
40
+50
90
44
1
48
+/- 80
50
488
244
244
60
519
285
285
MHz
ppm
%
ns
ns
us
us
Receive path
t4
t5
t6
t7
t8
t9
Clock recovery capture range (1)
RCLK duty cycle (2)
RCLK pulse width (2)
RCLK pulse width low time
RCLK pulse width high time
Rise/fall time (3)
Receive Data Setup Time
Receive Data Hold Time
RDN/RDP pulse width (MCLK = H) (4)
40
457
203
203
20
200
200
200
244
244
244
ppm
%
ns
ns
ns
ns
ns
ns
ns
NOTE:
1. Relative to nominal frequency, MCLK=+/-100 ppm
2. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement
for E1 per ITU G.823).
3. For all digital outputs. C load = 15 pF
4. Clock recovery is disabled in this mode.
42
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TCLK
t1
t2
TNn/TDPn
TDNn/BPVIn
Figure - 21. Transmit System Interface Timing
t4
RCLK
t6
t5
t7
t8
RDPn/RDn
(CLKE = 1)
RDNn/CVn
t7
RDPn/RDn
(CLKE = 0)
RDNn/CVn
Figure - 22. Receive System Interface Timing
43
t8
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
JTAG TIMING CHARACTERISTICS
Symbol
Parameter
t1
TCK Period
t2
TMS to TCK setup Time
TDI to TCK Setup Time
t3
TCK to TMS Hold Time
TCK to TDI Hold Time
t4
TCK to TDO Delay Time
Min
200
Typ
ns
50
ns
100
TCK
t3
TMS
TDI
t4
TDO
Figure - 23. JTAG Interface Timing
44
Unit
ns
50
t1
t2
Max
ns
Comments
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PARALLEL HOST INTERFACE TIMING CHARACTERISTICS
INTEL MODE READ TIMING CHARACTERISTICS
Parameter
Min Typ Max
90
Active RD Pulse Width
0
Active CS to Active RD Setup Time
0
Inactive RD to Inactive CS Hold Time
Valid Address to Inactive ALE Setup Time (in Multiplexed Mode)
5
0
Invalid RD to Address Hold Time (in Non-Multiplexed Mode)
7.5
15
Active RD to Data Output Enable Time
7.5
15
Inactive RD to Data Tri-State Delay Time
6
12
CS
Active
to RDY delay time
6
12
Inactive CS to RDY Tri-state Delay Time
20
Inactive RD to Inactive INT Delay Time
Address Latch Enable Pulse Width (in Multiplexed Mode)
10
0
Address Latch Enable to RD Setup Time (in Multiplexed Mode)
Address Setup time to Valid Data Time (in Non-Multiplexed Mode)
18
32
Inactive ALE to Valid Data Time (in Multiplexed Mode)
t14
10
15
Inactive RD to Active RDY Delay Time
t15
30
85
Active RD to Active RDY Delay Time
t16
Inactive ALE to Address Hold Time (in Multiplexed Mode)
5
Note 1: the t1 is determined by the start time of the valid data when the RDY signal is not used.
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
45
Unit Comments
ns
note 1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
t2
CS
t3
t1
RD
ALE(=1)
t13
t5
ADDRESS
A[7:0]
t6
t7
DATA OUT
D[7:0]
t14
t8
t9
RDY
t15
t10
INT
Figure - 24. Non-Multiplexed Intel Mode Read Timing
t2
CS
t3
t1
RD
t11
t12
t13
ALE
t16
t4
AD[7:0]
t6
t7
ADDRESS
DATA OUT
t14
t8
t9
RDY
t15
t10
INT
Figure - 25. Multiplexed Intel Mode Read Timing
46
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
INTEL MODE WRITE TIMING CHARACTERISTICS
Symbol
Parameter
t1
Active WR Pulse Width
t2
Active CS to Active WR Setup Time
t3
Inactive WR to Inactive CS Hold Time
t4
Valid Address to Latch Enable Setup Time (in Multiplexed Mode)
t5
Invalid WR to Address Hold Time (in Non-Multiplexed Mode)
t6
Valid Data to Inactive WR Setup Time
t7
Inactive WR to Data Hold Time
t8
Active CS to Inactive RDY Delay Time
t9
Active WR to Active RDY Delay Time
t10
Inactive WR to Inactive RDY Delay Time
t11
Invalid CS to RDY Tri-State Delay Time
t12
Address Latch Enable Pulse Width (in Multiplexed Mode)
t13
Inactive ALE to WR Setup Time (in Multiplexed Mode)
t14
Inactive ALE to Address hold time (in Multiplexed Mode)
t15
Address setup time to Inactive WR time (in Non-Multiplexed Mode)
Note 1: the t1 can be 15ns when RDY signal is not used.
Min
90
0
0
5
2
5
10
6
30
10
6
10
0
5
5
Typ Max Unit Comments
ns
note 1
ns
ns
ns
ns
ns
ns
12
ns
85
ns
15
ns
12
ns
ns
ns
ns
ns
CS
t2
t1
t3
WR
ALE(=1)
t15
t5
ADDRESS
A[7:0]
t6
t7
WRITE DATA
D[7:0]
t10
t8
t11
RDY
t9
Figure - 26. Non-Multiplexed Intel Mode Write Timing
t2
CS
t3
t1
WR
t12
t13
ALE
t14
t4
AD[7:0]
t6
ADDRESS
t8
t7
WRITE DATA
t11
t9
RDY
t10
Figure - 27. Multiplexed Intel Mode Write Timing
47
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
MOTOROLA MODE READ TIMING CHARACTERISTICS
Symbol
t1
t2
t3
t4
t5
t6
Parameter
Min Typ Max Unit Comments
90
ns
note 1
DS
Active
Pulse Width
0
ns
Active CS to Active DS Setup Time
0
ns
Inactive DS to Inactive CS Hold Time
0
ns
Valid R/W to Active DS Setup Time
0.5
ns
Inactive DS to R/W Hold Time
ns
Valid Address to Active DS Setup Time (in Non-Multiplexed Mode)
5
AS
Valid Address to
Setup Time (in Multiplexed Mode)
t7
ns
Active DS to Address Hold Time (in Non-Multiplexed Mode)
10
Active AS to Address Hold Time (in Multiplexed Mode)
t8
ns
Active DS to Data Valid Delay Time (in Non-Multiplexed Mode)
20
35
Active AS to Data Valid Delay Time ( in Multiplexed Mode)
t9
7.5
15
ns
Active DS to Data Output Enable Time
t10
7.5
15
ns
DS
Inactive
to Data Tri-State Delay Time
t11
30
85
ns
Active DS to Active ACK Delay Time
t12
10
15
ns
Inactive DS to Inactive ACK Delay Time
t13
20
ns
DS
INT
Inactive
to Invalid
Delay Time
t14
5
ns
Active AS to Active DS Setup Time (in Multiplexed Mode)
Note 1: the t1 is determined by the start time of the valid data when the ACK signal is not used.
CS
t4
t5
R/W
t2
DS
ALE(=1)
t1
t6
t3
t7
ADDRESS
A[7:0]
t10
t8
DATA OUT
D[7:0]
t9
ACK
INT
t12
t11
t13
Figure - 28. Non-Multiplexed Motorola Mode Read Timing
CS
t2
t3
R/W
t1
t4
DS
t5
t14
AS
t6
AD[7:0]
t7
ADDRESS
t8
t9
t10
DATA OUT
t11
t12
ACK
t13
INT
Figure - 29. Multiplexed Motorola Mode Read Timing
48
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
MOTOROLA MODE WRITE TIMING CHARACTERISTICS
Symbol
t1
t2
t3
t4
t5
t6
Parameter
Active DS Pulse Width
Active CS to Active DS Setup Time
Inactive DS to Inactive CS Hold Time
Valid R/ W to Active DS Setup Time
Inactive DS to R/W Hold Time
Valid Address to Active DS Setup Time (in Non-Multiplexed Mode)
Valid Address to AS Setup Time (in Multiplexed Mode)
t7
Valid DS to Address Hold Time (in Non-Multiplexed Mode)
Valid AS to Address Hold Time (in Multiplexed Mode)
t8
Valid Data to Inactive DS Setup Time
t9
Inactive DS to Data Hold Time
t10
Active DS to Active ACK Delay Time
t11
Inactive DS to Inactive ACK Delay Time
t12
Active AS to Active DS (in Multiplexed Mode)
t13
Inactive DS to Inactive AS Hold Time ( in Multiplexed Mode)
Note 1: the t1 can be 15ns when the ACK signal is not used.
Min
90
0
0
10
0
Typ Max Unit Comments
ns
note 1
ns
ns
ns
ns
ns
10
ns
10
5
10
30
10
0
15
ns
ns
ns
ns
ns
ns
85
15
CS
t4
t5
R/W
t2
DS
ALE(=1)
A[7:0]
t1
t6
t3
t7
ADDRESS
t8
t9
WRITE DATA
D[7:0]
t10
t11
ACK
Figure - 30. Non-Multiplexed Motorola Mode Write Timing
CS
t2
t3
R/W
t4
DS
t1
t5
t12
t13
AS
t6
AD[7:0]
t8
t7
ADDRESS
t9
WRITE DATA
t10
ACK
Figure - 31. Multiplexed Motorola Mode Writing Timing
49
t11
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
SERIAL HOST INTERFACE TIMING CHARACTERISTICS
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Parameter
SCLK High Time
SCLK Low Time
Active CS to SCLK Setup Time
Last SCLK Hold Time to Inactive CS Time
CS Idle Time
SDI to SCLK Setup Time
SCLK to SDI Hold Time
Rise/Fall Time (any pin)
SCLK Rise and Fall Time
SCLK to SDO Valid Delay Time
SCLK Falling Edge to SDO tri-state Hold Time (CLKE = 0)
CS Rising Edge to SDO tri-state Hold Time (CLKE = 1)
Min
25
25
10
50
50
5
5
Typ
Max
Unit Comments
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
50
100
100
CS
t3
t1
t4
t2
t5
SCLK
t6
SDI
t7
t7
LSB
LSB
MSB
CONTROL BYTE
DATA BYTE
Figure - 32. Serial Interface Write Timing
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
t4
CS
t11
SDO
0
1
2
3
4
5
6
7
13
14
15
16
Figure - 33. Serial Interface Read Timing with CLKE = 0
1
2
3
4
5
6
7
8
9
10
11
12
SCLK
t4
CS
t11
SDO
0
1
2
3
Figure - 34. Serial Interface Read Timing with CLKE = 1
50
4
5
6
7
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
JITTER TOLERANCE PERFORMANCE
1 10
3
100
18 UI @ 1.8 Hz
Jitter (UI)
G.823
IDT82V2048
10
1.5 UI @ 20 Hz
1
1.5 UI @ 2.4
kHz
0.2 UI @ 18 kHz
0.1
1
10
100
1 10
3
4
1 10
1 10
5
Frequency (Hz)
Figure - 35. E1 Jitter Tolerance Performance
Test condition: PRBS 2^15-1; Line code rule HDB3 is used.
JITTER TRANSFER PERFORMANCE
0.5 dB @ 3 Hz 0.5 dB @ 40 Hz
0
-20
-19.5 dB @ 20 kHz
Gain (dB)
G.736
-19.5 dB @
400 Hz
IDT82V2048
f3dB = 6.5 Hz
-40
-60
f3dB = 1.7 Hz
1
10
100
1 103
Frequency (Hz)
Figure - 36. E1 Jitter Transfer Performance
Test condition: PRBS 2^15-1; Line code rule HDB3 is used.
51
1 104
1 105
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXXXXX
Device Type
XX
X
Process/
Temperature
Range
Blank
Industrial (-40 °C to +85 °C)
BB
DA
Plastic Ball Grid Array (PBGA, BB160)
Thin Quad Flatpack (TQFP, DA144)
82V2058
E1 Short Haul LIU
Data Sheet Document History
11/4/2001
11/20/2001
11/28/2001
11/29/2001
12/5/2001
1/24/2002
2/21/2002
3/25/2002
4/17/2002
5/7/2002
1/15/2003
pgs. 2, 3, 10, 17
pgs. 5, 6, 11, 13, 16, 17, 24, 26, 31, 38, 39, 40, 50
pgs. 5, 24, 26, 31
pgs. 5
pgs. 9
pgs. 2, 3, 9, 14, 39, 40
pgs. 14, 16, 41
pgs. 1, 2, 52
pgs. 17
pgs. 14, 44, 45, 48
pgs. 1, 52
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email: [email protected]
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52
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