Samsung M366S2953MTS Pc133/pc100 unbuffered dimm Datasheet

Preliminary
PC133/PC100 Unbuffered DIMM
M366S2953MTS
M366S2953MTS SDRAM DIMM
128Mx64 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
FEATURE
The Samsung M366S2953MTS is a 64M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M366S2953MTS consists of sixteen CMOS 64M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each SDRAM.
The M366S2953MTS is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
• Performance range
Part No.
M366S2953MTS-C75
M366S3953MTS-C1H
M366S2953MTS-C1L
• Burst mode operation
•
•
•
•
Auto & self refresh capability (8192 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V ± 0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,375mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
*CB0
*CB1
VSS
NC
NC
VDD
WE
DQM0
Front
Pin Front Pin
29 DQM1 57
58
CS0
30
59
31
DU
60
32
VSS
61
33
A0
62
34
A2
63
35
A4
64
36
A6
65
37
A8
38 A10/AP 66
67
39
BA1
68
40
VDD
69
41
VDD
42 CLK0 70
71
43
VSS
72
44
DU
73
45
CS2
46 DQM2 74
47 DQM3 75
76
48
DU
77
49
VDD
78
50
NC
79
51
NC
52 *CB2 80
53 *CB3 81
82
54
VSS
55 DQ16 83
56 DQ17 84
DQ18
DQ19
VDD
DQ20
NC
*VREF
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
*WP
**SDA
**SCL
VDD
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Max Freq. (Speed)
133MHz@CL=3
100MHz @ CL=2
100MHz @ CL=3
PIN NAMES
Back
Pin
Back
Pin
Back
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
*CB4
*CB5
VSS
NC
NC
VDD
CAS
DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CLK1
A12
VSS
CKE0
CS3
DQM6
DQM7
*A13
VDD
NC
NC
*CB6
*CB7
VSS
DQ48
DQ49
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ50
DQ51
VDD
DQ52
NC
*VREF
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CLK3
NC
**SA0
**SA1
**SA2
VDD
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
BA0 ~ BA1
Select bank
DQ0 ~ DQ63
Data input/output
CLK0 ~ CLK3
Clock input
CKE0 ~ CKE1 Clock enable input
CS0 ~ CS3
Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM0 ~ 7
DQM
VDD
Power supply (3.3V)
VSS
Ground
*VREF
Power supply for reference
SDA
Serial data I/O
SCL
Serial clock
SA0 ~ 2
Address in EEPROM
*WP
Write protection
DU
Don′t use
NC
No connection
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 0.0 Dec. 2001
M366S2953MTS
PC133/PC100 Unbuffered DIMM
PIN CONFIGURATION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9,CA11
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
VDD/VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
REV. 0.0 Dec. 2001
M366S2953MTS
PC133/PC100 Unbuffered DIMM
FUNCTIONAL BLOCK DIAGRAM
CS1
CS0
DQM0
•
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS3
CS2
DQM2
DQM4
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
•
CS
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
•
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
•
•
U0
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U8
DQM5
U1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U9
DQM6
U2
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U10
•
DQM3
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM7
CS
U3
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0 ~ An, BA0 & 1
SDRAM U0 ~ U15
RAS
SDRAM U0 ~ U15
CAS
SDRAM U0 ~ U15
WE
SDRAM U0 ~ U15
CKE0
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U4
SDRAM U0 ~ U7
VDD
Vss
•
•
CS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U11
DQM CS
DQ0
DQ1
DQ2
U13
DQ3
DQ4
DQ5
DQ6
DQ7
•
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U6
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U7
10KΩ
•
WP
A0
To all SDRAMs
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U14
U15
SDA
A1
A2
SA0 SA1 SA2
SDRAM U8 ~ U15
•
10Ω
CLK0/1/2/3
U0/U1/U2/U3
U4/U5/U6/U7
•
•
•
•
Two 0.1uF Capacitors
per each SDRAM
CS
Serial PD
SCL
47KΩ
CKE1
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
•
VDD
Every DQpin of SDRAM
•
U12
•
DQM CS
DQ0
DQ1
DQ2
U5
DQ3
DQ4
DQ5
DQ6
DQ7
10Ω
DQn
CS
•
•
CS
•
U8/U9/U10/U11
U12/U13/U14/U15
1.5pF
REV. 0.0 Dec. 2001
M366S2953MTS
PC133/PC100 Unbuffered DIMM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
16
W
Short circuit current
IOS
50
mA
Storage temperature
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
VDD, VDDQ
3.0
3.3
3.6
V
Input logic high voltage
VIH
2.0
3.0
VDDQ+0.3
V
1
Input logic low voltage
VIL
-0.3
0
0.8
V
2
Output logic high voltage
VOH
2.4
-
-
V
IOH = -2mA
Output logic low voltage
VOL
-
-
0.4
V
IOL = 2mA
ILI
-10
-
10
uA
3
Supply voltage
Input leakage current
Note
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
CAPACITANCE
Pin
Address (A0 ~ A12, BA0 ~ BA1)
RAS, CAS, WE
Symbol
Min
Max
Unit
CADD
80
100
pF
CIN
80
100
pF
CKE (CKE0 ~ CKE1)
CCKE
50
60
pF
Clock (CLK0 ~ CLK3)
CCLK
40
45
pF
CS (CS0, CS2)
CCS
25
35
pF
DQM (DQM0 ~ DQM7)
CDQM
15
20
pF
DQ (DQ0 ~ DQ63)
COUT
10
15
pF
REV. 0.0 Dec. 2001
M366S2953MTS
PC133/PC100 Unbuffered DIMM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Version
Test Condition
-75
Operating current
(One bank active)
Precharge standby current in power-down mode
Precharge standby current in non power-down
mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
-1H
2000
1840
CKE ≤ VIL(max), tCC = 10ns
95
CKE & CLK ≤ VIL(max), tCC = ∞
80
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
480
Unit
Note
mA
1
-1L
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
160
CKE ≤ VIL(max), tCC = 10ns
160
CKE & CLK ≤ VIL(max), tCC = ∞
130
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
800
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
560
mA
mA
ICC4
IO = 0 mA
Page burst
4banks Activated.
tCCD = 2CLKs
2000
1760
mA
1
Refresh current
ICC5
tRC ≥ tRC(min)
3040
2880
mA
2
Self refresh current
ICC6
CKE ≤ 0.2V
Operating current
(Burst mode)
112
mA
mA
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
REV. 0.0 Dec. 2001
M366S2953MTS
PC133/PC100 Unbuffered DIMM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
870Ω
Output
Z0 = 50Ω
50pF
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
-75
-1H
-1L
Unit
Note
Row active to row active delay
tRRD(min)
15
20
20
ns
1
RAS to CAS delay
tRCD(min)
20
20
20
ns
1
Row precharge time
tRP(min)
20
20
20
ns
1
Row active time
tRAS(min)
45
50
50
ns
1
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to Active delay
100
ns
1
2
CLK
2, 5
tDAL(min)
2 CLK + tRP
-
5
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
ea
4
Number of valid output data
65
us
CAS latency=3
CAS latency=2
70
70
2
-
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
REV. 0.0 Dec. 2001
M366S2953MTS
PC133/PC100 Unbuffered DIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter
-75
Symbol
Min
CLK cycle time
CAS latency=3
tCC
CAS latency=2
CLK to valid
output delay
CAS latency=3
Output data
hold time
CAS latency=3
7.5
-1H
Max
1000
tSAC
CAS latency=2
tOH
CAS latency=2
Min
10
-1L
Max
1000
10
Min
10
Unit
Note
ns
1
ns
1,2
ns
2
Max
1000
12
5.4
6
6
-
6
7
3
3
3
-
3
3
CLK high pulse width
tCH
2.5
3
3
ns
3
CLK low pulse width
tCL
2.5
3
3
ns
3
Input setup time
tSS
1.5
2
2
ns
3
Input hold time
tSH
0.8
1
1
ns
3
CLK to output in Low-Z
tSLZ
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
tSHZ
5.4
6
6
-
6
7
ns
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
REV. 0.0 Dec. 2001
M366S2953MTS
PC133/PC100 Unbuffered DIMM
SIMPLIFIED TRUTH TABLE
Command
Register
Mode register set
Auto refresh
Refresh
Write &
column address
Exit
Auto precharge disable
RAS
CAS
WE
DQM
H
X
L
L
L
L
X
OP code
L
L
L
H
X
X
H
Auto precharge disable
L
H
L
H
H
H
H
X
X
X
X
Entry
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
X
L
H
L
L
L
Column
address
(A0 ~ A9,A11)
X
V
L
Column
address
(A0 ~ A9,A11)
H
H
X
L
H
H
L
X
H
X
L
L
H
L
X
H
L
L
H
Entry
H
L
Precharge power down mode
L
DQM
H
No operation command
H
H
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
X
H
X
X
X
L
H
H
H
3
Row address
H
Exit
Exit
3
3
All banks
Clock suspend or
active power down
1,2
X
H
H
Note
3
Auto precharge enable
Bank selection
A10/AP
L
Auto precharge enable
Burst stop
Precharge
CS
Entry
Self
refresh
Bank active & row addr.
Read &
column address
CKEn
H
BA0,1
A12, A11
A 9 ~ A0
CKEn-1
X
V
L
X
H
4
4,5
4
4,5
6
X
X
X
X
X
X
X
V
X
X
X
7
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Notes : 1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
REV. 0.0 Dec. 2001
M366S2953MTS
PC133/PC100 Unbuffered DIMM
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.250
(133.350)
R 0.079
(R 2.000)
0.350
(8.890)
0.700
(17.780)
0.250
(6.350)
.450
(11.430)
C
0.100 Min
B
A
.118DIA ± 0.004
(3.000DIA ± 0.100)
0.250
(6.350)
1.450
(36.830)
2.150
(54.61)
(2.540 Min)
0.118
0.157 ± 0.004
(4.000 ± 0.100)
(3.000)
1.375
(34.925)
0.089
(2.26)
5.014
(127.350)
0.118
(3.000)
4.550
(115.57)
0.200 Min
(5.08 Min)
0.150 Max
(3.81 Max)
0.100 Min
0.250
(6.350)
0.250
(6.350)
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100)
Detail A
(2.540 Min)
0.050 ± 0.0039
(1.270 ± 0.10)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100)
Detail B
0.008 ± 0.006
(0.200 ± 0.150)
0.050
(1.270)
Detail C
Tolerances : ± .005(.13) unless otherwise specified
The used device is 64Mx8 SDRAM, TSOP
SDRAM Part No. :K4S510832M
REV. 0.0 Dec. 2001
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