Keysight M3102A Pxie digitizers with optional real-time Datasheet

Keysight M3100A
PXIe Digitizers with Optional Real-Time
Sequencing and FPGA Programming
100 MSa/s, 14 Bits, 4/8 Channels
Data Sheet
02 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Improve Your Measurement Fidelity, Signal Integrity
and Measurement Throughput
The M3102A are high-performance, high-bandwidth digitizers with an advanced
data acquisition system (DAQ). Performance meets simplicity thanks to easy-touse programming libraries, real-time sequencing technology (HVI Hard Virtual
Instrumentation), and graphical FPGA programming technology.
Features
100 MSa/s simultaneous sampling, 14 bits, 4/8 channels, 100 MHz BW 1
Advanced data acquisition system (DAQ)
–– Flexible triggering (HW trigger, HVI trigger, SW trigger)
–– Programmable cycles and data bursts to avoid PC saturation
Optional HW programming for high-performance applications
–– Real-time sequencing (HVI technology)
–– FPGA programming
–– Xilinx Kintex-7, 325T or 410T FPGA
Up to 2 GB of onboard RAM (~ 1 Gsamples)
Mechanical/interface
–– 1 slot 3U (PXIe)
–– Up to 1.6 GB/s transfer BW with P2P capabilities (PCIe Gen 2)
–– Independent DMA channels for fast and efficient data transfer
Applications
General purpose digitizer
Hardware-in-the-loop (HIL)/automated test equipment (ATE)
R&D/scientific research equipment
Aerospace & defense (A/D)
1.
100 MHz refer to the Front End bandwidth. This digitizer can operate in 1st and 2nd Nyquist zones
(using undersampling technique), but its real-time BW is limited by Nyquist to some 50 MHz. As an
example for a band-limited signal of 70 MHz with a 10 MHz signal bandwidth the aliased component
will appear between 25 to 35 MHz (30 ± 5 MHz).
03 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Programming Technology and Software Tools
Software programming
–– Easy-to-use native programming libraries for most common languages: C, C++, Visual
Studio, LabVIEW, MATLAB, Python, and more
Hardware programming (optional)
–– Real-time sequencing (Hard Virtual Instrumentation or HVI technology)
–– Graphical flowchart-style M3601A design environment (-HV1 option required on HW)
–– Ultra-fast, fully-parallelized hard real-time execution
–– Ultra-fast, time-deterministic decision-making
–– Off-the-shelf inter-module synchronization & data exchange
–– FPGA programming
–– Graphical M3602A FPGA design environment (-FP1 option required on HW)
–– No FPGA know-how required
–– Include high-level to low-level design elements: off-the-shelf DSP blocks, MATLAB/
Simulink designs, Xilinx CORE Generator IP cores, Xilinx VIVADO/ISE projects, VHDL or
Verilog code
–– Ultra-fast, one-click compiling and on-the-fly programming
No programming
–– Ready-to-use SD1 SPF (software front panels)
PXIe Arbitrary Waveform Generators, Digitizers and Combination Modules
Outputs (AWGs)
Inputs (Digitizers)
Product
Type
Speed
(MSa/s)
Bits
Ch
BW
(MHz)
M3202A
AWG
1000
14
2/4
DC-400
M3201A
AWG
500
16
2/4
DC-200
M3102A
M3100A
M3302A
Combo
500
16
2
M3300A
Combo
500
16
2/4
Speed
(MSa/s)
Bits
Ch
BW
(MHz)
Digitizer
500
Digitizer
100
14
2/4
DC-200
14
4/8
DC-100
DC-200
500
14
2
DC-200
DC-200
100
14
4/8
DC-100
04 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Functional Block Diagram
Channel 1
Channel 1
output
Channel x
Input settings
Full scale, Z,
coupling (as
available)
Channel x
output
Prescaler
÷
Data
acquisition
(DAQx)
Analog
trigger
Channel n
Channel n
output
Figure 1. M3100A input functional block diagram, all channels have identical input structure
Ordering Information 1
Product
Description
M3100A
PXIe digitizer: 100 MSa/s, 14 Bits
Options
Description
M3100A-CH4 / -CH8
Four channels 2 / eight channels
M3100A-CLF
Fixed sampling clock, low jitter 2
M3100A-M01 / -M12 / -M20
Memory 16 MB, 8 MSamples 2 / 128 MB, 60 MSamples / 2 GB, 1 GSamples
HW programming options
Description
M3100A-HVI
Enabled HVI programming, requires an HVI design environment license (M3601A)
M3100A-FP1
Enabled FPGA programming, requires -K32 or -K41 option and an FPGA design environment license (M3602A)
M3100A-K32 / -K41
FPGA, Xilinx 7K325T / 7K410T, required for -FP1 option only (needs memory option -M20)
Related software
Description
M3601A
HVI design environment
M3602A
FPGA design environment
1. All options must be selected at time of purchase and are not upgradable
2. These options represent the standard configuration
05 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Technical Specifications and Characteristics
General characteristics
M3100A-CH4
Parameter
Min
Typ
Max
M3100A-CH8
Min
Typ
Max
Units
Comments
Inputs and outputs
Channels
4
8
Out
Reference clock 1
1
1
Out
Reference clock
2
1
1
In
1, 3
1
1
In/out
Reconfigurable
Triggers/markers 2, 3
8
8
In/out
Reconfigurable
Sampling rate
100
100
MSa/s
Voltage resolution
14
14
Bits
Triggers/markers
Input channels overview
Input frequency
DC
Real-time BW
Time skew
100
DC
50
100
50
<50
MHz
MHz
<50
ps
Between channels
Built-in functionalities
Input conditioning blocks
4
8
1 per channel
Analog trigger processors
4
8
1 per channel
Data acquisition blocks
4
8
1 per channel
Onboard memory
RAM memory
16
2048
1. At front panel
2. At backplane
3. Markers available from firmware version v3.0 or later
16
2048
MBytes
06 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
I/O specifications
Analog input characteristics
Number of channels
CH4 or CH8
Sampling rate
100 MSa/s option CLF
Configurable inputs: impedance
50Ω or 1 MΩ (HiZ)
Configurable inputs: Coupling
AC or DC
Input voltage range (50Ω)
400 mVpp to 6Vpp (continue: variable attenuator at input)
Input voltage range (HiZ)
200 mVpp to 20Vpp (continue: variable attenuator at input)
Bandwidth limit filters
100 MHz
Effective number of bits (ENOB)1
10.8 bits @30MHz (typical)
Noise floor
−142 dBm/Hz @30 MHz (typical)
SINAD
67 dB @30 MHz (typical)
Spurious free dynamic range (SFDR) + Total Harmonic Distorsion
79 dBc (typical)
1.
measured at -1 DBFS input signal with 1.5 Vpp 50Ω
M3100A
Parameter
Min
Typ
Max
Units
Comments
Reference clock output
Frequency
10 or 100
MHz
Generated from the internal clock. User selectable
Voltage
800
mVpp
On a 50 Ω load
Power
2
dBm
On a 50 Ω load
Source impedance
50
Ω
AC coupled
External I/O trigger/marker
VIH
2
5
V
VIL
0
0.8
V
VOH
2.4
3.3
V
On a high Z load
VOL
0
0.5
V
On a high Z load
Input impedance
10
KΩ
Source impedance
TTL
–
Speed
500
Mbps
07 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Data acquisition blocks (DAQs) specifications
M3100A-CH4
Parameter
Min
Typ
M3100A-CH8
Max
Min
Typ
Max
Units
Comments
General specifications
DAQs
4
Aggregated speed
8
400
Acquisition burst multiple
800
5
Acquisition RAM capacity
15
Acquisition RAM capacity effic.
Trigger
1 per channel
5
957M
15
957M
93.5
93.5
Selec.
Selec.
MSa/s
For all onboard DAQs combined
Samples
Burst length must be a multiple of this value
Samples
Maximum depends on onboard RAM
%
Effic. = waveform size / waveform size in RAM
Hardware trigger (analog channels, input
trigger, backplane triggers), software trigger
DAQ specifications
Speed
100
Resolution
100
14
14
MSa/s
Bits
Clock system specifications
M3100A-CH4
Parameter
Min
Typ
Max
M3100A-CH8
Min
Typ
Max
Units
General specifications
Clock frequency
100
100
MHz
Comments
Per DAQ
08 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
System Specifications
Environmental specifications (PXI Express)
M3100A-CH4
Parameter
Min
Typ
M3100A-CH8
Max
Min
Typ
Max
Units
Comments
Slot
PXI Express (CompactPCI Express compatible)
–
Automatic gen negotiation, chassis dependent
System bus
Slots
PCI Express type
1
Gen 1
PCI Express link
1
Gen 2
Gen 1
Gen 2
1
4
1
4
Lanes
Automatic lane negotiation, chassis dependent
PCI Express speed
400
1600
400
1600
MBytes/s
Depends on # of lanes, chassis, congestion, and more
Sustainable throughput
200
800
200
800
MPoints/s
Depends on # of lanes, chassis, congestion, and more
Power dissipation
3.3V PXIe power supply
1.5
1.5
A
~5W
12V PXIe power supply
2
2
A
~ 24 W
Environmental 1
Temperature range
Operating
Non-operating
0 to +55°C (10,000 feet)
-40 to +70 °C (up to 15,000 feet)
Max operative altitude
2000 m (10,000 feet)
Operating Humidity range (%RH)
10 to 95% at 40 °C
Non-operating Humidity range (%RH): 5 to 95
5 to 95%
Calibration interval
1 year
EMC
Complies with European EMC Directive
– IEC/EN 61326-1
– CISPR Pub 11 Group 1, class A
This ISM device is in compliance with Canadian ICES-001
Cet appareil ISM est conforme à la norme NMB-001 du Canada.
This ISM device is in compliance with Australian and New Zealand RCM
This ISM device is in compliance with South Korea EMC KCC
1.
Samples of this product have been type tested in accordance with the Keysight Environmental Test Manual and verified to be robust against the environmental stresses of Storage, Transportation and End-use; those stresses include but are not limited to temperature, humidity, shock, vibration, altitude and
power line conditions. Test Methods are aligned with IEC 60068-2 and levels are similar to MIL-PRF-28800F Class 3.
09 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
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Published in USA, February 20, 2018
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