IDT IDT7200LA40J Cmos asynchronous fifo 256 x 9, 512 x 9, 1,024 x 9 Datasheet

IDT7200L
IDT7201LA
IDT7202LA
CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9, 1,024 x 9
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
•
The IDT7200/7201/7202 are dual-port memories that load
and empty data on a first-in/first-out basis. The devices use
Full and Empty flags to prevent data overflow and underflow
and expansion logic to allow for unlimited expansion capability
in both word size and depth.
The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write (W) and Read (R) pins.
The devices utilize a 9-bit wide data array to allow for
control and parity bits at the user’s option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability
that allows for reset of the read pointer to its initial position
when RT is pulsed low to allow for retransmission from the
beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.
These FIFOs are fabricated using IDT’s high-speed CMOS
technology. They are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Military grade product is
manufactured in compliance with the latest revision of MILSTD-883, Class B.
•
•
•
•
•
•
•
•
•
•
First-In/First-Out dual-port memory
256 x 9 organization (IDT7200)
512 x 9 organization (IDT7201)
1,024 x 9 organization (IDT7202)
Low power consumption
— Active: 770mW (max.)
—Power-down: 2.75mW (max.)
Ultra high speed—12ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
Pin and functionally compatible with 720X family
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CEMOS technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962-87531, 5962-89666,
5962-89863 and 5962-89536 are listed on this function
Industrial temperature range (–40°C to +85°C) is
available (plastic packages only)
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D 0 –D 8)
W
WRITE
CONTROL
WRITE
POINTER
R
READ
CONTROL
THREESTATE
BUFFERS
DATA OUTPUTS
(Q 0 –Q 8 )
FLAG
LOGIC
EXPANSION
LOGIC
XI
RAM
ARRAY
256 x 9
512 x 9
1,024 x 9
EF
FF
READ
POINTER
RS
RESET
LOGIC
FL/RT
XO/HF
2679 drw 01
The IDT logo is a trademark of Integrated Device Technology, Inc.
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
1997 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
SEPTEMBER 1997
DSC-2679/7
1
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
W
1
28
VCC
D8
2
27
D4
4 3 2 1 32 31 30
D3
3
26
D5
D2
D1
4
5
25
24
D6
D7
D0
6
23
XI
FF
7
22
Q0
8
9
21
20
FL/RT
RS
EF
XO/HF
Q1
10
19
Q7
Q2
11
18
Q6
Q3
12
17
Q5
Q8
GND
13
14
16
15
Q4
D2
5
29
D6
D1
D0
XI
FF
6
7
8
9
28
27
26
25
D7
NC
FL/RT
Q0
Q1
NC
Q2
10
11
12
13
24
23
22
21
RS
EF
XO/HF
Q7
Q6
Reference
Identifier
P28-1
P28-2
D28-1
D28-3
SO28-3
E28-2
Order
Code
P
TP
D
TD
SO
XE
LCC(1)
PLCC
R
Q4
Q5
R
GND
NC
Q3
Q8
14 15 16 17 18 19 20
2679 drw 02a
PLASTIC DIP(1)
PLASTIC THIN DIP
CERDIP(1)
THIN CERDIP
SOIC
CERPAK(1)
D5
D3
D8
INDEX
NC
VCC
D4
PIN CONFIGURATIONS
W
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
Reference
Identifier
L32- 1
J32-1
2679 drw 02b
Order
Code
L
J
TOP VIEW
TOP VIEW
NOTE:
1. The 600-mil-wide DIP (P28-1 and D28-1), CERPACK and LCC are not available for the 7200.
RECOMMENDED OPERATING
CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
VTERM Terminal Voltage
with Respect
to GND
TSTG
Storage
Temperature
IOUT
DC Output
Current
Com’l & Ind'l
–0.5 to +7.0
Mil.
Unit
–0.5 to +7.0 V
–55 to +125
–65 to +155
°C
–50 to +50
–50 to +50
mA
NOTE:
2679 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
Symbol
CIN
COUT
Parameter(1)
Input Capacitance
Output Capacitance
Condition
VIN = 0V
VOUT = 0V
NOTE:
1. This parameter is sampled and not 100% tested.
Max.
8
8
Unit
pF
pF
2679 tbl 02
Symbol
Min.
Typ.
VCCM
Military Supply
Voltage
Parameter
4.5
5.0
Max. Unit
5.5
V
VCCC
Commercial Supply
Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
(1)
VIH
Input High Voltage
Commercial
2.0
—
—
V
VIH(1)
Input High Voltage
Military
2.2
—
—
V
VIL(2)
Input Low Voltage
Commercial and
Military
—
—
0.8
V
TA
Operating Temperature
Commercial
0
—
70
°C
TA
Operating Temperature
Industrial
–40
—
85
°C
TA
Operating Temperature
Military
–55
—
125
°C
NOTES:
1. VIH = 2.6V for XI input (commercial).
VIH = 2.8V for XI input (military).
2. 1.5V undershoots are allowed for 10ns once per cycle.
2679 tbl 03
2
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
IDT7200L
IDT7201LA
IDT7202LA
Com'l & Ind'l(1)
tA = 12, 15, 20, 25, 35 ns
Symbol
Parameter
Min.
Typ.
IDT7200L
IDT7201LA
IDT7202LA
Military
tA = 20, 30, 40 ns
Max.
Min.
Typ.
Max.
Unit
Input Leakage Current (Any Input)
–1
—
1
–10
—
10
µA
ILO(3)
Output Leakage Current
–10
—
10
–10
—
10
µA
VOH
Output Logic “1” Voltage IOH = –2mA
2.4
—
—
2.4
—
—
V
VOL
Output Logic “0” Voltage IOL = 8mA
—
—
0.4
—
—
0.4
V
ICC1(4,5,6)
Active Power Supply Current
—
—
125
—
—
140
mA
ICC2(4,6,7)
Standby Current (R=W=RS=FL/RT=VIH)
—
—
15
—
—
20
mA
Power Down Current
—
—
0.5
—
—
0.9
ILI
(2)
ICC3(L)
(4,6,7)
mA
2679 tbl 04
IDT7200L
IDT7201LA
IDT7202LA
Commercial
tA = 50 ns
Symbol
Parameter
IDT7200L
IDT7201LA
IDT7202LA
Military
tA = 50, 65, 80, 120 ns
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
ILI(2)
Input Leakage Current (Any Input)
–1
—
1
–10
—
10
µA
ILO(3)
Output Leakage Current
–10
—
10
–10
—
10
µA
VOH
Output Logic “1” Voltage IOH = –2mA
2.4
—
—
2.4
—
—
V
VOL
Output Logic “0” Voltage IOL = 8mA
—
—
0.4
—
—
0.4
V
ICC1(4,5,6)
Active Power Supply Current
—
50
80
—
70
100
mA
ICC2(4,6,7)
Standby Current (R=W=RS=FL/RT=VIH)
—
5
8
—
8
15
mA
ICC3(L)(4,6,7)
Power Down Current
—
—
0.5
—
—
0.9
mA
NOTES:
2679 tbl 05
1. Industrial temperature range product for the 25 ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. ICC measurements are made with outputs open.
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
2679 tbl 08
3
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Com'l & Mil. Com'l & Ind'l(2)
Commercial
7200L12 7200L15
7201LA12 7201LA15
7202LA12 7202LA15
Symbol
Parameter
7200L20
7201LA20
7202LA20
Min. Max. Min. Max. Min. Max.
7200L25
7201LA25
7202LA25
Military
Com'l
7200L30 7200L35
7201LA30 7201LA35
7202LA30 7202LA35
Min.
Max. Min. Max. Min. Max. Unit
tS
Shift Frequency
—
50
—
40
—
33.3
—
28.5
—
25
—
tRC
Read Cycle Time
20
—
25
—
30
—
35
—
40
—
45
—
ns
tA
Access Time
—
12
—
15
—
20
—
25
—
30
—
35
ns
tRR
Read Recovery Time
8
—
10
—
10
—
10
—
10
—
10
—
ns
tRPW
Read Pulse Width(3)
12
—
15
—
20
—
25
—
30
—
35
—
ns
tRLZ
Read Pulse Low to Data Bus at Low Z(4)
3
—
5
—
5
—
5
—
5
—
5
—
ns
tWLZ
Write Pulse High to Data Bus at Low Z(4,5)
3
—
5
—
5
—
5
—
5
—
10
—
ns
tDV
Data Valid from Read Pulse High
5
—
5
—
5
—
5
—
5
—
5
—
ns
(4)
22.2 MHz
tRHZ
Read Pulse High to Data Bus at High Z
—
12
—
15
—
15
—
18
—
20
—
20
ns
tWC
Write Cycle Time
20
—
25
—
30
—
35
—
40
—
45
—
ns
12
—
15
—
20
—
25
—
30
—
35
—
ns
(3)
tWPW
Write Pulse Width
tWR
Write Recovery Time
8
—
10
—
10
—
10
—
10
—
10
—
ns
tDS
Data Set-up Time
9
—
11
—
12
—
15
—
18
—
18
—
ns
tDH
Data Hold Time
0
—
0
—
0
—
0
—
0
—
0
—
ns
tRSC
Reset Cycle Time
20
—
25
—
30
—
35
—
40
—
45
—
ns
tRS
Reset Pulse Width(3)
12
—
15
—
20
—
25
—
30
—
35
—
ns
tRSS
Reset Set-up Time(4)
12
—
15
—
20
—
25
—
30
—
35
—
ns
tRSR
Reset Recovery Time
8
—
10
—
10
—
10
—
10
—
10
—
ns
tRTC
Retransmit Cycle Time
20
—
25
—
30
—
35
—
40
—
45
—
ns
tRT
(3)
Retransmit Pulse Width
12
—
15
—
20
—
25
—
30
—
35
—
ns
tRTS
Retransmit Set-up Time(4)
12
—
15
—
20
—
25
—
30
—
35
—
ns
tRTR
Retransmit Recovery Time
8
—
10
—
10
—
10
—
10
—
10
—
ns
tEFL
Reset to Empty Flag Low
—
12
—
25
—
30
—
35
—
40
—
45
ns
tHFH,FFH Reset to Half-Full and Full Flag High
—
17
—
25
—
30
—
35
—
40
—
45
ns
tRTF
Retransmit Low to Flags Valid
—
20
—
25
—
30
—
35
—
40
—
45
ns
tREF
Read Low to Empty Flag Low
—
12
—
15
—
20
—
25
—
30
—
30
ns
tRFF
Read High to Full Flag High
—
14
—
15
—
20
—
25
—
30
—
30
ns
tRPE
Read Pulse Width after EF High
12
—
15
—
20
—
25
—
30
—
35
—
ns
tWEF
Write High to Empty Flag High
—
12
—
15
—
20
—
25
—
30
—
30
ns
tWFF
Write Low to Full Flag Low
—
14
—
15
—
20
—
25
—
30
—
30
ns
tWHF
Write Low to Half-Full Flag Low
—
17
—
25
—
30
—
35
—
40
—
45
ns
tRHF
Read High to Half-Full Flag High
—
17
—
25
—
30
—
35
—
40
—
45
ns
tWPF
Write Pulse Width after FF High
12
—
15
—
20
—
25
—
30
—
35
—
ns
tXOL
Read/Write to XO Low
—
12
—
15
—
20
—
25
—
30
—
35
ns
tXOH
Read/Write to XO High
—
12
—
15
—
20
—
25
—
30
—
35
ns
tXI
XI Pulse Width
XI Recovery Time
XI Set-up Time
12
—
15
—
20
—
25
—
30
—
35
—
ns
8
—
10
—
10
—
10
—
10
—
10
—
ns
8
—
10
—
10
—
10
—
10
—
10
—
tXIR
tXIS
(3)
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Industrial temperature range is available by special order for
speed grades faster than 25ns.
ns
2679 tbl 06
3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
4
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1) (Continued)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Symbol
Com'l & Mil.
7200 L40
7201LA40
7202LA40
7200L50
7201LA50
7202LA50
Min.
7200L65
7201LA65
7202LA65
7200L80
7201LA80
7202LA80
7200L120
7201LA120
7202LA120
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Shift Frequency
—
20
—
15
—
12.5
—
10
—
7
MHz
tRC
Read Cycle Time
50
—
65
—
80
—
100
—
140
—
ns
tA
Access Time
—
40
—
50
—
65
—
80
—
120
ns
tRR
Read Recovery Time
10
—
15
—
15
—
20
—
20
—
ns
40
—
50
—
65
—
80
—
120
—
ns
(3)
Read Pulse Width
(4)
Max. Min.
Military(2)
tS
tRPW
Parameter
Military
tRLZ
Read Pulse Low to Data Bus at Low Z
5
—
10
—
10
—
10
—
10
—
ns
tWLZ
Write Pulse High to Data Bus at Low Z(4, 5)
10
—
15
—
15
—
20
—
20
—
ns
tDV
Data Valid from Read Pulse High
5
—
5
—
5
—
5
—
5
—
ns
(4)
tRHZ
Read Pulse High to Data Bus at High Z
—
25
—
30
—
30
—
30
—
35
ns
tWC
Write Cycle Time
50
—
65
—
80
—
100
—
140
—
ns
(3)
tWPW
Write Pulse Width
40
—
50
—
65
—
80
—
120
—
ns
tWR
Write Recovery Time
10
—
15
—
15
—
20
—
20
—
ns
tDS
Data Set-up Time
20
—
30
—
30
—
40
—
40
—
ns
tDH
Data Hold Time
0
—
5
—
10
—
10
—
10
—
ns
tRSC
Reset Cycle Time
50
—
65
—
80
—
100
—
140
—
ns
tRS
Reset Pulse Width(3)
40
—
50
—
65
—
80
—
120
—
ns
(4)
tRSS
Reset Set-up Time
40
—
50
—
65
—
80
—
120
—
ns
tRSR
Reset Recovery Time
10
—
15
—
15
—
20
—
20
—
ns
tRTC
Retransmit Cycle Time
50
—
65
—
80
—
100
—
140
—
ns
tRT
(3)
Retransmit Pulse Width
40
—
50
—
65
—
80
—
120
—
ns
tRTS
Retransmit Set-up Time(4)
40
—
50
—
65
—
80
—
120
—
ns
tRTR
Retransmit Recovery Time
10
—
15
—
15
—
20
—
20
—
ns
tEFL
Reset to Empty Flag Low
—
50
—
65
—
80
—
100
—
140
ns
tHFH,FFH Reset to Half-Full and Full Flag High
—
50
—
65
—
80
—
100
—
140
ns
tRTF
Retransmit Low to Flags Valid
—
50
—
65
—
80
—
100
—
140
ns
tREF
Read Low to Empty Flag Low
—
30
—
45
—
60
—
60
—
60
ns
tRFF
Read High to Full Flag High
—
35
—
45
—
60
—
60
—
60
ns
tRPE
Read Pulse Width after EF High
40
—
50
—
65
—
80
—
120
—
ns
tWEF
Write High to Empty Flag High
—
35
—
45
—
60
—
60
—
60
ns
tWFF
Write Low to Full Flag Low
—
35
—
45
—
60
—
60
—
60
ns
tWHF
Write Low to Half-Full Flag Low
—
50
—
65
—
80
—
100
—
140
ns
tRHF
Read High to Half-Full Flag High
—
50
—
65
—
80
—
100
—
140
ns
tWPF
Write Pulse Width after FF High
40
—
50
—
65
—
80
—
120
—
ns
tXOL
Read/Write to XO Low
—
40
—
50
—
65
—
80
—
120
ns
tXOH
Read/Write to XO High
—
40
—
50
—
65
—
80
—
120
ns
tXI
XI Pulse Width
XI Recovery Time
XI Set-up Time
40
—
50
—
65
—
80
—
120
—
ns
tXIR
tXIS
(3)
10
—
10
—
10
—
10
—
10
—
ns
10
—
15
—
15
—
15
—
15
—
ns
NOTES:
1. Timings referenced as in AC Test Conditions
2. Speed grades 65, 80 and 120 not available in the CERPACK
3. Pulse widths less than minimum value are not allowed.
2679 tbl 07
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
5
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
5V
1.1K
TO
OUTPUT
PIN
680Ω
30pF*
2679 drw 03
or equivalent circuit
Figure 1. Output Load
* Includes scope and jig capacitances.
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 – D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is
taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after
power up before a write operation can take place. Both the
Read Enable (R) and Write Enable (W) inputs must be in
the high state during the window shown in Figure 2, (i.e.,
tRSS before the rising edge of RS) and should not change
until tRSR after the rising edge of RS. Half-Full Flag (HF)
will be reset to high after Reset (RS).
WRITE ENABLE (W)
A write cycle is initiated on the falling edge of this input if the
Full Flag (FF) is not set. Data set-up and hold times must be
adhered to with respect to the rising edge of the Write Enable
(W). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
After half of the memory is filled and at the falling edge of
the next write operation, the Half-Full Flag (HF) will be set to
low and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then
reset by the rising edge of the read operation.
To prevent data overflow, the Full Flag (FF) will go low,
inhibiting further write operations. Upon the completion of a
valid read operation, the Full Flag (FF) will go high after tRFF,
allowing a valid write to begin. When the FIFO is full, the
internal write pointer is blocked from W, so external changes
in W will not affect the FIFO when it is full.
READ ENABLE (R)
A read cycle is initiated on the falling edge of the Read
Enable (R) provided the Empty Flag (EF) is not set. The data
is accessed on a First-In/First-Out basis, independent of any
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
ongoing write operations. After Read Enable (R) goes high,
the Data Outputs (Q0 – Q8) will return to a high impedance
condition until the next Read operation. When all data has
been read from the FIFO, the Empty Flag (EF) will go low,
allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go high after tWEF and a valid
Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from R so external changes in R will not
affect the FIFO when it is empty.
FIRST LOAD/RETRANSMIT (FL/RT)
This is a dual-purpose input. In the Depth Expansion Mode,
this pin is grounded to indicate that it is the first loaded (see
Operating Modes). In the Single Device Mode, this pin acts as
the restransmit input. The Single Device Mode is initiated by
grounding the Expansion In (XI).
The IDT7200/7201A/7202A can be made to retransmit
data when the Retransmit Enable control (RT) input is pulsed
low. A retransmit operation will set the internal read pointer to
the first location and will not affect the write pointer. Read
Enable (R) and Write Enable (W) must be in the high state
during retransmit. This feature is useful when less than 256/
512/1,024 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode
and will affect the Half-Full Flag (HF), depending on the
relative locations of the read and write pointers.
EXPANSION IN (XI)
This input is a dual-purpose pin. Expansion In (XI) is
grounded to indicate an operation in the single device mode.
Expansion In (XI) is connected to Expansion Out (XO) of the
previous device in the Depth Expansion or Daisy Chain Mode.
OUTPUTS:
FULL FLAG (FF)
The Full Flag (FF) will go low, inhibiting further write
operation, when the write pointer is one location less than the
read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (RS), the Full-Flag (FF) will go
low after 256 writes for IDT7200, 512 writes for the IDT7201A
and 1,024 writes for the IDT7202A.
EMPTY FLAG (EF)
The Empty Flag (EF) will go low, inhibiting further read
operations, when the read pointer is equal to the write pointer,
indicating that the device is empty.
EXPANSION OUT/HALF-FULL FLAG (XO/HF)
This is a dual-purpose output. In the single device mode,
when Expansion In (XI) is grounded, this output acts as an
indication of a half-full memory.
After half of the memory is filled and at the falling edge of
the next write operation, the Half-Full Flag (HF) will be set low
and will remain set until the difference between the write
6
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then
reset by using rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This
output acts as a signal to the next device in the Daisy Chain
by providing a pulse to the next device when the previous
device reaches the last location of memory.
DATA OUTPUTS (Q0 – Q8)
Data outputs for 9-bit wide data. This data is in a high
impedance condition whenever Read (R) is in a high state.
t RSC
t RS
RS
t RSS
t RSR
W
t RSS
R
t EFL
EF
t HFH , t FFH
HF, FF
2679 drw 04
NOTES:
1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.
2. W and R = VIH around the rising edge of RS.
Figure 2. Reset
t
t RPW
RC
t RR
tA
tA
R
t RLZ
t DV
Q0 – Q8
t RHZ
DATA OUT VALID
t WPW
t WC
DATA OUT VALID
t WR
W
t DS
D0 – D8
t DH
DATA IN VALID
DATA IN VALID
2679 drw 05
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
IGNORED
WRITE
FIRST READ
ADDITIONAL
READS
FIRST
WRITE
R
W
t WFF
t RFF
FF
2679 drw 06
Figure 4. Full Flag From Last Write to First Read
7
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
LAST READ
IGNORED
READ
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
FIRST WRITE
ADDITIONAL
WRITES
FIRST
READ
W
R
t WEF
t REF
EF
tA
DATA OUT
VALID
VALID
2679 drw 07
Figure 5. Empty Flag From Last Read to First Write
t
RTC
t RT
RT
t RTR
t RTS
W,R
t RTF
HF, EF, FF
FLAG VALID
2679 drw 08
Figure 6. Retransmit
W
t WEF
EF
t RPE
R
2679 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse
R
t RFF
FF
t WPF
W
2679 drw 10
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse
8
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
W
t RHF
R
t WHF
HF
HALF-FULL OR LESS
HALF-FULL OR LESS
MORE THAN HALF-FULL
2679 drw 11
Figure 9. Half-Full Flag Timing
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
W
R
t XOL
t XOH
t XOL
t XOH
2679 drw 12
XO
Figure 10. Expansion Out
t XI
t XIR
XI
W
t XIS WRITE TO
FIRST PHYSICAL
LOCATION
t XIS
READ FROM
FIRST PHYSICAL
LOCATION
R
2679 drw 13
Figure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is
monitored by each system (i.e. FF is monitored on the device
where W is used; EF is monitored on the device where R is
used). For additional information, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and
Tech Note 6: Designing with FIFOs.
Single Device Mode
A single IDT7200/7201A/7202A may be used when the
application requirements are for 256/512/1,024 words or less.
These devices are in a Single Device Configuration when the
Expansion In (XI) control input is grounded (see Figure 12).
Depth Expansion
The IDT7200/7201A/7202A can easily be adapted to applications when the requirements are for greater than 256/512/
1,024 words. Figure 14 demonstrates Depth Expansion using
three IDT7200/7201A/7202As. Any depth can be attained by
adding additional IDT7200/7201A/7202As. These FIFOs
operate in the Depth Expansion mode when the following
conditions are met:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be tied
to the Expansion In (XI) pin of the next device. See Figure
14.
4. External logic is needed to generate a composite Full Flag
(FF) and Empty Flag (EF). This requires the ORing of all
EFs and ORing of all FFs (i.e. all must be set to generate
the correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are
not available in the Depth Expansion Mode.
For additional information, refer to Tech Note 9: Cascading FIFOs or FIFO Modules.
9
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
USAGE MODES:
Width Expansion
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Status flags (EF, FF and HF) can be detected from any one
device. Figure 13 demonstrates an 18-bit word width by using
two IDT7200/7201A/7202As. Any word width can be attained
by adding additional IDT7200/7201A/7202As (Figure 13).
Bidirectional Operation
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT7200/7201A/7202As as shown
in Figure 16. Both Depth Expansion and Width Expansion
may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the
bus until the R line is raised from low-to-high, after which the
bus would go into a three-state mode after tRHZ ns. The EF line
would have a pulse showing temporary deassertion and then
would be asserted.
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The R line causes
the FF to be deasserted but the W line being low causes it to
be asserted again in anticipation of a new data word. On the
rising edge of W, the new word is loaded in the FIFO. The W
line must be toggled when FF is not asserted to write new data
in the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
(HF)
(HALF–FULL FLAG)
WRITE (W)
READ (R)
9
9
IDT
7200/
7201A/
7202A
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
EXPANSION IN (XI)
2679 drw 14
Figure 12. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9 FIFO
HF
18
HF
9
9
DATA IN (D)
WRITE (W)
FULL FLAG (FF)
RESET (RS)
IDT
7200/
7201A/
7202A
9
XI
READ (R)
IDT
7200/
7201A/
7202A
EMPTY FLAG (EF)
RETRANSMIT (RT)
9
XI
18
DATA OUT (Q)
2679 drw 15
Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18 FIFO Memory Used in Width Expansion Mode
10
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TABLE I—RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Inputs
Mode
Reset
Retransmit
Read/Write
RS
RT
XI
0
1
X
0
0
0
Internal Status
Read Pointer
Write Pointer
Location Zero
Location Zero
Location Zero
Unchanged
1
1
0
Increment(1)
Increment(1)
Outputs
EF
FF
HF
0
X
1
X
1
X
X
X
X
NOTE:
1. Pointer will increment if flag is High.
2679 tbl 09
TABLE II—RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs
Mode
Reset First Device
Reset All Other Devices
Read/Write
RS
FL
XI
0
0
0
1
(1)
(1)
1
X
(1)
NOTE:
1. XI is connected to XO of previous device. See Figure 14.
XI = Expansion Input, HF = Half-Full Flag Output
Internal Status
Read Pointer
Write Pointer
Location Zero
Location Zero
Location Zero
Location Zero
X
X
Outputs
EF
FF
0
0
1
1
X
X
2679 tbl 10
RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Flag Full Output,
XO
W
D
FF
9
9
IDT
7200/
7201A/
7202A
R
EF
9
FL
XI
Q
VCC
XO
FF
FULL
9
IDT
7200/
7201A/
7202A
EF
EMPTY
FL
XI
XO
FF
9
RS
IDT
7200/
7201A/
7202A
XI
EF
FL
2679 drw 16
Figure 14. Block Diagram of 768 x 9, 1,536 x 9, 3,072 x 9 FIFO Memory (Depth Expansion)
11
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
Q 0 –Q 8
Q 9 –Q 17
Q (N-8) -Q N
•••
Q 0 –Q 8
R, W, RS
Q 9 –Q 17
IDT7200/
IDT7201A/
IDT7202A
DEPTH
EXPANSION
BLOCK
Q (N-8) -Q N
IDT7200/
IDT7201A/
IDT7202A
DEPTH
EXPANSION
BLOCK
D 0 -D 8
IDT7200/
IDT7201A/
IDT7202A
DEPTH
EXPANSION
BLOCK
•••
D 9 -D 17
D (N-8) -D N
D 0 –D N
•••
D 9 -D N
D 18 -D N
D (N-8) -D N
2679 drw 17
NOTES:
1. For depth expsansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO Expansion
WA
FFA
RB
EF B
HF B
IDT
7200/
IDT
7201A/
7201A
7202A
DA 0-8
Q B 0-8
SYSTEM A
SYSTEM B
Q A 0-8
RA
HF A
EF A
D B 0-8
IDT
7200/
7201A/
7202A
WB
FFB
2679 drw 18
Figure 16. Bidirectional FIFO Mode
DATA IN
W
t RPE
R
EF
t WLZ
t WEF
tA
t REF
DATA OUT
DATA
OUT
VALID
2679 drw 19
Figure 17. Read Data Flow-Through Mode
12
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
R
t
W
WPF
t RFF
FF
t DH
t WFF
DATA
DATA IN
t
IN
VALID
t DS
A
DATA OUT
DATA
OUT
VALID
2679 drw 20
Figure 18. Write Data Flow-Through Mode
ORDERING INFORMATION
IDT
XXXX
X
XXX
X
X
Device Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I (1)
B
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
P
TP
D
TD
J
SO
L
XE
Plastic DIP
Plastic Thin DIP
CERDIP
Thin CERDIP
Plastic Leaded Chip Carrier PLCC
SOIC
LCC
Leadless Chip Carrier
CERPACK
12
15
20
25
30
35
40
50
65
80
120
Commercial Only
Commercial Only
(2)
Commercial and Industrial
Military Only
Commercial Only
Military Only
P28-1
P28-2
D28-1
D28-3
J32-1
SO28-3
L32-1
E28-2
(7201 & 7202 Only)
(7201 & 7202 Only)
(7201 & 7202 Only)
(7201 & 7202 Only)
Access Time (t A)
Speed in Nanoseconds
Military only-except XE
package
LA
Low Power
7200
7201
7202
256 x 9-Bit FIFO
512 x 9-Bit FIFO
1,024 x 9-Bit FIFO
2679 drw 21
NOTES:
1. Industrial temperature range is available for plastic packages by special order for speed grades faster than 25 ns.
2. "A" to be included for 7201 and 7202 ordering part number.
13
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