FAIRCHILD 74LCXP16245MEA

Revised June 2005
74LCXP16245
Low Voltage 16-Bit Bidirectional Transceiver with
5V Tolerant Inputs/Outputs and Pull-Down Resistors
General Description
Features
The LCXP16245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus
oriented applications. The device is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The device is byte
controlled. Each byte has separate control inputs which
could be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
In addition, A and B port datapath pins have built-in resistors to GND allowing the pins to float without any increase
in ICC current. This feature is intended to address modular
and space constrained applications where additional space
consumed by external resistors is not available.
■ 5V tolerant inputs and outputs
The LCXP16245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining CMOS low power dissipation.
Machine model ! 200V
■ 2.3V–3.6V VCC specifications provided
■ I/O pull-down resistors terminate inactive busses ensuring a stable bus state
■ 5.5 ns tPD max (VCC
3.3V), 20 PA ICC max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ r24 mA output drive (VCC
3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Pinout compatible with 74 series 16245
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human body model ! 2000V
Note 1: To ensure the high-impedance state during power up or down OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
Package Number
74LCXP16245MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Description
74LCXP16245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
© 2005 Fairchild Semiconductor Corporation
DS500053
Description
Output Enable Input
T/Rn
Transmit/Receive Input
A0–A15
Side A Inputs or 3-STATE Outputs
B0–B15
Side B Inputs or 3-STATE Outputs
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74LCXP16245 Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs/Outputs and Pull-Down
Resistors
August 1998
74LCXP16245
Connection Diagram
Truth Tables
Inputs
Outputs
OE1
T/R1
L
L
Bus B0–B7 Data to Bus A0–A7
L
H
Bus A0–A7 Data to Bus B0–B7
H
X
HIGH Z State on A0–A7, B0–B7 (Note 2)
Inputs
Outputs
OE2
T/R2
L
L
Bus B8–B15 Data to Bus A8–A15
L
H
Bus A8–A15 Data to Bus B8–B15
H
X
HIGH Z State on A8–A15, B8–B15 (Note 2)
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Note 2: A and B port inputs are still active.
Functional Descriptions
The OE inputs disable both the A and B ports by placing
them in a high impedance state. The pulldown resistor
(30K: normal) to GND is active only when the outputs are
3-STATED (OE HIGH). When the outputs become active
(OE LOW) the resistor is removed from the circuit.
The LCXP16245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs. the device is byte controlled. Each byte has separate control inputs which can be
shorted together for full 16-bit operation. The T/R inputs
determine the direction of data flow through the device.
Logic Diagram
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Symbol
Parameter
VCC
Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
DC Input Diode Current
IOK
DC Output Diode Current
Value
IO
DC Output Source/Sink Current
ICC
DC Supply Current per Supply Pin
IGND
DC Ground Current per Ground Pin
TSTG
Storage Temperature
Conditions
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
0.5 to VCC 0.5
50
50
50
r50
r100
r100
65 to 150
Units
V
V
Output in 3-STATE
V
Output in HIGH or LOW State (Note 4)
VI GND
mA
VO GND
mA
VO ! VCC
mA
mA
mA
qC
Recommended Operating Conditions
Symbol
VCC
Parameter
VI
Input Voltage
VO
Output Voltage
IOH/IOL
Min
Max
Operating
2.0
3.6
Data Retention
1.5
3.6
Supply Voltage
Output Current
TA
Free-Air Operating Temperature
't/'V
Input Edge Rate, VIN
0.8V–2.0V, VCC
V
0
5.5
HIGH or LOW State
0
VCC
3-STATE
0
5.5
VCC
3.0V 3.6V
VCC
2.7V 3.0V
VCC
2.3V 2.7V
Units
V
V
r24
r12
r8
3.0V
mA
40
85
qC
0
10
ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
Parameter
Conditions
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
VCC
TA
40qC to 85qC
(V)
Min
2.3 2.7
1.7
2.7 3.6
2.0
Max
V
2.3 2.7
0.7
2.7 3.6
0.8
IOH
100 PA
2.3 3.6
VCC 0.2
IOH
8 mA
2.3
1.8
IOH
12 mA
2.7
2.2
IOH
18 mA
3.0
2.4
2.2
Units
V
V
IOH
24 mA
3.0
IOL
100 PA
2.3 3.6
IOL
8 mA
2.3
0.6
IOL
12 mA
2.7
0.4
IOL
16 mA
3.0
0.4
IOL
24 mA
0.2
V
3.0
0.55
II
Input Leakage Current
0 d VI d 5.5V
2.3 3.6
r5.0
PA
IOZ(L)
3-STATE I/O Leakage
VI or VO
0.0V
2.3 3.6
r5.0
PA
IOZ(H)
3-STATE I/O Leakage
VI or VO
5.5V
2.3 3.6
500
PA
IOFF
Power-Off Leakage Current
VI or VO
5.5V
0
10
PA
ICC
Quiescent Supply Current
VI
2.3 3.6
20
2.3 3.6
r20
V CC or GND
3.6V d V I, VO d 5.5V (Note 5)
3
50
PA
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74LCXP16245
Absolute Maximum Ratings(Note 3)
74LCXP16245
DC Electrical Characteristics
Symbol
(Continued)
Parameter
VCC
Conditions
'ICC
Increase in ICC per Input
VIH
V CC 0.6V
40qC to 85qC
TA
(V)
Min
Units
Max
2.3 3.6
500
PA
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA
Symbol
Parameter
VCC
CL
40qC to 85qC, RL
3.3V r 0.3V
VCC
50 pF
CL
500:
2.7V
50 pF
VCC
CL
2.5V r 0.2V
Min
Max
Min
Max
Min
Max
tPHL
Propagation Delay
1.5
5.5
1.5
6.0
1.5
6.6
tPLH
An to Bn or Bn to An
1.5
5.5
1.5
6.0
1.5
6.6
tPZL
Output Enable Time
1.5
7.0
1.5
8.0
1.5
9.1
1.5
7.0
1.5
8.0
1.5
9.1
tPZH
tPLZ
Output Disable Time
tPHZ
tOSHL
1.5
7.0
1.5
7.5
1.5
8.4
1.5
7.0
1.5
7.5
1.5
8.4
Output to Output Skew (Note 6)
1.0
tOSLH
Units
50 pF
ns
ns
ns
ns
1.0
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
VCC
Conditions
TA
25qC
(V)
Typical
CL
50 pF, VIH
3.3V, VIL
0V
3.3
0.8
CL
30 pF, VIH
2.5V, VIL
0V
2.5
0.6
CL
50 pF, VIH
3.3V, VIL
0V
3.3
0.8
CL
30 pF, VIH
2.5V, VIL
0V
2.5
0.6
Units
V
V
Capacitance
Symbol
Parameter
Conditions
CIN
Input Capacitance
VCC
Open, V I
CI/O
Input/Output Capacitance
VCC
3.3V, V I
0V or VCC
CPD
Power Dissipation Capacitance
VCC
3.3V, V I
0V or VCC, f
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4
0V or VCC
10 MHz
Typical
Units
7
pF
8
pF
20
pF
74LCXP16245
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC 3.3 r 0.3V
VCC x 2 at VCC 2.5 r 0.2V
tPZH, tPHZ
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f = 1MHz, tr = tf = 3ns)
Symbol
VCC
3.3V r 0.3V
2.7V
2.5V r 0.2V
Vmi
1.5V
1.5V
VCC/2
Vmo
1.5V
1.5V
VCC/2
Vx
VOL 0.3V
VOL 0.3V
VOL 0.15V
Vy
VOH 0.3V
VOH 0.3V
VOH 0.15V
5
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74LCXP16245
Schematic Diagram Generic for LCX Family
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74LCXP16245
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
7
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74LCXP16245 Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs/Outputs and Pull-Down
Resistors
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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