Intersil HIP4020IB Half amp full bridge power driver for small 3v, 5v and 12v dc motor Datasheet

HIP4020
Half Amp Full Bridge Power Driver
for Small 3V, 5V and 12V DC Motors
June 1997
Features
Description
• Two Independent Controlled Complementary
MOS Power Output Half H-Drivers (Full-Bridge)
for Nominal 3V to 12V Power Supply Operation
In the Functional Block Diagram of the HIP4020, the four switches
and a load are arranged in an H-Configuration so that the drive voltage from terminals OUTA and OUTB can be cross-switched to
change the direction of current flow in the load. This is commonly
known as 4-quadrant load control. As shown in the Block Diagram,
switches Q1 and Q4 are conducting or in an ON state when current
flows from VDD through Q1 to the load, and then through Q4 to terminal VSSB; where load terminal OUTA is at a positive potential with
respect to OUTB. Switches Q1 and Q4 are operated synchronously
by the control logic. The control logic switches Q3 and Q2 to an open
or OFF state when Q1 and Q4 are switched ON. To reverse the current flow in the load, the switch states are reversed where Q1 and Q4
are OFF while Q2 and Q3 are ON. Consequently, current then flows
from VDD through Q3, through the load, and through Q2 to terminal
VSSA, and load terminal OUTB is then at a positive potential with
respect to OUTA.
• Split ±Voltage Power Supply Option for Output
Drivers
• Load Switching Capabilities to 0.5A
• Single Supply Range +2.5V to +15V
• Low Standby Current
• CMOS/TTL Compatible Input Logic
• Over-Temperature Shutdown Protection
• Over-Current Limit Protection
• Over-Current Fault Flag Output
• Direction, Braking and PWM Control
Applications
• DC Motor Driver
• Relay and Solenoid Drivers
• Stepper Motor Controller
• Air Core Gauge Instrument Driver
• Speedometer Displays
• Tachometer Displays
Terminals ENA and ENB are ENABLE Inputs for the Logic A and B
Input Controls. The ILF output is an Over-Current Limit Fault Flag Output and indicates a fault condition for either Output A or B or both. The
VDD and VSS are the Power Supply reference terminals for the A and
B Control Logic Inputs and ILF Output. While the VDD positive power
supply terminal is internally connected to each bridge driver, the VSSA
and VSSB Power Supply terminals are separate and independent from
VSS and may be more negative than the VSS ground reference terminal. The use of level shifters in the gate drive circuitry to the NMOS
(low-side) output stages allows controlled level shifting of the output
drive relative to ground.
Ordering Information
• Remote Power Switch
• Battery Operated Switch Circuits
• Logic and Microcontroller Operated Switch
HIP4020IB
-40 to 85
PACKAGE
20 Ld SOIC
PKG. NO.
M20.3
Block Diagram
HIP4020 SOIC
TOP VIEW
NC
1
ILF
2
19 VDD
B1
B2
3
18 NC
B2
ENB
4
17 OUTB
B1
5
16 VSSB
VSS
6
15 VSSA
ENA
7
14 OUTA
A1
8
13 NC
A2
9
12 VDD
NC 10
CONTROL CONTROL
LOGIC A LOGIC B
20 NC
ENB
A1
A2
ENA
ILF
OVER TEMP. AND CURRENT LIMIT,
LEVEL SHIFT, DRIVE CONTROL
VDD
ISENSE
ISENSE
Q3
Q1
OUTB
OUTA
TSENSE
LOAD
Pinout
TEMP.
RANGE (oC)
PART NUMBER
Q2
Q4
ISENSE
ISENSE
11 NC
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
VSSA
VSSB
File Number
3976.1
HIP4020
Absolute Maximum Ratings
Thermal Information
Supply Voltage; VDD to VSS or VSSA or VSSB . . . . . . . . . . . . . . +15V
Neg. Output Supply Voltage, (VSSA, VSSB). . . . . . . . . . . . . (Note 1)
DC Logic Input Voltage (Each Input) . . . (VSS -0.5V) to (VDD +0.5V)
DC Logic Input Current (Each Input) . . . . . . . . . . . . . . . . . . . . .±15mA
ILF Fault Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±15mA
Output Load Current, (Self Limiting, See Elec. Spec.). . . . . ±IO(LIMIT)
Thermal Resistance (Typical, Note 1)
θJA
Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . 105oC/W
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(Lead Tips Only)
Operating Conditions TA = 25oC
Typical Operating Supply Voltage Range, VDD . . . . . . . . +3 to +12V
Low Voltage Logic Retention, Min. VDD . . . . . . . . . . . . . . . . . . . +2V
Idle Supply Current; No Load, VDD = +5V . . . . . . . . . . . . . . . 0.8mA
Typical P+N Channel rDS(ON) , VDD = +5V, 0.5A Load . . . . . . . . . 2Ω
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25oC, VDD = +5V, VSSA = VSSB = VSS = 0V, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = +15V
MIN
TYP
MAX
UNITS
-
-
25
nA
Input Leakage Current
ILEAK
Low Level Input Voltage
VIL
VSS
-
0.8
V
High Level Input Voltage
VIH
2
-
VDD
V
ILF Output Low, Sink Current
IOH
VOUT = 0.4V, VDD = +12V
15
-
-
mA
ILF Output High, Source Current
IOL
VOUT = 11.6V, VDD = +12V
-
-
-15
mA
Input Capacitance
CIN
-
2
-
pF
P-Channel rDS(ON), Low Supply Voltage
rDS(ON)
VDD = +3V, ISOURCE = 250mA
-
1.6
2.1
Ω
N-Channel rDS(ON), Low Supply Voltage
rDS(ON)
VDD = +3V, ISINK = 250mA
-
1
1.5
Ω
P-Channel rDS(ON), High Supply Voltage
rDS(ON)
VDD = +12V, ISOURCE = 400mA
-
0.6
1.2
Ω
N-Channel rDS(ON), High Supply Voltage
rDS(ON)
VDD = +12V, ISINK = 400mA
-
0.5
1.1
Ω
OUTA, OUTB Source Current Limiting
IO(LIMIT)
VDD = +6V, VSS = 0V, VSSA = VSSB = -6V
480
625
1500
mA
OUTA, OUTB Sink Current Limiting
-IO(LIMIT)
VDD = +6V, VSS = 0V, VSSA = VSSB = -6V
480
800
1500
mA
-
0.8
1.5
mA
4.2
4.5
-
V
-
0.4
0.6
V
2.415
2.6
-
V
-
0.25
0.375
V
Idle Supply Current; No Load
IDD
OUTA, OUTB Voltage High
VOH
ISOURCE = 450mA
OUTA, OUTB Voltage Low
VOL
ISINK = 450mA
OUTA, OUTB Voltage High
VOH
VDD = +3V, ISOURCE = 250mA
OUTA, OUTB Voltage Low
VOL
VDD = +3V, ISINK = 250mA
OUTA, OUTB Source Current Limiting
IO(LIMIT)
VDD = +12V
480
625
1500
mA
OUTA, OUTB Sink Current Limiting
-IO(LIMIT)
VDD = +12V
480
800
1500
mA
OUTA, OUTB Source Current Limiting
IO(LIMIT)
VDD = +3V
480
625
1500
mA
OUTA, OUTB Sink Current Limiting
-IO(LIMIT)
VDD = +3V
480
800
1500
mA
-
145
-
oC
Thermal Shutdown
TSD
2
HIP4020
Electrical Specifications
PARAMETER
TA = 25oC, VDD = +5V, VSSA = VSSB = VSS = 0V, Unless Otherwise Specified (Continued)
SYMBOL
MIN
TYP
MAX
UNITS
tPLH
-
2.5
-
µs
tr
-
4
-
µs
tPHL
-
0.1
-
µs
tf
-
0.1
-
µs
IO = 0.5A (Note 2)
Response Time: VEN to VOUT
Turn-On: Prop Delay
Rise Time
Turn-Off: Prop Delay
Fall Time
TEST CONDITIONS
NOTES:
1. VSS is the required common ground reference for the logic input switching. The load currents may be switched positive and negative in
reference to the VSS common ground by using a split supply for VDD (positive) to VSSA and VSSB (negative). For an uneven split in the
supply voltage, the Maximum Negative Output Supply Voltage for VSSA and VSSB is limited by the Maximum VDD to VSSA or VSSB ratings.
Since the VDD pins are internally tied together, the voltage on each VDD pins must be equal and common.
2. Refer to the Truth Table and the VEN to VOUT Switching Waveforms. Current, IO refers to IOUTA or IOUTB as the Output Load current. Note
that ENA controls OUTA and ENB controls OUTB. Each Half H-Switch has independent control from the respective A1, A2, ENA or B1,
B2, ENB inputs. Refer to the Terminal Information Table for external pin connections to establish mode control switching. Figure 1 shows
a typical application circuit used to control a DC Motor.
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
12, 19
VDD
Positive Power Supply pins; internally common and externally connect to the same Positive Supply
(V+).
15
VSSA
Negative Power Supply pin; Negative or Ground return for Switch Driver A; externally connect to the
Supply (V-).
16
VSSB
Negative Power Supply pin; Negative or Ground return for Switch Driver B; externally connect to the
Supply (V-).
6
VSS
Common Ground pin for the Input Logic Control circuits. May be used as a common ground with
VSSA and VSSB.
8, 5
A1, B1
Input pins used to control the direction of output load current to/from OUTA and OUTB, respectively.
When connected, A1 and B1 can be controlled from the same logic signal to change the directional
rotation of a motor.
9, 3
A2, B2
Input pins used to force a low state on OUTA and OUTB, respectively. When connected, A2 and B2
can be controlled from the same logic signal to activate Dynamic Braking of a motor.
7, 4
ENA, ENB
Input pins used to Enable Switch Driver A and Switch Driver B, respectively. When Low, the respective output is in a high impedance (Z) off-state. Since each Switch Driver is independently controlled,
OUTA and OUTB may be a separately PWM controlled as Half H-Switch Drivers.
14, 17
OUTA, OUTB
2
ILF
Respectively, Switch Driver A and Switch Driver B Output pins.
Current Limiting Fault Output Flag pin; when in a high logic state, signifies that Switch Driver A or B
or both are in a Current Limiting Fault Mode.
3
HIP4020
V+
VDD
ON
CONTROL
LOGIC B
LEVEL SHIFTER
AND OC/OT LIMITER
ENB
OFF
A1
DIRECTION
CONTROL
LOGIC A
A2
Q1
D1
Q2
D2
LEVEL SHIFTER
AND OC/OT LIMITER
B2
BRAKE
OVER-TEMP LIMIT
B1
Q3
D3
D4
Q4
ENA
ENABLE
VSSA
VSS
OUTA
(LOGIC
GROUND)
OUTB
ILF
VSSB
LOAD
V-
FIGURE 1. TYPICAL MOTOR CONTROL APPLICATION CIRCUIT SHOWING DIRECTIONAL AND BRAKING CONTROL
TRUTH TABLE
SWITCH DRIVER A
INPUTS
VEN
SWITCH DRIVER B
OUTPUT
INPUTS
OUTPUT
VOUT
A1 A2 ENA
OUTA
B1 B2 ENB
OUTB
50%
tPLH
90%
10%
50%
tr
H
L
H
OH
L
L
H
OH
L
L
H
OL
H
L
H
OL
H
H
H
OL
L
H
H
OL
L
H
H
OL
H
H
H
OL
X
X
L
Z
X
X
L
Z
50%
VEN
tPHL
VOUT
L = Low logic level; H = High logic level
Z = High Impedance (off state)
OH = Output High (sourcing current to the output terminal)
OL = Output Low (sinking current from the output terminal)
X = Don’t Care
10%
90%
tf
SWITCHING WAVEFORMS
FIGURE 2.
4
50%
HIP4020
Application
flowing through Q4 (from the motor terminal OUTB), at the
moment of Dynamic Braking, would continue to flow through
Q4 to the VSSB and VSSA tie, and then continue through
diode D2 to the motor terminal OUTA, to dissipate the stored
kinetic energy as previously described.
The HIP4020 is designed to detect load current feedback from
sampling resistors of low value in the source connections of the
output drivers to VDD, VSSA and VSSB (See Figure 1). When the
sink or source current at OUTA or OUTB exceeds the preset
OC (Over-Current) limiting value of 550mA typical, the current
is held at the limiting value. If the OT (Over-Temperature) Shutdown Protection limit is exceeded, temperature sensing BiMOS
circuits limit the junction temperature to 150oC typical.
Where VDD to VSS are the Power Supply reference terminals
for the Control Logic, the lowest practical supply voltage for
proper logic control should be no less than 2.0V. The VSSA
and VSSB terminals are separate and independent from VSS
and may be more negative than the VSS ground reference
terminal. However, the maximum supply level from VDD to
VSSA or VSSB must not be greater than the Absolute Maximum Supply Voltage rating.
The circuit of Figure 1 shows the Full H-Switch in a small motordrive application. The left (A) and right (B) H-Switch’s are controlled from the A and B inputs via the A and B CONTROL
LOGIC to the MOS output transistors Q1, Q2, Q3 and Q4. The
circuit is intended to safely start, stop, and control rotational
direction for a motor requiring no more than 0.5A of supply current. The stop function includes a Dynamic Braking feature.
Terminals A1, B1, A2, B2, ENA and ENB are internally connected to protection circuits intended to guard the CMOS
gate-oxides against damage due to electrostatic discharge.
(See Figure 3) Inputs ENA, ENB, A1, B1 A2 and B2 have
CD74HCT4000 Logic Interface Protection and Level Converters for TTL or CMOS Input Logic. These inputs are
designed to typically provide ESD protection up to 2kV. However, these devices are sensitive to electrostatic discharge.
Proper I.C. handling procedures should be followed.
With the ENABLE Inputs Low, the MOS transistors Q1 and Q3
are OFF; which cuts-off supply current to OUTA and OUTB.
With the BRAKE terminal Low and ENABLE Inputs High, either
Q1 and Q4 or Q3 and Q2 will be driven into conduction by the
DIRECTION Input Control terminal. The MOS output transistor
pair chosen for conduction is determined by the logic level
applied to the DIRECTION control; resulting in either clockwise
(CW) or counter-clockwise (CCW) shaft rotation.
VDD
When the BRAKE terminal is switched high (while holding
the ENABLE input high), the gates of both Q2 and Q4 are
driven high. Current flowing through Q2 (from the motor terminal OUTA) at the moment of Dynamic Braking will continue to flow through Q2 to the VSSA and VSSB external
connection, and then continue through diode D4 to the motor
terminal OUTB. As such, the resistance of the motor winding
(and the series-connected path) dissipates the kinetic
energy stored in the system. Reversing rotation, current
INPUT
LEVEL
CONV.
FIGURE 3. LOGIC INPUT ESD INTERFACE PROTECTION
VDD
A1
(DIR)
P-DR
LIMIT
D1
A2
(BRAKE)
OT AND OC
PROTECT
Q1
OUTA
Q2
D2
N-DR
LIMIT
ENA
(ENABLE)
VSSA
VDD
B1
(DIR)
P-DR
LIMIT
D3
B2
(BRAKE)
OT AND OC
PROTECT
Q3
OUTB
Q4
D4
N-DR
LIMIT
ENB
(ENABLE)
VSSB
FIGURE 4. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS
5
HIP4020
Typical Performance Curves
P-CHANNEL DRAIN CURRENT (mA)
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
0.5Ω
1Ω
2Ω
VDD = 12V
VDD = 5V
VDD = 3V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7 0.8 0.9 1.0 1.1 1.2 1.3
DRAIN-TO-SOURCE VOLTAGE (V)
1.4
TYPICAL CURRENT
LIMITING
1.5
1.6
1.7
1.8
1.9
2.0
N-CHANNEL DRAIN CURRENT (mA)
FIGURE 5. TYPICAL CHARACTERISTIC OF THE P-MOSFET OUTPUT DRIVER DRAIN CURRENT vs DRAIN-TO-SOURCE
VOLTAGE, TAMBIENT = 25oC
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
VDD = 5V
0.5Ω
1Ω
2Ω
VDD = 3V
TYPICAL CURRENT
LIMITING
VDD = 12V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 6. TYPICAL CHARACTERISTIC OF THE N-MOSFET OUTPUT DRIVER DRAIN CURRENT vs DRAIN-TO-SOURCE
VOLTAGE, TAMBIENT = 25oC
SHORT CIRCUIT CURRENT (mA)
N-CHANNEL
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
P-CHANNEL
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0
VDD SUPPLY VOLTAGE (V)
FIGURE 7. TYPICAL CHARACTERISTIC OF THE P AND N OUTPUT DRIVER SHORT CIRCUIT CURRENT vs SUPPLY
VOLTAGE, TAMBIENT = 25oC
6
HIP4020
Typical Performance Curves
(Continued)
SATURATION VOLTAGE, VDD - VOUT (V)
0.65
HIP4020 SPLIT 5V COMMON GROUND
VSAT vs LOAD CURRENT
VDD = +5V
VSS = VSSA = VSSB = GND
0.60
0.55
0.50
HIGH
0.45
LOW
0.40
0.35
0.30
0.25
VSAT(P)
VSAT(N)
0.20
0.15
0.10
0.05
0.00
0
100
200
300
OUTPUT CURRENT, IO (A)
400
500
FIGURE 8. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A +5V SUPPLY, TAMBIENT = 25oC
SATURATION VOLTAGE, VDD - VOUT (V)
0.70
HIP4020 SPLIT ±3V
VSAT vs LOAD CURRENT
VDD = +3V
VSS = GND
VSSA = VSSB = -3V
0.65
0.60
0.55
0.50
HIGH
0.45
0.40
LOW
0.35
VSAT(P)
0.30
VSAT(N)
0.25
0.20
0.15
0.10
0.05
0.00
0
100
200
300
400
OUTPUT CURRENT, IO (A)
500
600
700
FIGURE 9. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A ±3V SPLIT SUPPLY, OUTPUT
REFERENCE EQUAL LOGIC GROUND, TAMBIENT = 25oC
SATURATION VOLTAGE, VDD - VOUT (V)
0.70
0.65
HIP4020 SPLIT ±6V
VSAT vs LOAD CURRENT
VDD = +6V
VSS = GND
VSSA = VSSB = -6V
0.60
0.55
0.50
0.45
0.40
HIGH
0.35
LOW
0.30
0.25
0.20
VSAT(P)
0.15
VSAT(N)
0.10
0.05
0.00
0
100
200
300
400
OUTPUT CURRENT, IO (A)
500
600
FIGURE 10. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A ±6V SPLIT SUPPLY, OUTPUT
REFERENCE EQUAL LOGIC GROUND, TAMBIENT = 25oC
7
HIP4020
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4961
0.5118
12.60
13.00
3
E
0.2914
0.2992
7.40
7.60
4
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
NOTES:
MILLIMETERS
MAX
A1
e
α
MIN
20
0o
20
7
8o
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
8
Similar pages