Renesas M5M5V216ATP-70HI 2097152-bit (131072-word by 16-bit) cmos static ram Datasheet

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Customer Support Dept.
April 1, 2003
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
FEATURES
DESCRIPTION
The M5M5V216A is a f amily of low v oltage 2-Mbit static RAMs
organized as 131,072-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.25µm CMOS technology .
The M5M5V216A is suitable f or memory applications where a
simple interf acing , battery operating and battery backup are the
important design objectiv es.
M5M5V216ATP, RT are packaged in a 44-pin 400mil thin small
outline package. M5M5V216ATP (normal lead bend ty pe package)
, M5M5V216ART (rev erse lead bend ty pe package) , both ty pes
are v ery easy t o design a printed circuit board.
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,ty p.)
No clocks, No ref resh
Data retention supply v oltage=2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S , BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prev ents data contention in the I/O bus
Process technology : 0.25µm CMOS
Package: 44 pin 400mil TSOP (II)
PART NAME TABLE
Version,
Operating
temperature
Power
Supply
Part name
M5M5V216ATP,RT -55HI
I-version
2.7 ~ 3.6V
-40 ~ +85°C
M5M5V216ATP,RT -70HI
Access
time
max.
Activ e
current
Ratings (max.)
Icc1
(3.0V,
ty p.)
25°C 40°C 70°C 85°C
45mA
(10MHz)
1µA 3µA 8µA 24µA
5mA
(1MHz)
Stand-by c urrent Icc (PD), Vcc=3.0V
ty pical *
25°C
40°C
55ns
0.3µA 1µA
70ns
* "ty pical" parameter is sampled, not 100% tested.
PIN CONFIGURATION
A4
A3
A2
A1
A0
S
DQ1
DQ2
DQ3
DQ4
Vcc
GND
DQ5
DQ6
DQ7
DQ8
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BC2
BC1
DQ16
DQ15
DQ14
DQ13
GND
Vcc
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
NC
A5
A6
A7
OE
BC2
BC1
DQ16
DQ15
DQ14
DQ13
GND
Vcc
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
S
DQ1
DQ2
DQ3
DQ4
Vcc
GND
DQ5
DQ6
DQ7
DQ8
WE
A16
A15
A14
A13
A12
Pin
A0 ~ A16
Function
Address input
DQ1 ~ DQ16 Data input / output
S
Chip select input
W
Write control input
OE
Output inable input
BC1
Lower By te (DQ1 ~ 8)
BC2
Vcc
Upper By te(DQ9 ~ 16)
GND
Ground supply
Power supply
Outline: TP : 44P3W - H
RT : 44P3W - J
NC: No Connection
1
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V216ATP,RT is organized as 131,072-words by
16-bit. These dev ices operate on a single +2.7~3.6V power
supply , and are directly TTL compatible to both input and
output. Its f ully s t atic circuit needs no clocks and no
ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1 , BC2 , S , W and OE.
Each mode is summarized in the f unction table.
A write operation is executed whenev er the low lev el W
ov erlaps with the low lev el BC1 and/or BC2 and the low
lev el S. The address(A0~A16) must be set up bef ore the
write cy c le and must be stable during the entire cy c le.
A read operation is executed by s etting W at a high lev el
and OE at a low lev el while BC1 and/or BC2 and S are in
an activ e state(S=L).
When setting BC1 at the high lev el and other pins are in
an activ e stage , upper-by te are in a selesctable mode in
which both reading and writing are enabled, and lower-by t e
are in a non-selectable mode. And when setting BC2 at a
high lev el and other pins are in an activ e stage, lowerby t e are in a selectable mode and upper-by te are in a
non-selectable mode.
When setting BC1 and BC2 at a high lev el or S at a high
lev el, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with
other chips and memory expansion by BC1, BC2 and S.
The power supply c urrent is reduced as low as 0.3µA(25 C,
ty pical), and the memory data can be held at +2V power
supply , enabling battery back-up operation during power
f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S BC1 BC2 W OE
Mode
DQ1~8
DQ9~16
Icc
H
X
X
X
X
Non selection
High-Z High-Z Standby
L
H
H
X
X
Non selection
High-Z High-Z Standby
Write
L
L
H
L
L
L
H
H
X
L
L
L
H
H
H
Read
Din
High-Z
Activ e
Dout
High-Z
Activ e
High-Z High-Z
Activ e
L
H
L
L
X
Write
High-Z
Din
Activ e
L
H
L
H
L
Read
High-Z
Dout
Activ e
L
H
L
H
H
L
L
L
L
X
Write
Note : "H" and "L" in this table mean VIH or VIL. L
"X" in this table should be "H" or "L".
L
L
L
H
L
Read
L
L
H
H
BLOCK DIAGRAM
A0
High-Z High-Z
Din
Din
Dout
Dout
High-Z High-Z
Activ e
Activ e
Activ e
Activ e
DQ
1
A1
MEMORY ARRAY
DQ
8
131072 WORDS
x 16 BITS
A 15
-
DQ
9
A 16
CLOCK
GENERATOR
DQ
16
S
BC1
BC2
Vcc
W
GND
OE
2
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VI
VO
Pd
Ta
Parameter
Conditions
Ratings
Supply v oltage
With respect to GND
Input v oltage
With respect to GND
Output v oltage
With respect to GND
Power dissipation
Ta=25ºC
Operating
temperature
I-v ersion
-0.5 * ~ +4.6
-0.5 * ~ Vcc + 0.5
0 ~ Vcc
700
(-HI)
Storage temperature
T stg
Units
V
mW
- 40 ~ +85
ºC
- 65 ~ +150
ºC
* -3.0V in case of AC (Pulse width <
= 30ns)
DC ELECTRICAL CHARACTERISTICS
Limits
Parameter
Symbol
V IH
V IL
V OH1
V OH2
V OL
II
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
Conditions
Min
High-lev el input v oltage
2.0
-0.3 *
2.4
Low-lev el input v oltage
High-level output voltage 1
High-level output voltage 2
Low-lev el output v oltage
Input leakage current
I OH= -0.5mA
I OH= -0.05mA
I OL=2mA
V I =0 ~ Vcc
Output leakage current
BC1 and BC2=VIH or S=VIH or OE=VIH, VI/O =0 ~ Vcc
Icc 1
Activ e supply c urrent
( AC,MOS lev el )
BC1 and BC2 <
= 0.2V , S<
= 0.2V
>
other inputs <
= 0.2V or = Vcc-0.2V
Output - open (duty 100%)
f = 10MHz
f = 1MHz
Icc 2
Activ e supply c urrent
( AC,TTL lev el )
BC1 and BC2=V IL , S=V IL
other pins =V IH or V IL
Output - open (duty 100%)
f = 10MHz
f = 1MHz
Icc 3
( AC,MOS lev el )
< 1 > S => Vcc - 0.2V,other inputs = 0 ~ Vcc
~ +25ºC
< 2 > BC1 and BC2 => Vcc - 0.2V
S<
= 0.2V Other inputs=0~Vcc
~ +40ºC
~ +70ºC
~ +85ºC
Icc 4
Stand by s upply current
( AC,TTL lev el )
BC1 and BC2=VIH , S=VIL
or
S=VIH
Other inputs= 0 ~ Vcc
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=3.0V and Ta=25ºC
Parameter
CI
Input capacitance
CO
Output capacitance
Units
Vcc+0.3V
0.6
V
0.4
±1
±1
-
µA
45
5
60
15
-
45
5
60
15
0.3
1
-
-
2
5
10
30
µA
-
-
0.5
mA
mA
* -3.0V in case of AC (Pulse width <
= 30ns)
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
CAPACITANCE
Symbol
Max
Vcc-0.5V
IO
Stand by s upply current
Ty p
Conditions
V I =GND, VI =25mVrms, f =1MHz
V O = GND,VO =25mVrms, f =1MHz
Min
Limits
Ty p
Max
Units
8
10
pF
3
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
(1) TEST CONDITIONS
Supply v oltage
2.7V~3.6V
V IH=2.4V,V IL=0.4V
Input rise time and f all time 5ns
1TTL
Input pulse
Ref erence lev el
Output loads
DQ
CL
V OH=V OL=1.5V
Transition is measured ±500mV f rom
steady state voltage.(f or ten,t dis )
Including scope and
jig capacitance
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits
Parameter
Symbol
t CR
t a(A)
t a(S)
t a(BC1)
t a(BC2)
t a(OE)
t dis (S)
t dis (BC1)
t dis (BC2)
t dis (OE)
t en(S)
t en(BC1)
t en(BC2)
t en(OE)
t V(A)
55HI
Read cy cle time
Address access time
Chip select access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af t er S high
Output disable time af t er BC1 high
Output disable time af t er BC2 high
Output disable time af t er OE high
Output enable time af ter S low
Output enable time af ter BC1 low
Output enable time af ter BC2 low
Output enable time af ter OE low
Data v alid time after address
Min
55
70HI
Max
Min
70
Units
Max
70
70
70
70
35
25
25
25
25
55
55
55
55
30
20
20
20
20
10
10
10
5
10
10
10
10
5
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Limits
Symbol
t CW
t w(W)
t su(A)
t su(A-WH)
t su(BC1)
t su(BC2)
t su(S)
t su(D)
t h(D)
t rec (W)
t dis (W)
t dis (OE)
t en(W)
t en(OE)
55HI
Parameter
Write cy cle time
Write pulse width
Address setup time
Address setup time with respect to W
By te control 1 setup time
By te control 2 setup time
Chip select setup time
Data setup time
Data hold time
Write recov ery time
Output disable time f rom W low
Output disable time f rom OE high
Output enable time f rom W high
Output enable time f rom OE low
Min
55
45
0
50
50
50
50
25
0
0
70HI
Max
Min
70
55
0
65
65
65
65
30
0
0
25
25
20
20
5
5
Units
Max
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
t CR
A 0~16
t a(A)
t a(BC1)
BC1
t v (A)
t a(BC2)
or
and / or
BC2
(Note3)
t dis (BC1) or t dis (BC1)
(Note3)
t dis (S)
(Note3)
t dis (OE)
(Note3)
t a(S)
S
(Note3)
t a (OE)
OE
(Note3)
t en (OE)
W = "H" lev el
t en (BC1)
t en (BC2)
t en (S)
DQ 1~16
VALID DATA
Write cycle ( W control mode )
t CW
A 0~16
t su (BC1) or t su (BC2)
BC1
and / or
BC2
(Note3)
(Note3)
t su (S)
S
t su (A-WH)
(Note3)
(Note3)
OE
t su (A)
t w (W)
t rec (W)
t dis (W)
W
t en (OE)
t dis (OE)
DQ 1~16
t en (W)
DATA IN
STABLE
t su (D)
t h (D)
5
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC control mode)
t CW
A 0~16
t su (A)
BC1
t su (BC1) or
t su (BC2)
t rec (W)
and / or
BC2
S
(Note3)
(Note3)
(Note5)
W
(Note4)
(Note3)
(Note3)
t su (D)
t h (D)
DATA IN
STABLE
DQ 1~16
Write cycle (S control mode)
t CW
A 0~16
BC1
(Note4)
and / or
BC2
(Note3)
t su (A)
t su (S)
t rec (W)
(Note3)
S
(Note5)
W
(Note4)
(Note3)
DQ 1~16
t su (D)
t h (D)
(Note3)
DATA IN
STABLE
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S low , ov erlaps BC1 and/or BC2 low and W low.
Note 5: When the f alling edge of W is simultaneously or priorto the f alling edge of BC1 and/or BC2 or the f alling edge of S,
the outputs are maintained in the high impedance state.
Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.
6
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Symbol
Vcc
Limits
Parameter
Test conditions
Min
(PD) Power down supply voltage
V I (BC)
V I (S)
Byte control input BC1 & BC2
Chip select input S
Vcc=3.0V
Icc
(PD)
~ +85ºC
1) S >
= Vcc - 0.2V
other inputs=0~Vcc
2) BC1 and BC2 >
= Vcc - 0.2V
S<
= 0.2V, other inputs=0~Vcc
Power down
supply c urrent
~ +70ºC
~ +40ºC
-40 ~ +25ºC
Ty p
Max
Units
V
2.0
2.0
2.0
-
-
-
1
0.3
V
V
24
8
3
1
µA
µA
µA
µA
Note 7: Typical parameter of Icc(PD) indicates the value for the
center of distribution at 3.0V, and not 100% tested.
(2) TIMING REQUIREMINTS
Symbol
t su (PD)
t rec (PD)
Limits
Parameter
Test conditions
Min
Ty p
0
5
Power down set up time
Power down recov ery t ime
Max
Units
ns
ms
(3) TIMING DIAGRAM
BC control mode
Note8: On the BC# control mode, the lev el of S# must be f ixed at S# > Vcc-0.2V or S# < 0.2V.
Vcc
t su (PD)
BC1
2.7V
2.7V
t rec (PD)
2.2V
2.2V
BC1 , BC2 >
= Vcc - 0.2V
BC2
S control mode
Vcc
t su (PD)
2.7V
2.7V
2.2V
2.2V
S
t rec (PD)
S>
= Vcc - 0.2V
7
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