To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY / M16C/20 SERIES
M30218
Group
User’s Manual
http://www.infomicom.maec.co.jp/indexe.htm
Before using this material, please visit the above website to confirm that this is the most
current document available.
REV.B
Revision date: Jun. 27, 2001
Keep safety first in your circuit designs!
●
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
●
●
●
●
●
●
●
●
These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without notice due
to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by
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www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information
and products. Mitsubishi Electric Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use
in a device or system that is used under circumstances in which human life is potentially at
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
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Preface
This user's manual describes the function and
features of the Mitsubishi M30218 Group CMOS
16-bit microcomputer. The software features are
explained to help designers take full advantage
of the M16C functions.
For details about the software, please refer to
the “M16C/60, M16C/20 series software manual”,
and for the development support tools, please
refer to the related instruction manual.
How to Use This Manual
This user's manual is written for the M30218 group.
The reader of this manual is expected to have the basic knowledge of electric and logic
circuits and microcomputers.
This manual is for the use of the models below.
• M30217MA-AXXXFP
• M30218MC-AXXXFP
• M30218FCFP
These products have similar features except for the memories, which differ from one product to
another. This manual gives descriptions of M30218MC-AXXXFP. Memories built-in are as shown
below. Be careful when writing a program, as the memories have different capacities.
RAM size
(Byte)
M30218MC-AXXXFP
M30218FCFP
12K
M30217MA-AXXXFP
5K
1K
512
ROM size
(Byte)
128K
96K
The figure of each register configuration describes its functions, contents at reset, and attributes
as follows :
• Bit attribute
R.....Read
O.....Possible to read
X.....Impossible to read
W.....Write
O.....Possible to write
X.....Impossible to write
Bit attribute
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ONSF
Bit symbol
Address
038216
When reset
00X000002
Bit name
TA0OS
Timer A0 one-shot start flag
TA1OS
Timer A1 one-shot start flag
TA2OS
Timer A2 one-shot start flag
TA3OS
Timer A3 one-shot start flag
TA4OS
Timer A4 one-shot start flag
Function
RW
1: Timer start
When read, the value is “0”
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if
read, turns out to be indeterminate.
TA0TGL
TA0TGH
Timer A0 event/trigger
select bit
b7 b6
0 0 : Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to “0”.
When TAiIN is selected, TAiOUT assigned on same pin can not be used. (i=0 to 4)
This manual comprises of five chapters. Use the suggested chapters as a reference for the
following topics:
* To understand hardware specifications ................................................... Chapter 1 Hardware
* To understand the basic way of using peripheral
features and the operation timing ................................ Chapter 2 Peripheral Functions Usage
* To observe applications of
peripheral features ........................ Chapter 3 Examples of Peripheral Functions Applications
* To understand interrupt timing in detail .................................................... Chapter 4 Interrupts
* To understand standard data............................................ Chapter 5 Standard Characteristics
This manual includes a quick reference immediately following the Table of Contents, indicate
the page of the topic to be pursued.
* To find a page describing a specific register
by the register address ............................... Quick Reference to Pages Classified by Address
M16C Family-related document list
Usages
(Microcomputer development flow)
Type of document
Outline design
of system
Hardware
Selection of
microcomputer
Data sheet and
data book
Hardware specifications (pin assignment,
memory map, specifications of peripheral functions, electrical characteristics, timing charts)
User’s manual
Detailed description about hardware specifications, operation, and application examples
(connection with peripherals, relationship with
software)
Programming
manual
Method for creating programs using assembly
and C languages
Software manual
Detailed description about operation of each
instruction (assembly language)
Software
development
Software
Detail design
of system
Hardware
development
Contents
System
evaluation
M16C Family Line-up
M16C Family
M16C/80 Series
M16C/80 Group
M16C/60 Series
M16C/60 Group
M16C/61 Group
M16C/62 Group
M16C/20 Series
M16C/20 Group
M16C/21 Group
Table of Contents
Chapter 1 Hardware ________________________________________
Description ............................................................................................................................................2
Pin Description ...................................................................................................................................... 7
Memory .................................................................................................................................................9
Central Processing Unit (CPU) ........................................................................................................... 12
Reset ................................................................................................................................................... 15
Software Reset ................................................................................................................................... 18
Clock Generating Circuit ..................................................................................................................... 19
Clock Output ....................................................................................................................................... 23
Stop Mode ..........................................................................................................................................23
Wait Mode ........................................................................................................................................... 23
Status Transition Of BCLK .................................................................................................................. 24
Power Control ..................................................................................................................................... 25
Protection ............................................................................................................................................ 27
Overview of Interrupt ........................................................................................................................... 28
Watchdog Timer .................................................................................................................................. 46
DMAC ................................................................................................................................................. 48
FLD Controller ..................................................................................................................................... 54
Timer ................................................................................................................................................... 71
Timer A ............................................................................................................................................... 72
Timer B ............................................................................................................................................... 82
Serial I/O ............................................................................................................................................. 88
Serial I/O2 ......................................................................................................................................... 102
A-D Converter ................................................................................................................................... 115
D-A Converter ................................................................................................................................... 125
CRC Calculation Circuit .................................................................................................................... 127
Programmable I/O Ports ................................................................................................................... 129
Exclusive High-breakdown-voltage Output Ports ............................................................................. 129
Flash Memory ................................................................................................................................... 154
Chapter 2 Peripheral Functions Usage ________________________
2.1 Protect ........................................................................................................................................ 178
2.1.1 Overview .............................................................................................................................. 178
2.1.2 Protect Operation ................................................................................................................. 178
2.2 Timer A ....................................................................................................................................... 180
2.2.1 Overview .............................................................................................................................. 180
2.2.2 Operation of Timer A (timer mode) ...................................................................................... 186
2.2.3 Operation of Timer A (timer mode, gate function selected) ................................................. 188
2.2.4 Operation of Timer A (timer mode, pulse output function selected) .................................... 190
2.2.5 Operation of Timer A (event counter mode, reload type selected) ...................................... 192
2.2.6 Operation of Timer A (event counter mode, free run type selected) .................................... 194
2.2.7 Operation of timer A (2-phase pulse signal process in event counter mode, normal mode selected) .................................................................................................................................. 196
2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode, multiply-by-4 mode
selected) .............................................................................................................................. 198
2.2.9 Operation of Timer A (one-shot timer mode) ....................................................................... 200
2.2.10 Operation of Timer A (one-shot timer mode, external trigger selected) ............................. 202
2.2.11 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected) .......... 204
2.2.12 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected) ............ 206
2.2.13 Precautions for Timer A (timer mode) ................................................................................ 208
2.2.14 Precautions for Timer A (event counter mode) .................................................................. 209
2.2.15 Precautions for Timer A (one-shot timer mode) ................................................................. 210
2.2.16 Precautions for Timer A (pulse width modulation mode) ................................................... 211
2.3 Timer B ....................................................................................................................................... 212
2.3.1 Overview .............................................................................................................................. 212
2.3.2 Operation of Timer B (timer mode) ...................................................................................... 216
2.3.3 Operation of Timer B (event counter mode) ........................................................................ 218
2.3.4 Operation of Timer B (pulse period measurement mode) ................................................... 220
2.3.5 Operation of Timer B (pulse width measurement mode) ..................................................... 222
2.3.6 Precautions for Timer B (timer mode, event counter mode) ................................................ 224
2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode) ........................... 225
2.4 Clock-Synchronous Serial I/O ..................................................................................................... 226
2.4.1 Overview .............................................................................................................................. 226
2.4.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode) ..................... 232
2.4.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O mode, transfer clock
output from multiple pins function selected) ........................................................................ 236
2.4.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode) ........................... 240
2.4.5 Precautions for Serial I/O (in clock-synchronous serial I/O) ................................................ 244
2.5 Clock-Asynchronous Serial I/O (UART) ...................................................................................... 246
2.5.1 Overview ..............................................................................................................................246
2.5.2 Operation of Serial I/O (transmission in UART mode) ......................................................... 254
2.5.3 Operation of Serial I/O (reception in UART mode) .............................................................. 258
2.6 Serial I/O2 ...................................................................................................................................262
2.6.1 Overview ..............................................................................................................................262
2.6.2 Serial I/O2 connection examples ......................................................................................... 267
2.6.3 Serial I/O2 modes ................................................................................................................ 269
2.6.4 Serial I/O2 Operations (transmission in 8-bit serial I/O mode) ........................................... 270
2.6.5 Serial I/O2 Operations (transmission/reception in automatic transfer serial I/O mode) ...... 274
2.6.6 Serial I/O2 Operations (transmission/reception in automatic transfer serial I/O mode, using
handshake signal) ............................................................................................................... 278
2.6.7 Precautions for Serial I/O2 ................................................................................................... 282
2.7 FLD (VFD) Controller ..................................................................................................................286
2.7.1 Overview ..............................................................................................................................286
2.7.2 FLD operation (FLD automatic display and key-scan using segments) .............................. 296
2.7.3 FLD operation (FLD automatic display and key-scan using digits) ...................................... 302
2.7.4 FLD operation (FLD display and key-scan using segment by software) ............................. 306
2.7.5 FLD operation (Display with digit expander M35501FP) ..................................................... 312
2.7.6 FLD operation (Display with digit expander M35501FP: column discrepancy) ................... 318
2.7.7 Precautions for FLD controller ............................................................................................. 325
2.8 A-D Converter .............................................................................................................................326
2.8.1 Overview ..............................................................................................................................326
2.8.2 Operation of A-D converter (one-shot mode) ...................................................................... 332
2.8.3 Operation of A-D Converter (in repeat mode) ...................................................................... 334
2.8.4 Operation of A-D Converter (in single sweep mode) ........................................................... 336
2.8.5 Operation of A-D Converter (in repeat sweep mode 0) ....................................................... 338
2.8.6 Operation of A-D Converter (in repeat sweep mode 1) ....................................................... 340
2.8.7 Precautions for A-D Converter ............................................................................................. 342
2.8.8 Method of A-D Conversion (10-bit mode) ............................................................................ 343
2.8.9 Method of A-D Conversion (8-bit mode) .............................................................................. 345
2.8.10 Absolute Accuracy and Differential Non-Linearity Error .................................................... 347
2.8.11 Internal Equivalent Circuit of Analog Input ......................................................................... 349
2.8.12 Sensor’s Output Impedance under A-D Conversion .......................................................... 350
2.9 D-A Converter ............................................................................................................................. 352
2.9.1 Overview .............................................................................................................................. 352
2.9.2 D-A Converter Operation ..................................................................................................... 353
2.10 DMAC ....................................................................................................................................... 354
2.10.1 Overview ............................................................................................................................ 354
2.10.2 Operation of DMAC (one-shot transfer mode) ................................................................... 358
2.10.3 Operation of DMAC (repeated transfer mode) ................................................................... 360
2.11 CRC Calculation Circuit ............................................................................................................ 362
2.11.1 Overview ............................................................................................................................ 362
2.11.2 Operation of CRC Calculation Circuit ................................................................................ 363
2.12 Watchdog Timer ....................................................................................................................... 364
2.12.1 Overview ............................................................................................................................ 364
2.12.2 Operation of Watchdog Timer ............................................................................................ 366
2.13 Address Match Interrupt ........................................................................................................... 368
2.13.1 Overview ............................................................................................................................ 368
2.13.2 Operation of Address Match Interrupt ................................................................................ 370
2.14 Power Control ........................................................................................................................... 372
2.14.1 Overview ............................................................................................................................ 372
2.14.2 Stop Mode Set-Up ............................................................................................................. 377
2.14.3 Wait Mode Set-Up ............................................................................................................. 378
2.14.4 Precautions in Power Control ............................................................................................ 379
2.15 Programmable I/O Ports ........................................................................................................... 380
2.15.1 Overview ............................................................................................................................ 380
Chapter 3 Examples of Peripheral functions Applications ________
3.1 Long-Period Timers ................................................................................................................ 388
3.2 Variable-Period Variable-Duty PWM Output ........................................................................... 392
3.3 Delayed One-Shot Output ...................................................................................................... 396
3.4 Buzzer Output ......................................................................................................................... 400
3.5 Solution for External Interrupt Pins Shortage ......................................................................... 402
3.6 Memory to Memory DMA Transfer ......................................................................................... 404
3.7 Controlling Power Using Stop Mode ....................................................................................... 408
3.8 Controling Power Using Wait Mode ........................................................................................ 412
Chapter 4 Interrupt_________________________________________
4.1 Overview of Interrupt ..................................................................................................................408
4.1.1 Type of Interrupts .................................................................................................................408
4.1.2 Software Interrupts .............................................................................................................. 409
4.1.3 Hardware Interrupts .............................................................................................................420
4.1.4 Interrupts and Interrupt Vector Tables ................................................................................. 421
4.2 Interrupt Control .......................................................................................................................... 423
4.2.1 Interrupt Enable Flag ...........................................................................................................425
4.2.2 Interrupt Request Bit ............................................................................................................ 425
4.2.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) .................... 426
4.2.4 Rewrite the interrupt control register .................................................................................... 427
4.3 Interrupt Sequence ..................................................................................................................... 428
4.3.1 Interrupt Response Time .....................................................................................................428
4.3.2 Variation of IPL when Interrupt Request is Accepted .......................................................... 429
4.3.3 Saving Registers ..................................................................................................................430
4.4 Returning from an Interrupt Routine ........................................................................................... 432
4.5 Interrupt Priority .......................................................................................................................... 432
4.6 Multiple Interrupts .......................................................................................................................434
4.7 Precautions for Interrupts ...........................................................................................................436
Chapter 5 Standard Characteristics ___________________________
5.1 Standard DC Characteristics ......................................................................................................440
5.1.1 Standard Ports Characteristics ............................................................................................ 440
5.1.2 Characteristics of ICC-f(XIN) ...............................................................................................444
5.2 Standard Characteristics of A-D Converter ................................................................................ 446
5.3 Standard Characteristics of D-A Converter ................................................................................ 448
5.4 Standard Characteristics of Pull-Up Resistor ............................................................................. 451
This page kept blank for layout purposes.
Quick Reference to Pages Classified by Address
Address
Register
Page
Address
000016
004016
000116
004116
000216
004216
000316
000416
000516
000616
000716
000A16
18
22
004416
004516
004616
004716
004816
Address match interrupt enable register (AIER)
Protect register (PRCR)
43
27
004916
004B16
000C16
004C16
000D16
000F16
34
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
34
004D16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
47
001016
001116
INT3 interrupt control register (INT3IC)
INT4 interrupt control register (INT4IC)
INT5 interrupt control register (INT5IC)
004A16
000B16
000E16
Page
004316
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
000816
000916
Register
Address match interrupt register 0 (RMAD0)
43
004E16
A-D conversion interrupt control register (ADIC)
004F16
SI/O2 automatic transfer interrupt control register (ASIOIC)
005016
FLD interrupt control register (FLDIC)
005116
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
001216
005216
001316
005316
001416
005416
001616
005616
001716
005716
001816
005816
001916
005916
001A16
005A16
001B16
005B16
001C16
005C16
001D16
005D16
001E16
005E16
001F16
005F16
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
INT2 interrupt control register (INT2IC)
002216
034016
Serial I/O2 automatic transfer data pointer (SIO2DP) 105
002316
034116
001516
Address match interrupt register 1 (RMAD1)
43
005516
34
002016
002116
DMA0 source pointer (SAR0)
51
034216
002416
002516
DMA0 destination pointer (DAR0)
51
002616
034416
002716
034516
002816
DMA0 transfer counter (TCR0)
002916
51
034616
034816
002B16
034916
DMA0 control register (DM0CON)
50
034B16
002E16
034C16
002F16
034D16
DMA1 source pointer (SAR1)
51
035016
003316
035116
003416
035216
DMA1 destination pointer (DAR1)
51
035416
003716
035516
DMA1 transfer counter (TCR1)
035616
51
Serial I/O2 control register 3 (SIO2CON3)
105
FLD mode register (FLDM)
FLD output control register (FLDCON)
Tdisp time set register (TDISP)
56
Toff1 time set register (TOFF1)
57
Toff2 time set register (TOFF2)
57
035716
003A16
035816
003B16
035916
003C16
105
035316
003616
003916
Serial I/O2 register / transfer counter (SIO2)
034F16
003216
003816
104
034E16
003016
003516
Serial I/O2 control register 2 (SIO2CON2)
034A16
002D16
003116
104
034716
002A16
002C16
Serial I/O2 control register 1 (SIO2CON1)
034316
DMA1 control register (DM1CON)
50
035A16
003D16
035B16
003E16
035C16
003F16
035D16
035E16
035F16
FLD data pointer (FLDDP)
P2 FLD/port switch register (P2FPR)
P3 FLD/port switch register (P3FPR)
P4 FLD/port switch register (P4FPR)
P5 digit output set register (P5DOR)
P6 digit output set register (P6DOR)
57
58
59
Quick Reference to Pages Classified by Address
Address
038016
038116
038216
038316
038416
Register
Count start flag (TABSR)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
Page
73
03C116
74
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
73
03C616
Timer A0 (TA0)
03C716
03C816
Timer A1 (TA1)
Timer A2 (TA2)
03C916
73
Timer A3 (TA3)
03CE16
03CF16
UART0 bit rate generator (U0BRG)
83
03D716
72
82
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
91
03DC16
03E016
03E116
90
UART1 transmit buffer register (U1TB)
90
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
91
92
03B016
UART transmit/receive control register 2 (UCON)
92
03E416
03E516
03E716
03E816
03EA16
03EC16
03ED16
117
D-A register 1 (DA1)
126
D-A control register (DACON)
126
Port P0 (P0)
Port P1 (P1)
132
Port P2 (P2)
Port P3 (P3)
132
Port P3 direction register (PD3)
Port P4 (P4)
Port P5 (P5)
Port P4 direction register (PD4)
132
Port P6 (P6)
Port P7 (P7)
132
Port P7 direction register (PD7)
Port P8 (P8)
Port P9 (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 (P10)
132
Port P10 direction register (PD10)
132
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
133
126
03EE16
03EF16
03F016
03F116
03B216
03F216
03F316
03B316
03B516
Flash memory control register 0 (FCON0) (Note)
Flash memory control register 1 (FCON1) (Note)
03B616
Flash command register (FCMD) (Note)
03F416
155
03F516
03F616
03F716
03B716
DMA0 request cause select register (DM0SL)
50
DMA1 request cause select register (DM1SL)
50
03F816
03F916
03B916
03FA16
03FB16
03BB16
03BE16
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
03E616
03B116
03BD16
118
03EB16
90
03BC16
A-D control register 2 (ADCON2)
03E216
03E916
UART1 receive buffer register (U1RB)
03BA16
A-D register 7 (AD7)
03E316
91
92
03AF16
03B816
A-D register 6 (AD6)
03DD16
UART1 bit rate generator (U1BRG)
03B416
A-D register 5 (AD5)
03DB16
03A916
03AE16
03D816
03DA16
91
03AD16
118
03D916
UART1 transmit/receive mode register (U1MR)
03AC16
A-D register 4 (AD4)
03D316
03D616
90
03AB16
A-D register 3 (AD3)
03D516
UART0 receive buffer register (U0RB)
03AA16
A-D register 2 (AD2)
03D216
03D416
03A816
03A716
A-D register 1 (AD1)
03DF16
03A116
03A616
A-D register 0 (AD0)
03DE16
UART0 transmit/receive mode register (U0MR)
03A516
Page
03D116
Timer B2 (TB2)
03A016
03A416
Register
03D016
Timer B0 (TB0)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
03CB16
03CD16
Timer A4 (TA4)
Timer B1 (TB1)
03CA16
03CC16
039F16
03A316
03C416
03C516
039E16
03A216
03C216
03C316
038516
038616
Address
03C016
CRC data register (CRCD)
03FC16
127
CRC input register (CRCIN)
03FD16
03FE16
03FF16
03BF16
Note: This register is only exist in flash memory version.
Chapter 1
Hardware
Mitsubishi microcomputers
M30218 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
The M30218 group of single-chip microcomputers are built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These
single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They
also feature a built-in multiplier and DMAC, making them ideal for controlling musical instruments, household appliances and other high-speed processing applications.
The M30218 group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
• Basic machine instructions ............. Compatible with the M16C/60 series
• Memory capacity ............................ ROM / RAM (See figure memory expansion)
• Shortest instruction execution time . 100ns (f(XIN)=10MHz)
• Supply voltage ................................ 4.0V to 5.5V (f(XIN)=10MHz)
2.7V to 5.5V (f(XIN)=3.5MHz)(Note)
• Interrupts ........................................ 19 internal and 6 external interrupt sources, 4 software
• Multifunction 16-bit timer ................ Timer A X 5, Timer B X 3
• FLD conrtoller ................................. total 56 pins
(high-breakdown-voltage P-channel open-drain output : 52pins)
• Serial I/O ......................................... 2 channels for UART or clock synchronous,
1 channels for clock synchronous
(max.256 bytes automatic transfer function)
• DMAC ............................................. 2 channels (triggers: 15 sources)
• A-D converter ................................. 10 bits X 8 channels
• D-A converter ................................. 8 bits X 2 channels
• CRC calculation circuit ................... 1 circuit
• Watchdog timer .............................. 1 pin
• Programmable I/O .......................... 48 pins
• High-breakdown-voltage output ...... 52 pins
• Clock generating circuit .................. 2 built-in clock generation circuit
(built-in feedback resistor, and external ceramic or quartz oscillator)
Note: Only mask ROM version.
Applications
Household appliances, office equipment, Audio etc.
------Table of Contents-----Central Processing Unit (CPU) ..................... 12
Reset............................................................. 15
Clock Generating Circuit ............................... 19
Protection ...................................................... 27
Interrupts ....................................................... 28
Watchdog Timer ............................................ 46
DMAC ........................................................... 48
FLD controller ............................................... 54
Timer ............................................................. 71
Serial I/O ....................................................... 88
A-D Converter ............................................. 115
D-A Converter ............................................. 125
CRC Calculation Circuit .............................. 127
Programmable I/O Ports ............................. 129
Flash memory ............................................. 154
2
81
82
83
84
85
86
87
88
89
90
91
92
Package:100P6S-A
Figure 1. Pin configuration (top view)
3
P76/TA3IN/TA1OUT/CLK1
P75/TA2IN/TA0OUT/RXD1
P74/TA1IN/TA4OUT/TXD1
P73/TA0IN/TA3OUT
P72/TB2IN
P71/TB1IN
P70/TB0IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P67/FLD7
P66/FLD6
P65/FLD5
P64/FLD4
P63/FLD3
P62/FLD2
P61/FLD1
P60/FLD0
VEE
P107/AN7
P106/AN6
P105/AN5
P104/AN4
P103/AN3
P102/AN2
P101/AN1
AVSS
P100/AN0
VR E F
AVCC
P77/TA4IN/TA2OUT/CTS1/RTS1/CLKS1
P97/DA0/CLKOUT/DIMOUT
P96/DA1/SCLK22
P95/SCLK21
P94/SOUT2
P93/SIN2
P92/SSTB2
P91/SBUSY2
P90/SRDY2
CNVSS
P87/XCIN
P86/XCOUT
RESET
XOUT
VSS
XIN
VC C
P85/INT5
P84/INT4
P83/INT3
P82/INT2
P81/INT1
P80/INT0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P50/FLD8
P51/FLD9
P52/FLD10
P53/FLD11
P54/FLD12
P55/FLD13
P56/FLD14
P57/FLD15
P00/FLD16
P01/FLD17
P02/FLD18
P03/FLD19
P04/FLD20
P05/FLD21
P06/FLD22
VS S
P07/FLD23
VC C
P10/FLD24
P11/FLD25
P12/FLD26
P13/FLD27
P14/FLD28
P15/FLD29
P16/FLD30
P17/FLD31
P20/FLD32
P21/FLD33
P22/FLD34
P23/FLD35
Mitsubishi microcomputers
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30218 Group
Pin Configuration
Figure 1 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
M30218MC-AXXXFP
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P24/FLD36
P25/FLD37
P26/FLD38
P27/FLD39
P30/FLD40
P31/FLD41
P32/FLD42
P33/FLD43
P34/FLD44
P35/FLD45
P36/FLD46
P37/FLD47
P40/FLD48
P41/FLD49
P42/FLD50
P43/FLD51
P44/TXD0/FLD52
P45/RXD0/FLD53
P46/CLK0/FLD54
P47/CTS0/RTS0/FLD55
Mitsubishi microcomputers
M30218 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block Diagram
Figure 2 shows a block diagram of the M30218 group.
Block diagram of the M30218 group
I/O ports
Port P0
8
8
8
Port P1
8
8
Port P2
Port P3
Port P4
(10 bits
X
8 channels)
Serial I/O
CRC arithmetic circuit (CCITT)
(Polynomial : X16+X12+X5+1)
UART/clock synchronous SI/O
(8 bits
X
2 channels)
Fluorescent display function
(56 contorol pins)
SI/O2 (clock synchronous)
(256 bytes automatic transfer)
(15 bits)
D-A converter
(8 bits X 2 channels)
PC
Vector table
INTB
Stack pointer
ISP
USP
SB
FLG
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Figure 2. Block diagram of M30218 group
4
ROM
(Note 1)
RAM (Note 2)
(includes FLDC,ASI/O RAM)
Multiplier
8
(2 channels)
R0H
R0L
R0H
R0L
R1
R1L
R1H
R1L
R
H
R2
R
2
R3
A0
3
A0
A1
A1
FB
FB
Memory
Port P10
DMAC
Program counter
8
Watchdog timer
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAA
AAAA
(52 high-breakdown-voltage ports)
M16C/60 series16-bit CPU core
Registers
8
bits)
bits)
bits)
bits)
bits)
bits)
bits)
bits)
8
(16
(16
(16
(16
(16
(16
(16
(16
Port P9
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
Port P8
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Port P6
System clock generator
XIN-XOUT
XCIN-XCOUT
A-D converter
Timer
Port P5
Port P7
Internal peripheral functions
8
8
Mitsubishi microcomputers
M30218 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Performance Outline
Table 1 shows a performance outline of M30218 group.
Table 1. Performance outline of M30218 group
Item
Number of basic instructions
Shortest instruction execution time
Memory
ROM
capacity
RAM
I/O port
P3, P4, P7 to P10
Output port
P0 to P2, P5, P6
Multifunction TA0, TA1, TA2, TA3, TA4
timer
TB0, TB1, TB2
Serial I/O
UART0, UART1
SI/O2
Fluorescent display
A-D converter
D-A converter
DMAC
CRC calculation circuit
Watchdog timer
Interrupt
Clock generating circuit
Supply voltage
Power consumption
I/O withstand voltage
I/O
characteristics
Output current
H
L
Operating ambient temperature
Device configuration
Package
Performance
91 instructions
100ns(f(XIN)=10MHz)
See figure memory expansion
See figure memory expansion
8 bits x 6
8 bit x 5
16 bits x 5
16 bits x 3
(UART or clock synchronous) x 2
(Clock synchronous) x 1 (with automatic transfer function)
56 pins
10 bits x 8 channels
8 bits x 2
2 channels (triggers :15 sources)
1 circuit (polynomial: X16 + X12 + X5 + 1)
15 bits x 1 (with prescaler)
19 internal and 6 external sources, 4 software sources, 7 levels
2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
4.0 to 5.5V (f(XIN)=10MHz)
2.7 to 5.5V (f(XIN)=3.5MHz) (Note)
18 mW (VCC=3V, f(XIN)=5MHz)
VCC-48V (output ports : P0 to P2, P5, P6, I/O ports : P3, P40 to P43)
0 to VCC (I/O ports :P44 to P47, P7 to P10)
- 18mA (P0 to P3, P40 to P43, P5, P6)
:high-breakdown-voltage, P-channel open-drain
- 5mA (P44 to P47, P7 to P10)
5mA (P44 to P47, P7 to P10)
–20 to 85oC
CMOS silicon gate
100-pin plastic mold QFP
Note: Only mask ROM version.
5
Mitsubishi microcomputers
M30218 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi plans to release the following products in the M30218 group:
(1) Support for mask ROM version and flash memory version
(2) Memory capacity
(3) Package
100P6S
: Plastic molded QFP (mask ROM version and flash memory version)
RAM size
(Byte)
M30218MC-AXXXFP
M30218FCFP
12K
5K
M30217MA-AXXXFP
1K
512
96K
128K
ROM size
(Byte)
Figure 3. ROM expansion
Type No.
M30218 M C – AXXX FP
Package type:
FP : Package
100P6S-A
ROM No.
Omitted for flash memory version
ROM capacity:
2 : 16K bytes
4 : 32K bytes
6 : 48K bytes
8 : 64K bytes
A : 96K bytes
C : 128K bytes
Memory type:
M : Mask ROM version
F : Flash memory version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/21 Group
M16C Family
Figure 4. Type No., memory size, and package
6
Mitsubishi microcomputers
M30218 Group
Pin Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin name
Signal name
Function
I/O type
Supply 2.7V(Note1) to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
Connect a bypass capacitor across the VCC pin and VSS pin.
VCC, VSS
Power supply
input
CNVSS
CNVSS
Input
Connect it to the VSS pin.
RESET
Reset input
Input
A “L” on this input resets the microcomputer.
XIN
Clock input
Input
XOUT
Clock output
Output
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the XIN and the XOUT pins. To
use an externally derived clock, input it to the XIN pin and leave the
XOUT pin open.
AVCC
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VCC.
AVSS
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VSS.
VREF
Reference
voltage input
VEE
pull-down
power source
P00/FLD16 to
P07/FLD23
Output port P0
Output
This is an 8-bit CMOS output port and high-breakdown-voltage Pchannel open-drain output structure. A pull-down resistor is built in
between port P0 and VEE pin. At reset, this port is set to VEE level. P0
function as FLD controller output pins as selected by software.
P10/FLD24 to
P17/FLD31
Output port P1
Output
This is an 8-bit output port equivalent to P0. Pins in this port also
function as FLD controller output pins as selected by software.
P20/FLD32 to
P27/FLD39
Output port P2
Output
This is an 8-bit output port equivalent to P0. A pull-down resistor is not
built in between P2 and VEE pin. Pins in this port also function as FLD
controller output pins as selected by software.
P30/FLD40 to
P37/FLD47
I/O port P3
Input/output
This is an 8-bit I/O port. A pull-down resistor is not built in between P3
and VEE pin. It has an input/output port direction register that allows the
user to set each pin for input or output. This is low-voltage input level,
and high-breakdown-voltage P-channel open-drain output structure.
Pins in this port also function as FLD controller output pins as selected
by software.
P40/FLD48 to
P47/FLD56
I/O port P4
Input/output
This is an 8-bit I/O port equivalent to P3. This is low-voltage input level.
P40 to P43 is high-breakdown-voltage P-channel open-drain output
structure, P44 to P47 is CMOS output. A pull-down resistor is not built
in between P4(P40 to P43) and VEE pin. Pins in this port also function
as FLD controller output pins as selected by software. P44 to P47 also
function as UART0 I/O pins as selected by software. When set for
input, the user can specify in units of four bits by software whether or
not they are tied to a pull-up resistor.
P50/FLD8 to
P57/FLD15
Output port P5
Output
This is an 8-bit output port equivalent to P0. Pins in this port also
function as FLD controller output pins as selected by software.
P60/FLD0 to
P67/FLD7
Output port P6
Output
This is an 8-bit output port equivalent to P0. Pins in this port also
function as FLD controller output pins as selected by software.
Input
This pin is a reference voltage input for the A-D converter.
Apply voltage supplied to pull-down resistors of ports P0 to P1,P5,P6.
7
Mitsubishi microcomputers
M30218 Group
Pin Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin name
Signal name
I/O type
Function
P70 to P77
I/O port P7
Input/output
This is an 8-bit I/O port equivalent to P3. This is CMOS input/output.
When set for input, the user can specify in units of four bits by software
whether or not they are tied to a pull-up resistor. P70 to P72 function as
TimerB0 to B2 input pins as selected by software. P73 function as
TimerA0 I/O pin as selected by software. P74 to P77 function as
TimerA1 to A4 I/O pins, and UART1 I/O pins as selected by software.
P80 to P87
I/O port P8
Input/output
This is an 8-bit I/O port equivalent to P7. When set for input, the user
can specify in units of four bits by software whether or not they are tied
to a pull-up resistor. P80 to P85 function as external interrupt input pins
as selected by software. P86,P87 function as sub-clock input pin as
selected by software. In this case, connect a quarts oscillator between
P86(XOUT pin) and P87(XCIN pin)
P90 to P97
I/O port P9
Input/output
This is an 8-bit I/O port equivalent to P7. When set for input, the user
can specify in units of four bits by software whether or not they are tied
to a pull-up resistor. P97 function as D-A converter output pins, clock
output pins (same frequency of XIN/8, XIN/32 or XCIN) and DIM signal
output pin of FLD controller as selected by software. P96 function as DA converter output pins and clock I/O pin of serial I/O with automatic
transfer as selected by software. P90 to P95 function as I/O pin of serial
I/O with automatic transfer as selected by software.
P100 to P107
I/O port P10
Input/output
This is an 8-bit I/O port equivalent to P7. When set for input, the user
can specify in units of four bits by software whether or not they are tied
to a pull-up resistor. Pins in this port also function as A-D converter
input pins as selected by software.
Note 1: Supply 4.0V to 5.5V to the VCC pin in flash memory version.
8
Mitsubishi microcomputers
M30218 Group
Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Operation of Functional Blocks
The M30218 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, FLD controller, serial I/O, D-A converter, DMAC, CRC
calculation circuit, A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 5 is a memory map of the M30218 group. The address space extends the 1M bytes from address
00000 16 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30218MC-AXXXFP, there is
128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as the
reset are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The
address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB).
See the section on interrupts for details.
From 0040016 up is RAM. For example, in the M30218MC-AXXXFP, there is 12K bytes of internal RAM
from 0040016 to 033FF 16. In addition to storing data, the RAM also stores the stack used when calling
subroutines and when interrupts are generated. (From 0040016 to 004FF16 is RAM for SIO2. From 0050016
to 005DF16 is RAM for FLD.)
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not
occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
0000016
SFR area
(For details, see
Figures 6 and 7)
FFE0016
0040016
RAM area for SI/O2
0050016
RAM area for FLD
(224 bytes)
Special page
vector table
005E016
Internal RAM area
FFFDC16
YYYYY16
Undefined instruction
Overflow
Type No.
Address
XXXXX16
M30218MC
M30218FC
E000016
033FF16
M30217MA
E800016
017FF16
BRK instruction
Address match
Single step
Watchdog timer
DBC
Address
YYYYY16
XXXXX16
Internal ROM area
FFFFF16
FFFFF16
Figure 5. Memory map
9
Reset
Mitsubishi microcomputers
M30218 Group
Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
000016
004016
000116
004116
000216
004216
004316
000316
000416
000516
000616
000716
004416
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
004516
004616
004716
004816
000816
000916
000A16
004916
Address match interrupt enable register (AIER)
Protect register (PRCR)
004A16
000B16
004B16
000C16
004C16
000F16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
001016
001116
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
004D16
000D16
000E16
INT3 interrupt control register (INT3IC)
INT4 interrupt control register (INT4IC)
INT5 interrupt control register (INT5IC)
Address match interrupt register 0 (RMAD0)
004E16
A-D conversion interrupt control register (ADIC)
004F16
SI/O automatic transfer interrupt control register (ASIOIC)
005016
FLD interrupt control register (FLDIC)
005116
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
001216
005216
001316
005316
005416
001416
001F16
005F16
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
INT2 interrupt control register (INT2IC)
002016
034016
Serial I/O2 automatic transfer data pointer (SIO2DP)
001516
005516
Address match interrupt register 1 (RMAD1)
001616
005616
001716
005716
001816
005816
001916
005916
001A16
005A16
001B16
005B16
001C16
005C16
001D16
005D16
001E16
005E16
002116
DMA0 source pointer (SAR0)
034116
002216
034216
002316
034316
002416
002516
034416
DMA0 destination pointer (DAR0)
034616
002716
034716
DMA0 transfer counter (TCR0)
034816
002916
034916
002A16
034A16
002B16
002C16
034D16
034E16
002F16
034F16
003016
035016
DMA1 source pointer (SAR1)
035116
003216
035216
003316
035316
003416
035416
DMA1 destination pointer (DAR1)
035616
003716
035716
003916
035816
DMA1 transfer counter (TCR1)
035916
003A16
035A16
003B16
003C16
FLD mode register (FLDM)
FLD output control register (FLDCON)
Tdisp time set register (TDISP)
Toff1 time set register (TOFF1)
035516
003616
003816
Serial I/O2 control register 3 (SIO2CON3)
034C16
002E16
003516
Serial I/O2 register / transfer counter (SIO2)
034B16
DMA0 control register (DM0CON)
002D16
003116
Serial I/O2 control register 2 (SIO2CON2)
034516
002616
002816
Serial I/O2 control register 1 (SIO2CON1)
035B16
DMA1 control register (DM1CON)
035C16
003D16
035D16
003E16
035E16
003F16
035F16
Figure 6. Location of peripheral unit control registers (1)
10
Toff2 time set register (TOFF2)
FLD data pointer (FLDDP)
P2 FLD/port switch register (P2FPR)
P3 FLD/port switch register (P3FPR)
P4 FLD/port switch register (P4FPR)
P5 digit output set register (P5DOR)
P6 digit output set register (P6DOR)
Mitsubishi microcomputers
M30218 Group
Memory
038016
038116
038216
038316
038416
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Count start flag (TABSR)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
03C016
03C116
03C216
03C316
03C416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
03C516
03C616
Timer A0 (TA0)
03C716
03C816
Timer A1 (TA1)
03C916
03CA16
Timer A2 (TA2)
03CB16
03CC16
Timer A3 (TA3)
03CD16
03CE16
Timer A4 (TA4)
03CF16
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03D416
03D616
03D716
03D816
03DA16
03DC16
D-A register 1 (DA1)
D-A control register (DACON)
03DF16
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
03E016
03E116
Port P0 (P0)
Port P1 (P1)
03E216
UART0 transmit buffer register (U0TB)
03E316
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
03E416
03E516
Port P2 (P2)
Port P3 (P3)
03E616
UART0 receive buffer register (U0RB)
03E716
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
03E816
03E916
03EA16
UART1 transmit buffer register (U1TB)
Port P3 direction register (PD3)
Port P4 (P4)
Port P5 (P5)
Port P4 direction register (PD4)
03EB16
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
03EC16
03ED16
Port P6 (P6)
Port P7 (P7)
03EE16
03EF16
03F016
03F216
03F316
03B316
Flash memory control register 0 (FCON0) (Note)
Flash memory control register 1 (FCON1) (Note)
Flash command register (FCMD) (Note)
03F416
Port P7 direction register (PD7)
Port P8 (P8)
Port P9 (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 (P10)
03F516
03F616
Port P10 direction register (PD10)
03F716
03B716
DMA0 request cause select register (DM0SL)
03F816
03F916
03B916
DMA1 request cause select register (DM1SL)
03FA16
03FB16
03BB16
03BE16
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
03DD16
03F116
03BD16
A-D control register 2 (ADCON2)
03DB16
03B216
03BC16
A-D register 7 (AD7)
03D916
03B116
03BA16
A-D register 6 (AD6)
03DE16
UART transmit/receive control register 2 (UCON)
03B816
A-D register 5 (AD5)
03D516
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
03B016
03B616
A-D register 4 (AD4)
03D316
Timer B2 (TB2)
UART1 receive buffer register (U1RB)
03B516
A-D register 3 (AD3)
03D216
Timer B1 (TB1)
03AF16
03B416
A-D register 2 (AD2)
03D116
039F16
03A116
A-D register 1 (AD1)
03D016
Timer B0 (TB0)
039E16
03A016
A-D register 0 (AD0)
03FC16
CRC data register (CRCD)
03FD16
CRC input register (CRCIN)
03FE16
03FF16
03BF16
Note: This register is only exist in flash memory version.
Figure 7. Location of peripheral unit control registers (2)
11
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Mitsubishi microcomputers
M30218 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 8. Seven of these registers (R0, R1, R2, R3, A0, A1,
and FB) come in two sets; therefore, these have two register banks.
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AA
AAAAAA
AA
AA
AA
A
AA
AA
A
AA
AA
AAAAAAAA
AAAAAA
AAAAA
A
b15
R0(Note)
b8 b7
b15
R1(Note)
R2(Note)
Data
registers
b19
b15
b0
b0
Address
registers
U
Static base
register
b0
FLG
IPL
Interrupt stack
pointer
b0
b15
Frame base
registers
User stack pointer
b0
b15
b0
Interrupt table
register
b0
b15
b0
Program counter
b0
L
H
SB
b15
FB(Note)
b0
ISP
b15
A1(Note)
b0
PC
USP
b15
A0(Note)
b19
b0
L
INTB
b15
R3(Note)
b8 b7
H
b15
b0
L
H
Flag register
I O B S Z D C
Note: These registers consist of two register banks.
Figure 8. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H, R1H),
and low-order bits as (R0L, R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0, R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
12
Mitsubishi microcomputers
M30218 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure CA-2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
13
Mitsubishi microcomputers
M30218 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
b15
b0
IPL
U
I O B S Z D C
Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 9. Flag register (FLG)
14
Mitsubishi microcomputers
M30218 Group
Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 10 shows the example reset circuit. Figure 11 shows the reset sequence.
5V
4.0V
VCC
0V
VCC
RESET
5V
RESET
0.8V
0V
Example when f(XIN) = 10MHz and VCC = 5V.
Figure 10. Example reset circuit
XIN
More than 20 cycles are needed
RESET
BCLK
24cycles
BCLK
(Internal clock)
Content of reset vector
Address
FFFFC16
(Internal address
signal)
Figure 11. Reset sequence
15
FFFFE16
Mitsubishi microcomputers
M30218 Group
Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Processor mode register 0
(000416)···
0 0 0 0
(24) Timer A0 interrupt control register
(005516)···
? 0 0 0
(005616)···
? 0 0 0
(2) Processor mode register 1
(000516)··· 0
0 0
(25) Timer A1 interrupt control register
(3) System clock control register 0
(000616)··· 0 1 0 0 1 0 0 0
(26) Timer A2 interrupt control register
(005716)···
? 0 0 0
(4) System clock control register 1
(000716)··· 0 0 1 0 0 0 0 0
(27) Timer A3 interrupt control register
(005816)···
? 0 0 0
(5) Address match interrupt enable register
(000916)···
0 0
(28) Timer A4 interrupt control register
(005916)···
? 0 0 0
(6) Protect register
(000A16)···
0 0 0
(29) Timer B0 interrupt control register
(005A16)···
? 0 0 0
(7) Watchdog timer control register
(000F16)··· 0 0 0 ? ? ? ? ?
(30) Timer B1 interrupt control register
(005B16)···
? 0 0 0
(8) Address match interrupt register 0
(001016)···
0016
(31) Timer B2 interrupt control register
(005C16)···
? 0 0 0
0016
(32) INT0 interrupt control register
(005D16)···
0 0 ? 0 0 0
(33) INT1 interrupt control register
(005E16)···
0 0 ? 0 0 0
(005F16)···
0 0 ? 0 0 0
(001116)···
(001216)···
0 0 0 0
(001416)···
0016
(34) INT2 interrupt control register
(001516)···
0016
(35) Serial I/O 2 control register 1
(034216)···
0016
0 0 0 0
(36) Serial I/O 2 control register 2
(034416)···
0016
(10) DMA0 control register
(002C16)··· 0 0 0 0 0 ? 0 0
(37) Serial I/O 2 control register 3
(034816)···
0016
(11) DMA1 control register
(003C16)··· 0 0 0 0 0 ? 0 0
(38) FLDC mode register
(035016)···
0016
(12) INT3 interrupt control register
(004416)···
0 0 ? 0 0 0
(39) FLD output control register
(035116)···
0016
(13) INT4 interrupt control register
(004816)···
0 0 ? 0 0 0
(40) Tdisp time set register
(035216)···
0016
(14) INT5 interrupt control register
(004916)···
0 0 ? 0 0 0
(41) Toff1 time set register
(035416)···
FF16
(15) DMA0 interrupt control register
(004B16)···
? 0 0 0
(42) Toff2 time set register
(035616)···
FF16
(16) DMA1 interrupt control register
(004C16)···
? 0 0 0
(43) P2 FLD/port switch register
(035916)···
0016
(035A16)···
0016
(9) Address match interrupt register 1
(001616)···
(17) A-D conversion interrupt control register
(004E16)···
? 0 0 0
(44) P3 FLD/port switch register
(18) SI/O automatic transfer interrupt
control register
(19) FLD interrupt control register
(004F16)···
? 0 0 0
(45) P4 FLD/port switch register
(035B16)···
0016
(005016)···
? 0 0 0
(46) P5 digit output set register
(035C16)···
0016
(20)UART0 transmit interrupt control register
(005116)···
? 0 0 0
(47) P6 digit output set register
(035D16)···
0016
(21)UART0 receive interrupt control register
(005216)···
? 0 0 0
(22)UART1 transmit interrupt control register
(005316)···
? 0 0 0
(23)UART1 receive interrupt control register
(005416)···
? 0 0 0
The content of other registers and RAM is undefined when the microcomputer is reset.
The initial values must therefore be set.
x : Nothing is mapped to this bit
? : Undefined
Figure 12. Device's internal status after a reset is cleared
16
Mitsubishi microcomputers
M30218 Group
Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(48) Count start flag
(038016)···
0016
(77) Port P3 direction register
(03E716)···
0016
(49) Clock prescaler reset flag
(038116)··· 0
(78) Port P4 direction register
(03EA16)···
0016
(50) One-shot start flag
(038216)··· 0 0
0 0 0 0 0
(79) Port P7 direction register
(03EF16)···
0016
(51) Trigger select flag
(038316)···
0016
(80) Port P8 direction register
(03F216)···
0016
(52) Up-down flag
(038416)···
0016
(81) Port P9 direction register
(03F316)···
0016
(53) Timer A0 mode register
(039616)···
0016
(82) Port P10 direction register
(03F616)···
0016
(54) Timer A1 mode register
(039716)···
0016
(83) Pull-up control register 0
(03FD16)···
0016
(55) Timer A2 mode register
(039816)···
0016
(84) Pull-up control register 1
(03FE16)···
0016
000016
(56) Timer A3 mode register
(039916)···
0016
(85) Data registers (R0/R1/R2/R3)
(57) Timer A4 mode register
(039A16)···
0016
(86) Address registers (A0/A1)
000016
(58) Timer B0 mode register
(039B16)··· 0 0 ?
0 0 0 0
(87) Frame base register (FB)
000016
0000016
(59) Timer B1 mode register
(039C16)··· 0 0 ?
0 0 0 0
(88) Interrupt table register (INTB)
(60) Timer B2 mode register
(039D16)··· 0 0 ?
0 0 0 0
(89) User stack pointer (USP)
000016
(61) UART0 transmit/receive mode register
(03A016)···
(90) Interrupt stack pointer (ISP)
000016
(62) UART0 transmit/receive control register 0
(03A416)··· 0 0 0 0 1 0 0 0
(91) Static base register (SB)
000016
(63) UART0 transmit/receive control register 1
(03A516)··· 0 0 0 0 0 0 1 0
(92) Flag register (FLG)
000016
(64) UART1 transmit/receive mode register
(03A816)···
0016
0016
(65) UART1 transmit/receive control register 0 (03AC16)··· 0 0 0 0 1 0 0 0
(66) UART1 transmit/receive control register 1 (03AD16)··· 0 0 0 0 0 0 1 0
(67) UART transmit/receive control register 2
(03B016)···
Flash memory control register 0
(68)
(Note )
(69) Flash memory control register 1
(Note)
(70) Flash command register (Note)
(03B416)··· 0 0 1 0 0 0 0 0
0 0 0 0 0 0 0
0 0
(03B516)···
(03B616)···
0016
(71) DMA0 cause select register
(03B816)···
0016
(72) DMA1 cause select register
(03BA16)···
0016
(73) A-D control register 2
(03D416)···
(74) A-D control register 0
(03D616)··· 0 0 0 0 0 ? ? ?
(75) A-D control register 1
(03D716)···
0016
(76) D-A control register
(03DC16)···
0016
0
The content of other registers and RAM is undefined when the microcomputer is reset.
The initial values must therefore be set.
x : Nothing is mapped to this bit
? : Undefined
Note: This register is only exist in flash memory version.
Figure 13. Device's internal status after a reset is cleared
17
Mitsubishi microcomputers
M30218 Group
Software Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software reset) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
Figure 14 shows the processor mode register 0 and 1.
Processor mode register 0 (Note)
Symbol
PM0
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Address
000416
Bit symbol
Bit name
Function
Must always be set to “0”
Reserved bit
PM03
When reset
XXXX00002
Software reset bit
The device is reset when this bit
is set to “1”. The value of this bit
is “0” when read.
A
A
A
R W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Processor mode register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Symbol
PM1
Bit symbol
Address
000516
Bit name
When reset
00XXXXX02
Function
Must always be set to “0”
Reserved bit
A
A
R W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Must always be set to “0”
Reserved bit
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new values
to this register.
Figure 14. Processor mode register 0 and 1
18
Mitsubishi microcomputers
M30218 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 2. Main clock and sub clock generating circuits
Main clock generating circuit
Sub clock generating circuit
Use of clock
• CPU’s operating clock source
• CPU’s operating clock source
• Internal peripheral units’
• Timer A/B’s count clock
operating clock source
source
Usable oscillator
Ceramic or crystal oscillator
Crystal oscillator
Pins to connect oscillator
XIN, XOUT
XCIN, XCOUT
Oscillation stop/restart function
Available
Available
Oscillator status immediately after reset Oscillating
Stopped
Other
Externally derived clock can be input
Example of oscillator circuit
Figure 15 shows some examples of the main clock circuit, one using an oscillator connected to the circuit,
and the other one using an externally derived clock for input. Figure 16 shows some examples of sub clock
circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock
for input. Circuit constants in Figures 15 and 16 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XIN
XOUT
XIN
XOUT
Open
(Note)
Rd
Externally derived clock
CIN
Vcc
COUT
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 15. Examples of main clock
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XCIN
XCOUT
XCIN
XCOUT
Open
(Note)
RCd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN
and XCOUT following the instruction.
Figure 16. Examples of sub clock
19
Mitsubishi microcomputers
M30218 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Control
Figure 17 shows the block diagram of the clock generating circuit.
XCIN
XCOUT
fC32
1/32
f1
CM04
f1SIO2
fAD
fC
f8SIO2
Sub clock
CM10 “1”
Write signal
f8
S Q
XIN
XOUT
AAA
AAA
b
R
a
RESET
Software reset
CM05
Main clock
CM02
f32
c
Divider
d
CM07=0
fC
CM07=1
BCLK
Interrupt request
level judgment output
S Q
WAIT instruction
R
c
b
a
1/2
1/2
1/2
1/2
1/2
CM06=0
CM17,CM16=11
CM06=1
CM06=0
CM17,CM16=10
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WDCi : Bit i at address 000F16
d
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=00
Details of divider
Figure 17. Clock generating circuit
20
Mitsubishi microcomputers
M30218 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can
be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expansion and the microprocessor modes.
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from highspeed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock(f1, f8, f32, fAD, f1SIO2, f8SIO2)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
21
Mitsubishi microcomputers
M30218 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 18 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM0
Address
000616
Bit symbol
When reset
4816
Bit name
Function
b1 b0
AAAA
AA
AA
AAAAA
AA
AAAA
RW
Clock output function
select bit
(Valid only in single-chip
mode)
0 0 : I/O port P97/DA0
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
WAIT peripheral function
clock stop bit
XCIN-XCOUT drive capacity
select bit (Note 2)
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
0 : LOW
1 : HIGH
CM04
Port XC select bit
0 : I/O port
1 : XCIN-XCOUT generation
CM05
Main clock (XIN-XOUT)
stop bit (Note 3, 4, 5)
0 : On
1 : Off
CM06
Main clock division select
bit 0 (Note 7)
0 : CM16 and CM17 valid
1 : Division by 8 mode
CM07
System clock select bit
(Note 6)
0 : XIN, XOUT
1 : XCIN, XCOUT
CM00
CM01
CM02
CM03
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shiffing to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and
operating with XIN, set this bit to “0”. When main clock oscillation is operating by itself, set system clock select
bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns
pulled up to XOUT (“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the
main clock oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: fC32 is not included.
System clock control register 1 (Note 1)
b7
b6
b5
b4
b3
b2
b1
0 0
0
0
b0
Symbol
CM1
Address
000716
Bit symbol
CM10
When reset
2016
Bit name
Function
All clock stop control bit
(Note4)
0 : Clock on
1 : All clocks off (stop mode)
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
CM15
XIN-XOUT drive capacity
select bit (Note 2)
CM16
Main clock division
select bit 1 (Note 3)
0 : LOW
1 : HIGH
b7 b6
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
CM17
AAA
AAA
AA
AAAA
AAAA
AA
RW
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is
fixed at 8.
Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn highimpedance state.
Figure 18. Clock control registers 0 and 1
22
Mitsubishi microcomputers
M30218 Group
Clock Output
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Output
The clock output function select bit (bit 0,1 at address 000616) allows you to choose the clock from f8, f32, or
fc to be output from the P97/DA0/CLKOUT/DIMOUT pin. When the WAIT peripheral function clock stop bit
(bit 2 at address 000616) is set to “1”, the output of f8 and f32 stop by executing of WAIT instruction.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V.
Because the oscillation of BCLK, f1 to f32, fc, fC32, and fAD stops in stop mode, peripheral functions such as
the fluorescent display function, serial I/O 2, A-D converter and watchdog timer do not function. However,
timer A and timer B operate provided that the event counter mode is set to an external pulse, and UART0
and UART2 functions provided an external clock is selected. Table 3 shows the status of the ports in stop
mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
Table 3. Port status during stop mode
Pin
Port
CLKOUT
When fC selected
When f8, f32 selected
States
Retains status before stop mode
“H”
Retains status before stop mode
Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this mode,
oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock
stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions,
allowing power dissipation to be reduced. Table 4 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Table 4. Port status during wait mode
Pin
States
Port
Retains status before wait mode
CLKOUT
When fC selected
Does not stop
When f8, f32 selected
Does not stop when the WAIT
peripheral function clock stop bit is
“0”. (Note)
When the WAIT peripheral function clock
stop bit is “1”, the status immediately prior
to entering wait mode is maintained.
Note: Attention that reducing the power dissipation is impossible.
23
Mitsubishi microcomputers
M30218 Group
Status Transition of BCLK
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table WA-4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
Table 5. Operating modes dictated by settings of system clock control registers 0 and 1
CM17
0
1
Invalid
1
0
Invalid
Invalid
CM16
1
0
Invalid
1
0
Invalid
Invalid
CM07
0
0
0
0
0
1
1
CM06
0
0
1
0
0
Invalid
Invalid
CM05
0
0
0
0
0
0
1
CM04
Invalid
Invalid
Invalid
Invalid
Invalid
1
1
24
Operating mode of BCLK
Division by 2 mode
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
Low-speed mode
Low power dissipation mode
Mitsubishi microcomputers
M30218 Group
Power Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal
clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock.
• Low-speed mode
fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the
secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fC
clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate
are those with the sub-clock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 19 shows the state transition diagram of the above modes.
25
Mitsubishi microcomputers
M30218 Group
Power Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transition of stop mode, wait mode
Reset
All oscillators stopped
Stop mode
CM10 = “1”
Interrupt
All oscillators stopped
Stop mode
CM10 = “1”
Interrupt
CPU operation stopped
WAIT
instruction
High-speed/mediumspeed mode
Wait mode
Interrupt
All oscillators stopped
Stop mode
Wait mode
Interrupt
Interrupt
CM10 = “1”
CPU operation stopped
WAIT
instruction
Medium-speed mode
(divided-by-8 mode)
CPU operation stopped
WAIT
instruction
Low-speed/low power
dissipation mode
Wait mode
Interrupt
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
(divided-by-8 mode)
CM06 = “1”
BCLK : f(XIN)/8
CM07 = “0” CM06 = “1”
Main clock is oscillating CM04 = “0”
Sub clock is oscillating
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM04 = “1”
(Notes 1, 3)
High-speed mode
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-8 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/8
CM07 = “0”
CM06 = “1”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Main clock is oscillating
Sub clock is oscillating
Low-speed mode
CM07 = “0”
(Note 1, 3)
BCLK : f(XCIN)
CM07 = “1”
CM07 = “1”
(Note 2)
CM05 = “0”
CM04 = “0”
CM06 = “0”
(Notes 1,3)
Main clock is oscillating
Sub clock is stopped
CM05 = “1”
CM04 = “1”
High-speed mode
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Main clock is stopped
Sub clock is oscillating
Low power dissipation mode
CM07 = “1” (Note 2)
CM05 = “1”
CM07 = “1”
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
Figure 19. State transition diagram of Power control mode
26
BCLK : f(XCIN)
Mitsubishi microcomputers
M30218 Group
Protection
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 20 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), and system clock control register 1 (address 000716) can only be changed when
the respective bit in the protect register is set to “1”.
The system clock control registers 0 and 1 write-enable bit (bit 0 at address 000A16) and processor mode
register 0 and 1 write-enable bit (bit 1 at address 000A16) do not automatically return to “0” after a value has
been written to an address. The program must therefore be written to return these bits to “0”.
Protect register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PRCR
Address
000A16
When reset
XXXXX0002
Bit symbol
Bit name
PRC0
Enables writing to system clock
control registers 0 and 1 (addresses
000616 and 000716)
Function
PRC1
Enables writing to processor mode
0 : Write-inhibited
registers 0 and 1 (addresses 000416
1 : Write-enabled
and 000516)
0 : Write-inhibited
1 : Write-enabled
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Figure 20. Protect register
27
R W
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview of Interrupt
Type of Interrupts
Figure 21 shows the types of interrupts.
Hardware
Special
Peripheral I/O (Note)
Interrupt
Software
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
DBC
Watchdog timer
Single step
Address matched
________
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 21. Classification of interrupts
• Maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
28
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/
O interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
29
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
____________
Reset occurs if an “L” is input to the RESET pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• DMA0 interrupt, DMA1 interrupt
These are interrupts that DMA generates.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0 and UART1 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt
These are interrupts that the serial I/O reception generates.
• SI/O automatic transfer interrupt
This is an interrupt that the SI/O automatic transfer generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
• Timer B0 interrupt through timer B2 interrupt
These are interrupts that timer B generates.
________
________
• INT0 interrupt through INT5 interrupt
______
______
An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.
30
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 22 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
MSB
LSB
Vector address + 0
Low address
Vector address + 1
Mid address
Vector address + 2
0000
High address
Vector address + 3
0000
0000
Figure 22. Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 6 shows the interrupts assigned to the fixed vector tables
and addresses of vector tables.
Table 6. Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt source
Undefined instruction
Overflow
BRK instruction
Vector table addresses
Address (L) to address (H)
FFFDC16 to FFFDF16
FFFE016 to FFFE316
FFFE416 to FFFE716
Remarks
Interrupt on UND instruction
Interrupt on INTO instruction
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Address match
FFFE816 to FFFEB16
Single step (Note)
FFFEC16 to FFFEF16
Watchdog timer
FFFF016 to FFFF316
________
DBC (Note)
FFFF416 to FFFF716
Do not use
FFFF816 to FFFFB16
Reset
FFFFC16 to FFFFF16
Note: Interrupts used for debugging purposes only.
31
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 7 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
Table 7. Interrupts assigned to the variable vector tables and addresses of vector tables
Software interrupt number
Vector table address
Interrupt source
Remarks
Address (L) to address (H)
Software interrupt number 0
+0 to +3 (Note)
BRK instruction
Software interrupt number 7
+28 to +31 (Note)
INT3
Software interrupt number 8
+32 to +35 (Note)
INT4
Software interrupt number 9
+36 to +39 (Note)
INT5
Software interrupt number 11
+44 to +47 (Note)
DMA0
Software interrupt number 12
+48 to +51 (Note)
DMA1
Software interrupt number 14
+56 to +59 (Note)
A-D
Software interrupt number 15
+60 to +63 (Note)
SI/O automatic transfer
Software interrupt number 16
+64 to +67 (Note)
FLD
Software interrupt number 17
+68 to +71 (Note)
UART0 transmit
Software interrupt number 18
+72 to +75 (Note)
UART0 receive
Software interrupt number 19
+76 to +79 (Note)
UART1 transmit
Software interrupt number 20
+80 to +83 (Note)
UART1 receive
Software interrupt number 21
+84 to +87 (Note)
Timer A0
Software interrupt number 22
+88 to +91 (Note)
Timer A1
Software interrupt number 23
+92 to +95 (Note)
Timer A2
Software interrupt number 24
+96 to +99 (Note)
Timer A3
Software interrupt number 25
+100 to +103 (Note)
Timer A4
Software interrupt number 26
+104 to +107 (Note)
Timer B0
Software interrupt number 27
+108 to +111 (Note)
Timer B1
Software interrupt number 28
+112 to +115 (Note)
Timer B2
Software interrupt number 29
+116 to +119 (Note)
INT0
Software interrupt number 30
+120 to +123 (Note)
INT1
Software interrupt number 31
+124 to +127 (Note)
INT2
Software interrupt number 32
+128 to +131 (Note)
to
Software interrupt number 63
to
+252 to +255 (Note)
Software interrupt
Note : Address relative to address in interrupt table register (INTB).
32
Cannot be masked I flag
Cannot be masked I flag
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is
indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit
are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the
IPL are located in the flag register (FLG).
Figure 23 shows the memory map of the interrupt control registers.
33
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt control register(Note2)
AAA
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DMiIC(i=0, 1)
ADIC
ASIOIC
FLDIC
SiTIC(i=0, 1)
SiRIC(i=0, 1)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
Bit symbol
ILVL0
Address
004B16 to 004C16
004E16
004F16
005016
005116, 005316
005216, 005416
005516 to 005916
005A16 to 005C16
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
When reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Interrupt request bit
Function
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
AAA
A
AA
b7 b6 b5 b4 b3 b2 b1 b0
0
AA
A
A
A
A
AA
AA
R
W
(Note1)
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
Symbol
INTiIC(i=0 to 5)
Bit symbol
ILVL0
Address
005D16 to 005F16
004716 to 004916
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
POL
When reset
XX00X0002
Interrupt request bit
Polarity select bit
Function
b2 b1 b0
W
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
Reserved bit
AA
AA
AA
AA
AA
A
A
AA
R
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
(Note1)
Note1 : This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
Figure 23. Interrupt control registers
34
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 8 shows the settings of interrupt priority levels and Table 9 shows the interrupt levels enabled,
according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 9. Interrupt levels enabled according
to the contents of the IPL
Table 8. Settings of interrupt priority levels
Interrupt priority
level select bit
Interrupt priority
level
Priority
order
IPL
b2 b1 b0
Enabled interrupt priority levels
IPL2 IPL1 IPL0
0
0
0
Level 0 (interrupt disabled)
0
0
0
Interrupt levels 1 and above are enabled
0
0
1
Level 1
0
0
1
Interrupt levels 2 and above are enabled
0
1
0
Level 2
0
1
0
Interrupt levels 3 and above are enabled
0
1
1
Level 3
0
1
1
Interrupt levels 4 and above are enabled
1
0
0
Level 4
1
0
0
Interrupt levels 5 and above are enabled
1
0
1
Level 5
1
0
1
Interrupt levels 6 and above are enabled
1
1
0
Level 6
1
1
0
Interrupt levels 7 and above are enabled
1
1
1
Level 7
1
1
1
All maskable interrupts are disabled
Low
High
35
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
;
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
;
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is
to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to
effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
36
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 24 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
Instruction in
interrupt routine
Interrupt sequence
(a)
(b)
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 24. Interrupt response time
37
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction.
Time (b) is as shown in Table 10.
Table 10. Time required for executing the interrupt sequence
Interrupt vector address
Stack pointer (SP) value
16-Bit bust
8-Bit bus
Even
Even
18 cycles (Note 1)
20 cycles (Note 1)
Even
Odd
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Even
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Odd
20 cycles (Note 1)
20 cycles (Note 1)
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address
0000
Address bus
Interrupt
information
Data bus
R
Indeterminate
SP-2
SP-4
SP-2
contents
Indeterminate
SP-4
contents
vec
vec+2
vec
contents
PC
vec+2
contents
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 25. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 11 shows set in the IPL.
Table 11. Relationship between interrupts without interrupt priority levels and IPL
Value set in the IPL
Interrupt sources without priority levels
Watchdog timer
7
Reset
0
Not changed
Other
38
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 26 shows the state of the stack as it was before the acceptance of the interrupt
request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
MSB
Stack area
Address
MSB
LSB
Stack area
LSB
m–4
m–4
Program counter (PCL)
m–3
m–3
Program counter (PCM)
m–2
m–2
Flag register (FLGL)
m–1
m–1
m
Content of previous stack
m+1
Content of previous stack
[SP]
Stack pointer
value before
interrupt occurs
Stack status before interrupt request
is acknowledged
Flag register
(FLGH)
Program
counter (PCH)
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
Figure 26. State of stack before and after acceptance of interrupt request
39
[SP]
New stack
pointer value
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer, at the time of acceptance of an interrupt request, is even or oDD- If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 27 shows the operation of the saving registers.
Note: Stack pointer indicated by U flag.
(1) Stack pointer (SP) contains even number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Odd)
[SP] – 4 (Even)
Program counter (PCL)
[SP] – 3(Odd)
Program counter (PCM)
[SP] – 2 (Even)
Flag register (FLGL)
[SP] – 1(Odd)
[SP]
Flag register
(FLGH)
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Program
counter (PCH)
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
Program counter (PCL)
(3)
[SP] – 3 (Even)
Program counter (PCM)
(4)
[SP] – 2(Odd)
Flag register (FLGL)
[SP] – 1 (Even)
[SP]
Flag register
(FLGH)
Saved simultaneously,
all 8 bits
(1)
Program
counter (PCH)
(2)
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 27. Operation of saving registers
40
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter
(PC), both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware
priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 28 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
________
Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 28. Hardware interrupts priorities
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest
priority level. Figure 29 shows the circuit that judges the interrupt priority level.
41
Mitsubishi microcomputers
M30218 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Priority level of each interrupt
Level 0 (initial value)
INT1
Timer B2
High
Timer B0
Timer A3
Timer A1
INT4
INT2
INT0
Timer B1
Timer A4
Timer A2
INT5
Priority of peripheral I/O
interrupts
(if priority levels are same)
INT3
UART1 reception
UART0 reception
FLD
A-D conversion
DMA1
Timer A0
UART1 transmission
UART0 transmission
SI/O2 automatic transfer
DMA0
Low
Processor interrupt priority level
(IPL)
Interrupt request level judgment output
Interrupt
request
accepted
Interrupt enable flag (I flag)
Address match
Watchdog timer
DBC
Reset
Figure 29. Maskable interrupts priorities
42
Mitsubishi microcomputers
M30218 Group
Interrupt Match Interrupt
Address
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC)
for an address match interrupt varies depending on the instruction being executed.
Figure 30 shows the address match interrupt-related registers.
Address match interrupt enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER
Bit symbol
Address
000916
When reset
XXXXXX002
Bit name
Function
AIER0
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
Function
Address setting register for address match interrupt
When reset
X0000016
X0000016
Values that can be set R W
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Figure 30. Address match interrupt-related registers
43
Mitsubishi microcomputers
M30218 Group
Interrupt
Precautions for Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 0000 16. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
the stack pointer before accepting an interrupt.
(3) External interrupt
________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
________
through INT5 regardless of the CPU operation clock.
________
________
• When the polarity of the INT0 through INT5 pins is changed, the interrupt request bit is sometimes set to
“1”. After changing the polarity, set the interrupt request bit to “0”. Figure 31 shows the procedure for
______
changing the INT interrupt generate factor.
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
______
Figure 31. Switching condition of INT interrupt request
44
Mitsubishi microcomputers
M30218 Group
Interrupt
Precautions for Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
;
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
;
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is
to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to
effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
45
Mitsubishi microcomputers
M30218 Group
Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the
BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by
16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7
of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error due to the prescaler.
With XIN chosen for BCLK
Watchdog timer period =
prescaler dividing ratio (16 or 128) X watchdog timer count (32768)
BCLK
With XCIN chosen for BCLK
Watchdog timer period =
prescaler dividing ratio (2) X watchdog timer count (32768)
BCLK
For example, suppose that BCLK runs at 10 MHz and that 16 has been chosen for the dividing ratio of the
prescaler, then the watchdog timer's period becomes approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 32 shows the block diagram of the watchdog timer. Figure 33 shows the watchdog timer-related
registers.
Prescaler
1/16
BCLK
1/128
“CM07 = 0”
“WDC7 = 0”
“CM07 = 0”
“WDC7 = 1”
Watchdog timer
“CM07 = 1”
1/2
Write to the watchdog timer
start register
(address 000E16)
Set to
“7FFF16”
RESET
Figure 32. Block diagram of watchdog timer
46
Watchdog timer
interrupt request
Mitsubishi microcomputers
M30218 Group
Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog timer control register
b7
b6
b5
0
0
b4
b3
b2
b1
b0
Symbol
WDC
Bit symbol
Address
000F16
When reset
000XXXXX2
Bit name
Function
High-order bit of watchdog timer
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “0”
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
AA
AA
A
AA
A
AA
A
AA
A
R W
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of whatever value is written.
Figure 33. Watchdog timer control and start registers
47
R W
A
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 34 shows the block diagram of the
DMAC. Table 12 shows the DMAC specifications. Figure 35 to Figure 36 show the registers used by the
DMAC.
AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAA
A
A
A
AA
AA
AA
AA
AA
AAA AAAA
AA
AAAA
AA
AA
A
AA
AA
A
AA
AA AA
A
AA
AA
A
AA
AA
AAAAA AAAA
AA
AA AA
A
AA AAAA
AA
AA
AA
A
AA A
A
AAAAAA
AAAAAA A
AAAAAAA A
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016)
DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016)
(addresses 002916, 002816)
DMA0 transfer counter TCR0 (16)
DMA1 destination pointer DAR1 (20)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20) (Note)
(addresses 003616 to 003416)
(addresses 003916, 003816)
DMA latch high-order bits
DMA1 transfer counter TCR1 (16)
DMA latch low-order bits
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 34. Block diagram of DMAC
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA
transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
48
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 12. DMAC specifications
Item
Specification
No. of channels
2 (cycle steal method)
Transfer memory space
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
________ ________
________
DMA request factors (Note)
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1)
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transmission and reception interrupt requests
UART1 transmission and reception interrupt requests
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
Transfer unit
8 bits or 16 bits
Transfer address direction
forward or fixed (forward direction cannot be specified for both source
and destination simultaneously)
Transfer mode
• Single transfer mode
After the transfer counter underflows, the DMA enable bit turns to
“0”, and the DMAC turns inactive
• Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.
The DMAC remains active unless a “0” is written to the DMA enable bit.
DMA interrupt request generation timing When an underflow occurs in the transfer counter
Active
When the DMA enable bit is set to “1”, the DMAC is active.
When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.
Inactive
• When the DMA enable bit is set to “0”, the DMAC is inactive.
• After the transfer counter underflows in single transfer mode
At the time of starting data transfer immediately after turning the DMAC active, re
Forward address pointer and
the value of one of source pointer and destination pointer - the one specified for the
load timing for transfer
forward direction - is reloaded to the forward direction address pointer,and the value
counter
of the transfer counter reload register is reloaded to the transfer counter.
Writing to register
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Reading the register
Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable
flag (I flag) nor by the interrupt priority level.
49
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DMiSL(i=0,1)
When reset
0016
Bit name
Bit symbol
DSEL0
Address
03B816,03BA16
DMA request cause
select bit
DSEL1
DSEL2
DSEL3
Function
R
W
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT0 / INT1
pin (Note)
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4
0 1 1 1 : Timer B0
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART1 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : A-D conversion
1 1 1 1 : Inhibited
Nothing is assigned. In an attempt to write to these bits, write “0”.
The value, if read, turns out to be “0”.
Software DMA request bit If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
Note: Address 03B816 is for INT0; address 03BA16 is for INT1.
DSR
DMAi control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DMiCON(i=0,1)
Address
002C16, 003C16
When reset
00000X002
Bit symbol
Bit name
DMBIT
Transfer unit bit select bit
0 : 16 bits
1 : 8 bits
DMASL
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMAS
DMA request bit (Note 1)
0 : DMA not requested
1 : DMA requested
DMA enable bit
0 : Disabled
1 : Enabled
DSD
Source address direction
select bit (Note 3)
0 : Fixed
1 : Forward
DAD
Destination address
0 : Fixed
direction select bit (Note 3) 1 : Forward
DMAE
Function
R
W
(Note 2)
Nothing is assigned. In an attempt to write to these bits, write “0”.
The value, if read, turns out to be “0”.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
Figure 35. DMAC-related registers (1)
50
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi source pointer (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
When reset
Indeterminate
Indeterminate
AAA
A
AA
Transfer count
specification
Function
• Source pointer
Stores the source address
R W
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi destination pointer (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
• Destination pointer
Stores the destination address
AA
R W
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
Function
• Transfer counter
Set a value one less than the transfer count
Figure 36. DMAC-related registers (2)
51
When reset
Indeterminate
Indeterminate
Transfer count
specification
000016 to FFFF16
AA
R W
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
Figure 37 shows the example of the transfer cycles (a state of internal bus) for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different
conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source
read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember
to apply the respective conditions to both the destination write cycle and the source read cycle.
(1) 8-bit transfers
16-bit transfers and the source address is even.
BCLK
Address
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(2) 16-bit transfers and the source address is odd
BCLK
Address
bus
CPU use
Source
Source + 1 Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Source + 1 Destination
Dummy
cycle
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 37. Example of transfer cycles for a source read (the state of internal bus)
52
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) DMAC Transfer
Any combination of even or odd transfer read and write addresses is possible. Table 13 shows the number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 13. No. of DMAC transfer cycles
Transfer unit
Access address
8-bit transfers
(DMBIT="1")
16-bit transfers
(DMBIT="0")
Even
Odd
Even
Odd
singelchip mode
No. of
No. of
read cycles
write cycles
1
1
1
1
1
1
2
2
Coefficient j, k
Internal memory
Internal ROM/RAM
SFR area
1
2
53
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FLD Controller
The M30218 group has fluorescent display (FLD) drive and control circuits.
Table 14 shows the FLD controller specifications.
Table 14. FLD controller specifications
Specification
•
52
pins
(
20
pins
can
switch
general
purpose port)
High-breakdown-volt-
Item
FLD
controller age output port
CMOS port
port
Display pixel number
Period
Dimmer time
Interrupt
Key-scan
Expand function
• 4 pins ( 4 pins can switch general purpose port)
(A driver must be installed externally)
• Used FLD output
28 segment X 28 digit (segment number + digit number ≤ 56)
• Used digit output
40 segment X 16 digit (segment number ≤ 40, digit number ≤ 16)
• Connected to M35501
56 segment X (connect number of M35501) digit
(segment number ≤ 56, digit number ≤ number of M35501 X 16)
• Used P44 to P47 expansion
52 segment X 16 digit (segment number ≤ 52, digit number ≤ 16)
• 3.2 µs to 819.2 µs (count source XIN/32,10MHz)
• 12.8 µs to 3276.8 µs (count source XIN/128,10MHz)
• 3.2 µs to 819.2 µs (count source XIN/32,10MHz)
• 12.8 µs to 3276.8 µs (count source XIN/128,10MHz)
• Digit interrupt
• FLD blanking interrupt
• Key-scan used digit
• Key-scan used segment
• Digit pulse output function
This function automatically outputs digit pulse.
• M35501 connect function
The number of digits can be increased easily by using the output of
DIMOUT(P97) as CLK for the M35501.
• Toff section generate / not generate function
This function does not generate Toff1 section when the connected outputs
are the same.
• Gradation display function
This function allows each segment to be set for dark or bright display.
• P44 to P47 expansion function
This function provides 16 lines of digit outputs from four ports by attaching a
4
16 decoder.
54
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Main
data bus
Main address bus
Local
data bus
FLD automatic display RAM
050016
Local address bus
P50/FLD8
P51/FLD9
P52/FLD10
P53/FLD11
P54/FLD12
P55/FLD13
P56/FLD14
P57/FLD15
03E916
05DF16
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD 8
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
035C16
P00/FLD16
P01/FLD17
P02/FLD18
P03/FLD19 8
P04/FLD20
P05/FLD21
P06/FLD22
P07/FLD23
03E016
P10/FLD24
P11/FLD25
P12/FLD26
P13/FLD27 8
P14/FLD28
P15/FLD29
P16/FLD30
P17/FLD31
03E116
P20/FLD32
P21/FLD33
P22/FLD34
8
P23/FLD35
P24/FLD36
P25/FLD37
P26/FLD38
P27/FLD39
03E416
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
035916
FLD/P P30/FLD40
FLD/P P31/FLD41
FLD/P P32/FLD42
8
FLD/P P33/FLD43
FLD/P P34/FLD44
FLD/P P35/FLD45
FLD/P P36/FLD46
FLD/P P37/FLD47
03E516
035A16
FLD/P P40/FLD48
FLD/P P41/FLD49
FLD/P P42/FLD50
8
FLD/P P43/FLD51
FLD/P P44/FLD52
FLD/P P45/FLD53
FLD/P P46/FLD54
FLD/P P47/FLD55
03E816
035B16
FLD/port switch register
FLDC mode register
(035016)
FLD data pointer
reload register
(035816)
Address
decoder
Digit output set register
P60/FLD0 DIG/FLD
P61/FLD1 DIG/FLD
P62/FLD2 DIG/FLD
8
P63/FLD3 DIG/FLD
P64/FLD4 DIG/FLD
P65/FLD5 DIG/FLD
P66/FLD6 DIG/FLD
P67/FLD7 DIG/FLD
03EC16
035D16
FLD data pointer
(035816)
FLD blanking interrupt
Timing generator
FLD digit interrupt
Figure 38. Block Diagram for FLD Control Circuit
55
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FLDC mode register
b7
b6
b5
b4
b3
b2
b1
Symbol
FLDM
b0
Address
035016
Bit symbol
When reset
0016
Bit name
Function
FLDM0
Automatic display
control bit
0 : General-purpose mode
1 : Automatic display mode
FLDM1
Display start bit
0 : Stop display
1 : Display
(start to display by switching “0” to “1”)
FLDM2
Tscan control bits
b3b2
00 : FLD digit interrupt
(at rising edge of each digit)
FLD blanking
01 : 1 X Tdisp
interrupt (at falling
10 : 2 X Tdisp
edge of last digit)
11 : 3 X Tdisp
}
FLDM3
Timing number control bit
0 : 16 timing mode
1 : 32 timing mode
FLDM5
Gradation display mode
selection control bit
0 : Not selecting
1 : Selecting (Note )
FLDM6
Tdisp counter
count source selection bit
0 : f(XIN)/32
1 : f(XIN)/128
FLDM4
High-breakdown voltage
port drivability select bit
AA
A
AA
A
AA
AA
A
A
A
AA
A
AA
A
AA
A
AA
A
A
AA
RW
0 : Drivability strong
1 : Drivability weak
Note : When a gradation display mode is selected, a number of timing is max. 16 timing.
(Set the timing number control bit to “0”.)
FLDM7
FLD output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FLDCON
Bit symbol
Address
035116
When reset
0016
Bit name
Function
0 : Output normally
FLDCON0 P44 to P47 FLD
output reverse bit
1 : Reverse output
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
P44 to P47 FLD
0 : Perform normally
Toff is invalid bit
1 : Toff is invalid
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
P97 dimmer output
0 : Output normally
FLDCON4
control bit
1 : Dimmer output
0 : section of Toff does NOT generate
FLDCON5 CMOS ports: section of
1 : section of Toff generates
Toff generate/not
generate bit
FLDCON6 High-breakdown-voltage ports: 0 : section of Toff does NOT generate
section of Toff
1 : section of Toff generates
generate/not generate bit
FLDCON2
FLDCON7
Toff2
SET/RESET change bit
AA
AA
A
A
A
A
AA
AA
RW
0 : gradation display data is reset at Toff2
(set at Toff1)
1 : gradation display data is set at Toff2
(reset at Toff1)
Tdisp time set register
b7
b0
Symbol
TDISP
Address
035216
When reset
0016
Function
Counts Tdisp time. Count source is selected by Tdisp
counter count source select bit.
Figure 39. FLDC-related Register(1)
56
AA
A
A
AA
Values that can be set R W
016 to FF16
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Toff1 time set register
b7
b0
Symbol
Address
When reset
TOFF1
035416
FF16
AA
Values that can be set R W
Function
Counts Toff1 time. Count source is selected by Tdisp counter count source
select bit.
3 to FF16
Toff2 time set register
b7
b0
Symbol
Address
When reset
TOFF2
035616
FF16
AAA
A
AA
Values that can be set R W
Function
Counts Toff2 time. Count source is selected by Tdisp counter count source
select bit.
3 to FF16
FLD data pointer
b7
b0
Symbol
Address
When reset
FLDDP
035816
indeterminate
Values that can be set R W
Function
Counts FLD output timing. Set this register to “FLD output data - 1 ”.
1 to 1F16
Note: Reading the FLD data pointer takes out the count at that moment.
AA
Port P2 FLD / port switch register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
P2FPR
035916
0016
Bit symbol
P2FPR0
P2FPR1
Bit name
Function
Port P20 FLD/port switch bit
Port P21 FLD/port switch bit
0 : Normal port
1 : FLD output port
0 : Normal port
1 : FLD output port
P2FPR2
Port P22 FLD/port switch bit
0 : Normal port
1 : FLD output port
P2FPR3
Port P23 FLD/port switch bit
0 : Normal port
1 : FLD output port
P2FPR4
Port P24 FLD/port switch bit
0 : Normal port
1 : FLD output port
P2FPR5
Port P25 FLD/port switch bit
0 : Normal port
1 : FLD output port
P2FPR6
Port P26 FLD/port switch bit
0 : Normal port
1 : FLD output port
P2FPR7
Port P27 FLD/port switch bit
0 : Normal port
1 : FLD output port
Figure 40. FLDC-related Register(2)
57
AAAA
AAAA
AAA
AA
AAA
AAA
AA
RW
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port P3 FLD / port switch register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
P3FPR
035A16
0016
Bit symbol
Bit name
Function
Port P30 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR1
Port P31 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR2
Port P32 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR3
Port P33 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR4
Port P34 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR5
Port P35 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR6
Port P36 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR7
Port P37 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR0
AA
AAAA
AA
AA
AA
AAAA
AA
AA
RW
Port P4 FLD / port switch register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
P4FPR
035B16
0016
Bit symbol
Bit name
Function
P4FPR0
Port P40 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR1
Port P41 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR2
Port P42 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR3
Port P43 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR4
Port P44 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR5
Port P45 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR6
Port P46 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR7
Port P47 FLD/port switch bit
0 : Normal port
1 : FLD output port
AA
AAAA
AA
AA
AA
AA
AAAA
AA
RW
Port P5 digit output set register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
P5DOR
035C16
0016
Bit symbol
Bit name
Function
P5DOR0
Port P50 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR1
Port P51 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR2
Port P52 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR3
Port P53 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR4
Port P54 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR5
Port P55 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR6
Port P56 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR7
Port P57 FLD/digit switch bit
0 : FLD output
1 : Digit output
Figure 41. FLDC-related Register(3)
58
AA
AA
AAAA
AA
AA
AA
AAAA
AA
RW
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port P6 digit output set register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
P6DOR
035D16
0016
Bit symbol
Bit name
Function
P6DOR0
Port P60 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR1
Port P61 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR2
Port P62 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR3
Port P63 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR4
Port P64 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR5
Port P65 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR6
Port P66 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR7
Port P67 FLD/digit switch bit
0 : FLD output
1 : Digit output
Figure 42. FLDC-related Register(4)
59
AA
AA
AA
AA
AA
AAAA
AAAA
RW
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FLD automatic display pins
P0 to P6 are the pins capable of automatic display output for the FLD. The FLD start operating by setting
the automatic display control bit (bit 0 at address 035016) to “1”. There is the FLD output function that
outputs RAM contents from the port every timing or the digit output function that drives the port high with
digit timing. The FLD can be displayed using the FLD output for the segments and the digit or FLD output for
the digits. When using the FLD output for the digits, be sure to write digit display patterns to the RAM in
advance. The remaining segment and digit lines can be used as general-purpose ports. Settings of each
port are shown below.
Table 15. Pins in FLD Automatic Display Mode
Port Name Automatic Display Pins Setting Method
The individual bits of the digit output set register (address 035C16,
P5, P6
FLD0 to FLD15
035D16) can set each pin either FLD port (“0”) or digit port (“1”).
When the pins are set for the digit port, the digit pulse output function is enabled, so the digit pulses can always be output regardless
the value of FLD automatic display RAM.
FLD exclusive use port (automatic display control bit (bit 0 of adP0, P1
FLD16 to FLD31
dress 035016)=“1”)
The individual bits of the FLD/port switch register (addresses
P2, P3,
FLD32 to FLD51
035916 to 035B16) can set each pin to either FLD port (“1”) or genP44 to P43
eral-purpose port (“0”).
The individual bits of the FLD/port switch register (address 035B16)
P44 to P47 FLD52 to FLD55
can set each pin to either FLD port (“1”) or general-purpose port
(“0”). The digit pulse output function turns to available, and the digit
pulse can output by setting of the FLD output set register (address
035116). The port output format is the CMOS output. When using
the port as a display pin, a driver must be installed externally.
Setting example 1
Shown below is a register setup example where only FLD output is used.
In this case, the digit display output pattern must be set in the FLD automatic
display RAM in advance.
Number of segments
Number of digits
Port P6
36
16
FLD0(DIG output)
FLD1(DIG output)
FLD2(DIG output)
FLD3(DIG output)
FLD4(DIG output)
FLD5(DIG output)
FLD6(DIG output)
FLD7(DIG output)
Port P5
Port P0
Port P1
FLD8(DIG output)
FLD9(DIG output)
FLD10(DIG output)
FLD11(DIG output)
FLD12(DIG output)
FLD13(DIG output)
FLD14(DIG output)
FLD15(DIG output)
FLD16(SEG output)
FLD17(SEG output)
FLD18(SEG output)
FLD19(SEG output)
FLD20(SEG output)
FLD21(SEG output)
FLD22(SEG output)
FLD23(SEG output)
FLD24(SEG output)
FLD25(SEG output)
FLD26(SEG output)
FLD27(SEG output)
FLD28(SEG output)
FLD29(SEG output)
FLD30(SEG output)
FLD31(SEG output)
The contents of digit output set register
(035C16, 035D16)
0
0
0
0
0
0
0
0
0
Setting example 2
Shown below is a register setup example where both FLD output and digit waveform
output are used. In this case, because the digit display output is automatically
generated, there is no need to set the display pattern in the FLD automatic display RAM.
Number of segments
Number of digits
Port P6
FLD/port switch register
(035916, 035B16)
28
12
FLD0(DIG output)
FLD1(DIG output)
FLD2(DIG output)
FLD3(DIG output)
FLD4(DIG output)
FLD5(DIG output)
FLD6(DIG output)
FLD7(DIG output)
Port P2
0
0
0
0
0
0
0
Port P3
Port P4
FLD32(SEG output)
FLD33(SEG output)
FLD34(SEG output)
FLD35(SEG output)
FLD36(SEG output)
FLD37(SEG output)
1 FLD38(SEG output)
1 FLD39(SEG output)
1
1
1
1
1
1
1
1
1
1
FLD40(SEG output)
Port P5
FLD11(DIG output)
FLD12(SEG output)
FLD13(SEG output)
FLD14(SEG output)
FLD15(SEG output)
Port P0
FLD41(SEG output)
FLD42(SEG output)
FLD43(SEG output)
1 FLD44(SEG output)
1 FLD45(SEG output)
1 FLD46(SEG output)
1 FLD47(SEG output)
FLD48(SEG output)
FLD49(SEG output)
FLD50(SEG output)
FLD51(SEG output)
FLD52(port output)
FLD53(port output)
0 FLD54(port output)
0 FLD55(port output)
1
1
1
1
0
0
FLD8(DIG output)
FLD9(DIG output)
FLD10(DIG output)
Port P1
FLD16(SEG output)
FLD17(SEG output)
FLD18(SEG output)
FLD19(SEG output)
FLD20(SEG output)
FLD21(SEG output)
FLD22(SEG output)
FLD23(SEG output)
FLD24(SEG output)
FLD25(SEG output)
FLD26(SEG output)
FLD27(SEG output)
FLD28(SEG output)
FLD29(SEG output)
FLD30(SEG output)
FLD31(SEG output)
The contents of digit output set register
(035C16, 035D16)
1
1
1
1
1
1
1
1
1
1
1
1
0
0
FLD/port switch register
(035916, 035B16)
Port P2
0
0
Port P3
Port P4
1 FLD32(SEG output)
1 FLD33(SEG output)
1 FLD34(SEG output)
1 FLD35(SEG output)
1 FLD36(SEG output)
1 FLD37(SEG output)
1 FLD38(SEG output)
1 FLD39(SEG output)
1 FLD40(SEG output)
1 FLD41(SEG output)
1 FLD42(SEG output)
1 FLD43(SEG output)
0 FLD44(port output)
0 FLD45(port output)
0 FLD46(port output)
0 FLD47(port output)
0 FLD48(port output)
0 FLD49(port output)
0 FLD50(port output)
0 FLD51(port output)
0 FLD52(port output)
0 FLD53(port output)
0 FLD54(port output)
0 FLD55(port output)
DIG output : This output is connected to digit of the FLD.
SEG output : This output is connected to segment of the FLD.
Port output : This output is general-purpose port ( used program).
DIG output : This output is connected to digit of the FLD.
SEG output : This output is connected to segment of the FLD.
Port output : This output is general-purpose port ( used program).
Figure 43. Segment/Digit Setting Example
60
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FLD automatic display RAM
The FLD automatic display RAM uses the 224 bytes of addresses 050016 to 05DF16. For FLD, the 3 modes
of 16-timing ordinary mode, 16-timing•gradation display mode and 32-timing mode are available depending
on the number of timings and the use/not use of gradation display.
The automatic display RAM in each mode is as follows:
(1) 16-timing•Ordinary Mode
This mode is used when the display timing is 16 or less. The 112 bytes of addresses 057016 to 05DF16
are used as a FLD display data store area. Because addresses 0500 16 to 056F16 are not used as the
automatic display RAM, they can be the ordinary RAM.
(2) 16-timing•Gradation Display Mode
This mode is used when the display timing is 16 or less, in which mode each segment can be set for dark
or bright display. The 224 bytes of addresses 050016 to 05DF16 are used. The 112 bytes of addresses
057016 to 05DF16 are used as an FLD display data store area, while the 112 bytes of addresses 0500 16
to 056F16 are used as a gradation display control data store area.
(3) 32-timing Mode
This mode is used when the display timing is 16 or greater. This mode can be used for up to 32-timing.
The 224 bytes of addresses 050016 to 05DF16 are used as an FLD display data store area.
The FLD data pointer (address 035816) is a register to count display timings. This pointer has a reload
register and when the terminal count is reached, it starts counting over again after being reloaded with the
initial count. Make sure the timing count – 1 is set to the FLD data pointer. When writing data to this address,
the data is written to the FLD data pointer reload register; when reading data from this address, the value in
the FLD data pointer is read.
16-timing•ordinary mode
16-timing•gradation display mode
050016
050016
1 to 32 timing display
data stored area
057016
1 to 16 timing display
data stored area
05DF16
050016
Gradation display
control data stored
area
Not used
057016
32-timing mode
1 to 16 timing display
data stored area
05DF16
05DF16
Figure 44. FLD Automatic Display RAM Assignment
61
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data setup
(1) 16-timing•Ordinary Mode
The area of addresses 057016 to 05DF16 are used as a FLD automatic display RAM.
When data is stored in the FLD automatic display RAM, the last data of FLD port P4 is stored at address 057016, the
last data of FLD port P3 is stored at address 058016, the last data of FLD port P2 is stored at address 059016, the last
data of FLD port P1 is stored at address 05A016, the last data of FLD port P0 is stored at address 05B016,
the last data of FLD port P5 is stored at address 05C016, and the last data of FLD port P6 is stored at address 05D016, to
assign in sequence from the last data respectively.
The first data of the FLD port P4, P3, P2, P1, P0, P5, and P6 is stored at an address which adds the value of (the
timing number – 1) to the corresponding address 057016, 058016, 059016, 05A016, 05B016, 05C016 and 05DF16.
Set the FLD data pointer reload register to the value given by the number of digits – 1.
(2) 16-timing•Gradation Display Mode
Display data setting is performed in the same way as that of the 16-timing•ordinary mode. Gradation display control
data is arranged at an address resulting from subtracting 007016 from the display data store address of each timing
and pin. Bright display is performed by setting “0”, and dark display is performed by setting “1” .
(3) 32-timing Mode
The area of addresses 050016 to 05DF16 are used as a FLD automatic display RAM.
When data is stored in the FLD automatic display RAM, the last data of FLD port P4 is stored at address 050016, the
last data of FLD port P3 is stored at address 052016, the last data of FLD port P2 is stored at address 054016,
the last data of FLD port P1 is stored at address 056016, the last data of FLD port P0 is stored at address 058016, the
last data of FLD port P5 is stored at address 05A016, and the last data of FLD port P6 is stored at address 05C016, to
assign in sequence from the last data respectively.
The first data of the FLD port P4, P3, P2, P0, P1, P5, and P6 is stored at an address which adds the value of (the
timing number – 1) to the corresponding address 050016, 052016, 054016, 056016, 058016, 05A016 and 05C016.
Set the FLD data pointer reload register to the value given by the number of digits - 1.
Number of timing: 8
(FLD data pointer reload register = 7)
Address
Bit
057016
057116
057216
057316
057416
057516
057616
057716
057816
057916
057A16
057B16
057C16
057D16
057E16
057F16
058016
058116
058216
058316
058416
058516
058616
058716
058816
058916
058A16
058B16
058C16
058D16
058E16
058F16
059016
059116
059216
059316
059416
059516
059616
059716
059816
059916
059A16
059B16
059C16
059D16
059E16
059F16
05A016
05A116
05A216
05A316
05A416
05A516
05A616
05A716
05A816
05A916
05AA16
05AB16
05AC16
05AD16
05AE16
05AF16
7
6
5
4
3
2
1
Bit
0
Address
05B016
05B116
05B216
05B316
05B416
05B516
05B616
05B716
05B816
05B916
05BA16
05BB16
05BC16
05BD16
05BE16
05BF16
05C016
05C116
05C216
05C316
05C416
05C516
05C616
05C716
05C816
05C916
05CA16
05CB16
05CC16
05CD16
05CE16
05CF16
05D016
05D116
05D216
05D316
05D416
05D516
05D616
05D716
05D816
05D916
05DA16
05DB16
05DC16
05DD16
05DE16
05DF16
The last timing
(The last data of FLDP4)
Timing for start
(The first data of FLDP4)
FLDP4 data area
The last timing
(The last data of FLDP3)
Timing for start
(The first data of FLDP3)
FLDP3 data area
The last timing
(The last data of FLDP2)
Timing for start
(The first data of FLDP2)
FLDP2 data area
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP0)
Timing for start
(The first data of FLDP0)
FLDP0 data area
The last timing
(The last data of FLDP5)
Timing for start
(The first data of FLDP5)
FLDP5 data area
The last timing
(The last data of FLDP6)
Timing for start
(The first data of FLDP6)
FLDP6 data area
The last timing
(The last data of FLDP1)
Timing for start
(The first data of FLDP1)
FLDP1 data area
Figure 45. Example of Using the FLD Automatic Display RAM in 16-timing•Ordinary Mode
62
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Number of timing: 15
(FLD data pointer reload register = 14)
Address
Bit
057016
057116
057216
057316
057416
057516
057616
057716
057816
057916
057A16
057B16
057C16
057D16
057E16
057F16
058016
058116
058216
058316
058416
058516
058616
058716
058816
058916
058A16
058B16
058C16
058D16
058E16
058F16
059016
059116
059216
059316
059416
059516
059616
059716
059816
059916
059A16
059B16
059C16
059D16
059E16
059F16
05A016
05A116
05A216
05A316
05A416
05A516
05A616
05A716
05A816
05A916
05AA16
05AB16
05AC16
05AD16
05AE16
05AF16
05B016
05B116
05B216
05B316
05B416
05B516
05B616
05B716
05B816
05B916
05BA16
05BB16
05BC16
05BD16
05BE16
05BF16
05C016
05C116
05C216
05C316
05C416
05C516
05C616
05C716
05C816
05C916
05CA16
05CB16
05CC16
05CD16
05CE16
05CF16
05D016
05D116
05D216
05D316
05D416
05D516
05D616
05D716
05D816
05D916
05DA16
05DB16
05DC16
05DD16
05DE16
05DF16
7
6
5
4
3
2
1
0
Address
Bit
050016
050116
050216
050316
050416
050516
050616
050716
050816
050916
050A16
050B16
050C16
050D16
050E16
050F16
051016
051116
051216
051316
051416
051516
051616
051716
051816
051916
051A16
051B16
051C16
051D16
051E16
051F16
052016
052116
052216
052316
052416
052516
052616
052716
052816
052916
052A16
052B16
052C16
052D16
052E16
052F16
053016
053116
053216
053316
053416
053516
053616
053716
053816
053916
053A16
053B16
053C16
053D16
053E16
053F16
054016
054116
054216
054316
054416
054516
054616
054716
054816
054916
054A16
054B16
054C16
054D16
054E16
054F16
055016
055116
055216
055316
055416
055516
055616
055716
055816
055916
055A16
055B16
055C16
055D16
055E16
055F16
056016
056116
056216
056316
056416
056516
056616
056716
056816
056916
056A16
056B16
056C16
056D16
056E16
056F16
The last timing
(The last data of FLDP4)
FLDP4 data area
Timing for start
(The first data of FLDP4)
The last timing
(The last data of FLDP3)
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP1)
FLDP1 data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP5)
FLDP5 data area
Timing for start
(The first data of FLDP5)
The last timing
(The last data of FLDP6)
FLDP6 data area
Timing for start
(The first data of FLDP6)
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP4)
FLDP4 gradation
display data area
Timing for start
(The first data of FLDP4)
The last timing
(The last data of FLDP3)
FLDP3 gradation
display data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP2)
FLDP2 gradation
display data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP1)
FLDP1 gradation
display data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP0)
FLDP0 gradation
display data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP5)
FLDP5 gradation
display data area
Timing for start
(The first data of FLDP5)
The last timing
(The last data of FLDP6)
FLDP6 gradation
display data area
Timing for start
(The first data of FLDP6)
Figure 46. Example of Using the FLD Automatic Display RAM in 16-timing•Gradation Display Mode
63
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Number of timing: 20
(FLD data pointer reload register = 19)
Address
Bit
057016
057116
057216
057316
057416
057516
057616
057716
057816
057916
057A16
057B16
057C16
057D16
057E16
057F16
058016
058116
058216
058316
058416
058516
058616
058716
058816
058916
058A16
058B16
058C16
058D16
058E16
058F16
059016
059116
059216
059316
059416
059516
059616
059716
059816
059916
059A16
059B16
059C16
059D16
059E16
059F16
05A016
05A116
05A216
05A316
05A416
05A516
05A616
05A716
05A816
05A916
05AA16
05AB16
05AC16
05AD16
05AE16
05AF16
05B016
05B116
05B216
05B316
05B416
05B516
05B616
05B716
05B816
05B916
05BA16
05BB16
05BC16
05BD16
05BE16
05BF16
05C016
05C116
05C216
05C316
05C416
05C516
05C616
05C716
05C816
05C916
05CA16
05CB16
05CC16
05CD16
05CE16
05CF16
05D016
05D116
05D216
05D316
05D416
05D516
05D616
05D716
05D816
05D916
05DA16
05DB16
05DC16
05DD16
05DE16
05DF16
7
6
5
4
3
2
1
0
Address
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP5)
FLDP5 data area
Timing for start
(The first data of FLDP5)
The last timing
(The last data of FLDP6)
FLDP6 data area
Timing for start
(The first data of FLDP6)
Bit
050016
050116
050216
050316
050416
050516
050616
050716
050816
050916
050A16
050B16
050C16
050D16
050E16
050F16
051016
051116
051216
051316
051416
051516
051616
051716
051816
051916
051A16
051B16
051C16
051D16
051E16
051F16
052016
052116
052216
052316
052416
052516
052616
052716
052816
052916
052A16
052B16
052C16
052D16
052E16
052F16
053016
053116
053216
053316
053416
053516
053616
053716
053816
053916
053A16
053B16
053C16
053D16
053E16
053F16
054016
054116
054216
054316
054416
054516
054616
054716
054816
054916
054A16
054B16
054C16
054D16
054E16
054F16
055016
055116
055216
055316
055416
055516
055616
055716
055816
055916
055A16
055B16
055C16
055D16
055E16
055F16
056016
056116
056216
056316
056416
056516
056616
056716
056816
056916
056A16
056B16
056C16
056D16
056E16
056F16
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP4)
FLDP4 data area
Timing for start
(The first data of FLDP4)
The last timing
(The last data of FLDP3)
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP1)
FLDP1 data area
Figure 47. Example of Using the FLD Automatic Display RAM in 32-timing Mode
64
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing setting
Each timing is set by the FLDC mode register, Tdisp time set register, Toff1 time set register, and Toff2 time set register.
•Tdisp time setting
The Tdisp time represents the length of display timing. In non-gradation display mode, it consists of a
FLD display output period and a Toff1 time. In gradation display mode, it consists of the display output
period and Toff1 time plus a low signal output period for dark display. Set the Tdisp time by the Tdisp
counter count source select bit of the FLDC mode register and the Tdisp time set register. Supposing that
the value of the Tdisp time set register is n, the Tdisp time is represented as Tdisp = (n+1) x t (t: count
source). When the Tdisp counter count source select bit of the FLDC mode register is “0” and the value
of the Tdisp time set register is 200 (C816), the Tdisp time is: Tdisp = (200+1) x 3.2 (at XIN= 10 MHz) =
643 µs. When reading the Tdisp time set register, the value in the counter is read out.
•Toff1 time setting
The Toff1 time represents a non-output (low signal output) time to prevent blurring of FLD, and to dim the
display. Use the Toff1 time set register to set this Toff1 time. Make sure the value set to Toff1 is smaller
than Tdisp and Toff2. Supposing that the value of the Toff1 time set register is n1, the Toff1 time is
represented as Toff1 = n1 x t. When the Tdisp counter count source select bit of the FLDC mode register
is “0” and the value of the Toff1 time set register is 30 (1E16), Toff1 = 30 x 3.2 (at XIN = 10 MHz) = 96 µs.
•Toff2 time setting
The Toff2 time is provided for dark display. For bright display, the FLD display output remains effective
until the counter that is counting Tdisp reaches the terminal count. For dark display, however, “L” (or “off”)
signal is output when the counter that is counting Toff2 reaches the terminal count. This Toff2 time setting
is valid only for FLD ports which are in the gradation display mode and whose gradation display control
RAM value is “1” .
Set the Toff2 time by the Toff2 time set register. Make sure the value set to Toff2 is smaller than Tdisp but
larger than Toff1. Supposing that the value of the Toff2 time set register is n2, the Toff2 time is represented as Toff2 = n2 x t. When the Tdisp counter count source select bit of the FLDC mode register is “0”
and the value of the Toff2 time set register is 180 (B416), Toff2 = 180 x 3.2 (at XIN = 10 MHz) = 576 µs.
Low output period for
blurring prevention
•Grayscale display mode is not selected
(Address 035016 bit 5 = “0”)
•Grayscale display mode is selected and set for bright display
(Address 035016 bit 5 = “1” and the corresponding grayscale
display control data = “0”)
Display output period
Toff1
Tdisp
Low output period for
blurring prevention
•Grayscale display mode is selected and set for dark display
(Address 035016 bit 5 = “1” and the corresponding grayscale
display control data = “1”)
Display output
period
Toff1
Toff2
Tdisp
Figure 48. FLDC Timing
65
Low output period for
dark display
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FLD automatic display start
Automatic display starts by setting both the automatic display control bit (bit 0 of address 035016) and the
display start bit (bit 1 of address 035016) to “1”. The RAM content at a location apart from the start address
of the automatic display RAM for each port by (FLD data pointer (address 035816) – 1) is output to each
port. The FLD data pointer (address 035816) counts down in the Tdisp interval. When the count “FF16” is
reached, the pointer is reloaded and starts counting over again. Before setting the display start bit (bit 1 of
address 035016) to “1”, be sure to set the FLD/port switch register, FLD/DIG switch register, FLDC mode
register, Tdisp time set register, Toff1 time set register, Toff2 time set register, and FLD data pointer.
During FLD automatic display, bit 1 of the FLDC mode register (address 0350 16) always keeps “1”, and
FLD automatic display can be interrupted by writing “0” to bit 1.
Key-scan and interrupt
Either a FLD digit interrupt or FLD blanking interrupt can be selected using the Tscan control bits (bits 2, 3
of address 035016).
The FLD digit interrupt is generated when the Toff1 time in each timing expires (at rising edge of digit
output). Key scanning that makes use of FLD digits can be achieved using each FLD digit interrupt. To use
FLD digit interrupts for key scanning, follow the procedure described below.
(1) Read the port value each time the interrupt occurs.
(2) The key is fixed on the last digit interrupt.
The digit positions output can be determined by reading the FLD data pointer (address 035816).
Repeat synchronous
Tdisp
Toff1
Tn
Tn-1 Tn-2
T4
T3
T2
T1
Tn
Tn-1 Tn-2
FLD digit output
FLD digit interrupt generated at the rising edge of digit ( each timing)
Figure 49. Timing using digit interrupt
66
T4
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The FLD blanking interrupt is generated when the FLD data pointer (address 035816) reaches “FF16”. The FLD automatic
display output is turned off for a duration of 1 x Tdisp, 2 x Tdisp, or 3 x Tdisp depending on post-interrupt settings. During
this time, key scanning that makes use of FLD segments can be achieved.
When a key-scan is performed with the segment during key-scan blanking period Tscan, take the following sequence:
1. Write “0” to bit 0 of the FLDC mode register (address 035016).
2. Set the port corresponding to the segment for key-scan to the output port.
3. Perform the key-scan.
4. After the key-scan is performed, write “1” to bit 0 of FLDC mode register (address 035016).
•Note:
When performing a key-scan according to the above steps 1 to 4, take the following points into consideration.
1. Do not set “0” in bit 1 of the FLDC mode register (address 035016).
2. Do not set “1” in the ports corresponding to digits.
Repeat synchronous
Tdisp
Tn
Tscan
Tn-1 Tn-2
T4
T3
T2
T1
Tn
Tn-1 Tn-2
FLD digit output
Segment setting by software
FLD blanking interrupt generated at the
falling of edge of the last digit
Figure 50. Timing using FLD blanking interrupt
67
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P44 to P47 Expansion Function
P44 to P47 are CMOS output-type ports. FLD digit outputs can be increased as many as 16 lines by connecting a 4-bit to 16-bit decoder to these ports. P44 to P47 have the function to allow for connection to a 4bit to 16-bit decoder.
(1) P44 to P47 Toff invalid Function
This function disables the Toff1 time and Toff2 time and outputs display data for the duration of Tdisp.
(See Figure 51.) This can be accomplished by setting the P44 to P47 Toff disable bit (address 035016 bit
2) to “1”.
Unlike the Toff section generate/not generate function, this function disables all display data.
(2) Dimmer signal output Function
This function allows a dimmer signal creation signal to be output from DIMOUT (P97). The dimmer function
can be materialized by controlling the decoder with this signal. (See Figure 51.) This function can be set
by writing P97 dimmer output control bit (bit 4 of address 035116) to “1”.
(3) P44 to P47 FLD Output Reverse Bit
P44 to P47 are provided with a function to reverse the polarity of the FLD output. This function is useful in
adjusting the polarity when using an externally installed driver.
The output polarity can be reversed by setting bit 0 of the FLD output control register (address 035116) to
“1” .
•Grayscale display mode is not selected
•Grayscale display mode is selected and
set for bright display
(grayscale display control data = “0”)
FLD output
•Grayscale display mode is selected and
set for dark display
(grayscale display control data = “1”)
•Grayscale display mode is selected and
Toff2 SET/RESET bit is “1”
(grayscale display control data = “1”)
Toff1
Toff2
Tdisp
Output selecting P44 to P47
Toff invalid
For dimmer signal
DIMOUT(P97)
Figure 51. P4 to P47 FLD Output pulses
68
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Toff section generate/not generate Function
The function is for reduction of useless noises which generated as every switching of ports, because of the
combined capacity of among FLD ports. In case the continuous data output to each FLD ports, the Toff1
section of the continuous parts is not generated. (See Figure 52)
If it needs Toff1 section on FLD pulses, set “CMOS ports: section of Toff generate / not generate bit” to “1”
and set “high-breakdown-voltage ports: section of Toff generate / not generate bit” to “1”. High-breakdownvoltage ports (P5, P6, P3, P2, P1, P0, P40 to P43, total 52 pins) generate Toff1 section, by setting “highbreakdown-voltage ports: section of Toff generate / not generate bit” to “1”.
The CMOS ports ( P44 to P47, total 4 pins ) generate Toff1 section, by setting “high-breakdown-voltage
ports: section of Toff generate / not generate bit” to “1”.
Tdisp
Toff1
“H” output
“L” output
“H” output
“H” output
“H” output
“H” output
“L” output
“H” output
“H” output
“L” output
“H” output
“H” output
P1X
Output waveform when “highbreakdown-voltage ports: section of Toff
generate/not generate bit”(bit 6 of 03511
6) is “1”.
P2X
P1X
Output waveform when “highSection of Toff1 is not generated because of output is same.
breakdown-voltage ports: section of Toff
generate/not generate bit”(bit 6 of 035116)
is “0”.
“H” output
“H” output
“L” output
“H” output
P2X
Section of Toff1 is not generated because of output is same.
Figure 52. Toff Section Generated/not generated Function
Toff2 SET/RESET change bit
In gradation display mode, the values set by the Toff2 time set register (TOFF2) are effective. When the
FLD output control register (bit 7 of address 035116 ) in the initial state = “0”, RAM data is output to the FLD
output ports (SET) at the time that is set by TOFF1 and is turned to “0” (RESET) at the time that is set by
TOFF2. When bit 7 = “1”, RAM data is output (SET) at the time that is set by TOFF2 and is turned to “0”
(RESET) when the Tdisp time expires.
69
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Digit pulses output Function
P50 to P57 and P60 to P67 allow digit pulses to be output using the FLD/digit switch register. Set the digit
output set register by writing as many consecutive 1s as the timing count from P60. The contents of FLD
automatic display RAM for the ports that have been selected for digit output are disabled, and the pulse
shown in Figure 53 is output automatically. In gradation display mode use, Toff2 time becomes effective for
the port which selected digit output. Because the contents of FLD automatic display RAM are disabled, the
segment data can be changed easily even when segment data and digit data coexist at the same address
in the FLD automatic display RAM.
This function is effective in 16-timing normal mode and 16-timing gradation display mode. If a value is set
exceeding the timing count (FLD data pointer reload register's set value + 1) for any port, the output of such
port is “L”.
Tdisp
Toff1
P57
P56
P55
P54
P53
P52
P51
P50
P67
P66
P65
P64
P63
P62
P61
P60
Low-order 4bits
of the data pointer
F
E
D
C
B
A
9
8
Figure 53. Digit Pulses Output Function
70
7
6
5
4
3
2
1
0
Mitsubishi microcomputers
M30218 Group
Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(three). All these timers function independently. Figure 54 shows the block diagram of timers.
Clock prescaler
XIN
f1
1/8
f8
1/4
f1 f8 f32 fc32
f32
1/32
XCIN
Reset
Clock prescaler reset flag
(bit 7 at address 038116) set to “1”
• Timer mode
• One-shot mode
• PWM mode
TA0IN/
TA3OUT
Timer A0 interrupt
Timer A0
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
TA1IN/
TA4OUT
Timer A1 interrupt
Timer A1
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
TA2IN/
TA0OUT
Timer A2 interrupt
Timer A2
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
TA3IN/
TA1OUT
fC32
Timer A3
Noise
filter
Timer A3 interrupt
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A4 interrupt
TA4IN/
TA2OUT
Timer A4
Noise
filter
• Event counter mode
• Timer mode
• Pulse width measuring mode
TB0IN
Noise
filter
Timer B0
Timer B0 interrupt
• Event counter mode
• Timer mode
• Pulse width measuring mode
TB1IN
Noise
filter
Timer B1 interrupt
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode
TB2IN
Noise
filter
Timer B2
• Event counter mode
Figure 54. Timer block diagram
71
Timer B2 interrupt
Mitsubishi microcomputers
M30218 Group
TimerA
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Figure 55 shows the block diagram of timer A. Figures 56 to 58 show the timer A-related registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer's over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f1
f8
f32
fC32
• Timer
(gate function)
Reload register (16)
• Event counter
Polarity
selection
TAiIN
(i = 0 to 4)
Counter (16)
Up count/down count
Always down count except
in event counter mode
Clock selection
Count start flag
(Address 038016)
Down count
TB2 overflow
TAj overflow
(j = i - 1. Note, however, that j = 4 when i = 0)
High-order
8 bits
Low-order
8 bits
External
trigger
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Up/down flag
(Address 038416)
TAk overflow
Addresses
038716 038616
038916 038816
038B16 038A16
038D16 038C16
038F16 038E16
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
T AiOUT
Timer A3
Timer A4
Timer A0
Timer A1
Timer A2
(k = i + 1. Note, however, that k = 0 when i = 4)
TAiOUT
Pulse output
(i = 0 to 4)
Toggle flip-flop
Figure 55. Block diagram of timer A
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b
1
b0
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
Address
When reset
039616 to 039A16
0016
Bit name
Operation mode select
bit
TMOD1
MR0
MR1
Function
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
Function varies with each operation mode
MR2
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Figure 56. Timer A-related registers (1)
72
AA
A
A
A
AA
A
AA
A
A
AA
A
A
AA
AA
R W
Mitsubishi microcomputers
M30218 Group
TimerA
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai register (Note)
(b15)
b7
(b8)
b0b7
b0
Symbol
TA0
TA1
TA2
TA3
TA4
Address
038716,038616
038916,038816
038B16,038A16
038D16,038C16
038F16,038E16
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
Values that can be set
• Timer mode
Counts an internal count source
RW
000016 to FFFF
• Event counter mode
Counts pulses from an external source or timer overflow
000016 to FFFF16
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
000016 to FFFE16
0016 to FE16
(Both high-order
and low-order
addresses)
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
Note: Read and write data is in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
Bit symbol
When reset
0016
Bit name
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Function
R W
0 : Stops counting
1 : Starts counting
Up/down flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UDF
Address
038416
Bit symbol
Bit name
TA0UD
Timer A0 up/down flag
TA1UD
Timer A1 up/down flag
TA2UD
Timer A2 up/down flag
TA3UD
Timer A3 up/down flag
TA4UD
Timer A4 up/down flag
TA2P
TA3P
TA4P
When reset
0016
Function
0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
Timer A2 two-phase pulse 0 : two-phase pulse signal
processing disabled
signal processing select bit
1 : two-phase pulse signal
processing enabled
Timer A3 two-phase pulse
signal processing select bit
When not using the two-phase
Timer A4 two-phase pulse pulse signal processing function,
signal processing select bit set the select bit to “0”
Figure 57. Timer A-related registers (2)
73
RW
Mitsubishi microcomputers
M30218 Group
TimerA
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
One-shot start flag
Symbol
ONSF
b7 b6 b5 b4 b3 b2 b1 b0
Address
038216
Bit symbol
When reset
00X000002
Bit name
Function
TA0OS
Timer A0 one-shot start flag
TA1OS
Timer A1 one-shot start flag
TA2OS
Timer A2 one-shot start flag
TA3OS
Timer A3 one-shot start flag
TA4OS
Timer A4 one-shot start flag
RW
1: Timer start
When read, the value is “0”
Nothing is assigned.
This bit can neither be set nor reset. When read, the content is indeterminate.
TA0TGL
Timer A0 event/trigger
select bit
TA0TGH
b7 b6
0 0 : Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to “0”.
When TAiIN is selected, TAiOUT assigned on same pin can not be used. (i=0 to 4)
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Address
038316
Bit symbol
TA1TGL
When reset
0016
Bit name
Function
Timer A1 event/trigger
select bit
b1 b0
Timer A2 event/trigger
select bit
b3 b2
Timer A3 event/trigger
select bit
b5 b4
Timer A4 event/trigger
select bit
b7 b6
TA1TGH
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TGH
R W
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
0 0 : Input on TA4IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”.
When TAiIN is selected, TAiOUT assigned on same pin can not be used. (i=0 to 4)
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
Bit symbol
When reset
0XXXXXXX2
Bit name
Function
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are indeterminate.
CPSR
Clock prescaler reset flag
Figure 58 Timer A-related registers (3)
74
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
RW
Mitsubishi microcomputers
M30218 Group
TimerA
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table16.) Figure 59 shows the
timer Ai mode register in timer mode.
Table 16. Specifications of timer mode
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
• Down count
• When the timer underflows, it reloads the reload register contents before continuing counting
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing When the timer underflows
TAiIN pin function
Programmable I/O port or gate input
TAiOUT pin function
Programmable I/O port or pulse output
Read from timer
Count value can be read out by reading timer Ai register
Write to timer
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Gate function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
Address
When reset
039616 to 039A16
0016
Bit name
Function
Operation mode
select bit
b1 b0
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
Gate function select bit
b4 b3
TMOD1
R W
0 0 : Timer mode
0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
1 0 : Timer counts only when TAiIN pin is
held “L” (Note 3)
1 1 : Timer counts only when TAiIN pin is
held “H” (Note 3)
MR2
MR3
0 (Must always be fixed to “0” in timer mode)
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register
are invalid.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0”.
Figure 59. Timer Ai mode register in timer mode
75
Mitsubishi microcomputers
M30218 Group
TimerA
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase
external signal. Table 17 lists timer specifications when counting a single-phase external signal. Figure
60 shows the timer Ai mode register in event counter mode.
Table 18 lists timer specifications when counting a two-phase external signal. Figure 61 shows the timer
Ai mode register in event counter mode.
Table 17. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
Count source
•External signals input to TAiIN pin (effective edge can be selected by software)
•TB2 overflow, TAj overflow
Count operation
•Up count or down count can be selected by external signal or software
•When the timer overflows or underflows, the reload register's content is reloaded
and the timer starts over again.(Note)
Divide ratio
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer overflows or underflows
TAiIN pin function
Programmable I/O port or count source input
TAiOUT pin function
Programmable I/O port, pulse output, or up/down count select input
Read from timer
Count value can be read out by reading timer Ai register
Write to timer
•When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
•When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
•Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
•Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TAiMR(i = 0, 1)
0 1
Address
039616, 039716
Bit symbol
Bit name
TMOD0
Operation mode select bit
When reset
0016
Function
RW
b1 b0
0 1 : Event counter mode (Note 1)
TMOD1
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TAiOUT pin is a pulse output pin)
MR1
Count polarity
select bit (Note 3)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
MR2
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 4)
MR3
0 (Must always be fixed to “0” in event counter mode)
TCK0
Count operation type select 0 : Reload type
bit
1 : Free-run type
TCK1
Invalid in event counter mode
Can be “0” or “1”
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
(addresses 038216 and 038316).
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”,
the upcount is activated. Set the corresponding port direction register to “0”.
Figure 60. Timer Ai mode register in event counter mode
76
Mitsubishi microcomputers
M30218 Group
TimerA
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 18. Timer specifications in event counter mode (when processing two-phase pulse signal with timer A2,A3 and A4
Item
Specification
Count source
•Two-phase pulse signals input to TAiIN or TAiOUT pin
Count operation
•Up count or down count can be selected by two-phase pulse signal
•When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
Divide ratio
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing Timer overflows or underflows
TAiIN pin function
Two-phase pulse input
TAiOUT pin function
Two-phase pulse input
Read from timer
Count value can be read out by reading timer A2, A3, or A4 register
Write to timer
•When counting stopped
When a value is written to timer A2, A3, or A4 register, it is written to both
reload register and counter
•When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only
reload register. (Transferred to counter at next reload time.)
Select function
•Normal processing operation
The timer counts up rising edges or counts down falling edges on the TAiIN
pin when input signal on the TAiOUT pin is “H”
TAiOUT
TAiIN
(i=2,3)
Up
count
Up
count
Up
count
Down
count
Down
count
Down
count
•Multiply-by-4 processing operation
If the phase relationship is such that the TAiIN pin goes “H” when the input
signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges
on the TAiOUT and TAiIN pins. If the phase relationship is such that the
TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count up all edges
Count down all edges
Count up all edges
Count down all edges
TAiIN
(i=3,4)
Note: This does not apply when the free-run function is selected.
77
Mitsubishi microcomputers
M30218 Group
TimerA
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register
(When not using two-phase pulse signal processing)
b7
b6
b5
b4
b3
b2
0
b1
b0
0 1
Symbol
Address
When reset
TAiMR(i = 2 to 4) 039816 to 039A16
0016
Bit symbol
Bit name
TMOD0
Operation mode select bit
TMOD1
Function
0 1 : Event counter mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
Count polarity
select bit (Note 2)
0 : Counts external signal's falling edges
1 : Counts external signal's rising edges
MR2
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 3)
MR3
0 (Must always be “0” in event counter mode)
TCK0
Count operation type select 0 : Reload type
bit
1 : Free-run type
Two-phase pulse signal
0 : Normal processing operation
processing operation
1 : Multiply-by-4 processing operation
select bit (Note 4)(Note 5)
MR0
TCK1
R W
b1 b0
Note 1: The settings of the corresponding port register and port direction register are invalid
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0”.
Note 4: This bit is valid for timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0 ”or “1”.
Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Timer Ai mode register
(When using two-phase pulse signal processing)
b7
b6
b5
b4
b3
b2
b1
b0
0 1 0 0 0 1
Symbol
Address
When reset
TAiMR(i = 2 to 4) 039816 to 039A16
0016
Bit symbol
TMOD0
Bit name
Operation mode select bit
TMOD1
Function
RW
b1 b0
0 1 : Event counter mode
M R0
0 (Must always be “0” when using two-phase pulse
signal processing)
M R1
0 (Must always be “0” when using two-phase pulse
signal processing)
M R2
1 (Must always be “1” when using two-phase pulse
signal processing)
M R3
0 (Must always be “0” when using two-phase pulse
signal processing)
TCK0
Count operation type select 0 : Reload type
bit
1 : Free-run type
TCK1
Two-phase pulse
processing operation
select bit (Note 1)(Note 2)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: This bit is valid for timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0” or “1”.
Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Figure 61. Timer Ai mode register in event counter m
78
Mitsubishi microcomputers
M30218 Group
TimerA
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 19.) When a trigger occurs, the timer starts up and
continues operating for a given period. Figure 62 shows the timer Ai mode register in one-shot timer mode.
Table 19. Timer specifications in one-shot timer mode
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio
1/n
n : Set value
Count start condition
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
Count stop condition
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Interrupt request generation timing The count reaches 000016
TAiIN pin function
Programmable I/O port or trigger input
TAiOUT pin function
Programmable I/O port or pulse output
Read from timer
When timer Ai register is read, it indicates an indeterminate value
Write to timer
•When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7
b6
b5
0
b4
b3
b2
b1
b0
1 0
Symbol
Address
When reset
TAiMR(i = 0 to 4) 039616 to 039A16
0016
Bit symbol
TMOD0
Bit name
Function
Operation mode select bit
TMOD1
1 0 : One-shot timer mode
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
External trigger select
bit (Note 2)
0 : Falling edge of TAiIN pin's input signal (Note 3)
1 : Rising edge of TAiIN pin's input signal (Note 3)
MR2
Trigger select bit
0 : One-shot start flag is valid
1 : Selected by event/trigger select
register
MR3
0 (Must always be “0” in one-shot timer mode)
TCK0
Count source select bit
TCK1
RW
b1 b0
b7 b6
0 0 : f1
0 1 : f8
1 0 : f3 2
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid
Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0”.
Figure 62. Timer Ai mode register in one-shot timer mode
79
Mitsubishi microcomputers
M30218 Group
TimerA
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 20.) In this mode, the counter
functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 63 shows the timer
Ai mode register in pulse width modulation mode. Figure 64 shows the example of how a 16-bit pulse width
modulator operates. Figure 65 shows the example of how an 8-bit pulse width modulator operates.
Table 20. Timer specifications in pulse width modulation mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
•The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
•The timer reloads a new count at a rising edge of PWM pulse and continues counting
•The timer is not affected by a trigger that occurs when counting
16-bit PWM
•High level width
n / fi n : Set value
•Cycle time
(216-1) / fi fixed
8-bit PWM
•High level width n X (m+1) / fi n : values set to timer Ai register’s high-order address
•Cycle time (28-1) X (m+1) / fi m : values set to timer Ai register’s low-order address
Count start condition
•External trigger is input
•The timer overflows
•The count start flag is set (= 1)
Count stop condition
•The count start flag is reset (= 0)
Interrupt request generation timing PWM pulse goes “L”
TAiIN pin function
Programmable I/O port or trigger input
TAiOUT pin function
Pulse output
Read from timer
When timer Ai register is read, it indicates an indeterminate value
Write to timer
•When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
•When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7
b6
b5
b4
b3
b2
b1
b0
1 1 1
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
TMOD1
Address
When reset
039616 to 039A16
0016
Bit name
Operation mode
select bit
Function
R W
b1 b0
1 1 : PWM mode
MR0
1 (Must always be fixed to “1” in PWM mode)
MR1
External trigger select
bit (Note 1)
0: Falling edge of TAiIN pin's input signal (Note 2)
1: Rising edge of TAiIN pin's input signal (Note 2)
MR2
Trigger select bit
0: Count start flag is valid
1: Selected by event/trigger select register
MR3
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
TCK0
Count source select bit
0 0 : f1
0 1 : f8
1 0 : f3 2
1 1 : fC32
b7 b6
TCK1
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0
Note 2: Set the corresponding port direction register to “0”.
Figure 63. Timer Ai mode register in pulse width modulation mode
80
Mitsubishi microcomputers
M30218 Group
TimerA
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Condition : Reload register = 000316, when external trigger
(falling edge of TA0IN pin's input signal) is selected.
1 / fi X (216 –1)
Count source
“H”
TA0IN pin's
input signal
“L”
Trigger is not generated by this signal
1 / fi X n
PWM pulse output “H”
from TA0OUT pin “L”
Timer A0 interrupt “1”
request bit
“0”
fi : Frequency of count source
(f1, f8, f32, fC32)
Cleared to “0” by software, or when interrupt request is accepted.
Note: n = 000016 to FFFE16.
Figure 64. Example of how a 16-bit pulse width modulator operates
Condition : Reload register's high-order 8 bits = 0216
Reload register's low-order bits 8 = 0216
When external trigger (falling edge of TA0IN pin's input signal) is selected.
1 / fi X (m + 1) X (28 – 1)
Count source
(Note 1)
TA0IN pin's input
signal
“H”
“L”
1 / fi X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note 2)“L”
1 / fi X (m + 1) X n
PWM pulse output
from TA0OUT pin
“H”
Timer A0 interrupt
request bit
“1”
“L”
“0”
fi : Frequency of count source
(f1, f8, f32, fC32)
Cleared to “0” by software, or when interrupt request is accepted.
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FE16; n = 0016 to FE16.
Figure 65. Example of how an 8-bit pulse width modulator operates
81
Mitsubishi microcomputers
M30218 Group
TimerB
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Figure 66 shows the block diagram of timer B. Figures 67 and 68 show the timer B-related registers.
Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
f1
f8
High-order 8 bits
Low-order 8 bits
• Timer
• Pulse period/pulse width measurement
Reload register (16)
f32
fc32
Counter (16)
• Event counter
Count start flag
(address 038016)
Polarity switching
and edge pulse
TBiIN
(i = 0 to 2)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Timer B0
Timer B1
Timer B2
TBj overflow
(j = i - 1. Note, however,
j = 2 when i = 0)
Address
039116 039016
039316 039216
039516 039416
TBj
Timer B2
Timer B0
Timer B1
Figure 66. Block diagram of timer B
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
TBiMR(i = 0 to 2) 039B16 to 039D16
Bit symbol
TMOD0
Function
Bit name
Operation mode select bit
TMOD1
MR0
When reset
00XX00002
R
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
Function varies with each operation mode
MR1
MR2
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note 1: Timer B0.
Note 2: Timer B1, timer B2.
Figure 67. Timer B-related registers (1)
82
W
Mitsubishi microcomputers
M30218 Group
TimerB
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Bi register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TB0
TB1
TB2
Address
039116, 039016
039316, 039216
039516, 039416
Function
When reset
Indeterminate
Indeterminate
Indeterminate
Values that can be set
• Timer mode
Counts the timer's period
000016 to FFFF16
• Event counter mode
Counts external pulses input or a timer overflow
000016 to FFFF16
RW
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note: Read and write data in 16-bit units.
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Bit symbol
Address
038016
When reset
0016
Bit name
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Function
R W
0 : Stops counting
1 : Starts counting
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Bit symbol
Address
038116
Bit name
When reset
0XXXXXXX2
Function
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
CPSR
Clock prescaler reset flag
Figure 68. Timer B-related registers (2)
83
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
RW
Mitsubishi microcomputers
M30218 Group
TimerB
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 21.) Figure 69 shows the
timer Bi mode register in timer mode.
Table 21. Timer specifications in timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
•Counts down
•When the timer underflows, the reload register's content is reloaded and the
timer starts over again.
Divide ratio
1/(n+1) n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Programmable I/O port
Read from timer
Count value is read out by reading timer Bi register
Write to timer
•When counting stopped
When a value is written to timer Bi register, it is written to both reload register
and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
TBiMR(i=0 to 2)
Bit symbol
TMOD0
Address
039B16 to 039D16
Bit name
Operation mode select bit
TMOD1
MR0
When reset
00XX00002
Function
0 0 : Timer mode
MR1
Invalid in timer mode
Can be “0” or “1”
MR2
0 (Fixed to “0” in timer mode ; i = 0)
Nothing is assigned (i = 1,2). In an attempt to write to this bit, write
“0”. The value, if read, turns out to be indeterminate.
MR3
Invalid in timer mode.
In an attempt to write to these bits, write “0”. The value, if read in
timer mode, turns out to be indeterminate.
TCK0
Count source select bit
TCK1
Note 1: Timer B0.
Note 2: Timer B1, timer B2.
Figure 69. Timer Bi mode register in timer mode
84
R
b1 b0
b7 b6
0 0 : f1
0 1 : f8
1 0 : f3 2
1 1 : fC32
(Note 1)
(Note 2)
W
Mitsubishi microcomputers
M30218 Group
TimerB
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 22.) Figure 70
shows the timer Bi mode register in event counter mode.
Table 22. Timer specifications in event counter mode
Item
Specification
Count source
•External signals input to TBiIN pin
•Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation
•Counts down
•When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Count source input
Read from timer
Count value can be read out by reading timer Bi register
Write to timer
•When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
•When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
0 1
Symbol
TBiMR(i=0 to 2)
Bit symbol
TMOD0
TMOD1
M R0
Address
039B16 to 039D16
Bit name
Function
Operation mode
select bit
b1 b0
Count polarity select
bit (Note 1)
b3 b2
R
0 1 : Event counter mode
M R1
M R2
When reset
00XX00002
0 0 : Counts external signal's falling edges
0 1 : Counts external signal's rising edges
1 0 : Counts external signal's falling and
rising edges
1 1 : Inhibited
0 (Fixed to “0” in event counter mode; i = 0)
Nothing is assigned (i = 1, 2).
In an attempt to write to this bit, write “0”. The value, if read,
turns out to be indeterminate.
M R3
Invalid in event counter mode.
In an attempt to write to this bit, write “0”. The value, if read in event
counter mode, turns out to be indeterminate.
TCK0
Invalid in event counter mode.
Can be “0” or “1”.
TCK1
Event clock select
0: Input from TBiIN pin (Note 4)
1: TBj overflow
(j = i-1; however, j = 2 when i = 0)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Timer B0.
Note 3: Timer B1, timer B2.
Note 4: Set the corresponding port direction register to “0”.
Figure 70. Timer Bi mode register in event counter mode
85
(Note 2)
(Note 3)
W
Mitsubishi microcomputers
M30218 Group
TimerB
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 23.)
Figure 71 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 72
shows the operation timing when measuring a pulse period. Figure 73 shows the operation timing when
measuring a pulse width.
Table 23. Timer specifications in pulse period/pulse width measurement mode
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
•Up count
•Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing •When measurement pulse's effective edge is input (Note 1)
•When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count start
flag is “1” and a value is written to the timer Bi mode register.)
TBiIN pin function
Measurement pulse input
Read from timer
When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
TBiMR (i=0 to 2)
Bit symbol
TMOD0
TMOD1
M R0
Address
039B16 to 039D16
Bit name
Function
Operation mode
select bit
b1 b0
Measurement mode
select bit
b3 b2
M R1
M R2
When reset
00XX00002
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
Nothing is assigned (i = 1, 2).
In an attempt to write to this bit, write “0”. The value, if read in event counter
mode, turns out to be indeterminate.
Timer Bi overflow
flag ( Note 1)
TCK0
Count source
select bit
TCK1
W
1 0 : Pulse period / pulse width measurement mode
0 (Fixed to “0” in pulse period/pulse width measurement mode; i = 0)
M R3
R
(Note 2)
(Note 3)
0 : Timer did not overflow
1 : Timer has overflowed
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Note 2: Timer B0.
Note 3: Timer B1, timer B2.
Figure 71. Timer Bi mode register in pulse period/pulse width measurement mode
86
Mitsubishi microcomputers
M30218 Group
TimerB
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Measurement of puls time interval from falling edge to falling edge
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
Transfer
(indeterminate value)
Transfer
(measured value)
counter
(Note 1)
(Note 1)
(Note 2)
Timing when counter
reaches “000016”
“1”
Count start
flag
“0”
Timer Bi interrupt
request bit
“1”
“0”
Cleared to “0” by software, or when interrupt request is accepted.
“1”
Timer Bi overflow
flag
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 72. Operation timing when measuring a pulse period
Count source
Measurement pulse
“H”
“L”
Transfer (indeterminate value)
Reload register
transfer timing
Transfer (measured value)
counter
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2)
Timing when counter
reaches “000016”
Count start
flag
Timer Bi interrupt
request bit
“1”
“0”
“1”
“0”
Cleared to “0” by software, or when interrupt request is accepted.
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 73. Operation timing when measuring a pulse width
87
Mitsubishi microcomputers
M30218 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O is configured as two channels: UART0 and UART1.
UART0 and UART1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Figure 74 shows the block diagram of UART0 and UART1. Figure 75 shows the block diagram of the transmit/receive unit.
UARTi (i=0, 1) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A016 and 03A816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART.
Although a few function are different, UART0 and UART1 have almost same functions.
Figures 76 through 78 show the registers related to UARTi.
(UART0)
TxD0
RxD0
UART reception
1/16
Clock source selection
f1
Internal
f8
f32
Bit rate generator
(address 03A116)
1 / (m+1)
Reception control
circuit
Clock synchronous type
UART transmission
1/16
Transmission
control circuit
Clock synchronous type
External
Receive clock
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when external clock is
selected)
Clock synchronous type
(when internal clock is selected)
CLK0
Polarity
reversing
circuit
CTS/RTS disabled
CTS/RTS selected
RTS0
CTS0 / RTS0
Vcc
CTS/RTS disabled
CTS0
(UART1)
RxD1
TxD1
UART reception
1/16
Clock source selection
f1
Internal
f8
f32
Bit rate generator
(address 03A916)
1 / (n+1)
External
UART transmission
1/16
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
Polarity
reversing
circuit
Clock output pin
select switch
CTS1 / RTS1
CLKS1
Transmission
control circuit
Clock synchronous type
1/2
CLK1
Reception control
circuit
Clock synchronous type
Receive
clock
CTS/RTS disabled
RTS1
VCC
CTS/RTS disabled
CTS1
m: Values set to UART0 bit rate generator (U0BRG)
n : Values set to UART1 bit rate generator (U1BRG)
Figure 74. Block diagram of UARTi (i = 0, 1)
88
Mitsubishi microcomputers
M30218 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
synchronous type
PAR
disabled
1SP
RxDi
SP
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
UARTi receive register
UART (7
bits)
PAR
SP
PAR
enabled
2SP
UART
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
0
0
0
0
0
0
0
D7
D8
D6
D5
D4
D3
D2
D1
D0
UARTi receive
buffer register
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
D0
UARTi transmit
buffer register
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D7
D8
D6
D5
D4
D3
D2
D1
UART (8 bits)
UART (9 bits)
UART (9 bits)
PAR
enabled
2SP
SP
UART
Clock
synchronouss
type
TxDi
PAR
SP
1SP
PAR
disabled
"0"
Clock
synchronous
type
UART (7 bits)
UARTi transmit register
UART (7 bits)
UART (8 bits)
Clock synchronous
type
Figure 75. Block diagram of transmit/receive unit
89
SP: Stop bit
PAR: Parity bit
Mitsubishi microcomputers
M30218 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0TB
U1TB
b0
Address
03A316, 03A216
03AB16, 03AA16
When reset
Indeterminate
Indeterminate
Function
R W
Transmission data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
UARTi receive buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U1RB
b0
Bit
symbol
Address
03A716, 03A616
03AF16, 03AE16
When reset
Indeterminate
Indeterminate
Function
(During clock synchronous
serial I/O mode)
Bit name
Reception data
Function
(During UART mode)
R W
Reception data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
OER
Overrun error flag (Note)
0 : No overrun error
1 : Overrun error found
FER
Framing error flag (Note) Invalid
0 : No framing error
1 : Framing error found
PER
Parity error flag (Note)
0 : No parity error
1 : Parity error found
Invalid
0 : No overrun error
1 : Overrun error found
0 : No error
1 : Error found
Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses
03A016 and 03A816) are set to “0002” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when
the lower byte of the UARTi receive buffer register (addresses 03A616 and 03AE16) is read out.
SUM
Error sum flag (Note)
Invalid
UARTi bit rate generator
b7
b0
Symbol
U0BRG
U1BRG
Address
03A116
03A916
When reset
Indeterminate
Indeterminate
Function
Assuming that set value = n, BRGi divides the count
source by (n + 1)
Figure 76. Serial I/O-related registers (1)
90
Values that can be set
0016 to FF16
R W
Mitsubishi microcomputers
M30218 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
Symbol
UiMR (i=0,1)
b0
Bit
symbol
Address
03A016, 03A816
Bit name
SMD0 Serial I/O mode select bit
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
Function
(During UART mode)
R W
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock
0 : Internal clock
1 : External clock
STPS
Stop bit length select bit
Invalid
0 : One stop bit
1 : Two stop bits
PRY
Odd/even parity select bit Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
Invalid
0 : Parity disabled
1 : Parity enabled
SLEP
Sleep select bit
Must always be “0”
0 : Sleep mode deselected
1 : Sleep mode selected
UARTi transmit/receive control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UiC0 (i=0,1)
Bit
symbol
CLK0
Address
When reset
0816
03A416, 03AC16
Bit name
TXEPT
b1 b0
Function
(During UART mode)
b1 b0
BRG count source
select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function
select bit
Valid when bit 4 = “0”
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CLK1
CRS
Function
(During clock synchronous
serial I/O mode)
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit
0 : Data present in transmit register
Transmit register empty
register (during transmission)
(during transmission)
flag
1 : No data present in transmit
1 : No data present in transmit
register
(transmission completed)
register (transmission completed)
CRD
CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P47 and P74 function as
programmable I/O port)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P47 and P77 function as
programmable I/O port)
NCH
Data output select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
CKPOL
CLK polarity select bit
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Must always be “0”
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Figure 77. Serial I/O-related registers (2)
91
R W
Mitsubishi microcomputers
M30218 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
Symbol
UiC1(i=0,1)
b0
Bit
symbol
Address
03A516, 03AD16
When reset
0216
Function
(During clock synchronous serial
I/O mode)
Bit name
Function
(During UART mode)
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer empty
flag
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
R W
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
UART transmit/receive control register 2
b7
b6
0
b5
b4
b3
b2
b1
b0
Symbol
UCON
Bit
symbol
Address
03B016
Bit name
When reset
X00000002
Function
(During clock synchronous serial
I/O mode)
Function
(During UART mode)
U0IRS
UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0RRM
UART0 continuous receive
mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Invalid
U1RRM
UART1 continuous receive
mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
CLKMD0
CLK/CLKS select bit 0
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD1
CLK/CLKS select bit 1
(Note)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
Must always be “0”
Must always be “0”
Must always be “0”
Reserved bit
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirement must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
Figure 78. Serial I/O-related registers (3)
92
RW
Mitsubishi microcomputers
M30218 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 24 lists
the specifications of the clock synchronous serial I/O mode. Figure 79 shows the UARTi transmit/receive
mode register.
Table 24. Specifications of clock synchronous serial I/O mode
Specification
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at address 03A016, 03A816 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When
external clock
is selected (bit 3 _______
at address
03A016, 03A816 =“1”) : Input from CLKi pin (Note 2)
_______
________
________
Transmission/reception control • CTS function/ RTS function/ CTS,RTS function chosen to be invalid
Transmission start condi- • To start transmission, the following requirements must be met:
_
tion Transmit enable bit (bit 0 at address 03A516, 03AD16) = “1”
_ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
_______
_______
_ When CTS function is selected, CTS input level = "L"
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “1”: CLKi input level = “L”
• To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at address 03A516, 03AD16) = “1”
Reception start condition
_ Transmit enable bit (bit 0 at address 03A516, 03AD16) = “1”
_ Transmit buffer empty flag (bit 1 at address 03A516, 03AD16) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “1”: CLKi input level = “L”
• When transmitting
_ Transmit interrupt cause select bit (bits 0,1 at address 03B016) = “0”:
Interrupt request
Interrupts requested when data transfer from UARTi transfer buffer register to
generation timing
UARTi transmit register is completed
_ Transmit interrupt cause select bit (bits 0,1 at address 03B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi reError detection
ceive buffer register are read out
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
Select function
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection
UART1 transfer clock can be set 2 pins, and can be selected to output from
which pin.
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: Maximum 5 Mbps.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
Item
Transfer data format
Transfer clock
93
Mitsubishi microcomputers
M30218 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7
b6
0
b5
b4
b3
b2
b1
b0
Symbol
UiMR(i=0,1)
0 0 1
Bit symbol
SMD0
Address
03A016, 03A816
Bit name
Function
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
Internal/external clock
select bit
RW
b2 b1 b0
0 0 1 : Clock synchronous serial
I/O mode
0 : Internal clock
1 : External clock
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
SLEP
0 (Must always be "0" in clock synchronous serial I/O mode)
Figure 79. UARTi transmit/receive mode register in clock synchronous serial I/O mode (i=0,1)
Table 25 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that
for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs
a “H”. (If the N-channel open-drain is selected, this pin is in floating state.)
Table 25. Input/output pin functions in clock synchronous serial I/O mode (i=0,1)
Pin name
Function
Method of selection
TxDi
(P44, P74)
Serial data output
(Outputs dummy data when performing reception only)
RxDi
(P45, P75)
Serial data input
Port P45, P75 direction register (bits 5 at address 03EA16 and 03EF16)= “0”
(Can be used as an input port when performing transmission only)
CLKi
(P46, P76)
Transfer clock output
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “0”
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1”
Port P46, P76 direction register (bits 6 at address 03EA16 and 03EF16) = “0”
CTS input
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) =“0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “0”
Port P47, P77 direction register (bits 7 address 03EA16 and 03EF16) = “0”
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “1”
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “1”
CTSi/RTSi
(P47, P77)
94
Mitsubishi microcomputers
M30218 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
“1”
“0”
Data is set in UARTi transmit buffer register
“1”
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
CTSi
“L”
TCLK
Stopped pulsing because CTS = “H”
Stopped pulsing because transfer enable bit = “0”
CLKi
TxDi
D0 D1 D2 D3 D4 D5 D6 D7
Transmit
register empty
flag (TXEPT)
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
“1”
“0”
Transmit interrupt “1”
request bit (IR)
“0”
Cleared to “0” by software, or when an interrupt request is accepted.
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi's count source (f1, f8, f32)
n: value set to BRGi
• Example of receive timing (when external clock is selected)
Receive enable
bit (RE)
“1”
Transmit enable
bit (TE)
“1”
Transmit buffer
empty flag (Tl)
“0”
“0”
Dummy data is set in UARTi transmit buffer register
“1”
“0”
“H”
Transferred from UARTi transmit buffer register to UARTi transmit register
RTSi
“L”
1 / fEXT
CLKi
Receive data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
RxDi
Receive complete “1”
flag (Rl)
“0”
Transferred from UARTi receive register
to UARTi receive buffer register
D0 D1 D2 D3 D4 D5
Read out from UARTi receive buffer register
Receive interrupt “1”
request bit (IR)
“0”
Cleared to “0” by software, or when an interrupt request is accepted.
fEXT: frequency of external clock
Shown in ( ) are bit symbols.
The above timing applies to the following settings.
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
Meet the following conditions when the CLK input before
data reception = “H”
• Transmit enable bit
“1”
• Receive enable bit
“1”
• Dummy data write to UARTi transmit buffer register
Figure 80. Typical transmit/receive timings in clock synchronous serial I/O mode
95
Mitsubishi microcomputers
M30218 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(a) Polarity select function
As shown in Figure 81, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16) allows selection
of the polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: The CLKi pin level when not
transferring data is “H”.
• When CLK polarity select bit = “1”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 2: The CLKi pin level when not
transferring data is “L”.
Figure 81. Polarity of transfer clock
(b) LSB first/MSB first sel82GA-9, when the transfer format select bit (bit 7 at addresses 03A416,
03AC16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB
first”.
• When transfer format select bit = “0”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
LSB first
RXDi
• When transfer format select bit = “1”
CLKi
TXDi
D7
D6
D5
D4
D3
D2
D1
D0
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
MSB first
Note: This applies when the CLK polarity select bit = “0”.
Figure 82. Transfer format
96
Mitsubishi microcomputers
M30218 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(c) Transfer clock output from multiple pins function
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 83.) The
multiple pins function is valid only when the internal clock is selected for UART1. Note that when this
_______ _______
function is selected, CTS/RTS function of UART1 cannot be used.
Microcomputer
TXD1 (P74)
CLKS1 (P77)
CLK1 (P76)
IN
IN
CLK
CLK
Note: This applies when the internal clock is selected and transmission is
performed only in clock synchronous serial I/O mode.
Figure 83. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016) is set to “1”, the unit is
placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit
simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer
register back again.
97
Mitsubishi microcomputers
M30218 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Clock asynchronous serial I/O (UART) mode
The UART allows transmitting and receiving data after setting the desired transfer rate and transfer data
format. Table 26 lists the specifications of the UART mode. Figure 84 shows the UARTi transmit/receive
mode register.
Table 26. Specifications of clock synchronous serial I/O mode
Item
Transfer data format
Specification
•Character bit (transfer data): 7 bits, 8 bits or 9 bits as selected
•Start bit: 1 bit
•Parity bit: Odd, even or nothing as selected
•Stop bit: 1 bit or 2 bits as selected
Transfer clock
•When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32
•When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) :
fEXT/16(n+1)_______
(Note 1) (Note
2)
_______
_______ _______
Transmission/reception control •CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition •To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
- Transmit
buffer empty flag (bit 1 _______
at addresses 03A516, 03AD16) = “0”
_______
- When CTS function is selected, CTS input level = “L”
Reception start condition •To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”
- Start bit detection
Interrupt request
•When transmitting
generation timing
- Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register to
UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is completed
•When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
•Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi receive
buffer register are read out
•Framing error
This error occurs when the number of stop bits set is not detected
•Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
•Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
select function
•Sleep mode selection
This mode is used to transfer data to and from one of multiple slave microcomputers
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
98
Mitsubishi microcomputers
M30218 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UiMR (i=0,1)
Bit symbol
SMD0
Address
03A016, 03A816
Bit name
Function
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
STPS
Internal/external clock
select bit
Stop bit length select bit
PRY
Odd/even parity select bit
PRYE
Parity enable bit
SLEP
Sleep select bit
R W
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
Figure 84. UARTi transmit/receive mode register in UART mode
Table 27 lists the functions of the input/output pins during UART mode. Note that for a period from when
the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the Nchannel open-drain is selected, this pin is in floating state.)
Table 27. Input/output pin functions in UART mode (i=0,1)
Pin name
Function
Method of selection
TxDi
(P44, P74)
Serial data output
(Outputs dummy data when performing reception only)
RxDi
(P45, P75)
CLKi
(P46, P76)
Serial data input
Programmable I/O port
Port P45, P75 direction register (bits 5 at address 03EA16 and 03EF16)= “0”
(Can be used as an input port when performing transmission only)
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “0”
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1”
CTS input
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) =“0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “0”
Port P47, P77 direction register (bits 7 at address 03EA16 and 03EF16) = “0”
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “1”
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “1”
CTSi/RTSi
(P47, P77)
99
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M30218 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Tc
Transfer clock
Transmit enablee
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register.
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
CTSi
“L”
Start
bit
TxDi
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
P
Stopped pulsing because transmit enable bit = “0”
Stop
bit
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1
SP
“1”
Transmit register
empty flag (TXEPT)
“0”
Transmit interrupt
request bit (IR)
“1”
“0”
Cleared to “0” by software, or when an interrupt request is accepted.
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi's count source (f1, f8, f32)
fEXT : frequency of BRGi's count source (external clock)
n : value set to BRGi
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
TxDi
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Transmit register
empty flag (TXEPT)
“1”
Transmit interrupt
request bit (IR)
“1”
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
“0”
“0”
Cleared to “0” by software, or when an interrupt request is accepted.
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
• Transmit interrupt causes select bit = “0”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi's count source (f1, f8, f32)
fEXT : frequency of BRGi's count source (external clock)
n : value set to BRGi
Figure 85. Typical transmit timings in UART mode
100
S T D0 D1
Mitsubishi microcomputers
M30218 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi's count
source
Receive
enable bit
“1”
“0”
Stop bit
Start bit
R xD i
D1
D0
D7
Sampled “L”
Receive data taken in
Transfer clock
Receive
complete flag
RTSi
“1”
Reception triggered when
transfer clock is genelated by
falling edge of start bit
Transferred from UARTi receive register to
UARTi receive buffer register
“0”
“H”
“L”
Receive interrupt “1”
request bit
“0”
Cleared to “0” by software, or when an interrupt request is accepted.
The above timing applies to the following settings :
• Parity is disabled.
• One stop bit.
• RTS function is selected.
Figure 86. Typical receive timing in UART mode
(a) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
101
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O2
Serial I/O2 is used as the clock synchronous serial I/O and has an ordinary mode and an automatic transfer
mode. In the automatic transfer mode, serial transfer is performed through the serial I/O automatic transfer
RAM which has up to 256 bytes (addresses 0040016 to 004FF16).
The SRDY2, SBUSY2 and SSTB2 pins each have a handshake I/O signal function and can select either “H”
active or “L” active for active logic.
Table 28. Specifications of clock synchronous serial I/O2
Item
Specification
Serial mode
• 8-bit serial I/O mode (non-automatic transfer)
• Automatic transfer serial I/O mode
• Transfer data length: 8 bits
• Full duplex mode / transmit-only mode selected by bit 5 at address 034216
Transfer clock
• When internal clock is selected (bit 2 at address 034216 = “0”) : selected by bits 5 to 7 at address 034816
• When external clock is selected (bit 2 at address 034216 = “1”) : Input from SCLK21 pin, SCLK22 pin(Note 2)
Transfer rate
• When internal clock is selected : f(XIN)/4, f(XIN)/8, f(XIN)/16, f(XIN)/32, f(XIN)/64, f(XIN)/128, f(XIN)/256
• When external clock is selected : input cycle 0.95 µs or less
Transmission/reception control • SSTB2 output / SBUSY2 input or output / SRDY2 input or output chosen
Transmission /
• To start transmission / reception, the following requirements must be met:
reception start condition _ Serial I/O initialization bit (bit 4 at address 034216) = “1”
_ When SBUSY2 input, or SRDY2 input is selected : selected input level = “H”
____________
_________
_ When SBUSY2 input, or SRDY2 input is selected : selected input level = “L”
• Furthermore, if external clock is selected, the following requirements must
also be met:
_ Input level of SCLK21 or SCLK22 = “H”
Transmission and
• To stop transmission and reception, set serial I/O initialization bit (bit 4 at
reception stop condition
address 034216) to “0” regardless internal clock and external clock.
Interrupt request
• 8-bit serial I/O mode : Interrupts requested when 8-bit data transfer is comgeneration timing
pleted
• Automatic transfer serial I/O mode :Interrupts requested when last receive
data transfer to Automatic transfer RAM
• SOUT2 P-channel output disable function
Select function
CMOS output or N-channel open-drain output can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Serial I/O2 clock pin select bit
Serial clock input/output can be selected; SCLK21 or SCLK22
• SBUSY output, SSTB2 output select function (only automatic transfer serial
mode)
SBUSY output, SSTB2 output can be selected; 1-byte data transfer unit or all
data transfer unit
• SOUT2 pin control bit
Either output active or high-impedance can be selected as a SOUT2 pin state at
serial non-transfer .
Note 1: It is necessary to set the serial I/O clock pin select bit ( bit 7 at address 034216)
Transfer data format
102
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Main address
bus
Local address
bus
Serial I/O automatic
transfer RAM
(0040016—004FF16)
Main
Local
data bus data bus
Serial I/O2
automatic transfer
data pointer
Address decoder
Serial I/O2
automatic transfer
controller
Serial I/O2
control register 3
XIN
“0”
SSTB2
Divider
Port latch
(SSTB2 pin control bit)
“1”
Port latch
SRDY2•SBUSY2 pin
control bit
“0”
SBUSY2
“1”
SRDY2•SBUSY2 pin
control bit
Internal synchronous
clock selection bits
Serial I/O2
synchronous clock
selection bit
“0
Synchronous
”
circuit
Port latch
SCLK2
“0”
SRDY2
“1”
1/4
1/8
1/16
1/32
1/64
1/128
1/256
“1”
Serial I/O2 clock
pin selection bit
“0”
“1”
Serial transfer
status flag
Port latch
“0”
SCLK21
“0”
“1”
“1”
SCLK22
Serial I/O2 counter
“1”
Serial I/O2 clock
pin selection bits
“0”
Port latch
“0”
SOUT2
Port latch
“1” Serial transfer selection bits
SIN2
Serial I/O2 register (8)
Figure 87. Block Diagram of Serial I/O2
103
Serial I/O2
interrupt request
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O2 control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
SIO2CON1
Bit symbol
SCON10
Address
034216
When reset
0016
Bit name
Serial transfer select bits
Function
R
W
b1 b0
00: Serial I/O disabled
(serial I/O pins are I/O ports)
01: 8-bits serial I/O
10: Inhibit
11: Automatic transfer serial I/O (8-bits)
SCON11
SCON12
Serial I/O2 synchronous
clock select bits
(SSTB2 pin control bit)
SCON13
SCON14
SCON15
b3 b2
00: Internal synchronous clock
(SSTB2 pin is an I/O port.)
01: External synchronous clock
(SSTB2 pin is an I/O port.)
10: Internal synchronous clock
(SSTB2 pin is an SSTB2 output.)
11: Internal synchronous clock
(SSTB2 pin is an SSTB2 output.)
Serial I/O initialization bit
0: Serial I/O initialization
1: Serial I/O enabled
Transfer mode select bit
0: Full duplex (transmit and receive) mode
(SIN2 pin is a SIN2 input.)
1: Transmit-only mode (SIN2 pin is an I/O port.)
SCON16
Transfer direction
select bit
0: LSB first
1: MSB first
SCON17
Serial I/O2 clock pin
select bit
0:SCLK21 (SCLK22 pin is an I/O port.)
1:SCLK22 (SCLK21 pin is an I/O port.)
Serial I/O2 control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
SIO2CON2
Bit symbol
Address
034416
Bit name
Function
SRDY2 • SBUSY2 pin
SCON20 control bits
b3b2b1b0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SCON21
SCON22
SCON23
SBUSY2 output • SSTB2 output
SCON24 function select bit
(Valid in automatic transfer mode)
SCON25
When reset
0016
Serial transfer status flag
SRDY2 pin
I/O port
Not used
SRDY2 output
SRDY2 output
I/O port
I/O port
I/O port
I/O port
SRDY2 input
SRDY2 input
SRDY2 input
SRDY2 input
SRDY2 output
SRDY2 output
SRDY2 output
SRDY2 output
R
SBUSY2 pin
I/O port
I/O port
I/O port
SBUSY2 input
SBUSY2 input
SBUSY2 output
SBUSY2 output
SBUSY2 output
SBUSY2 output
SBUSY2 output
SBUSY2 output
SBUSY2 input
SBUSY2 input
SBUSY2 input
SBUSY2 input
0: Functions as each 1-byte signal
1: Functions as signal for all transfer data
0: Serial transfer completion
1: Serial transferring
SCON26 SOUT2 pin control bit
(at no-transfer serial data)
0: Output active
1: Output high-impedance
SOUT2 P-channel output
SCON27 disable bit
0: CMOS 3-state (P-channel output is valid.)
1: N-channel open-drain
(P-channel output is invalid.)
Figure 88. Serial I/O2 Control Registers 1, 2
104
W
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O2 automatic transfer data pointer
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
SIO2DP
Address
034016
When reset
0016
Function
R
W
R
W
R
W
• Automatic transfer data pointer set
Specify the low-order 8 bits of the first data store address on the serial I/O
automatic transfer RAM.
Data is written into the latch and read from the decrement counter.
Serial I/O2 register/transfer counter
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
SIO2
Address
034616
When reset
0016
Function
• Number of automatic transfer data set
Set the number of automatic transfer data.
Set a value one less than number of transfer data.
Data is written into the latch and read from the decrement counter.
Serial I/O2 control register 3
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
SIO2CON3
Address
034816
Bit symbol
Bit name
TTRAN0
Automatic transfer
interval set bits
TTRAN1
TTRAN2
TTRAN3
Function
b4b3b2b1b0
00000 :2 cycles of transfer clocks
00001 :3 cycles of transfer clocks
:
11110 :32 cycles of transfer clocks
11111 :33 cycles of transfer clocks
Data is written to a latch and read from
a decrement counter.
TTRAN4
TCLK0
When reset
000000002
Internal synchronous
clock selection bits
TCLK1
TCLK2
Figure 89. Serial I/O2 automatic transfer data pointer
105
b7b6b5
000:f(XIN)/4
001:f(XIN)/8
010:f(XIN)/16
011:f(XIN)/32
100:f(XIN)/64
101:f(XIN)/128
110:f(XIN)/256
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 29 lists the functions of the serial I/O2 input/output pins
Table 29. Functions of the serial I/O2 input/output pins
Pin name
Function
Method of selection
SOUT2
(P94)
Serial data output
Port P94 direction register (bit 4 at address 03F316)= “1”
SOUT2 P-channel output disable bit (bit 7 at address 034416)= “0” , “1”
SOUT2 pin control bit (bit 6 at address 034416)= “0” , “1”
(Outputs dummy data when performing reception only)
SIN2
(P93)
Serial data input
Port P93 direction register (bit 4 at address 03F316)= “0”
Transfer mode select bit (bit 5 at address 034216)= “0”
(Input/output port when transfer mode select bit (bit 5 at address 034216)= “1”)
SCLK21
(P95)
Transfer clock output
Serial I/O2 synchronous clock select bits (bits 2, 3 at address 034216) = “00” , “01”
Serial I/O2 clock pin select bit (bit 7 at address 034216) = “0”
Transfer clock input
Serial I/O2 synchronous clock select bits (bits 2, 3 at address 034216) = “01” , “11”
Serial I/O2 clock pin select bit (bit 7 at address 034216) = “0”
Port P95 direction register (bit 5 at address 03F316)= “0”
Transfer clock output
Serial I/O2 synchronous clock select bits (bits 2, 3 at address 034216) = “00” , “01”
Serial I/O2 clock pin select bit (bit 7 at address 034216) = “1”
Transfer clock input
Serial I/O2 synchronous clock select bits (bits 2, 3 at address 034216) = “01” , “11”
Serial I/O2 clock pin select bit (bit 7 at address 034216) = “1”
Port P96 direction register (bit 6 at address 03F316)= “0”
SRDY2
(P90)
SRDY input / output
Set by SRDY2 • SBUSY2 pin control bits (bits 0 to 3 at address 034416)
SBUSY2
(P91)
SBUSY input / output
Set by SRDY2 • SBUSY2 pin control bits (bits 0 to 3 at address 034416)
SBUSY2 output • SSTB2 output function select bit (bit 4 at address 034416)= “0” , “1”
SSTB2
(P92)
SSTB input / output
Serial I/O2 synchronous clock select bits (bits 2, 3 at address 034216) = “10” , “11”
SBUSY2 output • SSTB2 output function select bit (bit 4 at address 034416)= “0” , “1”
SCLK22
(P96)
SOUT2 Output
Either output active or high-impedance can be selected as a S OUT2 pin state at serial non-transfer by the
SOUT2 pin control bit (bit 6 of address 034416).
However, when the external synchronous clock is selected, perform the following setup to put the SOUT2
pin into a high-impedance state.
When the SCLK2i ( i = 1, 2) input is “H” after completion of transfer, set the SOUT2 pin control bit to “1”. When
the SCLK2i ( i = 1, 2) input goes to “L” after the start of the next serial transfer, the SOUT2 pin control bit is
automatically reset to “0” and put into an output active state.
106
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O2 Mode
There are two types of serial I/O2 modes: 8-bit serial I/O mode where automatic transfer RAM is not
used, and an automatic transfer serial I/O mode.
(1) 8-bit Serial I/O Mode
Address 034616 is assigned to the serial I/O2 register. When the internal synchronous clock is
selected, a serial transfer of the 8-bit serial I/O is started by a write signal to the serial I/O2 register
(address 034616).
The serial transfer status flag (bit 5 of address 034416) is set to “1” by writing into the serial I/O2
register and reset to “0” after completion of 8-bit transfer. At the same time, a serial I/O2 interrupt
request occurs. If the transfer is completed, the receive data is read out from serial I/O2 register.
When the external synchronous clock is selected, the contents of the serial I/O2 register are continuously shifted while transfer clocks are input to SCLK21 or SCLK22. Therefore, the clock needs to
be controlled externally.
(2) Automatic Transfer Serial I/O Mode
Address 034616 is assigned to the transfer counter (1-byte units). The serial I/O2 automatic transfer controller controls the write and read operations of the serial I/O2 register. The serial I/O automatic transfer RAM is mapped to addresses 0040016 to 004FF16. Before starting transfer, make
sure the 8 low-order bits of the address that contains the beginning data to be serially transferred is
set to the automatic transfer data pointer (address 034016).
When the internal synchronous clock is selected, the transfer interval is inserted between one data
and another in the following cases:
1. When using no handshake signal
2. When using the SRDY2 output, SBUSY2 output, and SSTB2 output of the handshake signal inde
pendently
3. When using a combination of SRDY2 output and SSTB2 output or a combination of SBUSY2 output
and SSTB2 output of the handshake signal
The transfer interval can be set in the range of 2 to 23 cycles using the automatic transfer interval
set bit (bits 0–4 of address 034816 ).
Also, when using SBUSY2 output as a signal for each occurrence of the all transfer data, a transfer
interval is inserted before the system starts sending or receiving the first data and after the system
finished sending or receiving the last data, not just between one data and another.
Furthermore, when using SSTB2 output, the transfer interval between each 1-byte data is extended
by 2 cycles from the set value no matter how the SBUSY2 output. SSTB2 output function select bit (bit
4 of address 034416) is set.
When using SBUSY2 output and SSTB2 output in combination as a signal for each occurrence of the
all transfer data, the transfer interval after the system finished sending or receiving the last data is
extended by 2 cycles from the set value.
When an external synchronous clock is selected, the automatic transfer interval is disabled.
107
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When the internal synchronous clock is selected, automatic serial transfer starts by writing 1 less than
the number of transfer bytes to the transfer counter (address 034616). When an external sync clock is
selected, automatic serial transfer starts by writing 1 less than the number of transfer bytes to the
transfer counter and the transfer clock is input. In this case, allow for at least 5 cycles of internal
system clock before the transfer clock is input after writing to the transfer counter.
Also, for data to data transfer intervals, allow at least 5 cycles of internal system clock reckoning from
a rise of clock at the last bit of one-byte data.
Regardless of whether the internal or external synchronous clock is selected, the automatic transfer
data pointer and the transfer counter are decreased after each 1-byte data is received and then written
into the automatic transfer RAM. The serial transfer status flag (bit5 of address 0344 16) is set to “1” by
writing data into the transfer counter. The serial transfer status flag is reset to “0” after the last data is
written into the automatic transfer RAM. At the same time, a serial I/O2 interrupt request occurs.
The values written in the automatic transfer data pointer (address 034016) and the automatic transfer
interval set bits (bit 0 to bit 4 of address 034816) are held in the latch.
When data is written into the transfer counter, the values latched in the automatic transfer data pointer
(address 034016) and the automatic transfer interval set bits (bit 0 to bit 4) are transferred to the
decrement counter.
Automatic transfer RAM
004FF16
Automatic transfer
data pointer
5216
0045216
0045116
0045016
0044F16
0044E16
Transfer counter
0416
0040016
SIN2
SOUT2
Serial I/O2 register
Figure 90. Automatic Transfer Serial I/O Operation
108
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Handshake Signal
There are five types of handshake signal : SSTB2 output, SBUSY2 input/output, and SRDY2 input/output.
(1) SSTB2 output signal
The SSTB2 output is a signal to inform an end of transmission/reception to the serial transfer destination. The SSTB2 output signal can be used only when the internal synchronous clock is selected. In the
initial status [ serial I/O initialization bit (bit
4 of address 034216) = “0” ], the SSTB2 output goes to “L”
__________
(bits 2, 3 of address 034216=11), or the SSTB2 output goes to “H” (bits 2, 3 of address 034216=10).
At the end of transmit/receive operation, after the all data of the serial I/O2 register (address 034616) is
_________
output from SOUT2, SSTB2 output is “H” (or SSTB2 output is “L”) in the period of 1 cycle of the transfer clock.
Furthermore, after 1 cycle, the serial transfer status flag (bit 5 of address 034416) is reset to “0”.
In the automatic transfer serial I/O mode, whether the SSTB2 output is to be output at an end of each 1-byte
data or after completion of transfer of all data can be selected by the S BUSY2 output • SSTB2 output function
select bit (bit 4 of address 034416).
•Serial operation used SSTB2 output
Operation mode
: 8-bit serial I/O mode
: Internal synchronous clock
: Each 1-byte data
Transfer clock
SSTB2 output timing
Tc
Internal clock
Serial transfer status flag "1"
(bit 5 at address 034416)
"0"
SCLK2i
(i=1, 2)(output)
"H"
SSTB2(output)
"L"
SOUT2
D0
D1
D2
D3
D4 D5
D6
D7
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816
•Serial operation used SSTB2 output
Operation mode
Tc
: Automatic transfer serial I/O mode
: Internal synchronous clock
: Each transfer of all data
Automatic
transfer interval
D0
D1 D2
Transfer clock
SSTB2 output timing
Internal clock
Serial transfer status flag "1"
(bit 5 at address 034416) "0"
SCLK2i
(i=1, 2)(output)
"H"
SSTB2(output)
"L"
SOUT2
D3
D4
D5
D6 D7
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816
Figure 91. SSTB2 Output Operation
109
D0
D1
D2
D3
D4 D5
D6
D7
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) SBUSY2 input signal
The SBUSY2 input is a signal requested to stop of transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input a “H” level signal into the SBUSY2 input (or a “L”
___________
level signal into the SBUSY2 input) in the initial status [serial I/O initialization bit (bit 4 of address
____________
034216) = “0”]. When a “L” level signal into the SBUSY2 ( or “H” on SBUSY2 ) input for 1.5 cycles or more
of transfer clock, transfer clocks are output from SCLK2i (i = 1, 2), and transmit/receive operation is
____________
started. When SBUSY2 input is driven “H” (or SBUSY2 input is driven “L”) during transmit/receive
operation, the transfer clock being output from SCLK2i (i = 1, 2) remains active until after the system
finishes sending or receiving the designated number of bits, without stopping the transmit/receive
operation immediately. The handshake unit of the 8-bit serial I/O is 8 bits, and that of the automatic
transfer serial I/O is 8 bits.
•Serial operation used SBUSY2 input
Operation mode
: 8-bit serial I/O mode
: Internal synchronous clock
: Each 1-byte data
Transfer clock
SBUSY2 input timing
Tc
Internal clock
Serial transfer status flag "1"
(bit 5 at address 034416) "0"
SBUSY2(input)
1.5 cycle or more
"H"
"L"
SCLK2i
(i = 1, 2)(output)
SOUT2
D0
D1
D2
D3
D4 D 5
D6
D7
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816
Figure 92. SBUSY2 Input Operation (1)
When the external synchronous clock is selected, input a “H” level signal into the SBUSY2 input (or a “L”
___________
level signal into the SBUSY2 input) in the initial status[serial I/O initialization bit (bit 4 of address 034216)
= “0”]. At this time, the transfer clock become invalid. The transfer clock become valid while a “L” level
___________
signal is input into the SBUSY2 input (or a “H” level signal into the SBUSY2 input) and transmit/receive
operation work.
___________
When changing the input values into the SBUSY2 (or SBUSY2) input at these operations, change them
when the transfer clock input is in a “H” state. When the high-impedance of the SOUT2 output is
selected by the SOUT2 pin control bit (bit 6 of address 034416), the SOUT2 becomes high-impedance,
___________
while a “H” level signal is input into the SBUSY2 input (or a “L” level signal into the SBUSY2 input.)
•Serial operation used SBUSY2 input
Operation mode
Transfer clock
SBUSY2 input timing
Serial transfer status flag
(bit 5 at address 034416)
: 8-bit serial I/O mode
: External synchronous clock
: Each 1-byte data
"1"
"0"
"H"
SBUSY2(input)
"L"
SCLK2i
(i = 1, 2)(input)
Invalid
SOUT2
High-impedance
Note D0
D1
Note: The last output data
Figure 93. SBUSY2 Input Operation (2)
110
D2 D 3
D4
D5
D6
D7
High-impedance
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) SBUSY2 output signal
The SBUSY2 output is a signal which requests to stop of transmission/reception to the serial transfer
destination. In the automatic transfer serial I/O mode, regardless of the internal or external synchronous clock, whether the SBUSY2 output is to be output at transfer of each 1-byte data or during transfer
of all data can be selected by the SBUSY2 output • SSTB2 output function select bit (bit 4 of address
034416). In the initial status[ serial I/O initialization bit (bit 4 of address 034216) = “0” ], the status in
____________
which the SBUSY2 outputs “H” (or the SBUSY2 outputs “L”).
When the internal synchronous clock is selected, in the 8-bit serial I/O mode and the automatic transfer serial I/O mode (SBUSY2 output function: each 1-byte signal is selected), the SBUSY2 output goes to
____________
“L” (or the SBUSY2 output goes to “H”) before 0.5 cycle of the timing at which the transfer clock goes to
“L” . In the automatic transfer serial I/O mode (the SBUSY2 output function: all transfer data is selected),
____________
the SBUSY2 output goes to “L” (or the SBUSY2 output goes to “H”) when the first transmit data is written
into the serial I/O2 register (address 034616).
•Serial operation used SBUSY2 output
Operation mode
: 8-bit serial I/O mode
: Internal synchronous clock
: Each 1-byte data
Transfer clock
SBUSY2 output timing
Tc
Internal clock
Serial transfer status flag
(bit 5 at address 034416)
"1"
"0"
SCLK2i
(i = 1, 2)(output)
"H"
SBUSY2(output)
"L"
SOUT2
D0
D1
D2
D3
D4 D5
D6
D7
TC : Internal synchronous clock is selected by bits 5 to 7 of address 034816
Figure 94. SBUSY2 Output Operation (1)
____________
When the external synchronous clock is selected, the SBUSY2 output goes to “L” (or the SBUSY2 output
goes to “H”) when transmit data is written into the serial I/O2 register(address 034616), regardless of
the serial I/O transfer mode.
At termination of transmit/receive operation, in the 8-bit serial I/O mode, the SBUSY2 output goes to “H”
____________
(or the SBUSY2 output returns to “L”), when the serial transfer status flag is set to “0”, regardless of
whether the internal or external synchronous clock is selected. Furthermore, in the automatic transfer
serial I/O mode (SBUSY2 output function: each 1-byte signal is selected), the SBUSY2 output goes to “H”
____________
(or the SBUSY2 output goes to “L”) each time 1-byte of receive data is written into the automatic transfer RAM.
•Serial operation used SBUSY2 output
Operation mode
Transfer clock
SBUSY2 output timing
Serial transfer status flag
(bit 5 at address 034416)
: 8-bit serial I/O mode
: External synchronous clock
: Each 1-byte data
"1"
"0"
SCLK2i
(i = 1, 2)(Input)
"H"
SBUSY2(output)
"L"
SOUT2
D0
D1
Write to serial I/O register
(Address 034616)
Figure 95. SBUSY2 Output Operation (2)
111
D2 D3
D4
D5
D6
D7
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
•Serial operation used SBUSY2 output
Operation mode
Transfer clock
SBUSY2 output timing
: Automatic transfer serial I/O mode
: Internal synchronous clock
: Each 1-byte data
Automatic
transfer interval
Tc
Internal clock
Serial transfer status flag "1"
(bit 5 at address 034416) "0"
Automatic transfer RAM
Serial I/O2 register
Serial I/O2 register
Automatic transfer RAM
"H"
SBUSY2(output)
"L"
SCLK2i
(i = 1, 2)(output)
SOUT2
D0 D1
D2
D3
D4
D5 D6
D7
D0
D1
D2
D 3 D4
D5
D6
D7
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816
•Serial operation used SBUSY2 output
Operation mode
Transfer clock
SBUSY2 output timing
: Automatic transfer serial I/O mode
: Internal synchronous clock
: Each transfer of all data
Automatic
transfer interval
Tc
Internal clock
Serial transfer status flag "1"
(bit 5 at address 034416) "0"
Automatic transfer RAM
Serial I/O2 register
Serial I/O2 register
Automatic transfer RAM
"H"
SBUSY2(output)
"L"
SCLK2i
(i = 1, 2)(output)
SOUT2
D0
D1
D2 D 3
D4
D5
D6
D7
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816
Figure 96. SBUSY2 Output Operation (3)
112
D0 D1
D2
D3
D4
D5 D6
D7
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) SRDY2 output signal
The SRDY2 output is a transmit/receive enable signal which informs the serial transfer destination that
transmit/receive is ready. In the initial status[serial I/O initialization bit (bit 4 of address 034216) = “0” ],
__________
the SRDY2 output goes to “L” (or the SRDY2 output goes to “H”). When the transmitted data is written to
__________
the serial I/O2 register (address 034616), the SRDY2 output goes to “H” (or the SRDY2 output goes to
“L”). When a transmit/receive operation is started and the transfer clock goes to “L”, the SRDY2 output
__________
goes to “L” (or the SRDY2 output goes to “H”).
•Serial operation used SRDY2 output
Operation mode
Transfer clock
: 8-bit serial I/O mode
: Internal synchronous clock
Tc
Internal clock
"H"
SRDY2
(output) "L"
SCLK2i
(i = 1, 2) (output)
SOUT2
D0
D1
D2
D3 D 4
D5
D6
D7
Serial transfer status flag "1"
(bit 5 at address 034416) "0"
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816
Figure 97. SRDY2 Output Operation
(5) SRDY2 input signal
The SRDY2 input is a signal for receiving a transmit/receive ready completion signal from the serial
transfer destination. The SRDY2 input signal becomes valid only when the SRDY2 input and the SBUSY2
output are used.
When the internal synchronous clock is selected, input a “L” level signal into the S RDY2 input (or a “H”
__________
level signal into the SRDY2 input) in the initial status[serial I/O initialization bit (bit 4 of address 034216)
__________
= “0” ]. When a “H” level signal is input into the SRDY2 input (or a “L” level signal is input into the SRDY2
input) for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the SCLK2i (i =
__________
1, 2) output and a transmit/receive operation is started. When SRDY2 input is driven “L” (or SRDY2 input
is driven “H”) during transmit/receive operation, the transfer clock being output from S CLK2i (i = 1, 2)
remains active until after the system finishes sending or receiving the designated number of bits,
without stopping the transmit/receive operation immediately.
The handshake unit of the 8-bit serial I/O is 8 bits, and that of the automatic transfer serial I/O is 8 bits.
When the external synchronous clock is selected, the SRDY2 input becomes one of the triggers to
____________
output the SBUSY2 signal. To start a transmit/receive operation (SBUSY2 output: “L”, (or SBUSY2 output:
__________
“H”)), input a “H” level signal into the SRDY2 input (or a “L” level signal into the SRDY2 input,) and also
write transmit data into the serial I/O2 register (address 034616).
•Serial operation used SRDY2 input
Operation mode
Transfer clock
: 8-bit serial I/O mode
: Internal synchronous clock
Tc
Internal clock
Serial transfer status flag "1"
(bit 5 at address 034416) "0"
1.5 cycle or more
"H"
SRDY2
(input)
"L"
SCLK2i
(i = 1, 2) (output)
SOUT2
D0
D1
D2
D3
D 4 D5
D6
D7
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816
Figure 98. SRDY2 Input Operation
113
Mitsubishi microcomputers
M30218 Group
Serial I/O2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SCLK2i
(i = 1, 2)
SRDY2
SBUSY2
SCLK2i
(i = 1, 2)
A:
SRDY2
Write to serial
I/O2 register
SRDY2
SBUSY2
SBUSY2
A:
SCLK2i
(i = 1, 2)
B:
Internal synchronous
clock selection
External synchronous
clock selection
B:
Write to serial
I/O2 register
Figure 99. Handshake Operation at Serial I/O2 Mutual Connecting (1)
SCLK2i
SCLK2i
(i= 1, 2)
(i= 1, 2)
SRDY2
SRDY2
SBUSY2
A:
Write to serial
I/O2 register
SRDY2
SBUSY2
SBUSY2
A:
Internal synchronous
clock selection
SCLK2i
(i= 1, 2)
B:
External synchronous
clock selection
B:
Write to serial
I/O2 register
Figure 100. Handshake Operation at Serial I/O2 Mutual Connecting (2)
114
Mitsubishi microcomputers
M30218 Group
A-D converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P100 to P107 also function as the analog signal input pins. The direction registers of
these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D7 16)
can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF)
when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from
VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting
bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision,
the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit
precision, the low 8 bits are stored in the even addresses.
Table 30 shows the performance of the A-D converter. Figure 101 shows the block diagram of the A-D
converter, and Figures 102 and 103 show the A-D converter-related registers.
Table 30. Performance of A-D converter
Item
Performance
Method of A-D conversion
Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock φAD (Note 2) VCC = 5V fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
VCC = 3V divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
Resolution
8-bit or 10-bit (selectable)
Absolute precision
VCC = 5V • Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• Without sample and hold function (10-bit resolution)
±3LSB
VCC = 3V • Without sample and hold function (8-bit resolution)(Note 3)
±2LSB
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins
8pins (AN0 to AN7)
A-D conversion start condition •Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
Conversion speed per pin
•Without sample and hold function
8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Without sample and hold function, set the φAD frequency to 250kHz min.
With the sample and hold function, set the φAD frequency to 1MHz min.
Note 3: Only mask ROM version.
115
Mitsubishi microcomputers
M30218 Group
A-D converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CKS1=1
AD
CKS0=1
fA D
1/2
1/2
CKS0=0
CKS1=0
A-D conversion
rate selection
VCUT=0
AVSS
VCUT=1
VREF
Resistor ladder
Successive conversion register
A-D control register 1 (address 03D716)
A-D control register 0 (address 03D616)
Addresses
(03C116, 03C016)
(03C316, 03C216)
(03C516, 03C416)
(03C716, 03C616)
(03C916, 03C816)
A-D register 0(16)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
(03CD16, 03CC16)
A-D register 4(16)
A-D register 5(16)
A-D register 6(16)
(03CF16, 03CE16)
A-D register 7(16)
(03CB16, 03CA16)
Vref
Decoder
VI N
Data bus high-order
Data bus low-order
AN0
CH2,CH1,CH0=000
AN1
CH2,CH1,CH0=001
AN2
CH2,CH1,CH0=010
AN3
CH2,CH1,CH0=011
AN4
CH2,CH1,CH0=100
AN5
CH2,CH1,CH0=101
AN6
CH2,CH1,CH0=110
AN7
CH2,CH1,CH0=111
Figure 101. Block diagram of A-D converter
116
Comparator
Mitsubishi microcomputers
M30218 Group
A-D converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000XXX2
Bit name
Function
RW
b2 b1 b0
CH0
Analog input pin select bit
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
A-D operation mode
select bit 0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
CH1
CH2
MD0
MD1
b4 b3
Must always be “0”.
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
CKS0
Frequency select bit 0
A-D control register 1 (Note)
b7
b6
0 0
b5
b4
b3
b2
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
A-D sweep pin select
bit
Function
R W
When single sweep and repeat sweep
mode 0 are selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
When repeat sweep mode 1 is selected
SCAN1
b1 b0
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
MD2
BITS
CKS1
VCUT
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Vref connect bit
0 : Vref not connected
1 : Vref connected
Must always be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Figure 102. A-D converter-related registers (1)
117
Mitsubishi microcomputers
M30218 Group
A-D converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 2 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
ADCON2
03D416
XXXXXXX02
Bit symbol
SMP
Bit name
A-D conversion method
select bit
Function
R W
0 Without sample and hold
1 With sample and hold
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
A-D register i
(b15)
b7
(b8)
b0 b7
ADi (i=0 to 7)
Address
When reset
03C016 to 03CF16 Indeterminate
b0
Function
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
When read, the content is indeterminate
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be “0”.
Figure 103. A-D converter-related registers (2)
118
R W
Mitsubishi microcomputers
M30218 Group
A-D converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table
31 shows the specifications of one-shot mode. Figure 104 shows the A-D control register in one-shot mode.
Table 31. One-shot mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Start condition
Writing “1” to A-D conversion start flag
Stop condition
•End of A-D conversion (A-D conversion start flag changes to “0”)
•Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
One of AN0 to AN7, as selected
Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
Bit name
Function
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
CH2
MD1
RW
b2 b1 b0
Analog input pin
select bit
CH1
MD0
When reset
00000XXX2
b4 b3
A-D operation mode
select bit 0
0 0 : One-shot mode
Must always be “0”.
ADST
CKS0
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
0: fAD/4 is selected
Frequency select bit 0
1: fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
A-D control register 1 (Note)
b7
b6
b5
0 0 1
b4
b3
b2
0
b1
b0
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin
select bit
Invalid in one-shot mode
MD2
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
BITS
8/10-bit mode select bit
CKS1
Frequency select bit1
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
VCUT
Vref connect bit
SCAN0
R W
SCAN1
1 : Vref connected
Must always be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Figure 104. A-D conversion register in one-shot mode
119
Mitsubishi microcomputers
M30218 Group
A-D converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table
32 shows the specifications of repeat mode. Figure 105 shows the A-D control register in repeat mode.
Table 32. Repeat mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Star condition
Writing “1” to A-D conversion start flag
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
One of AN0 to AN7, as selected
Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
Bit name
Function
Analog input pin
select bit
b2 b1 b0
A-D operation mode
select bit 0
b4 b3
CH2
MD1
RW
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
CH1
MD0
When reset
00000XXX2
0 1 : Repeat mode
Must always be “0”.
ADST
A-D conversion start flag
CKS0
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversin
result is indeterminate.
A-D control register 1 (Note)
b7
b6
b5
0 0 1
b4
b3
b2
0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin select bit Invalid in repeat mode
SCAN1
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
VCUT
Vref connect bit
1 : Vref connected
MD2
BITS
Must always be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversn
result is indeterminate.
Figure 105. A-D conversion register in repeat mode
120
R W
Mitsubishi microcomputers
M30218 Group
A-D converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. Table 33 shows the specifications of single sweep mode. Figure 106 shows the A-D control
register in single sweep mode.
Table 33. Single sweep mode specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Start condition
Writing “1” to A-D converter start flag
Stop condition
•End of A-D conversion
(A-D conversion start flag changes to “0”, except when external trigger is selected)
•Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
0 1 0
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000XXX2
Bit name
Function
RW
Analog input pin select bit Invalid in single sweep mode
CH1
CH2
MD0
A-D operation mode
select bit 0
b4 b3
1 0 : Single sweep mode
MD1
Must always be “0”.
ADST
A-D conversion start flag
CKS0
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note)
b7
b6
b5
0 0 1
b4
b3
b2
0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin select bit
R W
When single sweep and repeat sweep mode 0
are selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
BITS
A-D operation mode
select bit 1
8/10-bit mode select bit
CKS1
Frequency select bit 1
VCUT
Vref connect bit
MD2
0 : Any mode other than repeat sweep mode 1
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
1 : Vref connected
Must always be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Figure 106. A-D conversion register in single sweep mode
121
Mitsubishi microcomputers
M30218 Group
A-D converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. Table 34 shows the specifications of repeat sweep mode 0. Figure 107 shows the A-D
control register in repeat sweep mode 0.
Table 34. Repeat sweep mode 0 specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion
Start condition
Writing “1” to A-D conversion start flag
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
0 1 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000XXX2
Bit name
Function
RW
Analog input pin select bit Invalid in repeat sweep mode 0
CH1
CH2
MD0
A-D operation mode
select bit 0
b4 b3
1 1 : Repeat sweep mode 0
MD1
Must always be “0”.
ADST
A-D conversion start flag
CKS0
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note)
b7
b6
b5
0 0 1
b4
b3
b2
0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin select bit
R W
When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
BITS
A-D operation mode
select bit 1
8/10-bit mode select bit
CKS1
Frequency select bit 1
VCUT
Vref connect bit
MD2
1 : Any mode other than repeat sweep mode 1
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
1 : Vref connected
Must always be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Figure 107. A-D conversion register in repeat sweep mode 0
122
Mitsubishi microcomputers
M30218 Group
A-D converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected
using the A-D sweep pin select bit. Table 35 shows the specifications of repeat sweep mode 1. Figure
108 shows the A-D control register in repeat sweep mode 1.
Table 35. Repeat sweep mode 1 specifications
Item
Specification
All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected -> AN0 -> AN1 -> AN0 -> AN2 -> AN0 -> AN3, etc
Start condition
Writing “1” to A-D conversion start flag
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
Emphasis on the pin AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins)
Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time)
Function
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
0 1 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000XXX2
Bit name
Function
RW
Analog input pin select bit Invalid in repeat sweep mode 0
CH1
CH2
MD0
A-D operation mode
select bit 0
b4 b3
1 1 : Repeat sweep mode 1
MD1
Must always be “0”.
ADST
A-D conversion start flag
CKS0
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note)
b7
b6
b5
0 0 1
b4
b3
b2
1
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin select bit
R W
When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0 (1 pins)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
SCAN1
BITS
A-D operation mode
select bit 1
8/10-bit mode select bit
CKS1
Frequency select bit 1
VCUT
Vref connect bit
MD2
1 : Repeat sweep mode 1
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
1 : Vref connected
Must always be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Figure 108. A-D conversion register in repeat sweep mode 1
123
Mitsubishi microcomputers
M30218 Group
A-D converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(a) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”.
When sample and hold is selected, the rate of conversion of each pin increases. As a result, 28 φ AD
cycles are achieved with 8-bit resolution and 33 φ AD cycles with 10-bit resolution. Sample and hold
can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion
whether sample and hold is to be used.
124
Mitsubishi microcomputers
M30218 Group
D-A converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A
output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the
target port to output mode if D-A conversion is to be performed.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 36 lists the performance of the D-A converter. Figure 109 shows the block diagram of the D-A
converter. Figure 110 shows the D-A control register. Figure 111 shows the D-A converter equivalent
circuit.
Table 36. Performance of D-A converter
Item
Conversion method
Resolution
Analog output pin
Performance
R-2R method
8 bits
2 channels
Data bus low-order bits
D-A register0 (8)
(Address 03D816)
AAAAAAA
AAAAAAA
D-A0 output enable bit
P97/DA0/CLKOUT/DIMOUT
R-2R resistor ladder
D-A register1 (8)
(Address 03DA16)
AAAAAA
D-A1 output enable bit
P96/DA1/SCLK22
R-2R resistor ladder
Figure 109. Block diagram of D-A converter
125
Mitsubishi microcomputers
M30218 Group
D-A converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A control register
b7
b6
b5
b4
b3
b2
b1
Symbol
DACON
b0
Address
03DC16
Bit symbol
When reset
0016
Bit name
Function
DA0E
D-A0 output enable bit
0 : Output disabled
1 : Output enabled
DA1E
D-A1 output enable bit
0 : Output disabled
1 : Output enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
D-A register
b7
Symbol
DAi (i = 0,1)
b0
Address
03D816, 03DA16
When reset
Indeterminate
Function
R
RW
W
Output value of D-A conversion
Figure 110. D-A control register
D-A0 output enable bit
"0"
R
R
R
R
2R
2R
2R
2R
R
R
R
2R
DA0
"1"
2R
MSB
2R
2R
2R
LSB
D-A0 register0
AVSS
VREF
Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16.
Note 2: The same circuit as this is also used for D-A1.
Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016
so that no current flows in the resistors Rs and 2Rs.
Figure 111. D-A converter equivalent circuit
126
Mitsubishi microcomputers
M30218 Group
CRC Calculation Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC
code is set in a CRC data register each time one byte of data is transferred to a CRC input register after
writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed in two machine cycles.
Figure 112 shows the block diagram of the CRC circuit. Figure 113 shows the CRC-related registers.
Figure 114 shows the calculation example using the CRC calculation circuit
Data bus high-order bits
AAAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAA
AAAAAA
Data bus low-order bits
Eight low-order bits
Eight high-order bits
CRC data register (16)
(Addresses 03BD16, 03BC16)
CRC code generating circt
x16 + x12 + x5 + 1
CRC input register (8)
(Address 03BE16)
Figure 112. Block diagram of CRC circuit
CRC data register
(b15)
b7
(b8)
b0 b7
b0
Symbol
CRCD
Address
03BD16, 03BC16
When reset
Indeterminate
Values that
can be set
Function
CRC calculation result output register
RW
000016 to FFFF16
CRC input register
b7
Symbo
CRCIN
b0
Function
Data input register
Address
03BE16
When reset
Indeterminate
Values that
can be set
0016 to FF16
Figure 113. CRC-related registers
127
RW
Mitsubishi microcomputers
M30218 Group
CRC Calculation Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
b15
b0
CRC data register CRCD
[03BD16, 03BC16]
(1) Setting 000016
b7
b0
CRC input register
(2) Setting 0116
CRCIN
[03BE16]
2 cycles
After CRC calculation is complete
b15
b0
CRC data register
118916
CRCD
[03BD16, 03BC16]
Stores CRC code
The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
(X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
LSB
MSB
1000 1000
1 0001 0000 0010 0001
9
1000 0000 0000
1000 1000 0001
1000 0001
1000 1000
1001
LSB
8
1
0000
0000
0000
0001
0001
0000
1
1000
0000
1000
0000
Modulo-2 operation is
operation that complies
with the law given below.
0+0=0
0+1=1
1+0=1
1+1=0
-1 = 1
0
1
1000
MSB
1
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
b7
b0
CRC input register
(3) Setting 2316
CRCIN
[03BE16]
After CRC calculation is complete
b15
b0
0A4116
CRC data register
Stores CRC code
Figure 114. Calculation example using the CRC calculation circuit
128
CRCD
[03BD16, 03BC16]
Mitsubishi microcomputers
M30218 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
There are 48 programmable I/O ports: P3, P4 and P7 to P10. Each port can be set independently for input
or output using the direction register. A pull-up resistance for each block of 4 ports can be set.
P3 and P40 to P4 3 are high-breakdown-voltage, P-channel open drain outputs, and have no built-in pulldown resistance.
Figures 115, 116 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are to be
used as the outputs for the D-A converter, do not set the direction registers to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 117 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin.
(2) Port registers
Figure 118 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 119 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
Note: P3, P40 to P4 3 have no built-in pull-up resistance, because of these pin's are high-breakdownvoltage, P-channel open drain outputs.
Exclusive High-breakdown-voltage Output Ports
There are 40 exclusive output Ports: P0 to P2, P5 and P6.
All ports have structure of high-breakdown-voltage P-channel open drain output. Exclusive output ports
except P2 have built-in pull-down resistance.
Figure UA-1 shows the configuration of the exclusive high-breakdown-voltage output ports.
129
Mitsubishi microcomputers
M30218 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P00 to P07, P10 to P17,
P50 to P57, P60 to P67,
(inside dotted-line included)
P20 to P27
(inside dotted-line not included)
Output
Data bus
Port latch
VEE
P30 to P37, P40 to P43
Direction register
“1”
Data bus
P70 to P72, P80 to P85, P87, P93
(inside dotted-line included)
P86
(inside dotted-line not included)
Data bus
Port latch
output
Pull-up selection
Direction register
Port latch
Input to respective peripheral functions
Pull-up selection
P44, P92,P94
Direction register
“1”
Data bus
Port latch
Figure 115. Programmable I/O ports (1)
130
output
Mitsubishi microcomputers
M30218 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up selection
P45 to P47, P73 to P77
P90, P91, P95
Direction register
“1”
Data bus
output
Port latch
Input to respective peripheral functions
Pull-up selection
P100 to P107
Direction register
Data bus
Port latch
Analog input
P96
(inside dotted-line included)
P97
(inside dotted-line not included)
Data
bus
Pull-up selection
Direction register
“1”
Port latch
output
Analog output
D-A output enabled
Input to respective peripheral functions
Figure 116. Programmable I/O ports (2)
131
Mitsubishi microcomputers
M30218 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port Pi direction register
b7
b6
b5
b4
b3
b2
b1
Symbol
PDi (i = 3 to 10, except 5, 6)
b0
Bit symbol
Address
03E716, 03EA16, 03EF16
03F216, 03F316, 03F616
Bit name
PDi_0
Port Pi0 direction register
PDi_1
Port Pi1 direction register
PDi_2
Port Pi2 direction register
PDi_3
Port Pi3 direction register
PDi_4
Port Pi4 direction register
PDi_5
Port Pi5 direction register
PDi_6
Port Pi6 direction register
PDi_7
Port Pi7 direction register
When reset
0016
0016
Function
RW
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 3 to 10 except 5, 6)
Figure 117. Direction register
Port Pi register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Pi (i = 0 to 10)
Bit symbol
Addres
03E016, 03E116, 03E416, 03E516, 03E816
03E916, 03EC16, 03ED16, 03F016, 03F116, 03F416
Bit name
Pi_0
Port Pi0 register
Pi_1
Port Pi1 register
Pi_2
Port Pi2 register
Pi_3
Port Pi3 register
Pi_4
Port Pi4 register
Pi_5
Port Pi5 register
Pi_6
Port Pi6 register
Pi_7
Port Pi7 register
Figure 118. Port register
132
When reset
Indeterminate
Indeterminate
Function
Data is input and output to and from
each pin by reading and writing to and
from each corresponding bit
0 : “L” level data
1 : “H” level data
(i = 0 to 10)
RW
Mitsubishi microcomputers
M30218 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR0
Bit symbol
Address
03FD16
Bit name
When reset
0016
Function
RW
Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if
read, turns out to be indeterminate.
PU01
P44 to P47 pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
PU06
P70 to P73 pull-up
PU07
P74 to P77 pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Pull-up control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR1
Bit symbol
PU10
Address
03FE16
Bit name
P80 to P83 pull-up
PU11
P84 to P87 pull-up
PU12
PU13
P90 to P93 pull-up
P94 to P97 pull-up
PU14
P100 to P103 pull-up
PU15
P104 to P107 pull-up
When reset
0016
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if
read, turns out to be indeterminate.
Figure 119. Pull-up control register
133
R W
Mitsubishi microcomputers
M30218 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 37. Example connection of unused pins
Pin name
Connection
Ports P3, P4, P7 to P10
Specify output mode, and leave these pins open;
or specify input mode, and connect to VSS via resistor (pull-down)
Ports P0 to P2, P5, P6
Leave these pins open
XOUT (Note 1), VEE
Open
AVCC
Connect to VCC (Note 2)
AVSS, VREF
Connect to VSS (Note 2)
CNVSS
Connect to VSS via resistor
Note 1: With external clock input to XIN pin.
Note 2: Connect a bypass capacitor.
Microcomputer
Port P3, P4, P7 to P10
(Input mode)
(Output mode)
Open
Port P0 to P2, P5, P6
(Output mode)
Open
XOUT
Open
Open
VEE
VCC
AVCC(Note 1)
CNVSS
AVSS(Note 1)
VREF(Note 1)
VSS
Note 1: Connect a bypass capacitor.
Figure 120. Example connection of unused pins
134
Mitsubishi microcomputers
M30218 Group
Pull-down
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Dissipation Calculating Method
(Fixed number depending on microcomputer’s standard)
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value = 68 k (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW
(Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number a; digit number b; segment number c
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: d
• All segment number during repeat cycle: e (= a X c)
• Total number of built-in resistor: for digit; f, for segment; g
• Digit pin current value h (mA)
• Segment pin current value i (mA)
(1) Digit pin power dissipation
{h X b X (1–Toff / Tdisp) X voltage} / a
(2) Segment pin power dissipation
{i X d X (1–Toff / Tdisp) X voltage} / a
(3) Pull-down resistor power dissipation (digit)
{power dissipation per 1 digit X (b X f / b) X (1–Toff / Tdisp) } / a
(4) Pull-down resistor power dissipation (segment)
{power dissipation per 1 segment X (d X g / c) X (1–Toff / Tdisp) } / a
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190 mW
(1) + (2)+ (3) + (4) + (5) = X mW
135
Mitsubishi microcomputers
M30218 Group
Pull-down
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Dissipation Calculating example 1
Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW
Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number 17; digit number 16; segment number 20
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 31
• All segment number during repeat cycle: 340 (= 17 X 20)
• Total number of built-in resistor: for digit; 16, for segment; 20
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA)
(1) Digit pin power dissipation
{18 X 16 X (1–1/16) X 2} / 17 = 31.77 mW
(2) Segment pin power dissipation
{3 X 31 X (1–1/16) X 2} / 17 = 10.26 mW
(3) Pull-down resistor power dissipation (digit)
(50 – 2)2 /68 X (16 X 16/16) X (1 – 1/16) / 17 = 29.90 mW
(4) Pull-down resistor power dissipation (segment)
(50 – 2)2 /68 X (31 X 20/20) X (1 – 1/16) / 17 = 57.93 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190.00 mW
(1) + (2)+ (3) + (4) + (5) = 319.86 mW
DIG0
DIG1
DIG2
DIG3
DIG13
DIG14
DIG15
Timing
number
1
2
3
14
15
16
17
Repeat cycle
Tscan
Figure 121. Digit timing waveform (1)
136
Mitsubishi microcomputers
M30218 Group
Pull-down
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Dissipation Calculating example 2(when 2 or more digit is turned ON at same time)
Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW
Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114
• All segment number during repeat cycle: 264 (= 11 X 24)
• Total number of built-in resistor: for digit; 10, for segment; 22
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA)
(1) Digit pin power dissipation
{18 X 12 X (1–1 / 16) X 2} / 11 = 36.82 mW
(2) Segment pin power dissipation
{3 X 114 X (1–1 / 16) X 2} / 11 = 58.30 mW
(3) Pull-down resistor power dissipation (digit)
(50– 2)2 / 68 X (12 X 10 / 12) X (1 – 1 / 16) / 11 = 28.88 mW
(4) Pull-down resistor power dissipation (segment)
(50 – 2)2 / 68 X (114 X 22 / 24) X (1 – 1 / 16) / 11 = 301.77 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190.00 mW
(1) + (2)+ (3) + (4) + (5) = 615.77 mW (There is a limit of use temperature)
DIG0
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
Timing
number
1
2
3
4
5
6
7
8
9
10
11
Repeat cycle
Tscan
Figure 122. Digit timing waveform (2)
137
Mitsubishi microcomputers
M30218 Group
Pull-down
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Dissipation Calculating example 3
(when 2 or more digit is turned ON at same time, and used Toff invalid function)
Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA
• Resistor value 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW
Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114 ( for Toff invalid waveform;50)
• All segment number during repeat cycle: 264 (= 11 X 24)
• Total number of built-in resistor: for digit; 10, for segment; 22
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA)
(1) Digit pin power dissipation
[{18 X 10 X (1–1/16) X 2} + {18 X 2 X 2}] / 11 = 37.23 mW
(2) Segment pin power dissipation
[{3 X 64 X (1–1/16) X 2} + {3 X 50 X 2}] / 11 = 60.00 mW
(3) Pull-down resistor power dissipation (digit)
[{(50– 2)2 / 68 X (10 X 10 / 12) X (1 – 1 / 16)} + {(50– 2)2 / 68 X (2 X 10 / 12) } ] /11 = 29.20 mW
(4) Pull-down resistor power dissipation (segment)
[{(50– 2)2 / 68 X (64 X 22 / 24) X (1 – 1 / 16)} + {(50– 2)2 / 68 X (50 X 22 / 24) } ] / 11 = 310.59 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190.00 mW
(1) + (2)+ (3) + (4) + (5) = 627.02 mW (There is a limit of use temperature)
DIG0
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
Timing
number
1
2
3
4
5
6
7
8
9
10
11
Repeat cycle
Tscan
Figure 123. Digit timing waveform (3)
138
Mitsubishi microcomputers
M30218 Group
Electrical characteristics
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 38. Absolute maximum ratings
Parameter
Symbol
Vcc
AVcc
V
Analog supply voltage
- 0.3 to 6.5
V
Vcc - 50 to Vcc+0.3V
V
Pull-down supply voltage
VI
Input voltage
RESET, CNVss,
P44 to P47, P70 to P77, P80 to P87,
P90 to P97, P100 to P107,
VREF, XIN
VI
Input voltage
VO
Output voltage P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P43, P50 to P57,
P60 to P67
Output voltage P44 to P47, P70 to P77, P80 to P87,
P90 to P97, P100 to P107,
XOUT
Pd
Unit
- 0.3 to 6.5
VEE
VO
Standard
Condition
Supply voltage
- 0.3 to Vcc+0.3
(Note)
P30 to P37, P40 to P43
Power
dissipation
Topr
Operating ambient temperature
Tstg
Storage temperature
V
Vcc - 50 to Vcc+0.3
V
Vcc - 50 to Vcc+0.3
V
-0.3 to Vcc+0.3
V
Ta=-20 to 60 C
750
mW
Ta=60 to 85 C
750-12 X (Ta-60)
-20 to 85
mW
C
-40 to 150
C
Note 1: When writing to flash ,only CNVss is –0.3 to 13 (V) .
Table 39. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = – 20 to
85oC unless otherwise specified) (Note)
Parameter
Symbol
Vcc
Supply voltage
AVcc
Analog supply voltage
Vss
AVss
VEE
Pull-down supply voltage
Min
2.7(Note1)
Standard
Typ.
Max.
5.0
5.5
Unit
V
Vcc
V
Supply voltage
0
V
Analog supply voltage
0
V
Vcc-48
Vcc
V
0.8Vcc
Vcc
V
VIH
HIGH input voltage
P70 to P77, P80 to P87, P90 to P97, P100 to P107,
XIN, RESET, CNVSS
VIH
HIGH input voltage
P44 to P47
0.50Vcc
Vcc
V
VIH
HIGH input voltage
P30 to P37, P40 to P43
0.52Vcc
Vcc
V
V IL
LOW input voltage
P70 to P77, P80 to P87, P90 to P97, P100 to P107,
XIN, RESET, CNVSS
0.2Vcc
V
V IL
LOW input voltage
P30 to P37, P40 to P43
0
0.16Vcc
V
V IL
LOW input voltage
P44 to P47
0
0.16Vcc
V
Note: VCC = 4.0V to 5.5V in flash memory version.
139
0
Mitsubishi microcomputers
M30218 Group
Electrical characteristics
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 40. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = – 20 to
85oC unless otherwise specified) (Note 6)
Symbol
Parameter
Min
Standard
Typ.
Max.
Unit
I OH (peak)
HIGH total peak output
current (Note 1)
P00 to P07, P50 to P57, P60 to P67
-240
mA
I OH (peak)
HIGH total peak output
current (Note 1)
P10 to P17, P20 to P27, P30 to P37, P40 to P43
-240
mA
I OH (peak)
HIGH total peak output
current (Note 1)
P44 to P47, P70 to P77, P80 to P85
-80
mA
I OH (peak)
HIGH total peak output
current (Note 1)
P86, P87, P90 to P97, P100 to P107
-80
mA
I OL (peak)
LOW total peak output
current (Note 1)
P44 to P47, P70 to P77, P80 to P85
80
mA
I OL (peak)
LOW total peak output
current (Note 1)
P86, P87, P90 to P97, P100 to P107
80
mA
I OH (avg)
HIGH total average
output current (Note 1)
P00 to P07, P50 to P57, P60 to P67
-120
mA
I OH (avg)
HIGH total average
output current (Note 1)
P10 to P17, P20 to P27, P30 to P37, P40 to P43
-120
mA
I OH (avg)
HIGH total average
output current (Note 1)
P44 to P47, P70 to P77, P80 to P85
-40
mA
I OH (avg)
HIGH total average
output current (Note 1)
P86, P87, P90 to P97, P100 to P107
-40
mA
I OL (avg)
LOW total average
output current (Note 1)
P44 to P47, P70 to P77, P80 to P85
40
mA
I OL (avg)
LOW total average
output current (Note 1)
P86, P87, P90 to P97, P100 to P107
40
mA
HIGH peak output
current (Note 2)
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
P40 to P43, P50 to P57, P60 to P67
-40
mA
I OH (peak)
HIGH peak output
current (Note 2)
P44 to P47, P70 to P77, P80 to P87
P90 to P97, P100 to P107
-10
mA
I OL (peak)
LOW peak output
current (Note 2)
P44 to P47, P70 to P77, P80 to P87
P90 to P97, P100 to P107
10
mA
I OH (avg)
HIGH average output
current (Note 3)
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
P40 to P43, P50 to P57, P60 to P67
I OH (avg)
HIGH average output
current (Note 3)
P44 to P47, P70 to P77, P80 to P87
I OL (avg)
LOW average output
current (Note 3)
I OH (peak)
P90 to P97, P100 to P107
P44 to P47, P70 to P77, P80 to P87
P90 to P97, P100 to P107
f (XIN)
Main clock input oscillation frequency (Note 4, 7)
f (XcIN)
Sub clock oscillation frequency (Note 4, 5)
Vcc=4.0V to 5.5V
0
Vcc=2.7V to 4.0V
0
-18
mA
-5
mA
5
mA
10
5 X Vcc-10
32.768
50
MHz
MHz
kHz
Note 1: The total output current is the sum of all the currents through the applicable ports. The total
average value measured over 100ms. The total peak current is the peak of all the currents.
Note 2: The peak output current is the peak current flowing in each port.
Note 3: The average output current in an average value measured over 100ms.
Note 4: When the oscillating frequency has a duty cycle of 50 %.
Note 5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency
on condition that f(XCIN) < f(XIN) / 3.
Note 6: VCC=4.0V to 5.5V in flash memory version.
Note 7: Relationship between main clock oscillation frequency and supply voltage.
Operating maximum frequency [MHZ]
Main clock input oscillation frequency
(No wait)
10.0
AAAAAA
AAAA
AAAAAA
AAAA
AAAAAA
AAAA
AAAA
AAAAAA
AAAAAA
AAAA
AAAAAA
AAAA
AAAAAA
AAAA
5 X VCC-10.000MHZ
3.5
0.0
2.7
4.0
5.5
Flash memory version
Supply voltage[V] (BCLK: no division)
140
Mitsubishi microcomputers
M30218 Group
Electrical characteristics (V CC=5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC=5V
o
Table 41. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25 C,
f(XIN) =10MHZ unless otherwise specified)
Symbol
VOH
Measuring condition
Parameter
HIGH output P00 to P07,P10 to P17,P20 to P27,
voltage
P30 to P37,P40 to P43,P50 to P57,
P60 to P67
VOH
HIGH output
voltage
VOH
HIGH output
voltage
VOL
LOW output
voltage
VOL
LOW output
voltage
Hysteresis
VT+-VT-
Standard
Min. Typ. Max.
IOH= - 18mA
3.5
IOH= - 5mA
4.5
IOH= - 5mA
3.0
V
P44 to P47,P70 to P77,P80 to P87,
P90 to P97,P100 to P107
XOUT
HIGH POWER
IOH= - 1mA
3.0
LOW POWER
IOH= - 0.5mA
3.0
P44 to P47,P70 to P77,P80 to P87,
P90 to P97,P100 to P107
XOUT
Unit
V
V
IOL=5mA
2.0
HIGH POWER
IOL=1mA
2.0
LOW POWER
IOL=0.5mA
2.0
TA0IN to TA4IN,TB0IN to TB2IN,
INT0 to INT5, CTS0, CTS1,
CLK0,CLK1,SRDY2IN,SBSY2IN,
V
V
0.2
0.8
V
0.2
1.8
V
SIN2,SCLK21,SCLK22,RxD0,
RxD1
VT+-VT-
Hysteresis
II H
HIGH input
current
P44 to P47,P70 to P77,P80 to P87,
P90 to P97,P100 to P107,
XIN, RESET, CNVss
VI=5V
5.0
µA
P30 to P37,P40 to P43(Note 1)
VI=5V
5.0
µA
LOW input
current
P44 to P47,P70 to P77,P80 to P87,
P90 to P97,P100 to P107,
XIN, RESET, CNVss
VI=0V
- 5.0
µA
P30 to P37,P40 to P43(Note1)
VI=0V
- 5.0
µA
Pull-up
resistance
P44 to P47,P70 to P77,
P80 to P87,P90 to P97,
P100 to P107
VI=0V
30.0
50.0
167.0
kΩ
RPULLD
Pull-down
resistance
P00 to P07,P10 to P17,
P50 to P57,P60 to P67
VEE=VCC - 48V,VOL=VCC
Output transistors “off”
68
80
120
kΩ
ILEAK
Output leak
current
P00 to P07,P10 to P17,
P20 to P27,P30 to P37,
P40 to P44,P50 to P57,
P60 to P67
VEE=VCC - 48V,VOL=VCC - 48V
Output transistors “off”
- 10
µA
IIH
II L
II L
RPULLUP
RESET
RfXIN
Feedback resistance XIN
1.0
MΩ
RfXCIN
Feedback resistance XCIN
6.0
MΩ
VRAM
RAM retention voltage
When clock is stopped
The output
pins are open
a n d o th e r
pins are VSS
f(XIN)=10MHz
Square wave, no division
f(XIN)=10MHz
Square wave, 8 division
f(XCIN)=32kHz
Square wave (Note2)
Icc
Power supply current (Note 3)
f(XCIN)=32kHz
2.0
V
19.0
38.0
4.2
mA
90.0
µA
4.0
µA
When a WAIT instruction is executed
(Note2)
Ta=25 C
when clock is stopped
1.0
Ta=85 C
when clock is stopped
20.0
µA
Note 1: Except when reading ports P3, P40 to P43.
Note 2: Fixed XCIN-XCOUT drive capacity select bit to “HIGH” and X IN pin to “H” level.
Note 3: This contains an electric current to flow into AVCC pin.
141
mA
Mitsubishi microcomputers
M30218 Group
Electrical characteristics (VCC=5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC=5V
Table 42. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS = 0V
at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified)
Symbol
RLADDER
tCONV
tCONV
tSAMP
VREF
VIA
Parameter
Measuring condition
Standard
Min. Typ. Max.
Unit
Resolution
VREF = VCC
10
Absolute
accuracy
Sample & hold function not available
V REF = VCC = 5V
±3
Bits
LSB
Sample & hold function available(10bit)
V REF =VCC AN0 to AN 7 input
= 5V
±3
LSB
Sample & hold function available(8bit)
V REF = VCC = 5V
±2
40
LSB
Ladder resistance
Conversion time (10bit)
Conversion time (8bit)
Sampling time
Reference voltage
Analog input voltage
VREF = VCC
10
3.3
2.8
0.3
kΩ
µs
2
VCC
µs
µs
V
0
VREF
V
Table 43. D-A conversion characteristics (referenced to VCC = 5V, VSS = AVSS = 0V, VREF = 5V
at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified)
Symbol
tsu
RO
IVREF
Parameter
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Measuring condition
Min.
4
(Note )
Standard
Typ. Max.
10
8
1.0
3
20
1.5
Unit
Bits
%
µs
kΩ
mA
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to
“0016”.
The A-D converter's ladder resistance is not included.
Also, when the Vref is unconnected at the A-D control register, IVREF is sent.
142
Mitsubishi microcomputers
M30218 Group
Timing (VCC=5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC=5V
o
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25 C unless otherwise specified)
Table 44. External clock input
Symbol
tc
tw(H)
tw(L)
tr
tf
Standard
Max.
Min.
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
Unit
ns
100
40
40
15
15
ns
ns
ns
ns
Switching characteristics (referenced to V CC = 5V, VSS = 0V at Ta = 25oC unless otherwise
specified)
Table 45. High-breakdown voltage p-channel open-drain output port
Symbol
tr(Pch-strg)
tr(Pch-weak)
Measuring condition
Parameter
P-channel high-breakdown
voltage output rising time
(Note 1)
P-channel high-breakdown
voltage output rising time
(Note 2)
Min.
Standard
Typ.
Max.
Unit
CL=100pF
VEE=VCC - 43V
55
ns
CL=100pF
VEE=VCC - 43V
1.8
µs
Note 1: When bit 7 of the FLDC mode register (address 035016) is at “0”.
Note 2: When bit 7 of the FLDC mode register (address 035016) is at “1”.
P0, P1, P2, P3,
P40 to P43, P5, P6
P-channel highbreakdown
voltage output
port (Note)
CL
VEE
Note: Ports P2, P3, and P40 to P43 need external resistors.
Figure 124. Circuit for measuring output switching characteristics
143
Mitsubishi microcomputers
M30218 Group
Timing (VCC=5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC=5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 46. Timer A input (counter input in event counter mode)
Symbol
Standard
Min.
Max.
100
40
Parameter
tc(TA)
TAiIN input cycle time
tw(TAH)
TAiIN input HIGH pulse width
tw(TAL)
TAiIN input LOW pulse width
40
Unit
ns
ns
ns
Table 47. Timer A input (gating input in timer mode)
Symbol
Standard
Min.
Max.
400
Parameter
tc(TA)
TAiIN input cycle time
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
200
200
Unit
ns
ns
ns
Table 48. Timer A input (external trigger input in one-shot timer mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Standard
Min.
Max.
Parameter
Unit
TAiIN input cycle time
200
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
100
100
ns
ns
Table 49. Timer A input (external trigger input in pulse width modulation mode)
Symbol
tw(TAH)
tw(TAL)
Standard
Min.
Max.
100
Parameter
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
100
Unit
ns
ns
Table 50. Timer A input (up/down input in event counter mode)
TAiOUT input cycle time
Standard
Min.
Max.
2000
TAiOUT input HIGH pulse width
1000
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
1000
400
Symbol
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
Parameter
400
144
Unit
ns
ns
ns
ns
ns
Mitsubishi microcomputers
M30218 Group
Timing (VCC=5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC=5V
o
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25 C unless otherwise specified)
Table 51. Timer B input (counter input in event counter mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input HIGH pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
40
200
ns
tc(TB)
tw(TBH)
TBiIN input HIGH pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN input LOW pulse width (counted on both edges)
80
ns
ns
Table 52. Timer B input (pulse period measurement mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
200
200
ns
ns
Table 53. Timer B input (pulse width measurement mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input HIGH pulse width
200
ns
tw(TBL)
TBiIN input LOW pulse width
200
ns
Table 54. Serial I/O
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input HIGH pulse width
100
ns
tw(CKL)
CLKi input LOW pulse width
100
td(C-Q)
TxDi output delay time
th(C-Q)
TxDi hold time
tsu(D-C)
RxDi input setup time
RxDi input hold time
th(C-D)
ns
80
ns
0
30
ns
90
ns
ns
_______
Table 55. External interrupt INTi inputs
Symbol
Standard
Parameter
Min.
Max.
Unit
tw(INH)
INTi input HIGH pulse width
250
ns
tw(INL)
INTi input LOW pulse width
250
ns
Table 56. Automatic transfer serial I/O
Symbol
tc(SCLK)
twH(SCLK)
twL(SCLK)
Standard
Parameter
Min.
Max.
Unit
0.95
µs
Serial I/O clock input HIGH pulse width
400
ns
Serial I/O clock input LOW pulse width
400
200
ns
ns
200
ns
Serial I/O clock input cycle time
tsu(SCLK-SIN) Serial I/O input setup time
th(SCLK-SIN) Serial I/O input hold time
145
Mitsubishi microcomputers
M30218 Group
Timing (VCC=5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC=5V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
th(TIN-UP) tsu(UP-TIN)
(When count on falling edge is selected)
TAiIN input
(When count on rising edge is selected)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TxDi
td(C-Q)
tsu(D-C)
th(C-D)
RxDi
tw(INL)
INTi input
tw(INH)
tC(SCLK)
tf(SCLK)
tr
tWL(SCLK)
tWH(SCLK)
SCLK
0.8VCC
0.2VCC
tSU(SiN-SCLK)
th(SCLK-SiN)
0.8VCC
0.2VCC
SIN
td(SCLK-SOUT)
tV(SCLK-SOUT)
SOUT
146
Mitsubishi microcomputers
Electrical characteristics(VCC=3V, only mask ROM version)
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC=3V
Table 57. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC,
f(XIN) =5MHZ unless otherwise specified)
Symbol
VOH
Measuring condition
Parameter
HIGH output P00 to P07,P10 to P17,P20 to P27,
voltage
P30 to P37,P40 to P43,P50 to P57,
P60 to P67
VOH
HIGH output P44 to P47,P70 to P77,P80 to P87,
voltage
P90 to P97,P100 to P107
VOH
HIGH output XOUT
voltage
VOL
VOL
LOW output
voltage
IOH= - 18mA
1.5
IOH= - 5mA
2.5
IOH= - 1mA
2.5
IOH= - 0.1mA
2.5
LOW POWER
IOH= - 50µA
2.5
P44 to P47,P70 to P77,P80 to P87,
P90 to P97,P100 to P107
V
V
IOL=1mA
0.5
HIGH POWER
IOL=0.1mA
0.5
LOW POWER
IOL=50µA
0.5
XOUT
Hysteresis
TA0IN to TA4IN,TB0IN to TB2IN,
INT0 to INT5, CTS0, CTS1,
Unit
V
HIGH POWER
LOW output
voltage
CLK0,CLK1,SRDY2IN,SBSY2IN,
VT+-VT-
Standard
Min. Typ. Max.
V
V
0.2
0.8
V
0.2
1.8
V
SIN2,SCLK21,SCLK22
RTS0,RTS1
VT+-VT-
Hysteresis
RESET
II H
HIGH input
current
P44 to P47,P70 to P77,P80 to P87,
P90 to P97,P100 to P107,
XIN, RESET, CNVss
VI=3V
4.0
µA
P30 to P37,P40 to P43(Note 1)
VI=3V
4.0
µA
P44 to P47,P70 to P77,P80 to P87,
P90 to P97,P100 to P107,
XIN, RESET, CNVss
VI=0V
- 4.0
µA
P30 to P37,P40 to P43(Note 1)
VI=0V
- 4.0
µA
Pull-up
resistance
P44 to P47,P70 to P77,
P80 to P87,P90 to P97,
P100 to P107
VI=0V
RPULLD
Pull-down
resistance
P00 to P07,P10 to P17,
P50 to P57,P60 to P67
VEE=VCC - 48V,VOL=VCC
Output transistors “off”
ILEAK
Output leak
current
P00 to P07,P10 to P17,
P20 to P27,P30 to P37,
P40 to P44,P50 to P57,
P60 to P67
VEE=VCC - 48V,VOL=VCC - 48V
Output transistors “off”
II H
II L
LOW input
current
IIL
RPULLUP
66.0
120.0
500.0
kΩ
68
80
120
kΩ
- 10
µA
RfXIN
Feedback resistance XIN
3.0
RfXCIN
Feedback resistance XCIN
10.0
VRAM
RAM retention voltage
When clock is stopped
The output
pins are open
a n d o th e r
pins are VSS
f(XIN)=5MHz
Square wave, no division
f(XIN)=5MHz
Square wave, 8 division
f(XCIN)=32kHz
Square wave
MΩ
MΩ
2.0
V
6.0
15.0
mA
1.6
mA
50.0
µA
2.8
µA
0.9
µA
f(XCIN)=32kHz
Icc
Power supply current (Note 3)
When a WAITinstruction
is executed.
Oscillation capacity High (Note2)
f(XCIN)=32kHz
When a WAIT instruction
is executed.
Oscillation capacity Low (Note2)
Ta=25 C
when clock is stopped
1.0
Ta=85 C
when clock is stopped
20.0
Note 1: Except when reading ports P3, P40 to P4 3.
Note 2: With one timer operated using fC32.
Note 3: This contains an electric current to flow into AVCC pin.
147
µA
Mitsubishi microcomputers
Electrical characteristics(VCC=3V, only mask ROM version)
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC=3V
Table 58. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 3V, Vss = AVSS = 0V
at Ta = 25oC, f(XIN) = 5MHZ unless otherwise specified)
Symbol
Parameter
Measuring condition
Resolution
VREF = VCC
Absolute accuracy Sample & hold function not available (8 bit)
RLADDER
tCONV
VREF
VIA
Standard
Min. Typ. Max
Ladder resistance
Conversion time (8bit)
Reference voltage
Analog input voltage
10
±2
40
VREF = VCC = 3V, φAD = f(X IN )/2
VREF = VCC
10
14.0
Unit
Bits
LSB
2.7
VCC
kΩ
µs
V
0
VREF
V
Table 59. D-A conversion characteristics (referenced to VCC = 3V, VSS = AVSS = 0V, VREF = 3V
at Ta = 25oC, f(XIN) = 5MHZ unless otherwise specified)
Symbol
tsu
RO
IVREF
Parameter
Measuring condition
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Standard
Min. Typ. Max
Unit
8
1.0
3
20
1.0
Bits
%
µs
kΩ
mA
4
(Note)
10
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”.
The A-D converter's ladder resistance is not included.
Also, when the Vref is unconnected at the A-D control register, IVREF is sent.
148
Mitsubishi microcomputers
M30218 Group
Timing(VCC=3V, only mask ROM version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC=3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 60. External clock input
Symbol
tc
tw(H)
tw(L)
tr
tf
Standard
Min.
Max.
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
200
85
85
18
18
149
Unit
ns
ns
ns
ns
ns
Mitsubishi microcomputers
M30218 Group
Timing(VCC=3V, only mask ROM version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC=3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 61. Timer A input (counter input in event counter mode)
Symbol
Standard
Min.
Max.
150
Parameter
Unit
tc(TA)
TAiIN input cycle time
tw(TAH)
TAiIN input HIGH pulse width
60
ns
ns
tw(TAL)
TAiIN input LOW pulse width
60
ns
Table 62. Timer A input (gating input in timer mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
600
ns
tw(TAH)
TAiIN input HIGH pulse width
300
ns
tw(TAL)
TAiIN input LOW pulse width
300
ns
Table 63. Timer A input (external trigger input in one-shot timer mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
300
tw(TAH)
TAiIN input HIGH pulse width
150
ns
tw(TAL)
TAiIN input LOW pulse width
150
ns
ns
Table 64. Timer A input (external trigger input in pulse width modulation mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tw(TAH)
TAiIN input HIGH pulse width
150
ns
tw(TAL)
TAiIN input LOW pulse width
150
ns
Table 65. Timer A input (up/down input in event counter mode)
Symbol
Standard
Parameter
tc(UP)
TAiOUT input cycle time
tw(UPH)
TAiOUT input HIGH pulse width
1500
tw(UPL)
TAiOUT input LOW pulse width
1500
ns
tsu(UP-TIN)
TAiOUT input setup time
600
ns
th(TIN-UP)
TAiOUT input hold time
600
ns
150
Max.
Unit
Min.
3000
ns
ns
Mitsubishi microcomputers
M30218 Group
Timing(VCC =3V, only mask ROM version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC=3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 66. Timer B input (counter input in event counter mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
tw(TBH)
TBiIN input HIGH pulse width (counted on one edge)
150
ns
60
ns
tw(TBL)
TBiIN input LOW pulse width (counted on one edge)
tc(TB)
TBiIN input cycle time (counted on both edges)
60
ns
300
tw(TBH)
TBiIN input HIGH pulse width (counted on both edges)
160
ns
ns
tw(TBL)
TBiIN input LOW pulse width (counted on both edges)
160
ns
Table 67. Timer B input (pulse period measurement mode)
Symbol
Standard
Parameter
Max.
Unit
tc(TB)
TBiIN input cycle time
Min.
600
tw(TBH)
TBiIN input HIGH pulse width
300
ns
tw(TBL)
TBiIN input LOW pulse width
300
ns
Standard
Min.
Max.
Unit
ns
Table 68. Timer B input (pulse width measurement mode)
Symbol
Parameter
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
TBiIN input HIGH pulse width
300
ns
tw(TBL)
TBiIN input LOW pulse width
300
ns
Table 69. Serial I/O
Symbol
Standard
Parameter
Min.
300
tc(CK)
CLKi input cycle time
tw(CKH)
CLKi input HIGH pulse width
150
tw(CKL)
CLKi input LOW pulse width
150
td(C-Q)
TxDi output delay time
th(C-Q)
TxDi hold time
tsu(D-C)
th(C-D)
Unit
Max.
ns
ns
ns
160
ns
0
ns
RxDi input setup time
50
ns
RxDi input hold time
90
ns
_______
Table 70. External interrupt INTi inputs
Symbol
Standard
Parameter
Min.
Max.
Unit
tw(INH)
INTi input HIGH pulse width
380
ns
tw(INL)
INTi input LOW pulse width
380
ns
Table 71. Automatic transfer serial I/O
Symbol
tc(SCLK)
Min.
Max.
Unit
2.0
µs
Serial I/O clock input HIGH pulse width
1000
ns
Serial I/O clock input LOW pulse width
1000
ns
400
ns
400
ns
Serial I/O clock input cycle time
twH(SCLK)
twL(SCLK)
tsu(SCLK-SIN)
Serial I/O input setup time
Serial I/O input hold time
th(SCLK-SIN)
Standard
Parameter
151
Mitsubishi microcomputers
M30218 Group
Timing(VCC=3V, only mask ROM version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC=3V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
th(TIN-UP) tsu(UP-TIN)
(When count on falling edge is selected)
TAiIN input
(When count on rising edge is selected)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TxDi
tsu(D-C)
td(C-Q)
th(C-D)
RxDi
tw(INL)
INTi input
tw(INH)
tC(SCLK)
tf(SCLK)
tr
tWL(SCLK)
tWH(SCLK)
SCLK
0.8VCC
0.2VCC
tSU(SiN-SCLK)
th(SCLK-SiN)
0.8VCC
0.2VCC
SIN
td(SCLK-SOUT)
tV(SCLK-SOUT)
SOUT
152
Mitsubishi microcomputers
M30218 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Outline Performance
Table 72 shows the outline performance of the M30218 group (flash memory version).
Table 72. Outline Performance of the M30218 group (flash memory version)
Item
Performance
Power supply voltage
4.0V to 5.5 V (f(XIN)=10MHz)
Program/erase voltage
VPP=12V ± 5% (f(XIN)=10MHz)
VCC=5V ± 10% (f(XIN)=10MHz)
Flash memory operation mode
Three modes (parallel I/O, standard serial I/O, CPU
rewrite)
Erase block
division
User ROM area
See Figure 1.AA.3.
Boot ROM area
One division (3.5 K bytes) (Note)
Program method
In units of byte
Erase method
Collective erase / block erase
Program/erase control method
Program/erase control by software command
Number of commands
6 commands
Program/erase count
100 times
ROM code protect
Standard serial I/O mode is supported.
Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it
when shipped from the factory. This area can be erased and programmed in only parallel I/O
mode.
153
Mitsubishi microcomputers
M30218 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
The M30218 group (flash memory version) contains the NOR type of flash memory that requires a highvoltage VPP power supply for program/erase operations, in addition to the VCC power supply for device
operation. For this flash memory, three flash memory modes are available in which to read, program, and
erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a
programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow.
In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash
memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and
standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored
in it when shipped from the factory. However, the user can write a rewrite control program in this area that
suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode.
Microcomputer mode
Parallel I/O mode
CPU rewrite mode
Standard serial I/O mode
0000016
SFR
SFR
SFR
RA M
RAM
RAM
0040016
YYYYY16
DF00016
Collective
erasable/
programmable
area
DFDFF16
Boot ROM
area
(3.5K bytes)
Boot ROM
area
(3.5K bytes)
E000016
Block 3
E800016
Block 2
F000016
Block 1
XXXXX16
User ROM
area
Collective
erasable/
programmable
area
Collective
erasable/
programmable
area
User ROM
area
User ROM
area
F800016
Block 0
FFFFF16
FFFFF16
Type No.
XXXXX16
YYYYY16
M30218FC
E000016
033FF16
Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area.
Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input.
The user ROM area is selected when this address input is high and the boot ROM area is selected
when this address input is low.
Figure 125. Block diagram of flash memory version
154
Mitsubishi microcomputers
M30218 Group
CPU Rewrite Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control
of the Central Processing Unit (CPU). In CPU rewrite mode, the flash memory can be operated on by
reading or writing to the flash memory control register and flash command register. Figure 126, Figure 127
show the flash memory control register, and flash command register respectively.
Also, in CPU rewrite mode, the CNV SS pin is used as the VPP power supply pin. Apply the power supply
voltage, VPPH, from an external source to this pin.
In CPU rewrite mode, only the user ROM area shown in Figure 128 can be rewritten; the boot ROM area
cannot be rewritten. Make sure the program and block commands are issued for only the user ROM area.
The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU
rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must
be transferred to internal RAM before it can be executed.
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0
FCON0
03B416
00100000 2
0
Bit symbol
Bit name
Function
FCON00 CPU rewrite mode
select bit
0: CPU rewrite mode is invalid
1: CPU rewrite mode is valid
Reserved bit
This bit can not write. The value, if
read, turns out to be indeterminate.
FCON02 CPU rewrite mode
monitor flag
0: CPU rewrite mode is invalid
1: CPU rewrite mode is valid
Reserved bit
Must always be set to "0".
FCON04 Erase / program
area select bit
FCON05
b6b5b4
R WW
R
000: Block 3 program/erase
001: Block 2 program/erase
010: Block 1 program/erase
011: Block 0 program/erase
110: Block 0 to 3 erase
111: Inhibit
FCON06
Must always be set to "0".
Reserved bit
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
Address
When reset
FCON1
03B516
XXXXXX00 2
Bit symbol
Bit name
Function
Reserved bit
R WW
R
Must always be set to "0".
Nothing is assigned. In an attempt to write these bits, write "0". The
value, if read, turns out to be indeterminate.
Figure 126. Flash memory control register
Flash command register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
FCMD
03B616
0016
Function
Writing of software command
<Software command name>
•Read command
•Program command
•Program verify command
•Erase command
•Erase verify command
•Reset command
<Command code>
"0016"
"4016"
"C016"
"2016" +"2016"
"A016"
"FF16" +"FF6"
Figure 127. Flash command register
155
R WW
R
A
Mitsubishi microcomputers
M30218 Group
CPU Rewrite Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard
serial I/O mode becomes unusable.)
See Figure 125 for details about the boot ROM area.
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low
(VSS). In this case, the CPU starts operating using the control program in the user ROM area.
When the microcomputer is reset by pulling the P52 pin high (VCC), the CNVSS pin high(VPPH), the CPU
starts operating using the control program in the boot ROM area. This mode is called the “boot” mode.
The control program in the boot ROM area can also be used to rewrite the user ROM area.
CPU rewrite mode operation procedure
The internal flash memory can be operated on to program, read, verify, or erase it while being placed onboard by writing commands from the CPU to the flash memory control register (addresses 03B4 16,
03B516) and flash command register (address 03B616). Note that when in CPU rewrite mode, the boot
ROM area cannot be accessed for program, read, verify, or erase operations. Before this can be accomplished, a CPU write control program must be written into the boot ROM area in parallel input/output
mode. The following shows a CPU rewrite mode operation procedure.
<Start procedure (Note 1)>
(1) Apply VPPH to the CNVSS/VPP pin and VCC to the port P46 pin for reset release. Or the user can
jump from the user ROM area to the boot ROM area using the JMP instruction and execute the CPU
write control program. In this case, set the CPU write mode select bit of the flash memory control
register to “1” before applying VPPH to the CNVSS/VPP pin.
(2) After transferring the CPU write control program from the boot ROM area to the internal RAM, jump
to this control program in RAM. (The operations described below are controlled by this program.)
(3) Set the CPU rewrite mode select bit to “1”.
(4) Read the CPU rewrite mode monitor flag to see that the CPU rewrite mode is enabled.
(5) Execute operation on the flash memory by writing software commands to the flash command register.
Note 1: In addition to the above, various other operations need to be performed, such as for entering the
data to be written to flash memory from an external source (e.g., serial I/O), initializing the ports, and
writing to the watchdog timer.
<Clearing procedure>
(1) Apply VSS to the CNVSS/VPP pin.
(2) Set the CPU rewrite mode select bit to “0”.
156
Mitsubishi microcomputers
M30218 Group
CPU Rewrite Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During erase/program mode, set BCLK to one of the following frequencies by changing the divide
ratio:
5 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state)
10 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)(Note 1)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
No interrupts can be used that look up the fixed vector table in the flash memory area. Maskable
interrupts may be used by setting the interrupt vector table in a location outside the flash memory
area.
Note 1: Internal access wait state can be set in CPU rewrite mode. In this time, the following function is
only used.
• CPU, ROM, RAM, timer, UART, SI/O2(non-automatic transfer), port
In case of setting internal access wait state, refer to the following explain (software wait).
Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note 2).
A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode
register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus
cycle is executed in two BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”.
The SFR area is always accessed in two BCLK cycles regardless of the setting of this control bit.
Table 73 shows the software wait and bus cycles. Figure 128 shows example bus timing when using
software waits.
Note 2: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 73. Software waits and bus cycles
Bus cycle
Area
Wait bit
SFR
Invalid
2 BCLK cycles
0
1 BCLK cycle
1
2 BCLK cycles
Internal
ROM/RAM
157
Mitsubishi microcomputers
M30218 Group
CPU Rewrite Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
< Internal bus (no wait) >
Bus cycle
BCLK
Write signal
Read signal
Output
Data bus
Address bus
Address
Input
Address
< Internal bus (with wait) >
Bus cycle
BCLK
Write signal
Read signal
Data bus
Address bus
Input
Output
Address
Address
Figure 128. Typical bus timings using software wait
158
Mitsubishi microcomputers
M30218 Group
CPU Rewrite Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Commands
Table 74 lists the software commands available with the M30218 group (flash memory version).
When CPU rewrite mode is enabled, write software commands to the flash command register to specify
the operation to erase or program.
The content of each software command is explained below.
Table 74. List of Software Commands (CPU Rewrite Mode)
First bus cycle
Command
Second bus cycle
Mode
Address
Data
(D0 to D7)
Read
Write
03B616
0016
Program
Write
03B616
Program verify
Write
Erase
Data
(D0 to D7)
Mode
Address
4016
Write
Program
address
Program
data
03B616
C016
Read
Verify
address
Verify
data
Write
03B616
2016
Write
03B616
2016
Erase verify
Write
03B616
A016
Read
Verify
address
Verify
data
Reset
Write
FF16
Write
03B616
FF16
03B616
Read Command (0016)
The read mode is entered by writing the command code “0016” to the flash command register in the
first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of
the specified address is read out at the data bus (D0–D7), 8 bits at a time.
The read mode is retained intact until another command is written.
After reset and after the reset command is executed, the read mode is set.
Program Command (4016)
The program mode is entered by writing the command code “4016” to the flash command register in
the first bus cycle. When the user execute an instruction to write byte data to the desired address (e.g.,
STE instruction) in the second bus cycle, the flash memory control circuit executes the program operation. The program operation requires approximately 20 µs. Wait for 20 µs or more before the user
go to the next processing.
During program operation, the watchdog timer remains idle, with the value “7FFF16” set in it.
Note 1: The write operation is not completed immediately by writing a program command once. The
user must always execute a program-verify command after each program command executed. And if
verification fails, the user need to execute the program command repeatedly until the verification
passes. See Figure 129 for an example of a programming flowchart.
159
Mitsubishi microcomputers
M30218 Group
CPU Rewrite Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Program-verify command (C016)
The program-verify mode is entered by writing the command code “C016” to the flash command
register in the first bus cycle. When the user execute an instruction (e.g., LDE instruction) to read byte
data from the address to be verified (the previously programmed address) in the second bus cycle,
the content that has actually been written to the address is read out from the memory.
The CPU compares this read data with the data that it previously wrote to the address using the
program command. If the compared data do not match, the user need to execute the program and
program-verify operations one more time.
Erase command (2016 + 2016)
The flash memory control circuit executes an erase operation by writing command code “2016” to the
flash command register in the first bus cycle and the same command code to the flash command
register again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20
ms or more before the user go to the next processing.
Before this erase command can be performed, all memory locations to be erased must have had data
“0016” written to by using the program and program-verify commands. During erase operation, the
watchdog timer remains idle, with the value “7FFF16 set in it.
Note 1: The erase operation is not completed immediately by writing an erase command once. The
user must always execute an erase-verify command after each erase command executed. And if
verification fails, the user need to execute the erase command repeatedly until the verification passes.
See Figure 129 for an example of an erase flowchart.
Erase-verify command (A016)
The erase-verify mode is entered by writing the command code “A016” to the flash command register
in the first bus cycle. When the user execute an instruction to read byte data from the address to be
verified (e.g., LDE instruction) in the second bus cycle, the content of the address is read out.
The CPU must sequentially erase-verify memory contents one address at a time, over the entire area
erased. If any address is encountered whose content is not “FF16” (not erased), the CPU must stop
erase-verify at that point and execute erase and erase-verify operations one more time.
Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to
execute erase and erase-verify operations one more time. In this case, however, the user does not
need to write data “0016” to memory before erasing.
160
Mitsubishi microcomputers
M30218 Group
CPU Rewrite Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset command (FF16 + FF16)
The reset command is used to stop the program command or the erase command in the middle of
operation. After writing command code “4016” or “2016” twice to the flash command register, write
command code “FF16” to the flash command register in the first bus cycle and the same command
code to the flash command register again in the second bus cycle. The program command or erase
command is disabled, with the flash memory placed in read mode.
Erase
Program
Start
Start
Address = first location
All bytes =
"0016"?
YES
Loop counter : X=0
NO
Write program data/
address
Program all bytes =
"0016"
Write : 4016
Write program command
Address = First address
Write : Program data
Loop counter X=0
Duration = 20 µs
Loop counter : X=X+1
Write erase command
Write:2016
Write erase command
Write:2016
Duration = 20ms
Write program verify
command
Write : C016
Loop counter X=X+1
Write erase verify
command/address
Duration = 6 µs
X=25 ?
Duration = 6µs
YES
NO
FAIL
PASS
Next address ?
NO
X=1000 ?
PASS
Verify
OK ?
Verify
OK ?
FAIL
FAIL
PASS
Verify
OK?
PASS
PASS
Next address
Write read command
YES
NO
Last
address ?
Write read command
Write:A016
Write : 0016
NO
FAIL
Write read command
Write read command
Figure 129. Program and erase execution flowchart in the CPU rewrite mode
161
Read:
expect value=FF16
Last
address?
PASS
FAIL
Verify
OK?
FAIL
Write:0016
Mitsubishi microcomputers
M30218 Group
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin functions (Flash memory standard serial I/O mode)
Name
Pin
Description
I/O
Apply 5V ± 10 % to Vcc pin and 0 V to Vss pin.
VCC,VSS
Power input
CNVSS
CNVSS
I
Apply 12V ± 5 % to this pin.
RESET
Reset input
I
Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to XIN pin.
XIN
Clock input
I
XOUT
Clock output
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN pin
and open XOUT pin.
AVCC, AVSS
Analog power supply input
VREF
Reference voltage input
I
P00 to P07
Output port P0
O
P10 to P17
Output port P1
O
Output exclusive use pin.
P20 to P27
Output port P2
O
Output exclusive use pin.
P30 to P37
Input port P3
I
Input "H" or "L" level signal or open.
P40 to P43
Input port P4
I
Input "H" or "L" level signal or open.
P44
TxD output
P45
RxD input
I
Serial data input pin.
I
Serial clock input pin.
O
Connect AVSS to Vss and AVcc to Vcc, respectively.
O
Enter the reference voltage for AD from this pin.
Output exclusive use pin.
Serial data output pin.
P46
SCLK input
P47
BUSY output
O
BUSY signal output pin.
P50 to P57
Output port P5
O
Output exclusive use pin.
P60 to P67
Output port P6
O
Output exclusive use pin.
P70 to P77
Input port P7
I
Input "H" or "L" level signal or open.
P80 to P87
Input port P8
I
Input "H" or "L" level signal or open.
P90 to P97
Input port P9
I
Input "H" or "L" level signal or open.
P100 to P107
Input port P10
I
Input "H" or "L" level signal or open.
162
RESET
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P50/FLD8
P51/FLD9
P52/FLD10
P53/FLD11
P54/FLD12
P55/FLD13
P56/FLD14
P57/FLD15
P00/FLD16
P01/FLD17
P02/FLD18
P03/FLD19
P04/FLD20
P05/FLD21
P06/FLD22
VSS
P07/FLD23
VCC
P10/FLD24
P11/FLD25
P12/FLD26
P13/FLD27
P14/FLD28
P15/FLD29
P16/FLD30
P17/FLD31
P20/FLD32
P21/FLD33
P22/FLD34
P23/FLD35
Vss
RESET
Vss
Vcc
VSS
P67/FLD7
P66/FLD6
P65/FLD5
P64/FLD4
P63/FLD3
P62/FLD2
P61/FLD1
P60/FLD0
VEE
P107/AN7
P106/AN6
P105/AN5
P104/AN4
P103/AN3
P102/AN2
P101/AN1
AVSS
P100/AN0
VREF
AVCC
90
91
92
93
Vcc
Value
VppH
Connect oscillator
circuit.
Figure 130. Pin connections for serial I/O mode (1)
163
P76/TA3IN/TA1OUT/CLK1
P75/TA2IN/TA0OUT/RXD1
P74/TA1IN/TA4OUT/TXD1
P73/TA0IN/TA3OUT
P72/TB2IN
P71/TB1IN
P70/TB0IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
CNVss
P77/TA4IN/TA2OUT/CTS1/RTS1/CLKS1
P97/DA0/CLKOUT/DIMOUT
P96/DA1/SCLK22
P95/SCLK21
P94/SOUT2
P93/SIN2
P92/SSTB2
P91/SBUSY2
P90/SRDY2
CNVss
CNVSS
P87/XCIN
P86/XCOUT
RESET
XOUT
VSS
Vss
XIN
Vcc
VCC
P85/INT5
P84/INT4
P83/INT3
P82/INT2
P81/INT1
P80/INT0
Mitsubishi microcomputers
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30218 Group
Mode setup method
VCC
81
82
50
49
83
84
85
86
87
48
47
46
45
44
88
89
43
42
41
40
39
38
M30218FCFP
94
95
96
97
98
99
37
36
35
34
33
32
100
31
P24/FLD36
P25/FLD37
P26/FLD38
P27/FLD39
P30/FLD40
P31/FLD41
P32/FLD42
P33/FLD43
P34/FLD44
P35/FLD45
P36/FLD46
P37/FLD47
P40/FLD48
P41/FLD49
P42/FLD50
P43/FLD51
P44/TXD0/FLD52
P45/RXD0/FLD53
P46/CLK0/FLD54
P47/CTS0/RTS0/FLD55
SCLK
TxD
BUSY
RxD
Mitsubishi microcomputers
M30218 Group
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
The standard serial I/O mode serially inputs and outputs the software commands, addresses and data
necessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specific
serial programmer.
The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations like
rewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard
serial I/O mode is started by clearing the reset with VPPH at the CNVss pin. (For the normal microprocessor
mode, set CNVss to “L”.)
This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, if
the boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used.
Figure 130 shows the pin connections for the standard serial I/O mode. Serial data I/O uses three UART0
pins: CLK0, RxD0, TxD0, and RTS0 (BUSY).
The CLK0 pin is the transfer clock input pin and it transfers the external transfer clock. The TxD0 pin outputs
the CMOS signal. The RTS0 (BUSY) pin outputs an “L” level when reception setup ends and an “H” level
when the reception operation starts. Transmission and reception data is transferred serially in 8-byte
blocks.
In the standard serial I/O mode, only the user ROM area shown in Figure 125 can be rewritten, the boot
ROM area cannot.
The standard serial I/O mode has a 7-byte ID code. When the flash memory is not blank and the ID code
does not match the content of the flash memory, the command sent from the programmer is not accepted.
Function Overview (Standard Serial I/O Mode)
In the standard serial I/O mode, software commands, addresses and data are input and output between
the flash memory and an external device (serial programmer, etc.) using a clock synchronized serial I/O
(UART0) . In reception, the software commands, addresses and program data are synchronized with the
rise of the transfer clock input to the CLK0 pin and input into the flash memory via the RxD0 pin.
In transmission, the read data and status are synchronized with the fall of the transfer clock and output to
the outside from the TxD0 pin.
The TxD0 pin is CMOS output. Transmission is in 8-bit blocks and LSB first.
When busy, either during transmission or reception, or while executing an erase operation or program,
the RTS0 (BUSY) pin is “H” level. Accordingly, do not start the next transmission until the RTS 0 (BUSY)
pin is “L” level.
Also, data in memory and the status register can be read after inputting a software command. It is possible to check flash memory operating status or whether a program or erase operation ended successfully or in error by reading the status register.
Software commands and the status register are explained here following.
164
Mitsubishi microcomputers
M30218 Group
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Commands
Table 75 lists software commands. In the standard serial I/O mode, erase operations, programs and
reading are controlled by transferring software commands via the RxD pin. Software commands are
explained here below.
Table 75. Software commands (Standard serial I/O mode)
Control command
1st byte
transfer
2nd byte
3rd byte
4th byte 5th byte 6th byte
Address
(middle)
Address
(high)
Data
output
Data
output
Data
output
Data
input
Data
input
1
Page read
FF16
2
Page program
4116
Address
(middle)
Address
(high)
Data
input
3
Bclock ease
2016
Address
(high)
D016
4
Erase all unlocked blocks
A716
Address
(middle)
D016
5
Read status register
7016
SRD
output
SRD1
output
6
Clear status register
5016
7
Read lockbit status
7116
8
ID check function
F516
9
Download function
FA16
10 Version data output function FB16
11 Boot area output function
FC16
Address
(middle)
Address
(high)
Address
(low)
Size
(low)
Address
(middle)
Size
(high)
Lock bit
data
output
Address
(high)
Checksum
Version
data
output
Address
(middle)
Version
data
output
Address
(high)
Version
data
output
Data
output
When ID is
not verificate
Not
acceptable
Data
output to
259th
byte
Data input
Not
to 259th acceptable
byte
Not
acceptable
Not
acceptable
Acceptable
Not
acceptable
Not
acceptable
ID size
ID1
To ID7
Acceptable
Data
input
To
Not
required
acceptable
number
of times
Version Version
Acceptable
Version
data
data data output
output output to 9th byte
Data
Data
Not
Data
output output
output to acceptable
259th byte
Note1: Shading indicates transfer from flash memory microcomputer to serial programmer. All other data is
transferred from the serial programmer to the flash memory microcomputer.
Note2: SRD refers to status register data. SRD1 refers to status register 1 data.
Note3: All commands can be accepted when the flash memory is totally blank.
165
Mitsubishi microcomputers
M30218 Group
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Send the “FF16” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
CLK0
RxD0
FF16
A8 to
A15
A16 to
A23
data0
TxD0
data255
RTS0(BUSY)
Figure 131. Timing for page read
Read Status Register Command
This command reads status information. When the “7016” command code is sent in the 1st byte of the
transmission, the contents of the status register (SRD) specified in the 2nd byte of the transmission
and the contents of status register 1 (SRD1) specified in the 3rd byte of the transmission are read.
CLK0
RxD0
7016
SRD
output
TxD0
RTS0(BUSY)
Figure 132. Timing for reading the status register
166
SRD1
output
Mitsubishi microcomputers
M30218 Group
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clear Status Register Command
This command clears the bits (SR3–SR4) which are set when the status register operation ends in
error. When the “5016” command code is sent in the 1st byte of the transmission, the aforementioned
bits are cleared. When the clear status register operation ends, the RTS0 (BUSY) signal changes
from the “H” to the “L” level.
CLK0
RxD0
5016
TxD0
RTS0(BUSY)
Figure 133. Timing for clearing the status register
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Send the “4116” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) From the 4th byte onward, as write data (D0–D7) for the page (256 bytes) specified with addresses
A8 to A23 is input sequentially from the smallest address first, that page is automatically written.
When reception setup for the next 256 bytes ends, the RTS0 (BUSY) signal changes from the “H” to
the “L” level. The result of the page program can be known by reading the status register. For more
information, see the section on the status register.
CLK0
RxD0
4116
A8 to
A15
A16 to
A23
TxD0
RTS0(BUSY)
Figure 134. Timing for the page program
167
data0
data255
Mitsubishi microcomputers
M30218 Group
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block Erase Command
This command erases the data in the specified block. Execute the block erase command as explained
here following.
(1) Send the “2016” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) Send the verify command code “D016” in the 4th byte of the transmission. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the
highest address of the specified block for addresses A16 to A23.
When block erasing ends, the RTS0 (BUSY) signal changes from the “H” to the “L” level. After block
erase ends, the result of the block erase operation can be known by reading the status register. For
more information, see the section on the status register.
Each block can be erase-protected with the lock bit. For more information, see the section on the data
protection function.
CLK0
RxD0
2016
A8 to
A15
A16 to
A23
TxD0
RTS0(BUSY)
Figure 135.Timing for block erasing
168
D016
Mitsubishi microcomputers
M30218 Group
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Send the “A716” command code in the 1st byte of the transmission.
(2) Send the verify command code “D016” in the 2nd byte of the transmission. With the verify command code, the erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the RTS0 (BUSY) signal changes from the “H” to the “L” level. The result of the
erase operation can be known by reading the status register.
CLK0
RxD0
A716
D016
TxD0
RTS0(BUSY)
Figure 136. Timing for erasing all unlocked blocks
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status command as explained here following.
(1) Send the “7116” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) The lock bit data of the specified block is output in the 4th byte of the transmission. Write the
highest address of the specified block for addresses A8 to A23.
The M30218 group (flash memory version) does not have the lock bit, so the read value is always
“1” (block unlock).
CLK0
RxD0
7116
A8 to
A15
TxD0
A16 to
A23
DQ6
RTS0(BUSY)
Figure 137. Timing for reading lock bit status
169
Mitsubishi microcomputers
M30218 Group
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Send the “FA16” command code in the 1st byte of the transmission.
(2) Send the program size in the 2nd and 3rd bytes of the transmission.
(3) Send the check sum in the 4th byte of the transmission. The check sum is added to all data sent
in the 5th byte onward.
(4) The program to execute is sent in the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
CLK0
RxD0
Check
sum
FA16
Data size (low)
TxD0
Data size (high)
RTS0(BUSY)
Figure 138. Timing for download
170
Program
data
Program
data
Mitsubishi microcomputers
M30218 Group
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Send the “FB16” command code in the 1st byte of the transmission.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
CLK0
RxD0
FB16
TxD0
'V'
'E'
'R'
'X'
RTS0(BUSY)
Figure 139. Timing for version information output
Boot Area Output Command
This command outputs the control program stored in the boot area in one page blocks (256 bytes).
Execute the boot area output command as explained here following.
(1) Send the “FC16” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.
CLK0
RxD0
FC16
A8 to
A15
A16 to
A23
TxD0
data0
RTS0(BUSY)
Figure 140. Timing for boot area output
171
data255
Mitsubishi microcomputers
M30218 Group
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Send the “F516” command code in the 1st byte of the transmission.
(2) Send addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code in the 2nd, 3rd
and 4th bytes of the transmission respectively.
(3) Send the number of data sets of the ID code in the 5th byte.
(4) The ID code is sent in the 6th byte onward, starting with the 1st byte of the code.
CLK0
RxD0
F516
DF16
FF16
0F16
ID size
ID1
ID7
TxD0
RTS0(BUSY)
Figure 141. Timing for the ID check
ID Code
When the flash memory is not blank, the ID code sent from the serial programmer and the ID code
written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the serial programmer is not accepted. An ID code contains 8 bits of data. Area is,
from the 1st byte, addresses 0FFFDF 16, 0FFFE3 16 , 0FFFEB 16 , 0FFFEF 16 , 0FFFF3 16 , and
0FFFF716 . Write a program into the flash memory, which already has the ID code set for these
addresses.
Address
0FFFDF16 to 0FFFDC16
ID1 Undefined instruction vector
0FFFE316 to 0FFFE016
ID2 Overflow vector
0FFFE716 to 0FFFE416
BRK instruction vector
0FFFEB16 to 0FFFE816
ID3 Address match vector
0FFFEF16 to 0FFFEC16
ID4 Single step vector
0FFFF316 to 0FFFF016
ID5 Watchdog timer vector
0FFFF716 to 0FFFF416
ID6 DBC vector
0FFFFB16 to 0FFFF816
ID7
0FFFFF16 to 0FFFFC16
Reset vector
4 bytes
Figure 142. ID code storage addresses
172
Mitsubishi microcomputers
M30218 Group
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table 76 gives the definition of each status register bit. After clearing the reset, the status register outputs
“8016”.
Table 76. Status register (SRD)
Definition
SRD0 bits
Status name
SR7 (bit7)
Status bit
Ready
Busy
SR6 (bit6)
Reserved
-
-
SR5 (bit5)
Erase bit
Terminated in error
Terminated normally
SR4 (bit4)
Program bit
Terminated in error
Terminated normally
SR3 (bit3)
Reserved
-
-
SR2 (bit2)
Reserved
-
-
SR1 (bit1)
Reserved
-
-
SR0 (bit0)
Reserved
-
-
"1"
"0"
Status Bit (SR7)
The status bit indicates the operating status of the flash memory. When power is turned on, “1” (ready)
is set for it. The bit is set to “0” (busy) during an auto write or auto erase operation, but it is set back to
“1” when the operation ends.
Erase Bit (SR5)
The erase bit reports the operating status of the auto erase operation. If an erase error occurs, it is set
to “1”. When the erase status is cleared, it is set to “0”.
Program Bit (SR4)
The program bit reports the operating status of the auto write operation. If a write error occurs, it is set
to “1”. When the program status is cleared, it is set to “0”.
173
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Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communications, results from ID checks and results from
check sum comparisons. It can be read after the SRD by writing the read status register command (7016).
Also, status register 1 is cleared by writing the clear status register command (5016).
Table 77 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and
the flag status is maintained even after the reset.
Table 77. Status register 1 (SRD1)
SRD1 bits
Status name
SR15 (bit7)
Boot update completed bit
SR14 (bit6)
Definition
"1"
"0"
Update completed
Not update
Reserved
-
-
SR13 (bit5)
Reserved
-
-
SR12 (bit4)
Checksum match bit
SR11 (bit3)
ID check completed bits
Match
00
01
10
11
SR10 (bit2)
SR9 (bit1)
Data receive time out
SR8 (bit0)
Reserved
Mismatch
Not verified
Verification mismatch
Reserved
Verified
Time out
Normal operation
-
-
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downloaded to the RAM or not, using the download function.
Check Sum Consistency Bit (SR12)
This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function.
ID Check Completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID
check.
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data reception. If this flag is attached
during data reception, the received data is discarded and the microcomputer returns to the command
wait state.
174
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M30218 Group
Appendix Standard Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example Circuit Application for The Standard Serial I/O Mode
The below figure shows a circuit application for the standard serial I/O mode. Control pins will vary according to programmer, therefore see the programmer manual for more information.
CLK0
Clock input
RTS output
RTS0(BUSY)
Data input
RXD0
Data output
TXD0
M30218 Flash
memory version
VPP
CNVss
(1) Control pins and external circuitry will vary according to programmer. For
more information, see the programmer manual.
(2) In this example, the microprocessor mode and standard serial I/O mode are
switched via a switch.
Figure 143. Example circuit application for the standard serial I/O mode
175
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
100P6S-A
Plastic 100pin 14✕20mm body QFP
EIAJ Package Code
QFP100-P-1420-0.65
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
81
1
b2
100
ME
HD
D
80
I2
Recommended Mount Pad
E
30
HE
Symbol
51
50
A
L1
c
A2
31
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
b
x
M
A1
F
e
L
Detail F
y
176
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
3.05
0.1
0.2
0
–
–
2.8
0.25
0.3
0.4
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
–
0.65
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
–
–
0.13
–
–
0.1
–
0°
10°
–
–
0.35
1.3
–
–
–
–
14.6
–
–
20.6
Chapter 2
Peripheral Functions Usage
Mitsubishi microcomputers
M30218 Group
Protect
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.1 Protect
2.1.1 Overview
'Protect' is a function that causes a value held in a register to be unchanged even when a program runs
away. The following is an overview of the protect function:
(1) Registers affected by the protect function
The registers affected by the protect function are:
(a) System clock control registers 0, 1 (addresses 000616 and 000716)
(b) Processor mode registers 0, 1 (addresses 000416 and 000516)
The values in registers (1) through (2) cannot be changed in write-protect state. To change values in
the registers, put the individual registers in write-enabled state.
(2) Protect register
Figure 2.1.1 shows protect register.
Protect register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PRCR
Address
000A16
When reset
XXXXX0002
Bit symbol
Bit name
PRC0
Enables writing to system clock
control registers 0 and 1 (addresses
000616 and 000716)
Function
PRC1
Enables writing to processor mode
0 : Write-inhibited
registers 0 and 1 (addresses 000416
1 : Write-enabled
and 000516)
R W
0 : Write-inhibited
1 : Write-enabled
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Figure 2.1.1. Protect register
2.1.2 Protect Operation
The following explains the protect operation. Figure 2.1.2 shows the set-up procedure.
Operation (1) Setting “1” in the write-enable bit of system clock control registers 0 and 1 causes system
clock control register 0 and system clock control register 1 to be in write-enabled state.
(2) The contents of system clock control register 0 and that of system clock control register 1 are changed.
(3) Setting “0” in the write-enable bit of system control registers 0 and 1 causes system clock
control register 0 and system control register 1 to be in write-inhibited state.
(4) To change the contents of processor mode register 0 and that of processor mode register 1,
follow the same steps as in dealing with system clock control registers.
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Mitsubishi microcomputers
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Protect
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Clearing the protect (set to write-enabled state)
b7
b0
1
Protect register [Address 000A 16]
PRCR
Enables writing to system clock control registers 0 and 1 (addresses 0006
1 : Write-enabled
(2)
16
and 0007 16)
16
and 0007 16)
Setting system clock control register i (i = 0, 1)
(3) Setting the protect (set to write-inhibited state)
b7
b0
0
Protect register [Address 000A 16]
PRCR
Enables writing to system clock control registers 0 and 1 (addresses 0006
0 : Write-inhibited
Figure 2.1.2. Set-up procedure for protect function
179
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2 Timer A
2.2.1 Overview
The following is an overview for timer A, a 16-bit timer.
(1) Mode
Timer A operates in one of the four modes:
(a) Timer mode
In this mode, the internal count source is counted. Two functions can be selected: the pulse output
function that reverses output from a port every time an overflow occurs, or the gate function which
controls the count start/stop according to the input signal from a port.
• Timer mode operation .............................................................................................................. P186
• Timer mode, gate function operation ........................................................................................ P188
• Timer mode, pulse output function operation ........................................................................... P190
(b) Event counter mode
This mode counts the pulses from the outside and the number of underflows in other timers. The
free-run type, in which nothing is reloaded from the reload register, can be selected when an underflow occurs. The pulse output function can also be selected. Please refer to the timer mode explanation for details, as the operation is identical.
• Event counter mode operation ................................................................................................. P192
• Event counter mode, free run type operation ........................................................................... P194
Furthermore, Timer A has a 2-phase pulse signal processing function which generates an up count
or down count in the event counter mode, depending on the phase of the two input signals.
• Operation of the 2-phase pulse signal processing function in normal event counter mode ..... P196
• Operation of the 2-phase pulse signal processing function in 4-multiplication mode ............... P198
(c) One-shot timer mode
In this mode, the timer is started by the trigger and stops when the timer goes to “0”. The trigger can
be selected from the following 3 types: an external input signal, an overflow of the timer, or a software
trigger. The pulse output function can also be selected. Please refer to the timer mode explanation
for details, as the operation is identical.
• Operation in one-shot timer mode effected by software ........................................................... P200
• Operation in one-shot timer mode effected by an external trigger ........................................... P202
(d) Pulse width modulation (PWM) mode
In this mode, the arbitrary pulses are successively output. Either a 16-bit fixed-period PWM mode or
8-bit variable-period mode can be selected. The trigger for initiating output can also be selected.
Please refer to the one-shot timer mode explanation for details, as the operation is identical.
• 16-bit PWM mode operation ..................................................................................................... P204
• 8-bit PWM mode operation ....................................................................................................... P206
180
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Count source
The internal count source can be selected from f1, f8, f32, and fC32. Clocks f1, f8, and f32 are derived
by dividing the CPU's main clock by 1, 8, and 32 respectively. Clock fC32 is derived by dividing the
CPU's secondary clock by 32.
(3) Frequency division ratio
In timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the
frequency division ratio. In event counter mode, [the set value + 1] becomes the frequency division
ratio when a down count is performed, or [FFFF16 - the set value + 1] becomes the frequency division
ratio when an up count is performed. In one-shot timer mode, the value set in the timer register becomes the frequency division ratio.
The counter overflows (or underflows) when a count source equal to a frequency division ratio is input,
and an interrupt occurs. For the pulse output function, the output from the port varies (the value in the
port register does not vary).
(4) Reading the timer
Either in timer mode or in event counter mode, reading the timer register takes out the count at that
moment. Read it in 16-bit units. The data either in one-shot timer mode or in pulse width modulation
mode is indeterminate.
(5) Writing to the timer
To write to the timer register when a count is in progress, the value is written only to the reload register.
When writing to the timer register when a count is stopped, the value is written both to the reload
register and to the counter. Write a value in 16-bit units.
(6) Relation between the input/output to/from the timer and the direction register
With the output function of the timer, pulses are output regardless of the direction register of the
relevant port. To input an external signal to the timer, set the direction register of the relevant port to
input.
(7) Pins related to timer A
(a) TA0IN, TA1IN, TA2IN, TA3IN, TA4IN
(b) TA0OUT, TA1OUT, TA2OUT, TA3OUT, TA4OUT
Input pins to timer A.
Output pins from timer A. They become input pins to
timer A when event counter mode is active.
(8) Registers related to timer A
Figure 2.2.1 shows the memory map of timer A-related registers. Figures 2.2.2 through 2.2.5 show
timer A-related registers.
181
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
005516
Timer A0 interrupt control register (TA0IC)
005616
Timer A1 interrupt control register (TA1IC)
005716
Timer A2 interrupt control register (TA2IC)
005816
Timer A3 interrupt control register (TA3IC)
005916
Timer A4 interrupt control register (TA4IC)
038016
Count start flag (TABSR)
Clock prescaler reset flag (CPSRF)
038116
038216
One-shot start flag (ONSF)
038316
Trigger select register (TRGSR)
038416
Up-down flag (UDF)
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
Timer A0 (TA0)
Timer A1 (TA1)
Timer A2 (TA2)
Timer A3 (TA3)
Timer A4 (TA4)
039616
Timer A0 mode register (TA0MR)
039716
Timer A1 mode register (TA1MR)
039816
Timer A2 mode register (TA2MR)
039916
Timer A3 mode register (TA3MR)
039A16
Timer A4 mode register (TA4MR)
Figure 2.2.1. Memory map of timer A-related registers
Timer Ai mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
Address
When reset
039616 to 039A16
0016
Bit name
Operation mode select bit
TMOD1
MR0
MR1
Function
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
Function varies with each operation mode
MR2
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Figure 2.2.2. Timer A-related registers (1)
182
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
RW
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA0
TA1
TA2
TA3
TA4
Address
038716,0386 16
038916,0388 16
038B16,038A 16
038D16,038C 16
038F16,038E 16
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
Values that can be set
• Timer mode
Counts an internal count source
000016 to FFFF 16
• Event counter mode
Counts pulses from an external source or timer overflow
000016 to FFFF 16
• One-shot timer mode
Counts a one shot width
0000 16 to FFFF 16
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
000016 to FFFE 16
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
R W
0016 to FE 16
(Both high-order
and low-order
addresses)
Note: Read and write data in 16-bit units.
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Address
0380 16
Bit symbol
Bit name
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Figure 2.2.3. Timer A-related registers (2)
183
When reset
0016
Function
0 : Stops counting
1 : Starts counting
R W
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Up/down flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UDF
Address
0384 16
Bit symbol
One-shot start flag
b7
b6
b5
b4
b3
b2
b1
b0
When reset
0016
Bit name
TA0UD
Timer A0 up/down flag
TA1UD
Timer A1 up/down flag
TA2UD
Timer A2 up/down flag
TA3UD
Timer A3 up/down flag
TA4UD
Timer A4 up/down flag
Function
0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
TA2P
Timer A2 two-phase pulse
signal processing select bit
TA3P
Timer A3 two-phase pulse
signal processing select bit
TA4P
Timer A4 two-phase pulse
signal processing select bit
Symbol
ONSF
Address
038216
Bit symbol
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
When reset
00X00000 2
Bit name
TA0OS
Timer A0 one-shot start flag
TA1OS
Timer A1 one-shot start flag
TA2OS
Timer A2 one-shot start flag
TA3OS
Timer A3 one-shot start flag
TA4OS
Timer A4 one-shot start flag
Function
1 : Timer start
When read, the value is “0”
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
TA0TGL
Timer A0 event/trigger
select bit
TA0TGH
b7 b6
0 0 : Input on TA0 IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to “0”.
When selecting the TAi IN (i = 0–4) pin, TAi OUT (i = 0–4) pin which is
assigned to the same pin cannot be used.
Figure 2.2.4. Timer A-related registers (3)
184
R W
RW
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Trigger select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TRGSR
Address
0383 16
Bit symbol
TA1TGL
Bit name
b1 b0
Timer A2 event/trigger
select bit
b3 b2
Timer A3 event/trigger
select bit
b5 b4
Timer A4 event/trigger
select bit
b7 b6
TA2TGH
TA3TGL
TA3TGH
TA4TGL
Function
Timer A1 event/trigger
select bit
TA1TGH
TA2TGL
When reset
0016
TA4TGH
R W
0 0 : Input on TA1 IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
0 0 : Input on TA2 IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
0 0 : Input on TA3 IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
0 0 : Input on TA4 IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”.
When selecting the TAi IN (i = 0–4) pin, TAi OUT (i = 0–4) pin which is
assigned to the same pin cannot be used.
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Address
0381 16
Bit symbol
Bit name
When reset
0XXXXXXX 2
Function
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
CPSR
Clock prescaler reset flag
Figure 2.2.5. Timer A-related registers (4)
185
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
RW
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.2 Operation of Timer A (timer mode)
In timer mode, choose functions from those listed in Table 2.2.1. Operations of the circled items are
described below. Figure 2.2.6 shows the operation timing, and Figure 2.2.7 shows the set-up procedure.
Table 2.2.1. Choosed functions
Item
Set-up
Count source
O
Pulse output function
O
Internal count source (f1 / f8 / f32 / fc32)
No pulses output
Pulses output
Gate function
O
No gate function
Performs count only for the period in which the TAiIN pin is at “L” level
Performs count only for the period in which the TAiIN pin is at “H” level
Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count
source.
(2) If an underflow occurs, the content of the reload register is reloaded, and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”.
(3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
Counter content (hex)
n = reload register content
FFFF16
(1) Start count
(2) Underflow
(3) Stop count
n
Start count again
000016
Time
Cleared to “0” by
software
Set to “1” by software
Count start flag
Set to “1” by software
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Ai interrupt
request bit
“1”
“0”
Figure 2.2.6. Operation timing of timer mode
186
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting timer mode and functions
b7
b0
0
0
0
0
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16]
TAiMR (i=0 to 4)
0
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TAiOUT pin is a normal port pin)
Gate function select bit
b4 b3
00:
01:
Gate function not available (TAiIN pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Count source period
Count
source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
[Address 038716, 038616] TA0
[Address 038916, 038816] TA1
[Address 038B16, 038A16] TA2
[Address 038D16, 038C16] TA3
[Address 038F16, 038E16] TA4
Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by
dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 038016]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.7. Set-up procedure of timer mode
187
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.3 Operation of Timer A (timer mode, gate function selected)
In timer mode, choose functions from those listed in Table 2.2.2. Operations of the circled items are
described below. Figure 2.2.8 shows the operation timing, and Figure 2.2.9 shows the set-up procedure.
Table 2.2.2. Choosed functions
Item
Set-up
Count source
O
Internal count source(f1 / f8 / f32 / fc32)
Pulse output function
O
No pulses output
Pulses output
Gate function
No gate function
Performs count only for the period in which the TAiIN pin is at “L” level
O
Performs count only for the period in which the TAiIN pin is at “H” level
Operation (1) When the count start flag is set to “1” and the TAiIN pin inputs at “H” level, the counter performs a down count on the count source.
(2) When the TAiIN pin inputs at “L” level, the counter holds its value and stops.
(3) If an underflow occurs, the content of the reload register is reloaded and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop.
Note
• Make the pulse width of the signal input to the TAiIN pin not less than two cycles of the count
source.
n = reload register content
FFFF16
(1) Start count
(3) Underflow
Counter content (hex)
n
(2) Stop count
(4) Stop count
Start count again.
000016
Cleared to “0” by
software
Set to “1” by software
Count start flag
“1”
“0”
TAiIN pin
input signal
“H”
“L”
Time
Set to “1” by software
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Ai interrupt
request bit
“1”
“0”
Figure 2.2.8. Operation timing of timer mode, gate function selected
188
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting timer mode and functions
b7
b0
0
1
1
0
0
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16]
TAiMR (i=0 to 4)
0
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TAiOUT pin is a normal port pin)
Gate function select bit
b4 b3
1 1 : Timer counts only when TAiIN pin is held “H” (Note)
0 (Must always be “0” in timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Count source period
Count
source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Note: Set the corresponding port direction register to “0”.
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
[Address 038716, 038616] TA0
[Address 038916, 038816] TA1
[Address 038B16, 038A16] TA2
[Address 038D16, 038C16] TA3
[Address 038F16, 038E16] TA4
Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by
dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 038016]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.9. Set-up procedure of timer mode, gate function selected
189
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.4 Operation of Timer A (timer mode, pulse output function selected)
In timer mode, choose functions from those listed in Table 2.2.3. Operations of the circled items are
described below. Figure 2.2.10 shows the operation timing, and Figure 2.2.11 shows the set-up procedure.
Table 2.2.3. Choosed functions
Item
Set-up
Count source
O
Pulse output function
Gate function
Internal count source(f1 / f8 / f32 / fc32)
No pulses output
O
Pulses output
O
No gate function
Performs count only for the period in which the TAiIN pin is at “L” level
Performs count only for the period in which the TAiIN pin is at “H” level
Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count
source.
(2) If an underflow occurs, the content of the reload register is reloaded and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”. Also, the output polarity of the
TAiOUT pin reverses.
(3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the
TAiOUT pin outputs an “L” level.
n = reload register content
(2) Underflow
Counter content (hex)
FFFF16
(1) Start count
(3) Stop count
n
Start count again
000016
Time
Set to “1” by software
Count start flag
Cleared to “0” by
software
Set to “1” by software
“1”
“0”
Pulse output from “H”
TAiOUT pin
“L”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Ai interrupt
request bit
“1”
“0”
Figure 2.2.10. Operation timing of timer mode, pulse output function selected
190
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting timer mode and functions
b7
b0
0
0
1
0
Timer Ai mode register (i=0 to 4) [Address 0396 16 to 039A 16]
TAiMR (i=0 to 4)
0
Selection of timer mode
Pulse output function select bit
1 : Pulse is output (Note) (TA iOUT pin is a pulse output pin)
Gate function select bit
b4 b3
00:
01:
Gate function not available (TAi IN pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
0 1 : f8
1 0 : f 32
1 1 : f C32
Count source period
Count
source f(XIN) : 10MH Z f(XcIN) : 32.768kH Z
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Note: The settings of the corresponding port register and port direction register are invalid.
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
[Address 0387 16, 0386 16] TA0
[Address 0389 16, 0388 16] TA1
[Address 038B 16, 038A 16] TA2
[Address 038D 16, 038C 16] TA3
[Address 038F 16, 038E 16] TA4
Can be set to 0000 16 to FFFF 16
Setting clock prescaler reset flag
(This function is effective when f C32 is selected as the count source. Reset the prescaler for generating f
dividing the X CIN by 32.)
b7
b0
Clock prescaler reset flag [Address 0381 16]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 0380 16]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.11. Set-up procedure of timer mode, pulse output function selected
191
C32
by
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.5 Operation of Timer A (event counter mode, reload type selected)
In event counter mode, choose functions from those listed in Table 2.2.4. Operations of the circled items
are described below. Figure 2.2.12 shows the operation timing, and Figure 2.2.13 shows the set-up
procedure.
Table 2.2.4. Choosed functions
Item
Set-up
Count source
O
Item
Set-up
Input signal to TAiIN
(counting falling edges)
Pulse output function O
Input signal to TAiIN
(counting rising edges)
Count operation type
O
Timer overflow
(TB2/TAj overflow)
Factor for switching
between up and
down
No pulses output
Pulses output
Reload type
Free-run type
O
Content of up/down flag
Input signal to TAiOUT
Note: j = i – 1, but j = 4 when i = 0.
Operation (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count
source.
(2) If an underflow occurs, the content of the reload register is reloaded, and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”.
(3) If switching from an up count to a down count or vice versa while a count is in progress, the
switch takes effect from the next effective edge of the count source.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop.
(5) If an overflow occurs, the content of the reload register is reloaded, and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”.
AAAA
AAAAAAAA
n = reload register content
FFFF16
(3) Switch count
Counter content (hex)
(1) Start count
n
(5) Overflow
(2) Underflow
(4) Stop count
Start count again
000016
Cleared to “0” by
software
Set to “1” by software
Count start flag
“1”
“0”
Up/down flag
“1”
“0”
Set to “1” by software
Time
Set to “1” by software
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Ai interrupt “1”
request bit
“0”
Figure 2.2.12. Operation timing of event counter mode, reload type selected
192
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting event counter mode and functions
b7
b0
0
0
0
0
0
0
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16]
TAiMR (i=0 to 4)
1
Selection of event counter mode
Pulse output function select bit
0 : Pulse is not output (TAiOUT pin is a normal port pin)
Count polarity select bit
0 : Counts external signal's falling edge
Up/down switching cause select bit
0 : Up/down flag's content
0 (Must always be “0” in event counter mode)
Count operation type select bit
0 : Reload type
Invalid in event counter mode (i = 0, 1)
Invalid when not using two-phase pulse signal processing(i = 2 to 4)
Setting up/down flag
b7
0
b0
0
Up/down flag [Address 038416]
UDF
0
Timer A0 up/down flag
0 : Down count
Timer A1 up/down flag
0 : Down count
Timer A2 up/down flag
0 : Down count
Timer A3 up/down flag
0 : Down count
Timer A4 up/down flag
0 : Down count
When not using the 2-phase pulse signal processing function, set the select bit to “0”.
Setting one-shot start flag and trigger select register
b7
b0
b7
One-shot start flag [Address 038216]
ONSF
Timer A0 event/trigger select bit
b0
Trigger select register [Address 038316]
TRGSR
Timer A1 event/trigger select bit
b1 b0
b7 b6
0 0 : Input on TA1IN is selected (Note)
0 0 : Input on TA0IN is selected (Note)
Timer A2 event/trigger select bit
b3 b2
0 0 : Input on TA2IN is selected (Note)
Timer A3 event/trigger select bit
b5 b4
0 0 : Input on TA3IN is selected (Note)
Timer A4 event/trigger select bit
b7 b6
0 0 : Input on TA4IN is selected (Note)
Note: Set the corresponding port direction register to “0”.
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
[Address 038716, 038616] TA0
[Address 038916, 038816] TA1
[Address 038B16, 038A16] TA2
[Address 038D16, 038C16] TA3
[Address 038F16, 038E16] TA4
Can be set to 000016 to FFFF16
Setting count start flag
b7
b0
Count start flag [Address 038016]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.13. Set-up procedure of event counter mode, reload type selected
193
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.6 Operation of Timer A (event counter mode, free run type selected)
In event counter mode, choose functions from those listed in Table 2.2.5. Operations of the circled items
are described below. Figure 2.2.14 shows the operation timing, and Figure 2.2.15 shows the set-up
procedure.
Table 2.2.5. Choosed functions
Item
Count source
Set-up
O
Item
Set-up
Input signal to TAiIN
(counting falling edges)
Pulse output function O
Input signal to TAiIN
(counting rising edges)
Count operation type
Timer overflow
(TB2/TAj overflow)
Factor for switching
between up and
down
No pulses output
Pulses output
Reload type
O
Free-run type
O
Content of up/down flag
Input signal to TAiOUT
Note: j = i – 1, but j = 4 when i = 0
Operation (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count
source.
(2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the timer Ai interrupt request bit goes to “1”.
(3) If switching from an up count to a down count or vice versa while a count is in progress, the
switch takes effect from the next effective edge of the count source.
(4) Even if an overflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the timer Ai interrupt request bit goes to “1”.
n = reload register content
(3) Switch count
(2) Underflow
(4) Overflow
Counter content (hex)
FFFF16
(1) Start count
n
000016
Time
Set to “1” by software
Count start flag
“1”
“0”
Up/down flag
Set to “1” by software
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Ai interrupt
request bit
“1”
“0”
Figure 2.2.14. Operation timing of event counter mode, free run type selected
194
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting event counter mode and functions
b7
b0
1
0
0
0
0
0
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16]
TAiMR (i=0 to 4)
1
Selection of event counter mode
Pulse output function select bit
0 : Pulse is not output (TAiOUT pin is a normal port pin)
Count polarity select bit
0 : Counts external signal's falling edge
Up/down switching cause select bit
0 : Up/down flag's content
0 (Must always be “0” in event counter mode)
Count operation type select bit
1 : Free-run type
Invalid in event counter mode (i = 0, 1)
Invalid when not using two-phase pulse signal processing(i = 2 to 4)
Setting up/down flag
b7
0
b0
0
Up/down flag [Address 038416]
UDF
0
Timer A0 up/down flag
0 : Down count
Timer A1 up/down flag
0 : Down count
Timer A2 up/down flag
0 : Down count
Timer A3 up/down flag
0 : Down count
Timer A4 up/down flag
0 : Down count
When not using the 2-phase pulse signal processing function, be sure to set the select bit to “0”.
Setting one-shot start flag and trigger select register
b7
b0
One-shot start flag [Address 038216]
ONSF
b7
b0
Timer A0 event/trigger select bit
Trigger select register [Address 038316]
TRGSR
Timer A1 event/trigger select bit
b1 b0
b7 b6
0 0 : Input on TA1IN is selected (Note)
0 0 : Input on TA0IN is selected (Note)
Timer A2 event/trigger select bit
b3 b2
0 0 : Input on TA2IN is selected (Note)
Timer A3 event/trigger select bit
b5 b4
0 0 : Input on TA3IN is selected (Note)
Timer A4 event/trigger select bit
Note: Set the corresponding port direction register to “0”.
b7 b6
0 0 : Input on TA4IN is selected (Note)
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
[Address 038716, 038616] TA0
[Address 038916, 038816] TA1
[Address 038B16, 038A16] TA2
[Address 038D16, 038C16] TA3
[Address 038F16, 038E16] TA4
Can be set to 000016 to FFFF16
Setting count start flag
b7
b0
Count start flag [Address 038016]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.15. Set-up procedure of event counter mode, free run type selected
195
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.7 Operation of timer A (2-phase pulse signal process in event counter mode,
normal mode selected)
In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table
2.2.6. Operations of the circled items are described below. Figure 2.2.16 shows the operation timing, and
Figure 2.2.17 shows the set-up procedure.
Table 2.2.6. Choosed functions
Item
Set-up
Reload type
Count operation type
2-phase pulses
process (Note)
O
Free run type
O
Normal processing
4-multiplication processing
Note: Timer A3 alone can be selected. Timer A2 is solely used for normal processes, and timer A4 is solely used for 4
multiplication processes.
Operation (1) Setting the count start flag to “1” causes the counter to count effective edges of the count
source.
(2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the timer Ai interrupt request bit goes to “1”.
(3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the timer Ai interrupt request bit goes to “1”.
• The up count or down count conditions are as follows:
If a rising edge is present at the TAiIN pin when the input signal level to the TAiOUT pin is “H”,
an up count is performed.
If a falling edge is present at the TAiIN pin when the input signal level to the TAiOUT pin is “H”,
a down count is performed.
Note
Counter content (hex)
Input pulse
(1) Start count
TAiOUT
TAiIN
“H”
“L”
“H”
“L”
(2) Underflow
(3) Overflow
FFFF16
000016
Count start flag
Time
Set to “1” by software
“1”
“0”
Timer Ai interrupt “1”
request bit
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 2.2.16. Operation timing of 2-phase pulse signal process in event counter mode, normal mode selected
196
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting event counter mode and functions
b7
0
b0
1
0
1
0
0
0
Timer Ai mode register (i= 2, 3) [Address 039816, 039916]
TAiMR (i= 2, 3)
1
Selection of event counter mode
0 (Must always be “0” when using two-phase pulse signal processing)
0 (Must always be “0” when using two-phase pulse signal processing)
1 (Must always be “1” when using two-phase pulse signal processing)
0 (Must always be “0” when using two-phase pulse signal processing)
Count operation type select bit
1 : Free-run type
Two-phase pulse signal processing operation select bit
0 : Normal processing operation
Two-phase pulse signal processing select bit
b7
b0
Up/down flag [Address 038416]
UDF
Timer A2 two-phase pulse signal processing select bit
1 : Two-phase pulse signal processing enabled
Timer A3 two-phase pulse signal processing select bit
1 : Two-phase pulse signal processing enabled
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A2 register [Address 038B16, 038A16] TA2
Timer A3 register [Address 038D16, 038C16] TA3
Can be set to 000016 to FFFF16
Setting count start flag
b7
b0
Count start flag [Address 038016]
TABSR
Timer A2 count start flag
Timer A3 count start flag
Start count
Figure 2.2.17. Set-up procedure of 2-phase pulse signal process in event counter mode, normal mode selected
197
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode,
multiply-by-4 mode selected)
In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table
2.2.7. Operations of the circled items are described below. Figure 2.2.18 shows the operation timing, and
Figure 2.2.19 shows the set-up procedure.
Table 2.2.7. Choosed functions
Item
Set-up
Count operation type
Item
Reload type
O
Set-up
Processing 2 phase
pulses (Note)
Free run type
Normal processing
O
4-multiplication processing
Note: Timer A3 alone can be selected. Timer A2 is solely used for normal processes, and timer A4 is solely used for 4multiplication processes.
Operation (1) Setting the count start flag to “1” causes the counter to count effective edges of the count source.
(2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the interrupt request bit goes to “1”.
(3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the interrupt request bit goes to “1”.
Note
• The up count or down count conditions are as follows:
Table 2.2.8. The up count or down count conditions
Input signal to the
TAiOUT pin
Up count
Input signal to the
TAiIN pin
Input signal to the
TAiOUT pin
Input signal to the
TAiIN pin
“H” level
Falling
“L” level
Rising
“L” level
Rising
“H” level
“H” level
Falling
“L” level
“H” level
Rising
“L” level
Falling
Rising
Falling
Down
count
TAiOUT
TAiIN
Counter content (hex)
Input pulse
(1) Start count
“H”
“L”
“H”
“L”
FFFF16
000016
Time
Set to “1” by software
(2) Underflow
Count start flag
(3) Overflow
“1”
“0”
Timer Ai interrupt “1”
request bit
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 2.2.18. Operation timing of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected
198
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting event counter mode and functions
b7
1
b0
1
0
1
0
0
0
Timer Ai mode register (i= 3, 4) [Address 039916, 039A16]
TAiMR (i= 3, 4)
1
Selection of event counter mode
0 (Must always be “0” when using two-phase pulse signal processing)
0 (Must always be “0” when using two-phase pulse signal processing)
1 (Must always be “1” when using two-phase pulse signal processing)
0 (Must always be “0” when using two-phase pulse signal processing)
Count operation type select bit
1 : Free-run type
Two-phase pulse signal processing operation select bit
1 : Multiply-by-4 processing operation
Two-phase pulse signal processing select bit
b7
b0
Up/down flag [address 038416]
UDF
Timer A3 two-phase pulse signal processing select bit
1 : Two-phase pulse signal processing enabled
Timer A4 two-phase pulse signal processing select bit
1 : Two-phase pulse signal processing enabled
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A3 register [Address 038D16, 038C16] TA3
Timer A4 register [Address 038F16, 038E16] TA4
Can be set to 000016 to FFFF16
Setting count start flag
b7
b0
Count start flag [Address 038016]
TABSR
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.19. Set-up procedure of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected
199
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.9 Operation of Timer A (one-shot timer mode)
In one-shot timer mode, choose functions from those listed in Table 2.2.9. Operations of the circled items
are described below. Figure 2.2.20 shows the operation timing, and Figure 2.2.21 shows the set-up
procedure.
Table 2.2.9. Choosed functions
Item
Count source
Set-up
O
Pulse output function
Internal count source (f1 / f8 / f32 / fc32)
No pulses output
O
Count start condition
Pulses output
External trigger input (falling edge of input signal to the TAiIN pin)
External trigger input (rising edge of input signal to the TAiIN pin)
Timer overflow (TB2/TAj/TAk overflow)
O
Writing “1” to the one-shot start flag
Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4.
Operation (1) Setting the one-shot start flag to “1” with the count start flag set to “1” causes the counter to
perform a down count on the count source. At this time, the TAiOUT pin outputs an “H” level.
(2) The instant the value of the counter becomes “0000 16”, the TAiOUT pin outputs an “L” level,
and the counter reloads the content of the reload register and stops counting. At this time, the
timer Ai interrupt request bit goes to “1”.
(3) If a trigger occurs while a count is in progress, the counter reloads the value in the reload
register again and continues counting. The reload timing is in step with the next count source
input after the trigger.
(4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the
reload register. Also, the TAiOUT pin outputs an “L” level. At this time, the timer Ai interrupt
request bit goes to “1”.
Counter content (hex)
n = reload register content
FFFF16
(2) Stop count
(3) Start count
(1) Start count
Start count
(4) Stop count
n
Reload
Reload
Reload
000116
Cleared to “0” by software
Set to “1” by software
Count start flag
Time
“1”
“0”
Write signal to
one-shot start flag
1 / fi X (n)
1 / fi X (n+1)
One-shot pulse output “H”
from TAiOUT pin
“L”
Timer Ai interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 2.2.20. Operation timing of one-shot mode
200
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting one-shot timer mode and functions
b7
b0
0
0
1
1
Timer Ai mode register (i=0 to 4) [Address 0396 16 to 039A 16]
TAiMR (i=0 to 4)
0
Selection of one-shot timer mode
Pulse output function select bit
1 : Pulse is output
External trigger select bit
When internal is selected, this bit can be “1” or “0”
Trigger select bit
0 : When the one-shot start flag is set “1”
0 (Must always be “0” in one-shot timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
0 1 : f8
1 0 : f 32
1 1 : f C32
Clearing timer Ai interrupt request bit
b7
b0
0
Count source period
Count
source f(XIN) : 10MH Z f(Xc IN) : 32.768kH Z
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Refer to 'Precaution for Timer A (one-shot timer mode)'
Timer Ai interrupt control register [Address 0055 16 to 0059 16]
TAiIC (i=0 to 4)
Interrupt request bit
Setting one-shot timer's time
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
[Address 0387 16, 0386 16] TA0
[Address 0389 16, 0388 16] TA1
[Address 038B 16, 038A 16] TA2
[Address 038D 16, 038C 16] TA3
[Address 038F 16, 038E16] TA4
Can be set to 0001 16 to FFFF 16
Setting clock prescaler reset flag
(This function is effective when f C32 is selected as the count source. Reset the prescaler for generating f
by dividing the X CIN by 32.)
b7
b0
Clock prescaler reset flag [Address 0381 16]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 0380 16]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Setting one-shot start flag
b7
b0
One-shot start flag [Address 0382 16]
ONSF
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
Start count
Figure 2.2.21. Set-up procedure of one-shot mode
201
C32
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.10 Operation of Timer A (one-shot timer mode, external trigger selected)
In one-shot timer mode, choose functions from those listed in Table 2.2.10. Operations of the circled
items are described below. Figure 2.2.22 shows the operation timing, and Figure 2.2.23 shows the set-up
procedure.
Table 2.2.10. Choosed functions
Item
Set-up
Count source
O
Pulse output function
Internal count source (f1 / f8 / f32 / fc32)
No pulses output
O
Pulses output
O
External trigger input (rising edge of input signal to the TAiIN pin)
Count start condition
External trigger input (falling edge of input signal to the TAiIN pin)
Timer overflow (TB2/TAj/TAk overflow)
Writing “1” to the one-shot start flag
Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4.
Operation (1) If the TAiIN pin input level changes from “L” to “H” with the count start flag set to “1”, the
counter performs a down count on the count source. At this time, the TAiOUT pin output level
goes to “H” level.
(2) If the value of the counter becomes “000016”, the TAiOUT pin outputs an “L” level, and the
counter reloads the content of the reload register and stops counting. At this time, the timer Ai
interrupt request bit goes to “1”.
(3) If a trigger occurs while a count is in progress, the counter reloads the value of the reload
register again and continues counting. The reload timing is in step with the next count source
input after the trigger.
(4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the
reload register. Also, the TAiOUT pin outputs an “L” level. At this time, the timer Ai interrupt
request bit goes to “1”.
FFFF16
n = reload register content
(2) Stop count
(3) Start count
Counter content (hex)
(1) Start count
Start count
(4) Stop count
n
Reload
Reload
Reload
000116
Set to “1” by software
Count start flag
“1”
“0”
TAiIN pin
input signal
“H”
Cleared to “0” by software
Trigger during count
“L”
1 / fi X (n)
1 / fi X (n+1)
One-shot pulse output “H”
from TAiOUT pin
“L”
Timer Ai interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 2.2.22. Operation timing of one-shot mode, external trigger selected
202
Time
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting one-shot timer mode and functions
b7
b0
0
1
1
1
1
Timer Ai mode register (i=0 to 4) [Address 0396 16 to 039A 16]
TAiMR (i=0 to 4)
0
Selection of one-shot timer mode
Pulse output function select bit
1 : Pulse is output
External trigger select bit
1 : Rising edge of TAi IN pin's input signal
Trigger select bit
1 : Selected by event/trigger select bit
0 (Must always be “0” in one-shot timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
0 1 : f8
1 0 : f 32
1 1 : f C32
Clearing timer Ai interrupt request bit
b7
Count source period
Count
source f(XIN) : 10MH Z f(XcIN) : 32.768kH Z
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Refer to 'Precaution for Timer A (one-shot timer mode)'
b0
Timer Ai interrupt control register [Address 0055 16 to 0059 16]
TAiIC (i=0 to 4)
0
Interrupt request bit
Setting event/trigger select bit
b7
b0
b7
b0
Trigger select register [Address 0383 16]
TRGSR
One-shot start flag [Address 0382 16]
ONSF
Timer A0 event/trigger select bit
Timer A1 event/trigger select bit
b1 b0
b7 b6
0 0 : Input on TA1 IN is selected (Note)
0 0 : Input on TA0 IN is selected (Note)
Timer A2 event/trigger select bit
b3 b2
0 0 : Input on TA2 IN is selected (Note)
Timer A3 event/trigger select bit
b5 b4
0 0 : Input on TA3 IN is selected (Note)
Timer A4 event/trigger select bit
b7 b6
Note: Set the corresponding port direction register to “0”.
Setting one-shot timer's time
(b15)
b7
(b8)
b0 b7
b0
0 0 : Input on TA4 IN is selected (Note)
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
[Address 0387 16, 0386 16] TA0
[Address 0389 16, 0388 16] TA1
[Address 038B 16, 038A16] TA2
[Address 038D 16, 038C 16] TA3
[Address 038F 16, 038E16] TA4
Can be set to 0001 16 to FFFF 16
Setting clock prescaler reset flag
(This function is effective when f C32 is selected as the count source. Reset the prescaler for generating f
b7
b0
C32
by dividing the X CIN by 32.)
Clock prescaler reset flag [Address 0381 16]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 0380 16]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.23. Set-up procedure of one-shot mode, external trigger selected
203
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.11 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected)
In pulse width modulation mode, choose functions from those listed in Table 2.2.11. Operations of the
circled items are described below. Figure 2.2.24 shows the operation timing, and Figure 2.2.25 shows the
set-up procedure.
Table 2.2.11. Choosed functions
Item
Set-up
Count source
O
Internal count source (f1 / f8 / f32 / fc32)
PWM mode
O
16-bit PWM
8-bit PWM
Count start condition
External trigger input (falling edge of input signal to the TAiIN pin)
O
External trigger input (rising edge of input signal to the TAiIN pin)
Timer overflow (TB2/TAj/TAk overflow)
Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4.
Operation (1) If the TAiIN pin input level changes from “L” to “H” with the count start flag set to “1”, the counter
performs a down count on the count source. Also, the TAiOUT pin outputs an “H” level.
(2) The TAiOUT pin output level changes from “H” to “L” when a set time period elapses. At this
time, the timer Ai interrupt request bit goes to “1”.
(3) The counter reloads the content of the reload register every time PWM pulses are output for
one cycle, and continues counting.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the
TAiOUT outputs an “L” level.
Note
• The period of PWM pulses becomes (216 – 1)/fi, and the “H” level pulse width becomes n/fi. If
the timer Ai register is set to “000016”, the pulse width modulator does not work, and the
TAiOUT pin output level remains at “L”.
(fi : frequency of the count source f1, f8, f32, fC32; n : value of the timer)
Conditions: Reload register = 000316, external trigger (rising edge of TAiIN pin input signal) is selected
16
1 / fi X (2
–1)
Count source
“H”
TAiIN pin
input signal
“L”
Trigger is not generated by this signal
Cleared to “0”
by software
Set to “1” by software
Count start flag
“1”
“0”
(1) Start count
(2) Output level “H” to “L”
1 / fi X n
PWM pulse output
from TAiOUT pin
“H”
Timer Ai interrupt
request bit
“1”
(3) One period is complete
(4) Stop count
“L”
Cleared to “0” when interrupt request is
accepted, or cleared by software
“0”
Note: n = 000016 to FFFE16
Figure 2.2.24. Operation timing of pulse width modulation mode, 16-bit PWM mode selected
204
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting PWM mode and functions
b7
b0
0
1
1
1
1
Timer Ai mode register (i=0 to 4) [Address 0396 16 to 039A 16]
TAiMR (i=0 to 4)
1
Selection of PWM mode
1 (Must always be “1” in PWM mode)
External trigger select bit
1 : Rising edge of TAi IN pin's input signal (Note 1)
Trigger select bit
1 : Selected by event/trigger select register
Note 1: Set the corresponding port direction
register to “0”.
16/8-bit PWM mode select bit
0 : Functions as a 16-bit pulse width modulator
Count source select bit
0 0 : f1
0 1 : f8
1 0 : f 32
1 1 : f C32
Clearing timer Ai interrupt request bit
b7
b0
0
Count source period
Count
source f(XIN) : 10MH Z f(XcIN) : 32.768kH Z
b7 b6
b7 b6
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Refer to 'Precaution for Timer A (pulse width modulation mode)'
Timer Ai interrupt control register [Address 0055
TAiIC (i=0 to 4)
16 to
0059 16]
Interrupt request bit
Setting event/trigger select bit
b7
b0
b7
b0
Trigger select register [Address 0383 16]
TRGSR
One-shot start flag [Address 0382 16]
ONSF
Timer A0 event/trigger select bit
Timer A1 event/trigger select bit
b1 b0
b7 b6
0 0 : Input on TA1 IN is selected (Note 2)
0 0 : Input on TA0 IN is selected (Note 2)
Timer A2 event/trigger select bit
b3 b2
0 0 : Input on TA2 IN is selected (Note 2)
Timer A3 event/trigger select bit
b5 b4
0 0 : Input on TA3 IN is selected (Note 2)
Timer A4 event/trigger select bit
Note 2: Set the corresponding port direction register to “0”.
b7 b6
0 0 : Input on TA4 IN is selected (Note 2)
Setting PWM pulse's “H” level width
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
[Address 0387 16, 0386 16] TA0
[Address 0389 16, 0388 16] TA1
[Address 038B 16, 038A16] TA2
[Address 038D 16, 038C16] TA3
[Address 038F 16, 038E 16] TA4
Can be set to 0000 16 to FFFE 16
Setting clock prescaler reset flag
(This function is effective when f C32 is selected as the count source. Reset the prescaler for generating f
b7
C32
by dividing the X CIN by 32.)
b0
Clock prescaler reset flag [Address 0381 16]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 0380 16]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.25. Set-up procedure of pulse width modulation mode, 16-bit PWM mode selected
205
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.12 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected)
In pulse width modulation mode, choose functions from those listed in Table 2.2.12. Operations of the
circled items are described below. Figure 2.2.26 shows the operation timing, and Figure 2.2.27 shows the
set-up procedure.
Table 2.2.12. Choosed functions
Item
Set-up
Count source
O
PWM mode
Internal count source (f1 / f8 / f32 / fc32)
16-bit PWM
Count start condition
O
8-bit PWM
O
External trigger input (falling edge of input signal to the TAiIN pin)
External trigger input (rising edge of input signal to the TAiIN pin)
Timer overflow (TB2/TAj/TAk overflow)
Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4.
Operation (1) If the TAiIN pin input level changes from “H” to “L” with the count start flag set to “1”, the counter
performs a down count on the count source. Also, the TAiOUT pin outputs an “H” level.
(2) The TAiOUT pin output level changes from “H” to “L” when a set time period elapses. At this
time, the timer Ai interrupt request bit goes to “1”.
(3) The counter reloads the content of the reload register every time PWM pulses are output for
one cycle, and continues counting.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the
TAiOUT pin outputs an “L” level.
Note
• The period of PWM pulses becomes (m + 1) X (28 – 1) / fi, and the “H” level pulse width
becomes n X (m + 1) / fi. If “0016” is set in the eight higher-order bits of the timer Ai register, the
pulse width modulator does not work, and the TAiOUT pin output level remains at “L”.
(fi : frequency of the count source f1, f8, f32, fc32; n : value of the timer)
• When a trigger is generated, the TAiOUT pin outputs “L” level of same amplitude as “H” level of
the set PWM pulse, after which it starts PWM pulse output.
Conditions: Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
(4) Stop count
8
1 / fi X (m + 1) X (2 – 1)
Count source (Note 1)
“1”
Count start flag
“0”
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
“H”
TAiIN pin input
(1) Start count
(2) Output level “H” to “L”
(3) One period is
complete
“L”
Underflow signal of 8-bit “H”
prescaler (Note 2)
“L”
PWM pulse output from
TAiOUT pin
Timer Ai interrupt
request bit
“H”
1 / fi X (m+1)
1 / fi X (m + 1) X n
“L”
Cleared to “0” when interrupt request
is accepted, or cleared by software
“1”
“0”
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FE16; n = 0016 to FE16.
Figure 2.2.26. Operation timing of pulse width modulation mode, with 8-bit PWM mode selected
206
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting PWM mode and function
b7
b0
1
1
0
1
1
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16]
TAiMR (i=0 to 4)
1
Selection of PWM mode
1 (Must always be “1” in PWM mode)
External trigger select bit
0 : Falling edge of TAiIN pin's input signal (Note1)
Trigger select bit
1 : Selected by event/trigger select register
Note 1: Set the corresponding port direction
register to “0”.
16/8-bit PWM mode select bit
1: Functions as an 8-bit pulse width modulator
Count source select bit
b7 b6
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Clearing timer Ai interrupt request bit
b
7
b0
Count source period
Count
source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Refer to 'Precaution for Timer A (pulse width modulation mode)'
Timer Ai interrupt control register [Address 005516 to 005916]
TAiIC (i=0 to 4)
0
Interrupt request bit
Setting event/trigger select bit
b7
b0
b7
One-shot start flag [Address 038216]
ONSF
b0
Trigger select register [Address 038316]
TRGSR
Timer A1 event/trigger select bit
Timer A0 event/trigger select bit
b1 b0
b7 b6
0 0 : Input on TA1IN is selected (Note 2)
0 0 : Input on TA0IN is selected (Note 2)
Timer A2 event/trigger select bit
b3 b2
0 0 : Input on TA2IN is selected (Note 2)
Timer A3 event/trigger select bit
b5 b4
0 0 : Input on TA3IN is selected (Note 2)
Timer A4 event/trigger select bit
b7 b6
Note 2: Set the corresponding port direction register to “0”.
0 0 : Input on TA4IN is selected (Note 2)
Setting PWM pulse's period and “H” level width
(b15)
b7
(b8)
b0 b7
Timer A0 register [Address 038716, 038616] TA0
Timer A1 register [Address 038916, 038816] TA1
Timer A2 register [Address 038B16, 038A16] TA2
Timer A3 register [Address 038D16, 038C16] TA3
Timer A4 register [Address 038F16, 038E16] TA4
Can be set to 0016 to FE16
b0
Can be set to 0016 to FE16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 038016]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.27. Set-up procedure of pulse width modulation mode, 8-bit PWM mode selected
207
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.13 Precautions for Timer A (timer mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the
flag to “1”.
(2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing,
the value of the counter. Reading the timer Ai register with the reload timing shown in Figure
2.2.28 gets “FFFF16”. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value.
Reload
Counter value (Hex.)
2
1
0
n
n–1
Read value (Hex.)
2
1
0
FFFF
n–1
Time
n = reload register content
Figure 2.2.28. Reading timer Ai register
208
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.14 Precautions for Timer A (event counter mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the
flag to “1”.
(2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing,
the value of the counter. Reading the timer Ai register with the reload timing shown in Figure
2.2.29 gets “FFFF16” by underflow or “000016” by overflow. Reading the timer Ai register after
setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value.
(3) Please note the standards for the differences between the 2 pulses used in the 2-phase pulse
signals input signals to the TAiIN pin and TAiOUT pin (i = 2, 3, 4), as shown in Figure 2.2.30.
(4) When free run type is selected, if count is stopped, set a value in the timer Ai register again.
(1) Down count
AA
AA
(2) Up count
Reload
Counter value
(Hex.)
2
1
0
Read value
(Hex.)
2
1
0
n
Reload
n–1
FFFF n – 1
Counter value
(Hex.)
FFFD FFFE FFFF
Read value
(Hex.)
FFFD FFFE FFFF 0000 n + 1
Time
n
n+1
Time
n = reload register content
n = reload register content
Figure 2.2.29. Reading timer Ai register
Vcc = 5V, f(XIN) = 10MHz
T1
TA2IN
TA3IN
TA4IN
TA2OUT
TA3OUT
TA4OUT
T1
(Min.)
T2, T3
(Min.)
800ns
200ns
Vcc = 3V, f(XIN) = 7MHz, one-wait
T2
T3
Figure 2.2.30. Standard of 2-phase pulses
209
T1
(Min.)
T2, T3
(Min.)
2µs
500ns
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.15 Precautions for Timer A (one-shot timer mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the
flag to “1”.
(2) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request is generated and the timer Ai interrupt request bit goes to “1”.
(3) The output from the one-shot timer synchronizes with the count source generated internally.
Therefore, when an external trigger has been selected, a delay of one cycle of the maximum
count source occurs between the trigger input to the TAiIN pin and the one-shot timer output.
(4) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of
the following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to
“0” after the above listed changes have been made.
(5) If a trigger occurs while a count is in progress, after the counter performs one down count
following the reoccurrence of a trigger, the reload register contents are reloaded, and the
count continues. To generate a trigger while a count is in progress, generate the second
trigger after an elapse longer than one cycle of the timer's count source after the previous
trigger occurred.
TAiIN pin input signal
“H”
“L”
Trigger input
Count source
One-shot pulse
output from TAiOUT pin
Start one-shot pulse output
Note: The above applies when an external trigger (falling edge of TAiIN pin input signal) is selected.
Figure 2.2.31. One-shot timer delay
210
Mitsubishi microcomputers
M30218 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.16 Precautions for Timer A (pulse width modulation mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the
flag to “1”.
(2) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to
“0” after the above listed changes have been made.
(3) Setting the count start flag to “0” while PWM pulses are being output causes the counter to
stop counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level
goes to “L”, and the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an
“L” level in this instance, the level does not change, and the timer Ai interrupt request bit does
not becomes “1”.
211
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.3 Timer B
2.3.1 Overview
The following is an overview for timer B, a 16-bit timer.
(1) Mode
Timer B operates in one of three modes:
(a) Timer mode
The internal count source is counted.
• Operation in timer mode ........................................................................................................... P216
(b) Event counter mode
The number of pulses coming from outside and the number of the timer overflows are counted.
• Operation in event counter mode ............................................................................................. P218
(c) Pulse period measurement/pulse width measurement mode
External pulse period or external pulse widths are measured. If pulse period measurement mode is
selected, the periods of input pulses are continuously measured. If pulse width measurement mode
is selected, widths of “H” level pulses and those of “L” level pulses are continuously measured.
• Operation in pulse period measurement mode ........................................................................ P220
• Operation in pulse width measurement mode .......................................................................... P222
(2) Count source
An internal count source can be selected from f1, f8, f32, and fC32. f1, f8, and f32 are clocks obtained by
dividing the CPU main clock by 1, 8, and 32 respectively. fC32 is the clock obtained by dividing the
CPU secondary clock by 32.
(3) Frequency division ratio
The frequency division ratio equals [the value set in the timer register + 1]. The counter underflows
when a count source equal to a frequency division ratio is input, and an interrupt request occurs.
(4) Reading the timer
In timer mode or event counter mode, the count value at the time of reading the timer register will be
read. Read the register in 16-bit increments. In both the pulse period measurement mode and pulse
width measurement mode, an indeterminate value is read until the second effective edge is input after
a count is started, otherwise, the measurement results are read.
(5) Writing to the timer
When writing to the timer register while a count is in progress, the value is written only to the reload
register. When writing to the timer register while a count has stopped, the value is written both to the
reload register and the count. Write the value in 16-bit increments. The timer register cannot be
written to in either the pulse period measurement mode or the pulse width measurement mode.
212
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(6) Input to the timer and the direction register
To input an external signal to the timer, set the direction register of the relevant port to input.
(7) Pins related to timer B
(a) TB0IN, TB1IN, TB2IN
Input pins to timer B.
(8) Registers related to timer B
Figure 2.3.1 shows the memory map of timer B-related registers. Figures 2.3.2 and 2.3.3 show timer
B-related registers.
005A16
Timer B0 interrupt control register (TB0IC)
005B16
Timer B1 interrupt control register (TB1IC)
005C16
Timer B2 interrupt control register (TB2IC)
038016
Count start flag (TABSR)
038116
Clock prescaler reset flag (CPSRF)
039016
039116
039216
039316
039416
039516
Timer B0 (TB0)
Timer B1 (TB1)
Timer B2 (TB2)
039B16
Timer B0 mode register (TB0MR)
039C16
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
039D16
Figure 2.3.1. Memory map of timer B-related registers
213
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
TBiMR(i = 0 to 2) 039B16 to 039D16
Bit symbol
TMOD0
Function
Bit name
Operation mode select bit
TMOD1
MR0
When reset
00XX00002
R
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
Function varies with each operation mode
MR1
MR2
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note 1: Timer B0.
Note 2: Timer B1, timer B2.
Figure 2.3.2. Timer B-related registers (1)
214
W
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Bi register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TB0
TB1
TB2
Address
039116, 0390 16
039316, 0392 16
039516, 0394 16
Function
When reset
Indeterminate
Indeterminate
Indeterminate
Values that can be set
• Timer mode
Counts the timer's period
0000 16 to FFFF 16
• Event counter mode
Counts external pulses input or a timer overflow
0000 16 to FFFF 16
RW
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note: Read and write data in 16-bit units.
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Address
038016
Bit symbol
When reset
0016
Bit name
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Function
R W
0 : Stops counting
1 : Starts counting
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Address
038116
Bit symbol
Bit name
When reset
0XXXXXXX 2
Function
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
CPSR
Clock prescaler reset flag
Figure 2.3.3. Timer B-related registers (2)
215
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
R W
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.3.2 Operation of Timer B (timer mode)
In timer mode, choose functions from those listed in Table 2.3.1. Operations of the circled items are
described below. Figure 2.3.4 shows the operation timing, and Figure 2.3.5 shows the set-up procedure.
Table 2.3.1. Choosed functions
Item
Set-up
Count source
O
Internal count source (f1 / f8 / f32 / fc32)
Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count
source.
(2) If an underflow occurs, the content of the reload register is reloaded, and the counter continues counting. At this time, the timer Bi interrupt request bit goes to “1”.
(3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
Counter content (hex)
n = reload register content
FFFF16
(1) Start count
(2) Underflow
(3) Stop count
n
Start count
again
000016
Time
Cleared to “0” by
software
Set to “1” by software
Count start flag
Set to “1” by software
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Bi interrupt “1”
request bit
“0”
Figure 2.3.4. Operation timing of timer mode
216
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting timer mode and functions
b7
b0
0
Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16]
TBiMR (i=0 to 2)
0
Selection of timer mode
Invalid in timer mode
Can be “0” or “1”
Fixed to “0” in timer mode ( i = 0)
This bit can neither be set nor reset (i = 1, 2)
Invalid in timer mode
Count source select bit
b7 b6
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Count source period
Count
source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register [Address 039116, 039016] TB0
Timer B1 register [Address 039316, 039216] TB1
Timer B2 register [Address 039516, 039416] TB2
Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by
dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 038016]
TABSR
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
Start count
Figure 2.3.5. Set-up procedure of timer mode
217
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.3.3 Operation of Timer B (event counter mode)
In event counter mode, choose functions from those listed in Table 2.3.2. Operations of the circled items are
described below. Figure 2.3.6 shows the operation timing, and Figure 2.3.7 shows the set-up procedure.
Table 2.3.2. Choosed functions
Item
Count source
Set-up
O
Input signal to the TBiIN pin (counting falling edges)
Input signal to the TBiIN pin (counting rising edges)
Input signal to the TBiIN pin (counting rising edges and falling edges)
Timer overflow(TBj overflow)
Note: j = i – 1, but j = 2 when i = 0
Operation (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count
source.
(2) If an underflow occurs, the content of the reload register is reloaded, and the count continues.
At this time, the timer Bi interrupt request bit goes to “1”.
(3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
Counter content (hex)
n = reload register content
FFFF16
(2) Underflow
(1) Start count
(3) Stop count
n
Start count again
000016
Time
Cleared to “0” by
software
Set to “1” by software
Count start flag
Set to “1” by software
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Bi interrupt “1”
request bit
“0”
Figure 2.3.6. Operation timing of event counter mode
218
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting event counter mode and functions
b7
0
b0
0
0
0
Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16]
TBiMR (i=0 to 2)
1
Selection of event counter mode
Count polarity select bit
b3 b2
0 0 : Counts external signal falling edges
Fixed to “0” in event counter mode ( i = 0)
This bit can neither be set nor reset (i = 1, 2)
Invalid in event counter mode
Event clock select
0 : Input from TBiIN pin (Note)
Note: Set the corresponding port direction register to “0”.
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register [Address 039116, 039016] TB0
Timer B1 register [Address 039316, 039216] TB1
Timer B2 register [Address 039516, 039416] TB2
Can be set to 000016 to FFFF16 (n)
Setting count start flag
b7
b0
Count start flag [Address 038016]
TABSR
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
Start count
Figure 2.3.7. Set-up procedure of event counter mode
219
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.3.4 Operation of Timer B (pulse period measurement mode)
In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.3.3. Operations of the circled items are described below. Figure 2.3.8 shows the operation timing, and Figure
2.3.9 shows the set-up procedure.
Table 2.3.3. Choosed functions
Item
Set-up
Count source
O Internal count source (f1 / f8 / f32 / fc32)
Measurement
mode
O Pulse period measurement (interval between measurement pulse falling edge to falling edge)
Pulse period measurement (interval between measurement pulse rising edge to rising edge)
Pulse width measurement (interval between measurement pulse falling edge to rising edge,
and between rising edge to falling edge)
Operation (1) Setting the count start flag to “1” causes the counter to start counting the count source.
(2) If a measurement pulse changes from “H” to “L”, the value of the counter goes to “000016”,
and measurement is started. In this instance, an indeterminate value is transferred to the
reload register. The timer Bi interrupt request is not generated.
(3) If a measurement pulse changes from “H” to “L” again, the value of the counter is transferred
to the reload register, and the timer Bi interrupt request bit goes to “1”. Then the value of the
counter becomes “000016”, and the measurement is started again.
Note
• The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse is
input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the
timer Bi overflow flag within the interrupt routine.
• The value of the counter at the beginning of a count is indeterminate. Thus there can be instances in which the timer Bi overflow flag goes to “1” immediately after a count is performed.
• The timer Bi overflow flag goes to “0” if timer Bi mode register is written to when the count start
flag is “1”. This flag cannot be set to “1” by software.
Measurement of pulse time interval from falling edge to falling edge
(1) Start count
(2) Start measurement
(3) Start measurement again
Count source
Measurement pulse
“H”
“L”
Transfer
(indeterminate value)
Reload register ← counter
transfer timing
(Note 1)
(Note 1)
Transfer
(measured value)
(Note 2)
Timing at which counter
reaches “000016”
“1”
Count start flag
“0”
Timer Bi interrupt
request bit
“1”
“0”
Timer Bi overflow flag
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 2.3.8. Operation timing of pulse period measurement mode
220
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting pulse period / pulse width measurement mode and functions
b7
b0
0
0
1
Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16]
TBiMR (i=0 to 2)
0
Selection of pulse period / pulse width measurement mode
Measurement mode select bit
b3 b2
0 0 : Pulse period measurement
(Interval between measurement pulse falling edge to falling edge)
Fixed to “0” in pulse period/pulse width measurement mode (i = 0)
This bit can neither be set nor reset (i = 1,2)
Timer Bi overflow flag
0 : Timer did not overflow
1 : Timer has overflowed
Count source select bit
b7 b6
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Count
source
Count source period
f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by
dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 038016]
TABSR
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
Start count
Clearing overflow flag
b7
b0
0
Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16]
TBiMR (i=0 to 2)
Timer Bi overflow flag
0 : Timer did not overflow
Figure 2.3.9. Set-up procedure of pulse period measurement mode
221
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.3.5 Operation of Timer B (pulse width measurement mode)
In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.3.4. Operations of the circled items are described below. Figure 2.3.10 shows the operation timing, and Figure
2.3.11 shows the set-up procedure.
Table 2.3.4. Choosed functions
Item
Count source
Set-up
O
Internal count source (f1 / f8 / f32 / fc32)
Pulse period measurement (interval between measurement pulse falling edge to falling edge)
Measurement
mode
Pulse period measurement (interval between measurement pulse rising edge to rising edge)
O
Pulse width measurement (interval between measurement pulse falling edge to rising edge,
and between rising edge to falling edge)
Operation (1) Setting the count start flag to “1” causes the counter to start counting the count source.
(2) If an effective edge of a pulse to be measured is input, the value of the counter goes to
“000016”, and measurement is started. In this instance, an indeterminate value is transferred
to the reload register. The timer Bi interrupt request is not generated.
(3) If an effective edge of a pulse to be measured is input again, the value of the counter is
transferred to the reload register, and the timer Bi interrupt request bit goes to “1”. Then the
value of the counter becomes “000016”, and measurement is started again.
Note
• The timer Bi interrupt request bit goes to “1” when an effective edge of a pulse to be measured
is input or timer Bi overflows. The factor of interrupt request can be determined by use of the
timer Bi overflow flag within the interrupt routine.
• The value of the counter at the beginning of a count is indeterminate. Thus there can be instances in which the timer Bi overflow flag goes to “1” immediately after a count is performed.
• The timer Bi overflow flag goes to “0” if timer Bi mode register is written to when the count start
flag is “1”. This flag cannot be set to “1” by software.
(1) Start count
(3) Start measurement again
(2) Start measurement
Count source
Measurement pulse
“H”
“L”
Reload register ← counter
transfer timing
Transfer
(indeterminate
value)
Transfer(measured value)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Timing at which counter
reaches “000016”
Count start flag
“1”
“0”
Timer Bi interrupt request bit “1”
“0”
Timer Bi overflow flag
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 2.3.10. Operation timing of pulse width measurement mode
222
(Note 2)
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting pulse period / pulse width measurement mode and functions
b7
b0
1
0
1
Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16]
TBiMR (i=0 to 2)
0
Selection of pulse period / pulse width measurement mode
Measurement mode select bit
b3 b2
1 0 : Pulse width measurement (Interval between measurement pulse falling edge to
rising edge, and between rising edge to falling edge)
Fixed to “0” in pulse period/pulse width measurement mode (i = 0)
This bit can neither be set nor reset (i = 1, 2)
Timer Bi overflow flag
0 : Timer did not overflow
1 : Timer has overflowed
Count source select bit
b7 b6
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Count source period
Count
source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by
dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 038016]
TABSR
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
Start count
Clearing overflow flag
b7
b0
0
Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16]
TBiMR (i=0 to 2)
Timer Bi overflow flag
0 : Timer did not overflow
Figure 2.3.11. Set-up procedure of pulse width measurement mode
223
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.3.6 Precautions for Timer B (timer mode, event counter mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Bi register, then set the
flag to “1”.
(2) Reading the timer Bi register while a count is in progress allows reading, with arbitrary timing,
the value of the counter. Reading the timer Bi register with the reload timing shown in Figure
2.3.12 gets “FFFF16”. Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value.
Reload
Counter value (Hex.)
2
1
0
n
n–1
Read value (Hex.)
2
1
0
FFFF
n–1
Time
n = reload register content
Figure 2.3.12. Reading timer Bi register
224
Mitsubishi microcomputers
M30218 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode)
(1) The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse
is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of
the timer Bi overflow flag within the interrupt routine.
(2) If the timer overflow occurs simultaneously with the input of a measurement pulse, and if the
interrupt factor cannot be determined from the timer Bi overflow flag, connect the timers and
count the number of overflows.
(3) When reset, the timer Bi overflow flag goes to “1”. This flag can be set to “0” by writing to the
timer Bi mode register when the count start flag is “1”.
(4) Use the timer Bi interrupt request bit to detect only overflows. Use the timer Bi overflow flag
only to determine the interrupt factor within the interrupt routine.
(5) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated.
(6) The value of the counter is indeterminate at the beginning of a count. Therefore the timer Bi
overflow flag may go to “1” immediately after a count is started.
(7) If changing the measurement mode select bit is set after a count is started, the timer Bi
interrupt request bit goes to “1”.
(8) If the input signal to the TBiIN pin is affected by noise, precise measurement may not be
performed in some cases. It is recommended to see that measurements fall within a specific
range by use of software.
(9) For pulse width measurement, pulse widths are successively measured. Use software to
check whether the measurement result is an “H” level width or an “L” level width.
225
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.4 Clock-Synchronous Serial I/O
2.4.1 Overview
Clock-synchronous serial I/O carries out 8-bit data communications in synchronization with the clock. The
following is an overview of the clock-synchronous serial I/O.
(1) Transmission/reception format
8-bit data
(2) Transfer rate
If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit
rate generator division, becomes the transfer rate. The bit rate generator count source can be selected from the following: f1, f8, and f32. Clocks f1, f8, and f32 are derived by dividing the CPU’s main
clock by 1, 8, and 32 respectively.
Furthermore, if an external clock is selected as the transfer clock, the clock frequency input to the CLK
pin becomes the transfer rate.
(3) Error detection
Only overrun error can be detected. Overrun error is an error that occurs when the next data is made
ready before the reception buffer register is read.
(4) How to deal with an error
When receiving data, read an error flag and reception data simultaneously to determine which error
has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive buffer
register, then receive the data again.
To initialize the UARTi receive buffer register
1. Set the receive enable bit to “0” (disable reception).
2. Set the serial I/O mode select bit to “0002” (invalid serial I/O).
3. Set the serial I/O mode select bit.
4. Set the receive enable bit to “1” again (enable reception).
To transmit data again due to an error on the reception side, set the UARTi transmit buffer register
again, then transmit the data again.
To set the UARTi transmit buffer register again
1. Set the serial I/O mode select bits to “0002” (invalidate serial I/O).
2. Set the serial I/O mode select bits again.
3. Set the transmit enable bit to “1” (enable transmission), then set transmission data in the UARTi
transmit buffer register.
(5) Function selection
For clock-synchronous serial I/O, the following functions can be selected:
_______ _______
(a) CTS/RTS function
_______
In the CTS function, an external IC can start transmission/reception by inputting an “L” level to the
_______
_______
CTS pin. The CTS pin input level is detected when transmission/reception starts. Therefore, if the
level is set to “H” during transmission/reception, it will stop from the next data.
_______
_______
_______
The RTS function informs an external IC that RTS is reception-ready and has changed to “L”. RTS
goes to “H” at the falling edge of the transfer clock.
_______ _______
The clock-synchronous serial I/O has three types of CTS/RTS functions to choose from:
_______ _______
_______ _______
• CTS/RTS functions disabled
CTS/RTS pin is a programmable I/O port.
_______
_______ _______
_______
• CTS function only enabled
CTS/RTS pin performs the CTS function.
_______
_______ _______
_______
• RTS function only enabled
CTS/RTS pin performs the RTS function.
226
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(b) Function for choosing polarity
This function switches the polarity of the transfer clock. The following operations are available:
• Data is input at the falling edge of the transfer clock, and is output at the rising edge.
• Data is input at the rising edge of the transfer clock, and is output at the falling edge.
(c) Function for choosing which bit to transmit first
This function is to choose whether to transmit data from bit 0 or from bit 7. Choose either of the
following:
• LSB first
Data is transmitted from bit 0.
• MSB first
Data is transmitted from bit 7.
(d) Function for choosing successive reception mode
Successive reception mode is a mode in which reading the receive buffer register makes the reception-enabled status ready. In this mode, there is no need to write dummy data to the transmit buffer
register so as to make the reception-enabled status ready. But at the time of starting reception, read
the receive buffer register into a dummy manner.
• Normal mode
Writing dummy data to the transmit buffer register makes the
reception enabled status ready.
Reading the reception buffer register makes the reception-enabled
• Successive reception mode
status ready.
(e) Function for outputting transfer clock to multiple pins
This function is to switch among pins to output the transfer clock. This function is effective only when
selecting the internal clock. Switching among pins for outputting the transfer clock allows data transmission to two external ICs in a time-sharing manner.
(f) Function for choosing a transmission interrupt factor
The timing to generate a transmission interrupt can be selected from the following: the instant the
transmission buffer is emptied or the instant the transmission register is emptied. When transmission buffer empty timing is selected, an interrupt occurs when transmitted data is moved from the
transmission buffer to the transmission register. Therefore, data can be transmitted in succession.
When transmission register empty timing is selected, an interrupt occurs when data transmission is
complete.
Following are some examples in which various functions (a) through (f) are selected:
_______
• Transmission Operation WITH: CTS function, transmission at falling edge of transfer clock, LSB
First, interrupt at instant transmission buffer is emptied; WITHOUT transfer clock output to multiple
pins function ............................................................................................................................ P232
_______ _______
• Transmission Operation WITH: CTS/RTS function disabled, transmission at falling edge of transfer
clock, LSB First, interrupt at instant transmission is completed; WITH transfer clock output to multiple pins function (UART0 selection available) ....................................................................... P236
_______
• Reception WITH: RTS function, reception at falling edge of transfer clock, LSB First, successive
reception mode disabled; WITHOUT transfer clock output to multiple pins function .............. P240
227
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(6) Input to the serial I/O and the direction register
To input an external signal to the serial I/O, set the direction register of the relevant port to input.
(7) Pins related to the serial I/O
_______
_______
• CTS0, CTS1 pins
Input pins for the CTS function
________
_______
• RTS0, RTS1 pins
Output pins for the RTS function
• CLK0, CLK1 pins
Input/output pins for the transfer clock
• RxD0, RxD1 pins
Input pins for data
• TxD0, TxD1 pins
Output pins for data.
• CLKS1 pin
Output pin for transfer clock. Can be used as transfer clock output pin in
the transfer clock output to multiple pins function.
(8) Registers related to the serial I/O
Figure 2.4.1 shows the memory map of serial I/O-related registers, and Figures 2.4.2 to 2.4.4 show
serial I/O-related registers.
005116
005416
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control regster(S1TIC)
UART1 receive interrupt control register(S1RIC)
03A016
UART0 transmit/receive mode register (U0MR)
03A116
UART0 bit rate generator (U0BRG)
005216
005316
03A216
03A316
03A416
03A516
03A616
03A716
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
03A816
UART1 transmit/receive mode register (U1MR)
03A916
UART1 bit rate generator (U1BRG)
03AA16
03AB16
03AC16
03AD16
03AE16
UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
03AF16
UART1 receive buffer register (U1RB)
03B016
UART transmit/receive control register 2 (UCON)
03B116
Figure 2.4.1. Memory map of serial I/O-related registers
228
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit buffer register
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0TB
U1TB
Address
03A316, 03A216
03AB16, 03AA16
When reset
Indeterminate
Indeterminate
Function
R W
Transmission data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
UARTi receive buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U1RB
b0
Bit
symbol
Address
03A716, 03A616
03AF16, 03AE16
When reset
Indeterminate
Indeterminate
Function
(During clock synchronous
serial I/O mode)
Bit name
Reception data
Function
(During UART mode)
R W
Reception data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
OER
Overrun error flag (Note)
0 : No overrun error
1 : Overrun error found
FER
Framing error flag (Note) Invalid
0 : No framing error
1 : Framing error found
PER
Parity error flag (Note)
0 : No parity error
1 : Parity error found
Invalid
0 : No overrun error
1 : Overrun error found
0 : No error
1 : Error found
Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses
03A016 and 03A816) are set to “0002” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when
the lower byte of the UARTi receive buffer register (addresses 03A616 and 03AE16) is read out.
SUM
Error sum flag (Note)
Invalid
UARTi bit rate generator
b7
b0
Symbol
U0BRG
U1BRG
Address
03A116
03A916
When reset
Indeterminate
Indeterminate
Function
Assuming that set value = n, BRGi divides the count
source by (n + 1)
Figure 2.4.2. Serial I/O-related registers (1)
229
Values that can be set
0016 to FF16
R W
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
Symbol
UiMR (i=0,1)
b0
Bit
symbol
Address
03A016, 03A816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit name
SMD0 Serial I/O mode select bit
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
Function
(During UART mode)
R W
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock
0 : Internal clock
1 : External clock
STPS
Stop bit length select bit
Invalid
0 : One stop bit
1 : Two stop bits
PRY
Odd/even parity select bit Invalid
PRYE
Parity enable bit
Invalid
0 : Parity disabled
1 : Parity enabled
SLEP
Sleep select bit
Must always be “0”
0 : Sleep mode deselected
1 : Sleep mode selected
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
UARTi transmit/receive control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UiC0 (i=0,1)
Bit
symbol
CLK0
Address
When reset
03A416, 03AC16
0816
Bit name
TXEPT
b1 b0
Function
(During UART mode)
b1 b0
BRG count source
select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function
select bit
Valid when bit 4 = “0”
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CLK1
CRS
Function
(During clock synchronous
serial I/O mode)
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit register
Transmit register empty 0 : Data present in transmit
register (during transmission)
(during transmission)
flag
1 : No data present in transmit
register
(transmission completed)
1 : No data present in transmit
register (transmission completed)
CRD
CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P47 and P77 function as
programmable I/O port)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P47 and P77 function as
programmable I/O port)
NCH
Data output select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
CKPOL
CLK polarity select bit
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Must always be “0”
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Figure 2.4.3. Serial I/O-related registers (2)
230
R W
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
Symbol
UiC1(i=0,1)
b0
Bit
symbol
Address
03A516, 03AD16
When reset
0216
Function
(During clock synchronous serial
I/O mode)
Bit name
Function
(During UART mode)
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer empty
flag
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
R W
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
UART transmit/receive control register 2
b7
b6
0
b5
b4
b3
b2
b1
b0
Symbol
UCON
Bit
symbol
Address
03B016
When reset
X00000002
Function
(During clock synchronous serial
I/O mode)
Bit name
Function
(During UART mode)
U0IRS
UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0RRM
UART0 continuous receive
mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Invalid
U1RRM
UART1 continuous receive
mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
CLKMD0
CLK/CLKS select bit 0
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD1
CLK/CLKS select bit 1
(Note)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
Must always be “0”
Must always be “0”
Must always be “0”
Reserved bit
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirement must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
Figure 2.4.4. Serial I/O-related registers (3)
231
RW
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.4.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode)
In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table
2.4.1. Operations of the circled items are described below. Figure 2.4.5 shows the operation timing, and
Figures 2.4.6 and 2.4.7 show the set-up procedures.
Table 2.4.1. Choosed functions
Item
Set-up
Transfer clock
source
O
CTS function
O
Item
Internal clock (f 1 / f8 / f32)
External clock (CLKi pin)
CTS function enabled
CTS function disabled
CLK polarity
O
Set-up
Transmission
interrupt factor
O
Output transfer clock
to multiple pins
(Note)
O
Transmission buffer empty
Transmission complete
Not selected
Selected
Output transmission data at
the falling edge of the
transfer clock
Output transmission data at
the rising edge of the
transfer clock
Transfer clock
O
LSB first
MSB first
Note: This can be selected only when UART1 is used in combination with the internal clock. When this function is
_______ _______
_______ _______
selected, UART1 CTS/RTS function cannot be utilized. Set the UART1 CTS/RTS disable bit to “1”.
Operation (1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit
buffer register makes data transmissible status ready.
________
_______
(2) When input to the CTSi pin goes to “L” level, transmission starts (the CTSi pin must be
controlled on the reception side).
(3) In synchronization with the first falling edge of the transfer clock, transmission data held in the
UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the
UARTi transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is
transmitted from the TxDi pin. Then the data is transmitted bit by bit from the lower order in
synchronization with the falling edges.
(4) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”,
which indicates that transmission is completed. The transfer clock stops at “H” level.
(5) If the next transmission data is set in the UARTi transmit buffer register while transmission is
in progress (before the eighth bit has been transmitted), the data is transmitted in succession.
232
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example of wiring
Microcomputer
Receiver side IC
CLKi
CLK
TXDi
RXD
CTSi
Port
Example of operation
AAAAAAAAA
AAAAAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA AAAAAAAAA
(1) Transmission enabled
(2) Confirming CTS
(3) Start transmission Tc
(4) Transmission is complete
(5) Transmit next data
Transfer clock
Transmit
enable bit (TE)
“1”
Transmit
buffer empty
flag (Tl)
“1”
“0”
Data is set to UARTi transmit buffer register
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
CTSi
“L”
TCLK
Stopped pulsing because CTSi = “H”
Stopped pulsing because
transfer enable bit = “0”
CLKi
TxDi
D0 D1 D2 D3 D4 D5 D6
D7
D0 D 1 D 2 D 3 D4 D5 D 6 D 7
D 0 D1 D 2 D 3 D 4 D 5 D 6 D7
Transmit register “1”
empty flag
“0”
(TXEPT)
“1”
Transmit
interrupt request “0”
bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f1, f8, f32)
n: value set to BRGi
Figure 2.4.5. Operation timing of transmission in clock-synchronous serial I/O mode
233
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M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting UARTi transmit/receive mode register (i=0, 1)
b7
0
0
0
0
b0
UART0 transmit/receive mode register
1
U0MR [Address 03A016]
UART1 transmit/receive mode register
U1MR [Address 03A816]
Must be fixed to “001”
Internal/external clock select bit
0 : Internal clock
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Sleep select bit
Must be “0” in clock synchronous I/O mode
Setting UARTi transmit/receive control register 0 (i=0, 1)
b7
0
b0
0
0
0
UART0 transmit/receive control register 0
U0C0 [Address 03A4 16]
UART1 transmit/receive control register 0
U1C0 [Address 03AC 16]
BRG count source select bit
b1 b0
0 0 : f 1 is selected
0 1 : f 8 is selected
1 0 : f 32 is selected
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = “0”)
0 : CTS function is selected (Note)
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
0 : CTS/RTS function enabled
Data output select bit
0 : TxDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
CLK polarity select bit
0 : Transmission data is output at falling edge
of transfer clock and reception data is input
at rising edge
Transfer format select bit
0 : LSB first
Note: Set the corresponding port direction register to “0” .
Setting UART transmit/receive control register 2
b7
b0
0
0
0
0
UART transmit/receive control register 2
UCON [Address 03B0 16]
UART0 transmit interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
UART1 transmit interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
Valid when bit 5 = “1”
CLK/CLKS select bit 1
0 : Normal mode (CLK output is CLK1 only)
Fix “0” to this bit.
Continued to the next page
Figure 2.4.6. Set-up procedure of transmission in clock-synchronous serial I/O mode (1)
234
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M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Setting UARTi bit rate generator (i = 0, 1)
b7
b0
UARTi bit rate generator (i = 0, 1) [Address 03A1 16, 03A916]
UiBRG (i = 0, 1)
Can be set to 00 16 to FF 16 (Note)
Note: Write to UARTi bit rate generator when transmission/reception is halted.
Transmission enabled
b7
UART0 transmit/receive control register 1
U0C1 [Address 03A5 16]
1 UART1 transmit/receive control register 1
U1C1 [Address 03AD 16]
b0
Transmit enable bit
1 : Transmission enabled
Writing transmit data
(b15)
b7
(b8)
b0 b7
b0
UART0 receive buffer register [Address 03A3 16, 03A216] U0TB
UART1 receive buffer register [Address 03AB 16, 03AA16] U1TB
Setting transmission data
When CTSi input level = “L”
Start transmission
Checking the status of UARTi transmit /receive control register (i = 0, 1)
b7
b0
UART0 transmit/receive control register 1
U0C1 [Address 03A5 16]
UART1 transmit/receive control register 1
U1C1 [Address 03AD 16]
Transmit buffer empty flag
0 : Data present in transmit
buffer register
1 : No data present in transmit
buffer register
(Writing next transmit data enabled)
Writing next transmit data
(b15)
b7
(b8)
b0 b7
b0
UART0 transmit buffer register [Address 03A3 16, 03A2 16] U0TB
UART1 transmit buffer register [Address 03AB 16, 03AA 16] U1TB
Setting transmission data
Transmission is complete
Figure 2.4.7. Set-up procedure of transmission in clock-synchronous serial I/O mode (2)
235
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.4.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O
mode, transfer clock output from multiple pins function selected)
In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table
2.4.2. Operations of the circled items are described below. Figure 2.4.8 shows the operation timing, and
Figures 2.4.9 and 2.4.10 show the set-up procedures.
Table 2.4.2. Choosed functions
Item
Transfer clock
source
Set-up
O
Item
Internal clock (f 1 / f8 / f32)
External clock (CLKi pin)
CTS function enabled
CTS function
O
CTS function disabled
O
Output transmission data at
the falling edge of the
transfer clock
CLK polarity
Transmission
interrupt factor
Output transfer clock
to multiple pins
(Note 1)
Set-up
Transmission buffer empty
O
Transmission complete
Not selected
O
Selected
Output transmission data at
the rising edge of the
transfer clock
Transfer clock
O
LSB first
MSB first
Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is
_______ _______
_______ _______
selected, UART1 CTS/RTS function cannot be utilized. Set the UART1 CTS/RTS disable bit to “1”.
Operation (1) Setting the transmit enable bit to “1” makes data transmissible status ready.
(2) When transmission data is written to the UART1 transmit buffer register, transmission data
held in the UART1 transmit buffer register is transmitted to the UART1 transmit register in
synchronization with the first falling edge of the transfer clock. At this time, the first bit of the
transmission data is transmitted from the TxD1 pin. Then the data is transmitted bit by bit
from the lower order in synchronization with the falling edges of the transfer clock.
(3) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”,
which indicates that the transmission is completed. The transfer clock stops at “H” level. At
this time, the UART1 transmit interrupt request bit goes to “1”.
(4) Setting CLK/CLKS select bit 1 to “1” and setting CLK/CLKS select bit 0 to “1” causes the
CLKS1 pin to go to the transfer clock output pin. Change the transfer clock output pin when
transmission is halted.
236
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example of wiring
Microcomputer
TXD1 (P6 7)
CLKS 1 (P6 4)
CLK1 (P6 5)
IN
IN
CLK
CLK
Note: This applies when performing only transmission with an internal
clock selected in the clock synchronous serial I/O mode.
Example of operation
(1) Transmission enabled
(3) Transmission is complete
(2) Start transmission
(4) Clock switched
Transfer clock
Transmit enable bit
“1”
“0”
Transmit buffer
empty flag
CLK, CLKS
select bit 1
CLK, CLKS
select bit 0
“1”
“0”
“1”
“0”
“1”
“0”
CLK1
CLKS1
D0 D1 D 2 D3 D4 D5 D6 D7
TxD1
Transmit interrupt
request bit
D0 D1 D2 D3 D4 D5 D6 D7
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 2.4.8. Operation timing of transmission in clock-synchronous serial I/O mode, transfer
clock output from multiple pins function selected
237
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting UART1 transmit/receive mode register
b7
b0
0
0
0
0
1
UART1 transmit/receive mode register [Address 03A8
U1MR
16]
Must be fixed to “001”
Internal/external clock select bit
0 : Internal clock
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Sleep select bit
Must be “0” in clock synchronous I/O mode
Setting UART1 transmit/receive control register 0
b7
0
b0
0
1
UART1 transmit/receive control register 0 [Address 03AC
U1C0
16]
BRG count source select bit
b1 b0
0 0 : f 1 is selected
0 1 : f 8 is selected
1 0 : f 32 is selected
1 1 : Inhibited
Valid when bit 4 = “0”
Transmit register empty flag
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register (transmission completed)
CTS/RTS disable bit
1 : CTS/RTS function disabled
Data output select bit
0 : TXDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
CLK polarity select bit
0 : Transmission data is output at falling edge of transfer clock and
reception data is input at rising edge
Transfer format select bit
0 : LSB first
Setting UART transmit/receive control register 2
b7
b0
0
1
1
UART transmit/receive control register 2 [Address 03B0
UCON
16]
UART0 transmit interrupt cause select bit
1 : Transmission completed (TXEPT = 1)
CLK/CLKS select bit 0
0 : Clock output to CLK1
1 : Clock output to CLKS1
CLK/CLKS select bit 1
1 : Transfer clock output from multiple pins function selected
Fix “0” to this bit.
Continued to the next page
Figure 2.4.9. Set-up procedure of transmission in clock-synchronous serial I/O mode, transfer
clock output from multiple pins function selected (1)
238
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M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Setting UART1 bit rate generator
b7
b0
UART1 bit rate generator [Address 03A9 16]
U1BRG
Can be set to 00 16 to FF 16 (Note)
Note: Write to UARTi bit rate generator when transmission/reception is halted.
Transmission enabled
b7
b0
1
UART1 transmit/receive control register 1 [Address 03AD
U1C1
16]
Transmit enable bit
1 : Transmission enabled
Writing transmit data
(b15)
b7
(b8)
b0 b7
b0
UART1 transmit buffer register [Address 03AB 16, 03AA16]
U1TB
Setting transmission data
Start transmission
Checking the status of UART1 transmit buffer register
b7
b0
UART1 transmit/receive control register 1 [Address 03AD
U1C1
16]
Transmit buffer empty flag
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register (Writing next transmit data enabled)
Writing next transmit data
(b15)
b7
(b8)
b0 b7
b0
UART1 transmit buffer register [Address 03AB 16, 03AA16]
U1TB
Setting transmission data
Transmission is complete
Figure 2.4.10. Set-up procedure of transmission in clock-synchronous serial I/O mode, transfer
clock output from multiple pins function selected (2)
239
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.4.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode)
In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.4.3.
Operations of the circled items are described below. Figure 2.4.11 shows the operation timing, and Figures 2.4.12 and 2.4.13 show the set-up procedures.
Table 2.4.3. Choosed functions
Item
Transfer clock
source
RTS function
Set-up
Item
Internal clock (f 1 / f8 / f32)
O
O
External clock (CLKi pin)
RTS function enabled
RTS function disabled
CLK polarity
O
Set-up
Continuous receive
mode
O
Output transfer clock
to multiple pins
(Note 1)
O
Disabled
Enabled
Not selected
Selected
Input reception data at
the rising edge of the
transfer clock
Input reception data at
the falling edge of the
transfer clock
Transfer clock
O
LSB first
MSB first
Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is
_______ _______
_______ _______
selected, UART1 CTS/RTS function cannot be utilized. Set the UART1 CTS/RTS disable bit to “1”.
Operation (1) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”,
and the transmit enable bit to “1”, makes the data receivable status ready. At this time, the
________
output from the RTSi pin goes to “L” level, which informs the transmission side that the data
receivable status is ready (output the transfer clock from the IC on the transmission side after
_______
checking that the RTS output has gone to “L” level).
(2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDi
pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting
right the content of the UARTi reception data in synchronization with the rising edges of the
transfer clock.
(3) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive
register is transmitted to the UARTi receive buffer register. The transfer clock stops at “H”
level. At this time, the receive complete flag and the UARTi receive interrupt request bit goes
to “1”.
(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi receive buffer
register is read.
240
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example of wiring
Microcomputer
Transmitter side IC
CLKi
CLK
RXDi
TXD
RTSi
Port
Example of operation
(1) Reception enabled
(3) Reception is complete
(2) Start reception
“1”
Receive enable
bit (RE)
“0”
Transmit enable
bit (TE)
“0”
Transmit buffer
empty flag (Tl)
(4) Read of reception data
“1”
Dummy data is set in UARTi transmit buffer register
“1”
“0”
“H”
Transferred from UARTi transmit buffer register to UARTi transmit register
RTSi
“L”
1 / fEXT
CLKi
Reception data is taken in
D0 D1 D2 D3 D4 D5 D6
RxDi
Receive complete “1”
flag (Rl)
“0”
Receive interrupt
request bit (IR)
Transferred from UARTi receive register
to UARTi receive buffer register
D7
D0 D1 D2
D3 D4 D5
Read out from UARTi receive buffer register
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
Make sure that the following conditions are met when
the CLKi pin input =“H” before data reception
• Transmit enable bit → “1”
• Receive enable bit → “1”
• Dummy data write to UARTi transmit buffer register
fEXT: frequency of external clock
Figure 2.4.11. Operation timing of reception in clock-synchronous serial I/O mode
241
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting UARTi transmit/receive mode register (i=0, 1)
b7
b0
0
1
0
0
1
UART0 transmit/receive mode register
U0MR [Address 03A016]
UART1 transmit/receive mode register
U1MR [Address 03A816]
Must be fixed to “001”
Internal/external clock select bit
1 : External clock
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Sleep select bit
Must be “0” in clock synchronous I/O mode
Setting UARTi transmit/receive control register 0 (i=0, 1)
b7
0
b0
0
0
1
UART0 transmit/receive control register 0
U0C0 [Address 03A4 16]
UART1 transmit/receive control register 0
U1C0 [Address 03AC 16]
BRG count source select bit
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = “0”)
1 : RTS function is selected
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
0 : CTS/RTS function enabled
Data output select bit
0 : TxDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
CLK polarity select bit
0 : Transmission data is output at falling edge
of transfer clock and reception data is input
at rising edge
Transfer format select bit
0 : LSB first
Setting UART transmit/receive control register 2
b7
b0
0
0
0
0
UART transmit/receive control register 2
UCON [Address 03B0 16]
UART0 continuous receive mode enable bit
0 : Continuous receive mode disabled
UART1 continuous receive mode enable bit
0 : Continuous receive mode disabled
Valid when bit 5 = “1”
CLK/CLKS select bit 1
0 : Normal mode (CLK output is CLK1 only)
Fix “0” to this bit.
Continued to the next page
Figure 2.4.12. Set-up procedure of reception in clock-synchronous serial I/O mode (1)
242
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Reception enabled
b7
b0
1
UART0 transmit/receive control register 1 [Address 03A5 16] U0C1
UART1 transmit/receive control register 1 [Address 03AD 16] U1C1
1
Transmit enable bit
1 : Transmission enabled
Receive enable bit
1 : Reception enabled
Writing dummy data
(b15)
b7
(b8)
b0 b7
b0
UART0 transmit buffer register [Address 03A3 16, 03A216] U0TB
UART1 transmit buffer register [Address 03AB 16, 03AA16] U1TB
Setting dummy data
Start reception
Checking completion of reception
b7
b0
UART0 transmit/receive control register 1 [Address 03A5 16] U0C1
UART1 transmit/receive control register 1 [Address 03AD 16] U1C1
Receive complete flag
0 : No data present in receive buffer register
1 : Data present in receive buffer register
Checking error
(b15)
b7
(b8)
b0 b7
b0
UART0 receive buffer register [Address 03A7 16, 03A6 16]U0RB
UART1 receive buffer register [Address 03AF 16, 03AE 16]U1RB
Receive data
Overrun error flag
0 : No overrun error
1 : Overrun error found
Processing after reading out reception data
Figure 2.4.13. Set-up procedure of reception in clock-synchronous serial I/O mode (2)
243
Mitsubishi microcomputers
M30218 Group
Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.4.5 Precautions for Serial I/O (in clock-synchronous serial I/O)
Transmission/reception
_______
________
(1) With an external clock selected, and choosing the RTS function, the output level of the RTSi
pin goes to “L” when the data-receivable status becomes ready, which informs the transmis________
sion side that the reception has become ready. The output level of the RTSi pin goes to “H”
________
________
when reception starts. So if the RTSi pin is connected to the CTSi pin on the transmission
side, the circuit can transmission and reception data with consistent timing. With the internal
_______
clock, the RTS function has no effect. Figure 2.4.14 shows an example of wiring.
Transmitter side IC
Receiver side IC
TxDi
TxDi
RxDi
RxDi
CLKi
CLKi
CTSi
RTSi
Figure 2.4.14. Example of wiring
244
Mitsubishi microcomputers
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Clock-Synchronous Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transmission
(1) With an external clock selected, perform the following set-up procedure with the CLKi pin
input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the
CLK polarity select bit = “1”:
1. Set the transmit enable bit (to “1”)
2. Write transmission data to the UARTi transmit buffer register
________
_______
3. “L” level input to the CTSi pin (when the CTS function is selected)
Reception (1) In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock.
Fix settings for transmission even when using the device only for reception. Dummy data is
output to the outside from the TxDi pin (transmission pin) when receiving data.
(2) With the internal clock selected, setting the transmit enable bit to “1” (transmission-enabled
status) and setting dummy data in the UARTi transmission buffer register generates a shift
clock.
With the external clock selected, a shift clock is generated when the transmit enable bit is set
to “1”, dummy data is set in the UARTi transmit buffer register, and the external clock is input
to the CLKi pin.
(3) In receiving data in succession, an overrun error occurs when the next reception data is made
ready in the UARTi receive register with the receive complete flag set to “1” (before the
content of the UARTi receive buffer register is read), and overrun error flag is set to “1”. In this
instance, the next data is written to the UARTi receive buffer register, so handle with this
problem by writing programs on transmission side and reception side so that the previous
data is transmitted again.
If an overrun error occurs, the UARTi receive interrupt request bit does not go to “1”.
(4) To receive data in succession, set dummy data in the lower-order byte of the UARTi transmit
buffer register every time reception is made.
(5) With an external clock selected, perform the following set-up procedure with the CLKi pin
input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the
CLK polarity select bit = “1”:
1. Set receive enable bit (to “1”)
2. Set transmit enable bit (to “1”)
3. Write dummy data to the UARTi transmit buffer register
_______
(6) Output from the RTS pin goes to “L” level as soon as the receive enable bit is set to “1”. This
is not related to the content of the transmit buffer empty flag or the content of the transmit
enable bit.
_______
Output from the RTS pin goes to “H” level when reception starts, and goes to “L” level when
reception is completed. This is not related to the content of the transmit buffer empty flag or
the content of the receive complete flag.
245
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.5 Clock-Asynchronous Serial I/O (UART)
2.5.1 Overview
UART handles communications by means of character-by-character synchronization. The transmission
side and the reception side are independent of each other, so full-duplex communication is possible. The
following is an overview of the clock-asynchronous serial I/O.
(1) Transmission/reception format
Figure 2.5.1 shows the transmission/reception format, and Table 2.5.1 shows the names and functions of transmission data.
Transfer data length : 7 bits
1ST – 7DATA
1ST – 7DATA
1ST – 7DATA – 1PAR –
1ST – 7DATA – 1PAR –
1SP
2SP
1SP
2SP
Transfer data length : 8 bits
1ST – 8DATA
1ST – 8DATA
1ST – 8DATA – 1PAR –
1ST – 8DATA – 1PAR –
1SP
2SP
1SP
2SP
Transfer data length : 9 bits
1ST – 9DATA
1ST – 9DATA
1ST – 9DATA – 1PAR –
1ST – 9DATA – 1PAR –
1SP
2SP
1SP
2SP
ST
DATA
PAR
SP
: Start bit
: Character bit (Transfer data)
: Parity bit
: Stop bit
Figure 2.5.1. Transmission/reception format
Table 2.5.1. Transmission data names and functions
Name
ST (start bit)
Function
A 1-bit “L” signal to be added immediately before character bits.
This bit signals the start of data transmission.
DATA (character bits)
Transmission data set in the UARTi transmit buffer register.
PAR (parity bit)
A signal to be added immediately after character bits so as to increase data
reliability. The level of this signal so varies that the total number of 1's in
character bits and this bit always becomes even or odd depending on which
parity is chosen, even or odd.
SP (stop bit)
Either 1-bit or 2-bit “H” signal to be added immediately after character bits (after
the parity bit if parity is checked). This / they signals the end of data
transmission.
246
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Transfer rate
The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the transfer rate. The count source for the bit rate generator can be selected from f 1, f8, f32, and the input from
the CLK pin. Clocks f1, f8, f32 are derived by dividing the CPU’s main clock by 1, 8, and 32 respectively.
Table 2.5.2. Example of baud rate setting
Baud rate
(bps)
BRG's
count source
System clock : 10MHz
BRG's set value : n
System clock : 7.3728MHz
Actual time (bps)
BRG's set value : n
Actual time (bps)
600
f8
129 (8116)
600
95 (5F16)
600
1200
f8
64 (4016)
1201
47 (2F16)
1200
2400
f8
32 (2016)
2367
23 (1716)
2400
4800
f1
129 (8116)
4807
95 (5F16)
4800
9600
f1
64 (4016)
9615
47 (2F16)
9600
14400
f1
42 (2A16)
14534
31 (1F16)
14400
19200
f1
32 (2016)
18939
23 (1716)
19200
28800
f1
21 (1516)
28409
15 (F16)
28800
31250
f1
19 (1316)
31250
(3) An error detection
In clock-asynchronous serial I/O mode, detect errors are shown in Table 2.5.3.
Table 2.5.3. Error detection
Type of error
Overrun error
Description
When the flag turns on
• This error occurs when the
next data lines up before the
content of the UARTi receive
buffer register is read.
• The next data is written to the
UARTi receive buffer register.
• The UARTi receive interrupt
request bit does not go to “1”.
Framing error
• This error occurs when the
stop bit falls short of the set
number of stop bits.
Parity error
• With parity enabled, this error
occurs when the total number
of 1's in character bits and the
parity bit is different from the
specified number.
Error-sum flag
• This flag turns on when any
error (overrun, framing, or
parity) is detected.
How to clear the flag
• Set the serial I/O mode select
bits to “0002”.
• Set the receive enable bit to
“0”.
The error is detected
• Set the serial I/O mode select
when data is
bits to ”0002”.
transferred from the
•
UARTi receive register Set the receive enable bit to
“0”.
to the UARTi receive
•
Read the lower-order byte of
buffer register.
the UARTi receive buffer
register.
• When all error (overrun,
framing, and parity) are
removed, the flag is cleared.
247
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) How to deal with an error
When receiving data, read an error flag and reception data simultaneously to determine which error
has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive buffer
register, then receive the data again.
To initialize the UARTi receive buffer register
1. Set the receive enable bit to “0” (disable reception).
2. Set the receive enable bit to “1” again (enable reception).
To transmit data again due to an error on the reception side, set the UARTi transmit buffer register
again, then transmit the data again.
To set the UARTi transmit buffer register again
1. Set the serial I/O mode select bits to “0002” (invalidate serial I/O).
2. Set the serial I/O mode select bits again.
3. Set the transmit enable bit to “1” (enable transmission), then set transmission data in the UARTi
transmit buffer register.
(5) Functions selection
In operating UART, the following functions can be used:
_______ _______
(a) CTS/RTS function
_______
CTS function is a function in which an external IC can start transmission/reception by means of
_______
_______
inputting an “L” level to the CTS pin. The CTS pin input level is detected when transmission/reception
starts, so if the level is gone to“ H” while transmission/reception is in progress, transmission/reception stops at the next data.
_______
_______
RTS function is a function to inform an external IC that RTS pin output level has changed to “L” when
_______
reception is ready. RTS regoes to “H” at the falling edge of the transfer clock.
_______ _______
When using clock-asynchronous serial I/O, choose one of three types of CTS/RTS functions.
_______ _______
_______ _______
• CTS/RTS functions disabled
CTS/RTS pin is a programmable I/O port.
_______
_______ _______
_______
• CTS function only enabled
CTS/RTS pin performs the CTS function.
_______
_______ _______
_______
• RTS function only enabled
CTS/RTS pin performs the RTS function.
(b) Sleep mode
Sleep mode is a mode in which data is transferred to a particular microcomputer among those connected by use of clock-asynchronous serial I/O devices.
(c) Data logic select function
This function is to reserve data when writing to transmit buffer register or reading from receive buffer
register.
The following are examples in which functions (a) to (c) are chosen:
_______
• Transmission WITH: CTS function, WITHOUT: other functions ............................................... P254
_______
• Reception WITH: RTS function, WITHOUT: other functions .................................................... P258
248
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(6) Input to the serial I/O and the direction register
To input an external signal to the serial I/O, set the direction register of the relevant port to input.
(7) Pins related to the serial I/O
_________ _________
_______
• CTS0, CTS1 pins
:Input pins for the CTS function
_________ _________
_______
• RTS0, RTS1 pins
:Output pins for the RTS function
• CLK0, CLK1 pins
:Input pins for the transfer clock
• RxD0, RxD1 pins
:Input pins for data
• TxD0, TxD1 pins
:Output pins for data/
249
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M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(8) Registers related to the serial I/O
Figure 2.5.2 shows the memory map of serial I/O-related registers, and Figures 2.5.3 to 2.5.5 show
UARTi-related registers.
005116
UART0 transmit interrupt control register (S0TIC)
005216
UART0 receive interrupt control register (S0RIC)
005316
UART1 transmit interrupt control regster(S1TIC)
005416
UART1 receive interrupt control register(S1RIC)
03A016
UART0 transmit/receive mode register (U0MR)
03A116
UART0 bit rate generator (U0BRG)
03A216
03A316
UART0 transmit buffer register (U0TB)
03A416
UART0 transmit/receive control register 0 (U0C0)
03A516
UART0 transmit/receive control register 1 (U0C1)
03A616
UART0 receive buffer register (U0RB)
03A716
03A816
UART1 transmit/receive mode register (U1MR)
03A916
UART1 bit rate generator (U1BRG)
03AA16
UART1 transmit buffer register (U1TB)
03AB16
03AC16
UART1 transmit/receive control register 0 (U1C0)
03AD16
UART1 transmit/receive control register 1 (U1C1)
03AE16
03AF16
03B016
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
Figure 2.5.2. Memory map of UARTi-related registers
250
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0TB
U1TB
b0
Address
03A316, 03A216
03AB16, 03AA16
When reset
Indeterminate
Indeterminate
Function
R W
Transmission data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
UARTi receive buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U1RB
b0
Bit
symbol
Address
03A716, 03A616
03AF16, 03AE16
When reset
Indeterminate
Indeterminate
Function
(During clock synchronous
serial I/O mode)
Bit name
Reception data
Function
(During UART mode)
R W
Reception data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
OER
Overrun error flag (Note)
0 : No overrun error
1 : Overrun error found
FER
Framing error flag (Note) Invalid
0 : No framing error
1 : Framing error found
PER
Parity error flag (Note)
0 : No parity error
1 : Parity error found
Invalid
0 : No overrun error
1 : Overrun error found
0 : No error
1 : Error found
Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses
03A016 and 03A816) are set to “0002” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when
the lower byte of the UARTi receive buffer register (addresses 03A616 and 03AE16) is read out.
SUM
Invalid
Error sum flag (Note)
UARTi bit rate generator
b7
b0
Symbol
U0BRG
U1BRG
Address
03A116
03A916
When reset
Indeterminate
Indeterminate
Function
Assuming that set value = n, BRGi divides the count
source by (n + 1)
Figure 2.5.3. UARTi-related registers (1)
251
Values that can be set
0016 to FF16
R W
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
Symbol
UiMR (i=0,1)
b0
Bit
symbol
Address
03A016, 03A816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit name
SMD0 Serial I/O mode select bit
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
Function
(During UART mode)
R W
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock
0 : Internal clock
1 : External clock
STPS
Stop bit length select bit
Invalid
0 : One stop bit
1 : Two stop bits
PRY
Odd/even parity select bit Invalid
PRYE
Parity enable bit
Invalid
0 : Parity disabled
1 : Parity enabled
SLEP
Sleep select bit
Must always be “0”
0 : Sleep mode deselected
1 : Sleep mode selected
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
UARTi transmit/receive control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UiC0 (i=0,1)
Bit
symbol
CLK0
Address
When reset
03A416, 03AC16
0816
Bit name
TXEPT
b1 b0
Function
(During UART mode)
b1 b0
BRG count source
select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function
select bit
Valid when bit 4 = “0”
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CLK1
CRS
Function
(During clock synchronous
serial I/O mode)
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit
0 : Data present in transmit register
Transmit register empty
register (during transmission)
(during transmission)
flag
1 : No data present in transmit
1 : No data present in transmit
register
(transmission completed)
register (transmission completed)
CRD
CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P47 and P77 function as
programmable I/O port)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P47 and P77 function as
programmable I/O port)
NCH
Data output select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
CKPOL
CLK polarity select bit
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Must always be “0”
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Figure 2.5.4. UARTi-related registers (2)
252
R W
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
Symbol
UiC1(i=0,1)
b0
Bit
symbol
Address
03A516, 03AD16
When reset
0216
Function
(During clock synchronous serial
I/O mode)
Bit name
Function
(During UART mode)
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer empty
flag
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
R W
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
UART transmit/receive control register 2
b7
b6
0
b5
b4
b3
b2
b1
b0
Symbol
UCON
Bit
symbol
Address
03B016
When reset
X00000002
Function
(During clock synchronous serial
I/O mode)
Bit name
Function
(During UART mode)
U0IRS
UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0RRM
UART0 continuous receive
mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Invalid
U1RRM
UART1 continuous receive
mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
CLKMD0
CLK/CLKS select bit 0
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD1
CLK/CLKS select bit 1
(Note)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
Must always be “0”
Must always be “0”
Must always be “0”
Reserved bit
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirement must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
Figure 2.5.5. UARTi-related registers (3)
253
RW
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.5.2 Operation of Serial I/O (transmission in UART mode)
In transmitting data in UART mode, choose functions from those listed in Table 2.5.4. Operations of the
circled items are described below. Figure 2.5.6 shows the operation timing, and Figures 2.5.7 and 2.5.8
show the set-up procedures.
Table 2.5.4. Choosed functions
Item
Set-up
Transfer clock
source
O
CTS function
O
Internal clock (f 1 / f8 / f32)
External clock (CLKi pin)
CTS function enabled
CTS function disabled
Transmission
interrupt factor
Sleep mode
Transmission buffer empty
O
Transmission complete
O
Sleep mode off
Sleep mode selected
Operation (1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit
buffer register readies the data transmissible status.
________
________
(2) When input to the CTSi pin goes to “L”, transmission starts (the CTSi pin needs to be controlled on the reception side).
(3) Transmission data held in the UARTi transmit buffer register is transmitted to the UARTi
transmit register. At this time, the first bit (the start bit) of the transmission data is transmitted
from the TxDi pin. Then, data is transmitted, bit by bit, in sequence: LSB, ····, MSB, parity bit,
and stop bit(s).
(4) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to “1”, which
indicates that transmission is completed. At this time, the UARTi transmit interrupt request bit
goes to “1”. The transfer clock stops at “H” level.
(5) If the transmission condition of the next data is ready when transmission is completed, a start
bit is generated following to stop bit(s), and the next data is transmitted.
254
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example of wiring
Microcomputer
Receiver side IC
TXDi
RXD
CTSi
Port
Example of operation
Tc
When confirming stop bit, stopped transfer clock once because CTS = “H”
Started transfer clock again to start transmitting immediately after confirming CTS = “L”
Transfer clock
(1) Transmission enabled
(4) Confirme stop bit
(2) Confirme CTS
(3) Start transmission
Transmit
enable bit (TE)
(5) Start transmission
“1”
“0”
Data is set in UARTi transmit buffer register
Transmit buffer “1”
empty flag (Tl) “0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
CTSi
“L”
Parity Stop
bit
bit
Start
bit
TxDi
ST D0 D1 D2 D3 D4 D5 D6 D7
Transmit
register empty
flag (TXEPT)
P
SP
Stopped pulsing because transfer enable bit = “0”
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1
“1”
“0”
Transmit
“1”
interrupt request
“0”
bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Figure 2.5.6. Operation timing of transmission in UART mode
255
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting UARTi transmit/receive mode register (i=0, 1)
b7
0
b0
1
0
0
0
1
0
1
UART0 transmit/receive mode register
U0MR [Address 03A0 16]
UART1 transmit/receive mode register
U1MR [Address 03A8 16]
Serial I/O mode select bit
b2 b1 b0
1 0 1 : Transfer data 8 bits long
Internal/external clock select bit
0 : Internal clock
Stop bit length select bit
0 : One stop bit
Odd/even parity select bit (Valid when bit 6 = “1” )
0 : Odd parity
Parity enable bit
1 : Parity enabled
Sleep select bit
0 : Invalid
Setting UARTi transmit/receive control register 0 (i = 0, 1)
b7
0
b0
0
0
0
UART0 transmit/receive control register 0
U0C0 [Address 03A4 16]
UART1 transmit/receive control register 0
U1C0 [Address 03AC 16]
BRG count source select bit
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function select bit (Valid when bit 4 = “0”)
0 : CTS function is selected
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
0 : CTS/RTS function enabled
Data output select bit
0 : TxDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
Must be “0” in UART mode
Must be “0” in UART mode
Setting UART transmit/receive control register 2
b7
b0
0
0
UART transmit/receive control register 2
UCON [Address 03B0 16]
UART0 transmit interrupt cause select bit
1 : Transmission completed (TXEPT = 1)
UART1 transmit interrupt cause select bit
1 : Transmission completed (TXEPT = 1)
Invalid in UART mode
Invalid in UART mode
Invalid in UART mode
Must be “0” in UART mode
Reserved bit
Fix “0” to this bit.
Continued to the next page
Figure 2.5.7. Set-up procedure of transmission in UART mode (1)
256
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Setting UARTi bit rate generator (i = 0, 1)
b7
b0
UARTi bit rate generator (i = 0, 1) [Address 03A1 16, 03A9 16]
UiBRG (i = 0, 1)
Can be set to 00 16 to FF 16 (Note)
Note: Write to UARTi bit rate generator when transmission/reception is halted.
Transmission enabled
b7
b0
UART0 transmit/receive control register 1 [Address 03A5 16] U0C1
UART1 transmit/receive control register 1 [Address 03AD 16] U1C1
1
Transmit enable bit
1 : Transmission enabled
Writing transmit data
(b15)
b7
(b8)
b0 b7
b0
UART0 transmit buffer register [Address 03A3 16, 03A216] U0TB
UART1 transmit buffer register [Address 03AB 16, 03AA 16] U1TB
Setting transmission data
When CTSi input level = “L”
Start transmission
Checking the status of UARTi transmit/receive control (i = 0, 1)
b7
b0
UART0 transmit/receive control register 1 [Address 03A5 16] U0C1
UART1 transmit/receive control register 1 [Address 03AD 16] U1C1
Transmit buffer empty flag
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register
(Writing next transmit data enabled)
Writing next transmit data
(b15)
b7
(b8)
b0 b7
b0
UART0 transmit buffer register [Address 03A3 16, 03A2 16] U0TB
UART1 transmit buffer register [Address 03AB 16, 03AA 16] U1TB
Setting transmission data
Transmission is complete
Figure 2.5.8. Set-up procedure of transmission in UART mode (2)
257
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.5.3 Operation of Serial I/O (reception in UART mode)
In receiving data in UART mode, choose functions from those listed in Table 2.5.5. Operations of the
circled items are described below. Figure 2.5.9 shows the operation timing, and Figures 2.5.10 and
2.5.11 show the set-up procedures.
Table 2.5.5. Choosed functions
Item
Transfer clock
source
RTS function
Set-up
Internal clock (f 1 / f8 / f32)
O
External clock (CLKi pin)
O
RTS function enabled
RTS function disabled
Sleep mode
O
Sleep mode off
Sleep mode selected
Operation (1) Setting the receive enable bit to “1” readies data-receivable status. At this time, output from
________
the RTSi pin goes to “L” level to inform the transmission side that the receivable status is
ready.
(2) When the first bit (the start bit) of reception data is received from the RxDi pin, output from the
_______
RTS goes to “H” level. Then, data is received, bit by bit, in sequence: LSB, ····, MSB, and stop
bit(s).
(3) When the stop bit(s) is (are) received, the content of the UARTi receive register is transmitted
to the UARTi receive buffer register.
At this time, the receive complete flag goes to “1” to indicate that the reception is completed,
_______
the UARTi receive interrupt request bit goes to “1”, and output from the RTS pin goes to “L”
level.
(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi receive buffer
register is read.
258
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example of wiring
Microcomputer
Transmitter side IC
CLKi
CLK
RXDi
TXD
RTSi
Port
Example of operation
(4) Data is
read
(1) Reception enabled
(2) Start reception
(3) Receiving is
completed
BRGi's count
source
Receive enable
bit
“1”
“0”
Start bit
RxDi
D1
D0
D7
Stop bit
Sampled “L”
Receive data taken in
Transfer clock
Receive
complete flag
RTSi
“1”
Reception started when transfer
clock is generated by falling edge
of start bit
Transferred from UARTi receive register
to UARTi receive buffer register
“0”
“H”
“L”
Receive interrupt “1”
request bit
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timing of transfer data 8 bits long applies to the following settings :
•Transfer data length is 8 bits.
•Parity is disabled.
•One stop bit
•RTS function is selected.
Figure 2.5.9. Operation timing of reception in UART mode
259
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting UARTi transmit/receive mode register (i=0, 1)
b7
0
b0
0
0
1
1
0
1
UART0 transmit/receive mode register [Address 03A016] U0MR
UART1 transmit/receive mode register [Address 03A816] U1MR
Serial I/O mode select bit
b2 b1 b0
1 0 1 : Transfer data 8 bits long
Internal/external clock select bit
1 : External clock
Stop bit length select bit
0 : One stop bit
Valid when bit 6 = “1”
Parity enable bit
0 : Parity diabled
Sleep select bit
0 : Sleep mode deselected
Setting UARTi transmit/receive control register 0 (i=0, 1)
b7
0
b0
0
0
0
UART0 transmit/receive control register 0 [Address 03A4 16] U0C0
UART1 transmit/receive control register 0 [Address 03AC 16] U1C0
1
BRG count source select bit
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = “0”)
1 : RTS function is selected
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
0 : CTS/RTS function enabled
Data output select bit
0 : TxDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
Must be fixed to “0” in UART mode
Must be fixed to “0” in UART mode
Setting UART transmit/receive control register 2
b7
b0
0
0
UART transmit/receive control register 2 [Address 03B0
16]
UCON
Invalid in UART mode
Invalid in UART mode
Invalid in UART mode
Must be fixed to “0” in UART mode
Reserved bit
Fix “0” to this bit.
Continued to the next page
Figure 2.5.10. Set-up procedure of reception in UART mode (1)
260
Mitsubishi microcomputers
M30218 Group
UART
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Setting UARTi bit rate generator (i = 0, 1)
b7
b0
UARTi bit rate generator (i = 0 , )1[Address 03A1 16, 03A916]
UiBRG (i = 0, 1)
Can be set to 00 16 to FF 16
Note: Write to UARTi bit rate generator when transmission/reception is halted.
Reception enabled
b7
b0
UART0 transmit/receive control register 1 [Address 03A5 16] U0C1
UART1 transmit/receive control register 1 [Address 03AD 16] U1C1
1
Receive enable bit
1 : Reception enabled
Start reception
Checking completion of reception
b7
b0
UART0 transmit/receive control register 1 [Address 03A5 16] U0C1
UART1 transmit/receive control register 1 [Address 03AD 16] U1C1
Receive complete flag
0 : No data present in receive buffer register
1 : Data present in receive buffer register
Checking error
(b15)
b7
(b8)
b0 b7
b0
UART0 receive buffer register [Address 03A7 16, 03A616]U0RB
UART1 receive buffer register [Address 03AF 16, 03AE16]U1RB
Receive data
Overrun error flag
0 : No overrun error
1 : Overrun error found
Framing error flag
0 : No framing error
1 : Framing error found
Parity error flag
0 : No parity error
1 : Parity error found
Error sum flag
0 : No error
1 : Error found
Processing after reading out reception data
Figure 2.5.11. Set-up procedure of reception in UART mode (2)
261
Serial I/O2
2.6 Serial I/O2
2.6.1 Overview
Serial I/O2 performs 8-bit data serial communication, synchronized with the clocks. In the automatic
transfer serial I/O mode, serial communication of up to 256 bytes can be continuously performed without
use of the CPU. The following is the Serial I/O2 overview.
(1) Transfer format
Transfer format is 8-bit data.
(2) Transfer rate
When selecting an internal clock as the transfer clock, the transfer rate is the division ratio selected by
the internal synchronous clock selection bits. Any one of f(XIN)/4, f(XIN)/8, f(XIN)/16, f(X IN)/32,
f(XIN)/64, f(XIN)/128 or f(XIN)/256 can be selected by the internal synchronous clock selection bits.
When selecting an external clock as the transfer clock, the transfer rate is the frequency of the clock
input to the CLK pin.
(3) Automatic transfer serial I/O mode
Clock synchronous communication, which does not depend on the CPU, can be continuously performed up to 256 bytes.
(4) Selection function
The following selection functions can be applied to Serial I/O2.
(a) SSTB2 output (for selecting internal synchronous clock)
•STB function invalid: SSTB2 output pin is used as a programmable I/O pin.
•STB function valid: SSTB2 output pin functions as SSTB2 or SSTB2 output.
(b) SBUSY2 input/output
•SBUSY2 input/output function invalid: SBUSY2 pin is used as a programmable I/O pin.
•SBUSY2 input/output function valid: SBUSY2 pin functions as input/output of SBUSY2 or SBUSY2.
(c) SRDY2 input/output
•SRDY2 input/output function invalid: SRDY2 pin is used as a programmable I/O pin.
•SRDY2 input/output function valid: SRDY2 pin functions as input/output of SRDY2 or SRDY2.
(d) SOUT2 P-channel output disable (invalid for P94 as I/O port)
The SOUT2 output pin can be switched between C-MOS 3 state and N-channel open-drain when in
the 8-bit or the automatic transfer serial I/O mode. The mode is selected by the serial transfer select
bits.
(e) LSB first/MSB first
This function switches the starting bit for the transmission/reception; either bit 0 or bit 7. The following
two types can be selected with the transfer direction select bit:
•LSB first: transmission/reception begins with from bit 0.
•MSB first: transmission/reception begins with from bit 7.
262
Serial I/O2
(f) Transfer mode
Either the full duplex mode or the transmit-only mode can be selected. The SIN2 pin can be used as
a programmable input/output port in the transmit-only mode.
(g) Plural transfer clock input/output pin
This function switches the pins for transfer clock input/output. By switching the transfer clock pins,
data can be transmitted/received to two external ICs in a time-sharing manner.
(h) SOUT2 pin control
This pin selects either output active (value of last transmitted data or undefined value) or high-impedance as the SOUT2 pin state for non-transfer periods (i.e. before and after serial transfers).
(5) Input to serial I/O2 and direction register
When inputting external signals to Serial I/O2, set the corresponding port direction register to input.
(6) Serial I/O2-related pins
(a) SSTB2 pin: Output pin for STB and STB functions.
(b) SBUSY2 pin: Input/output pin for BUSY and BUSY functions.
(c) SRDY2 pin: Input/output pin for RDY and RDY functions.
(d) SCLK21, SCLK22 pins: Input/output pins for transfer clocks. Pin is selectable by user.
(e) SIN2 pin: Data input pin.
(f) SOUT2 pin: Data output pin.
263
Serial I/O2
(7) Registers related to Serial I/O2
Figure 2.6.1 shows the memory map of Serial I/O2 related-registers.
Figures 2.6.2 and 2.6.3 show the Serial I/O2 related-registers.
004F16 SI/O automatic transfer interrupt control register (ASIOIC)
034016 Serial I/O2 automatic transfer data pointer (SIO2DP)
034116
034216 Serial I/O2 control register 1 (SIO2CON1)
034316
034416 Serial I/O2 control register 2 (SIO2CON2)
034516
034616 Serial I/O2 register / transfer counter (SIO2)
034716
034816 Serial I/O2 control register 3 (SIO2CON3)
040016
:
:
Automatic transfer RAM
:
:
04FF16
Figure 2.6.1. Memory map of Serial I/O2 related-registers
264
Serial I/O2
Serial I/O2 control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
SIO2CON1
Bit symbol
SCON10
Address
034216
When reset
0016
Bit name
Function
Serial transfer select bits
R
W
b1 b0
00: Serial I/O disabled
(serial I/O pins are I/O ports)
01: 8-bits serial I/O
10: Inhibit
11: Automatic transfer serial I/O (8-bits)
SCON11
SCON12
Serial I/O2 synchronous
clock select bits
(SSTB2 pin control bit)
SCON13
SCON14
SCON15
b3 b2
00: Internal synchronous clock
(SSTB2 pin is an I/O port.)
01: External synchronous clock
(SSTB2 pin is an I/O port.)
10: Internal synchronous clock
(SSTB2 pin is an SSTB2 output.)
11: Internal synchronous clock
(SSTB2 pin is an SSTB2 output.)
Serial I/O initialization bit
0: Serial I/O initialization
1: Serial I/O enabled
Transfer mode select bit
0: Full duplex (transmit and receive) mode
(SIN2 pin is a SIN2 input.)
1: Transmit-only mode (SIN2 pin is an I/O port.)
SCON16
Transfer direction
select bit
0: LSB first
1: MSB first
SCON17
Serial I/O2 clock pin
select bit
0:SCLK21 (SCLK22 pin is an I/O port.)
1:SCLK22 (SCLK21 pin is an I/O port.)
Serial I/O2 control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
SIO2CON2
Bit symbol
Address
034416
Bit name
Function
SRDY2 • SBUSY2 pin
SCON20 control bits
b3b2b1b0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SCON21
SCON22
SCON23
SBUSY2 output • SSTB2 output
SCON24 function select bit
(Valid in automatic transfer mode)
SCON25
When reset
0016
Serial transfer status flag
SRDY2 pin
I/O port
Not used
SRDY2 output
SRDY2 output
I/O port
I/O port
I/O port
I/O port
SRDY2 input
SRDY2 input
SRDY2 input
SRDY2 input
SRDY2 output
SRDY2 output
SRDY2 output
SRDY2 output
R
SBUSY2 pin
I/O port
I/O port
I/O port
SBUSY2 input
SBUSY2 input
SBUSY2 output
SBUSY2 output
SBUSY2 output
SBUSY2 output
SBUSY2 output
SBUSY2 output
SBUSY2 input
SBUSY2 input
SBUSY2 input
SBUSY2 input
0: Functions as each 1-byte signal
1: Functions as signal for all transfer data
0: Serial transfer completion
1: Serial transferring
SCON26 SOUT2 pin control bit
(at no-transfer serial data)
0: Output active
1: Output high-impedance
SOUT2 P-channel output
SCON27 disable bit
0: CMOS 3-state (P-channel output is valid.)
1: N-channel open-drain
(P-channel output is invalid.)
Figure 2.6.2. Serial I/O2 related-registers (1)
265
W
Serial I/O2
Serial I/O2 automatic transfer data pointer
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
SIO2DP
Address
034016
When reset
0016
Function
R
W
R
W
R
W
• Automatic transfer data pointer set
Specify the low-order 8 bits of the first data store address on the serial I/O
automatic transfer RAM.
Data is written into the latch and read from the decrement counter.
Serial I/O2 register/transfer counter
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
SIO2
Address
034616
When reset
0016
Function
• Number of automatic transfer data set
Set the number of automatic transfer data.
Set a value one less than number of transfer data.
Data is written into the latch and read from the decrement counter.
Serial I/O2 control register 3
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
SIO2CON3
Bit symbol
TTRAN0
Address
034816
Bit name
Automatic transfer
interval set bits
TTRAN1
TTRAN2
TTRAN3
Function
b4b3b2b1b0
00000 :2 cycles of transfer clocks
00001 :3 cycles of transfer clocks
:
11110 :32 cycles of transfer clocks
11111 :33 cycles of transfer clocks
Data is written to a latch and read from
a decrement counter.
TTRAN4
TCLK0
When reset
000000002
Internal synchronous
clock selection bits
TCLK1
TCLK2
Figure 2.6.3. Serial I/O2 related-registers (2)
266
b7b6b5
000:f(XIN)/4
001:f(XIN)/8
010:f(XIN)/16
011:f(XIN)/32
100:f(XIN)/64
101:f(XIN)/128
110:f(XIN)/256
Serial I/O2
2.6.2 Serial I/O2 connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.6.4 shows connection examples with peripheral ICs which have the CS pin. The automatic
transfer function can be used in all examples.
(1) Only transmission
(Using SIN2 pin as I/O port)
SBUSY2
SCLK21
SOUT2
(2) Transmission and reception
CS
CLK
SBUSY2
SCLK21
SOUT2
SIN2
DATA
CS
CLK
IN
OUT
Peripheral IC
M30218 group (OSD controller, etc.)
M30218 group
(3) Transmission and reception
(When connecting SIN2 with SOUT2)
(When connecting IN with OUT in
peripheral IC)
(4) Connection of plural IC
SBUSY2
SCLK21
SOUT2
SIN2
M30218 group✽1
Port
CS
CLK
IN
OUT
CS
SCLK21
CL K
SOUT2
IN
SIN2
Port
Peripheral IC ✽2
(EEPROM, etc.)
Peripheral IC
(EEPROM, etc.)
O UT
Peripheral IC 1
M30218 group
✽1: Select an N-channel open-drain output for SOUT2 pin
output control.
✽2: Use the OUT pin of peripheral IC which is an Nchannel open-drain output and becomes high impedance during receiving data.
CS
CLK
IN
OUT
Peripheral IC 2
Note: “Port” means an output port controlled by software.
Figure 2.6.4. Serial I/O2 onnection examples (1)
267
Serial I/O2
(2) MCU connections
Figure 2.6.5 shows connection examples with other MCUs.
(1) Selecting internal clock
(2) Selecting external clock
SCLK21
CLK
SCLK21
CLK
SOUT2
IN
SOUT2
IN
SIN2
M30218 group
SIN2
OUT
M30218 group
Microcomputer
(3) Using SRDY2 signal output function
(Selecting external clock)
SRDY2
SCLK21
SOUT2
SIN2
M30218 group
OUT
Microcomputer
(4) Using switch function of CLK signal output
pins, SCLK22 (Selecting internal clock)
RDY
SCLK21
CLK
CLK
SOUT2
IN
SIN2
IN
OUT
SCLK22
OUT
Port
Microcomputer
Microcomputer
M30218 group
CLK
IN
OUT
CS
Peripheral IC
Figure 2.6.5. Serial I/O2 onnection examples (2)
268
Serial I/O2
2.6.3 Serial I/O2 modes
Figure 2.6.6 shows Serial I/O2 modes.
Output SRDY2 ✽ signal
Input SRDY2 ✽ signal (Note)
Using
handshake
signal
Output SBUSY2 ✽ signal
Input SBUSY2 ✽ signal
Internal
clock
Full duplex
mode
8-bit serial
I/O
Transmitonly mode
Automatic
transfer
serial I/O
Output SSTB2 ✽ signal
Not using
handshake
signal
Serial I/O2
Output SRDY2 ✽ signal
Using
handshake
signal
External
clock
Input SRDY2 ✽ signal (Note)
Output SBUSY2 ✽ signal
Input SBUSY2 ✽ signal
Not using
handshake
signal
Note: This is only valid when outputting the SBUSY2 signal.
✽ Active logic can apply to each signal of SRDY2, SBUSY2, SSTB2.
Figure 2.6.6. Serial I/O2 modes
269
Serial I/O2
2.6.4 Serial I/O2 Operations (transmission in 8-bit serial I/O mode)
The functions listed in Table 2.6.1 can be selected in the 8-bit serial I/O mode for Serial I/O2 transmission/
reception. Operations of the circled items are described below. Figure 2.6.7 shows the operation timing,
and Figures 2.6.8 and 2.6.9 show the set-up procedure.
Table 2.6.1. Selectable functions
Item
Set-up
Transfer clock
source
O
Automatic transfer
serial I/O
SSTB2 output function
Item
Internal clock (f1 / f8 / f32)
SBUSY2 function
Not selected
External clock (CLKi pin)
SBUSY2 input
O
Not selected
SBUSY2 output (“H” at stop
required)
O
Not selected
Selected
SSTB2 (“H” at transmission/
reception completed)
SSTB2 (“L” at transmission/
reception completed)
Transfer direction
Set-up
O
SRDY2 function
O
SBUSY2 output (“L” at stop
required)
O
Not selected
SRDY2 input
SRDY2 output
LSB first
SRDY2 output (“H” at ready)
MSB first
SRDY2 output (“L” at ready)
Operation (1) Serial I/O2 becomes transmission-enabled with the following settings: serial transfer select
bits SCON10 to “1” and SCON11 to “0”; transfer mode select bit (SCON15) to “1”; serial I/O
initialization bit (SCON14) to “1”.
(2) When transmission data is written to the serial I/O2 register, transmission starts and the serial
transfer status flag is set to “1”.
(3) The transmission data is transmitted bit by bit from the lower bits, synchronized with each
falling edge.
(4) When one-byte data transmission is completed, the serial transfer status flag is set to “0” to
indicate the transmission completion. The transfer clock stops at “H” level.
(5) Continuous transmission can be performed by setting the next transmission data in the serial
I/O2 register during transmission, before output of the 8th bit.
270
Serial I/O2
Connection example
M30218 group
Peripheral IC
SBUSY2
CS
SCLK21
CLK
SOUT2
DATA
Operation example
(2) Transmission start
(4) Transmission is completed
TC
Internal clock
Serial transfer status flag “1”
(bit 5 of address 034416) “0”
SBUSY2 (output)
“H”
“L”
SCLK21
(output)
SOUT2
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Tc: Internal synchronous clock which is selected with bits 5 to 7 of address 034816
The above timing applies to the following settings:
• Internal clock is selected
• 8-bit serial I/O mode
• SBUSY2 output timing: Each 1 byte
Figure 2.6.7. Operation timing of transmission in 8-bit serial I/O mode, using plural transfer clock
output function output
271
Serial I/O2
Serial I/O2 control register 1 set-up
b7
b0
0 0 1 0 0 0 0 0
Serial I/O2 control register 1 [Address 034216]
SIO2CON1
Serial transfer select bits
b1 b0
0 0 : Serial I/O disabled (serial I/O pins are I/O ports)
Serial I/O2 synchronous clock select bits
b3 b2
0 0 : Internal synchronous clock (SSTB2 pin is an I/O port.)
Serial I/O initialization bit
0 : Serial I/O initialization
Transfer mode select bit
1 : Transmit-only mode (SIN2 pin is an I/O port.)
Transfer direction select bit
0 : LSB first
Serial I/O2 clock pin select bit
0 : SCLK21 (SCLK22 pin is an I/O port.)
Serial I/O2 control register 2 set-up
b7
0 0
b0
0 0 1 1 0
Serial I/O2 control register 2 [Address 034416]
SIO2CON2
SRDY2 • SBUSY2 pin control bits
b3 b2 b1 b0
0 1 1 0 : SRDY2 pin as I/O port, SBUSY2 pin as SBUSY2 output
SBUSY2 output • SSTB2 output function select bit
0 : Functions as each 1-byte signal
Serial transfer status flag
0 : Serial transfer completion
1 : Serial transferring
SOUT2 pin control bit
0 : Output active
SOUT2 P-channel output disable bit
0 : CMOS 3-state (P-channel output is valid.)
Serial I/O2 control register 3 set-up
b7
b0
Serial I/O2 control register 3 [Address 034816]
SIO2CON3
0 1 1
Automatic transfer interval set bits
b4 b3 b2 b1 b0
0000
0000
:
1111
1111
0 : 2 cycles of transfer clocks
1 : 3 cycles of transfer clocks
0 : 32 cycles of transfer clocks
1 : 33 cycles of transfer clocks
Internal synchronous clock selection bits
b7 b6 b5
0 1 1 : f(XIN)/32
Serial I/O2 control register 1 set-up
0 1
Serial I/O2 control register 1 [Address 034216]
SIO2CON1
Serial transfer select bits
b1 b0
0 1 : 8-bit serial I/O disabled
Continued to the next page
Figure 2.6.8. Set-up procedure for transmission in 8-bit serial I/O mode, using plural transfer
clock output function output (1)
272
Serial I/O2
From the previous page
Enabling transmission
b7
b0
Serial I/O2 control register 1 [Address 034216]
SIO2CON1
1
Serial I/O initialization bit (Note)
1 : Serial I/O enabled
Note: After setting the serial transfer select bits, perform this set-up.
Writing transmission data
b7
b0
Serial I/O2 register [Address 034616]
SIO2
Set transmission data
Confirmation of complete transmission
b7
b0
Serial I/O2 control register 2 [Address 034416]
SIO2CON2
Serial transfer status flag
0 : Serial transfer completion
1 : Serial transferring
Transmission is completed
Figure 2.6.9. Set-up procedure for transmission in 8-bit serial I/O mode, using plural transfer
clock output function output (2)
273
Serial I/O2
2.6.5 Serial I/O2 Operations (transmission/reception in automatic transfer serial I/O mode)
The functions listed in Table 2.6.2 can be selected in the automatic transfer serial I/O mode for Serial I/O2
transmission/reception. Operations of the circled items are described below. Figure 2.6.10 shows the
operation timing, and Figures 2.6.11 and 2.6.12 show the set-up procedure.
Table 2.6.2. Selectable functions
Item
Transfer clock
source
Automatic transfer
serial I/O
SSTB2 output function
Set-up
O
Item
Internal clock (f1 / f8 / f32)
Not selected
SBUSY2 input
Not selected
SBUSY2 output (“H” at stop
required)
O
Selected
O
Not selected
O
O
External clock (CLKi pin)
SBUSY2 output (“L” at stop
required)
SSTB2 (“H” at transmission/
reception completed)
SSTB2 (“L” at transmission/
reception completed)
Transfer direction
SBUSY2 function
Set-up
SRDY2 function
O
Not selected
SRDY2 input
SRDY2 output
LSB first
SRDY2 output (“H” at ready)
MSB first
SRDY2 output (“L” at ready)
Operation (1) After setting the relevant registers, by writing the transfer byte number to the serial I/O2
transfer counter, the serial transfer status flag is set to “1” and automatic transfer starts.
(2) The transmission data is transmitted bit by bit from the lower bits, synchronized with each
falling edge. The reception data is received bit by bit from the upper bits, synchronized with
each rising edge.
(3) When eight-byte data transmission/reception is completed, the serial transfer status flag is
set to “0” to indicate the transmission/reception completion. The transfer clock stops at “H”
level.
274
Serial I/O2
Connection example
M30218 group
Peripheral IC
SCLK21
CLK
SOUT2
SI N
SIN2
SOUT
Operation example
(1) Transmission/reception start
TC
Transmission/reception of
the second byte
Transfer interval
Transmission/reception of
the eighth byte
(3) Transmission/reception
is completed
Transfer interval
Transfer clock
Serial transfer status flag “1”
(bit 5 of address 034416) “0”
Writing to serial I/O2
transfer counter
(address 034616)
SCLK21
SIN2
SOUT2
D0
D1 D2 D3 D4 D5 D6
D7
D0 D1
D4 D5 D6
D7
D0
D1 D2 D3 D4 D5 D6
D7
D0 D1 D2 D3 D4 D5 D6
D7
D0 D1
D4
D7
D0 D1 D2 D3 D4 D5 D6
D7
D5 D6
Serial I/O2 “1”
interrupt request “0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc: Internal synchronous clock which is selected with bits 5 to 7 of address 034816
The above timing applies to the following settings:
• Internal clock is selected
• Automatic transfer serial I/O mode
Figure 2.6.10. Operation timing of transmission/reception in automatic transfer serial I/O mode
275
Serial I/O2
Serial I/O2 control register 1 set-up
b7
b0
0 0 0 0 0 0 0 0
Serial I/O2 control register 1 [Address 034216]
SIO2CON1
Serial transfer select bits
b1 b0
0 0 : Serial I/O disabled (serial I/O pins are I/O ports)
Serial I/O2 synchronous clock select bits
b3 b2
0 0 : Internal synchronous clock (SSTB2 pin is an I/O port.)
Serial I/O initialization bit
0 : Serial I/O initialization
Transfer mode select bit
0 : Full duplex (transmit and receive) mode (SIN2 pin is a SIN2 input.)
Transfer direction select bit
0 : LSB first
Serial I/O2 clock pin select bit
0 : SCLK21 (SCLK22 pin is an I/O port.)
Serial I/O2 control register 2 set-up
b7
0 0
b0
0 0 0 0
Serial I/O2 control register 2 [Address 034416]
SIO2CON2
SRDY2 • SBUSY2 pin control bits
b3 b2 b1 b0
0 0 0 0 : SRDY2 pin and SBUSY2 pin as I/O port
SBUSY2 output • SSTB2 output function select bit
0 : Functions as each 1-byte signal
1 : Functions as signal for all transfer data
Serial transfer status flag
0 : Serial transfer completion
1 : Serial transferring
SOUT2 pin control bit
0 : Output active
SOUT2 P-channel output disable bit
0 : CMOS 3-state (P-channel output is valid.)
Serial I/O2 control register 3 set-up
b7
b0
0 1 1 0 0 0 0 0
Serial I/O2 control register 3 [Address 034816]
SIO2CON3
Automatic transfer interval set bits
b4 b3 b2 b1 b0
0 0 0 0 0 : 2 cycles of transfer clocks
Internal synchronous clock selection bits
b7 b6 b5
0 1 1 : f(XIN)/32
Serial I/O2 control register 1 set-up
1 1
Serial I/O2 control register 1 [Address 034216]
SIO2CON1
Serial transfer select bits
b1 b0
1 1 : Automatic transfer serial I/O (8-bit)
Continued to the next page
Figure 2.6.11. Set-up procedure for transmission/reception in automatic transfer serial I/O mode (1)
276
Serial I/O2
From the previous page
Serial I/O2 automatic transfer data pointer
b7
b0
0 0 0 0 0 1 1 1
Serial I/O2 automatic transfer data pointer [Address 034016]
SIO2DP
Set the lower 8 bits (0716) of address 040716 (Note)
Note: Specify the lower 8 bits of the first data store address on the serial I/O automatic transfer RAM.
When setting a value, write at non-transmission/reception.
Enabling transmission
b7
b0
Serial I/O2 control register 1 [Address 034216]
SIO2CON1
1
Serial I/O initialization bit
1 : Serial I/O enabled
Writing transmission data
b7
b0
Automatic transfer RAM [Addresses 040016 to 04FF16]
Set transmission data for transmission byte number (8 bytes) to addresses 040016 to
040716. The area from addresses 040816 to 04FF16, which is not used in this example,
can be used as general-purpose RAM.
Automatic transfer start
b7
b0
Serial I/O2 transfer counter [Address 034616]
SIO2
Set 7 = (Transfer byte number – 1)
Writing to this register starts automatic transfer.
Other processes can be performed while automatic transfer is being performed.
Confirmation of complete automatic transmission
b7
b0
Serial I/O2 control register 2 [Address 034416]
SIO2CON2
Serial transfer status flag
0 : Serial transfer completion
1 : Serial transferring
Taking in reception data
b7
b0
Automatic transfer RAM [Addresses 040016 to 04FF16]
Take in reception data at addresses 040016 to 040716 into the RAM for process.
Transmission/reception is completed
Figure 2.6.12. Set-up procedure for transmission/reception in automatic transfer serial I/O mode (2)
277
Serial I/O2
2.6.6 Serial I/O2 Operations (transmission/reception in automatic transfer serial I/O
mode, using handshake signal)
The functions listed in Table 2.6.3 can be selected in the automatic transfer serial I/O mode for Serial I/O2
transmission/reception. Operations of the circled items are described below. Figure 2.6.13 shows the
operation timing, and Figures 2.6.14 and 2.6.15 show the set-up procedure.
Table 2.6.3. Selectable functions
Item
Transfer clock
source
Automatic transfer
serial I/O
SSTB2 output function
Transfer direction
Set-up
O
Item
Internal clock (f1 / f8 / f32)
Set-up
SBUSY2 function
External clock (CLKi pin)
Not selected
O
SBUSY2 input
SBUSY2 output (“H” at stop
required)
Not selected
O
Selected
O
Not selected
O
SSTB2 (“H” at transmission/
reception completed)
SSTB2 (“L” at transmission/
reception completed)
LSB first
SBUSY2 output (“L” at stop
required)
MSB first
SRDY2 function
Not selected
SRDY2 input
O
SRDY2 output
SRDY2 output (“H” at ready)
SRDY2 output (“L” at ready)
Operation (1) After setting the relevant registers, by writing the transfer byte number to the serial I/O2
transfer counter, the serial transfer status flag is set to “1” and automatic transfer starts.
SRDY2 output simultaneously goes to “H” level.
(2) When “L” level is input to the SBUSY2 pin, the SRDY2 output goes to “L” level, synchronized
with the falling edge of the transfer clock, and the serial transfer starts.
(3) The transmission data is transmitted bit by bit from the lower bits, synchronized with each
falling edge. The reception data is received bit by bit from the upper bits, synchronized with
each rising edge.
(4) When sixteen-byte data transmission/reception is completed, the serial transfer status flag is
set to “0” to indicate the transmission/reception completion. The transfer clock stops at “H”
level.
278
Serial I/O2
Connection example
M30218 group
Peripheral IC
CLK21
C LK
SOUT2
IN
SIN2
O UT
SRDY2
RDY
SBUSY2
BU SY
Operation example
(1) Automatic transfer start
Transmission/reception of
the second byte
(2) Transmission/reception start
Transfer interval
TC
Transmission/reception of
the sixteenth byte
(4) Transmission/reception
is completed
Transfer interval
Transfer clock
Serial transfer status flag “1”
(bit 5 of address 034416) “0”
Writing to serial I/O2
transfer counter
(address 034616)
SRDY2
SBUSY2
SCLK21
SIN2
SO U T 2
D0 D1 D2 D3 D4 D5 D6
D7
D0
D1
D 4 D 5 D6
D7
D0 D1 D2 D3 D4 D5 D6
D7
D0
D7
D0
D1
D 4 D 5 D6
D7
D0 D1 D2 D3 D4 D5 D6
D7
D1 D2 D3 D4
D5 D6
Serial I/O2 “1”
interrupt request “0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc: Internal synchronous clock which is selected with bits 5 to 7 of address 034816
The above timing applies to the following settings:
• Internal clock is selected
• Automatic transfer serial I/O mode
Figure 2.6.13. Operation timing of transmission/reception in automatic transfer serial I/O mode
279
Serial I/O2
Serial I/O2 control register 1 set-up
b7
b0
0 0 0 0 0 0 0 0
Serial I/O2 control register 1 [Address 034216]
SIO2CON1
Serial transfer select bits
b1 b0
0 0 : Serial I/O disabled (serial I/O pins are I/O ports)
Serial I/O2 synchronous clock select bits
b3 b2
0 0 : Internal synchronous clock (SSTB2 pin is an I/O port.)
Serial I/O initialization bit
0 : Serial I/O initialization
Transfer mode select bit
0 : Full duplex (transmit and receive) mode (SIN2 pin is a SIN2 input.)
Transfer direction select bit
0 : LSB first
Serial I/O2 clock pin select bit
0 : SCLK21 (SCLK22 pin is an I/O port.)
Serial I/O2 control register 2 set-up
b7
0 0
b0
1 1 1 1 1
Serial I/O2 control register 2 [Address 034416]
SIO2CON2
SRDY2 • SBUSY2 pin control bits
b3 b2 b1 b0
1 1 1 1 : SRDY2 pin as SRDY2 output, SBUSY2 pin as SBUSY2 input
SBUSY2 output • SSTB2 output function select bit
1 : Functions as signal for all transfer data
Serial transfer status flag
0 : Serial transfer completion
1 : Serial transferring
SOUT2 pin control bit
0 : Output active
SOUT2 P-channel output disable bit
0 : CMOS 3-state (P-channel output is valid.)
Serial I/O2 control register 3 set-up
b7
b0
0 1 1 0 0 0 0 0
Serial I/O2 control register 3 [Address 034816]
SIO2CON3
Automatic transfer interval set bits
b4 b3 b2 b1 b0
0 0 0 0 0 : 2 cycles of transfer clocks
Internal synchronous clock selection bits
b7 b6 b5
0 1 1 : f(XIN)/32
Serial I/O2 control register 1 set-up
1 1
Serial I/O2 control register 1 [Address 034216]
SIO2CON1
Serial transfer select bits
b1 b0
1 1 : Automatic transfer serial I/O (8-bit)
Continued to the next page
Figure 2.6.14. Set-up procedure for transmission/reception in automatic transfer serial I/O mode (1)
280
Serial I/O2
From the previous page
Serial I/O2 automatic transfer data pointer
b7
b0
0 0 0 0 1 1 1 1
Serial I/O2 automatic transfer data pointer [Address 034016]
SIO2DP
Set 0F16 (Note)
Note: Specify the lower 8 bits of the first data store address on the serial I/O automatic transfer RAM.
When setting a value, write at non-transmission/reception.
Enabling transmission
b7
b0
Serial I/O2 control register 1 [Address 034216]
SIO2CON1
1
Serial I/O initialization bit
1 : Serial I/O enabled
Writing transmission data
b7
b0
Automatic transfer RAM [Addresses 040016 to 04FF16]
Set transmission data for transmission byte number (16 bytes) to addresses 040016 to
040F16. The area from addresses 041016 to 04FF16, which is not used in this example,
can be used as general-purpose RAM.
Automatic transfer start
b7
b0
Serial I/O2 transfer counter [Address 034616]
SIO2
Set 15 = (Transfer byte number – 1)
Writing to this register starts automatic transfer.
Other processes can be performed while automatic transfer is being performed.
Confirmation of complete automatic transmission
b7
b0
Serial I/O2 control register 2 [Address 034416]
SIO2CON2
Serial transfer status flag
0 : Serial transfer completion
1 : Serial transferring
Taking in reception data
b7
b0
Automatic transfer RAM [Addresses 040016 to 04FF16]
Take in reception data at addresses 040016 to 040F16 into the RAM for process.
Transmission/reception is completed
Figure 2.6.15. Set-up procedure for transmission/reception in automatic transfer serial I/O mode (2)
281
Serial I/O2
2.6.7 Precautions for Serial I/O2
(1) Clock
(a) Using internal clock
After setting the synchronous clock to an internal clock, clear the serial I/O interrupt request bit
before performing a normal serial I/O transfer or a serial I/O automatic transfer.
(b) Using external clock
After inputting “H” level to the external clock input pin, clear the serial I/O interrupt request bit before
performing a normal serial I/O transfer or a serial I/O automatic transfer.
(2) Using Serial I/O2 interrupt
Clear bit 3 of the interrupt control register to “0” by software before enabling interrupts.
(3) State of SOUT2 pin
The SOUT2 pin control bit of the serial I/O2 control register 2 can be used to select the SOUT2 pin state
for non-transfer periods. Either output active or high-impedance can be selected. However, when
using an external synchronous clock, set the SOUT2 pin control bit to “1” while the serial I/O2 clock
input is in “H” level (after transfer completion) in order to put the SOUT2 pin in the high-impedance state.
(4) Serial I/O initialization bit
•To terminate a serial transfer while transferring, set “0” to the serial I/O initialization bit of the serial
I/O2 control register 1.
•When “1” is written to the serial I/O initialization bit, Serial I/O2 is enabled, however, each register is
not initialized. The value of each register needs to be set by software.
(5) Handshake signal
(a) SBUSY2 input signal
Input “H” level to the SBUSY2 input and “L” level to the SBUSY2 input in the initial state. When using the
external synchronous clock, switch the input level to the SBUSY2 input and the SBUSY2 input while the
serial I/O2 clock input is in “H” level.
(b) SRDY2 input/output signal
When using the internal synchronous clock, input “L” level to the SRDY2 input and “H” level to the
SRDY2 input in the initial state.
(6) In 8-bit serial I/O mode
When the external synchronous clock is used, the contents of the serial I/O2 register are being shifted
continually while the transfer clock is input to the serial I/O2 clock pin. At this time, the clock must be
controlled externally.
282
Serial I/O2
(7) In automatic transfer serial I/O mode
<How to set automatic transfer interval>
(a)
When using
•SBUSY2 output and,
•SBUSY2 output•SSTB2 output function as signals for each transfer data, which is set by SBUSY2
output•SSTB2 output function select bit of the serial I/O2 control register 2,
then the transfer interval is inserted before the first data is transmitted/received and after the last data
is transmitted/received.
Accordingly, regardless of the contents of the SBUSY2 output•SSTB2 output function select bit, the
transfer interval for each 1-byte data becomes 2 cycles longer than the value set by the automatic
transfer interval set bits of the serial I/O2 control register 3.
(b)
When using SSTB2 output, regardless of the contents of the SBUSY2 output•SSTB2 output function
select bit, the transfer interval for each 1-byte data becomes 2 cycles longer than the value set by the
automatic transfer interval set bits of the serial I/O2 control register 3.
(c)
When using the combined output of SBUSY2 and SSTB2 as the signal for each transfer data set, the
transfer interval after completion of transmission/reception of the last data becomes 2 cycles longer
than the value set by the automatic transfer interval set bits.
283
Serial I/O2
(d)
Set the automatic transfer interval for each 1-byte data transfer as explained below to avoid incorrect
transmit/receive of the serial data.
•Not using FLD controller
Keep the interval open for 5 cycles or more of the internal system clock from the rising edge of the
last bit of 1-byte data.
•Using FLD controller
a. Gradation display OFF
Keep the interval open for 17 cycles or more of the internal system clock from the rising edge of
the last bit of 1-byte data.
b. Gradation Display ON
Keep the interval open for 27 cycles or more of the internal system clock from the rising edge of
the last bit of 1-byte data.
Tables 2.6.4 and 2.6.5 show the serial I/O2 control register 3 (address 034816) setting example.
(e)
When using an external clock, the automatic transfer interval setting becomes invalid.
Table 2.6.4 Serial I/O2 control register 3, SIO2CON3 (address 034816) setting example (with internal
synchronous clock)
Gradation
Serial I/O2 control register 3, SIO2CON3 (address 0348 16)
Not using
Gradation
display mode display mode
FLDC
Automatic transfer interval set bits
Internal synchronous
OFF
ON
(b4 to b0)
clock selection bits
b7 b6 b5
0 0 0 0 0 : 2 cycles of transfer clocks Usable
Prohibited
Prohibited
0 0 0 : f(X IN ) / 4
0 0 0 0 1 : 3 cycles of transfer clocks Usable
Prohibited
Prohibited
0 0 0 1 0 : 4 cycles of transfer clocks Usable
Prohibited
Prohibited
0 0 0 1 1 : 5 cycles of transfer clocks Usable
Usable
Prohibited
0 0 1 0 0 : 6 cycles of transfer clocks Usable
Usable
Prohibited
0 0 1 0 1 : 7 cycles of transfer clocks Usable
Usable
Usable
0 0 1 : f(X IN ) / 8
0 0 0 0 0 : 2 cycles of transfer clocks Usable
Prohibited
Prohibited
0 0 0 0 1 : 3 cycles of transfer clocks Usable
Usable
Prohibited
0 0 0 1 0 : 4 cycles of transfer clocks Usable
Usable
Usable
0 1 0 : f(X IN ) / 16
0 0 0 0 0 : 2 cycles of transfer clocks Usable
Usable
Usable
Note: Do not perform the following in the automatic transfer serial I/O mode:
•Transfer within the RAM area (addresses 0040016 to 005FF16) using the DMAC
•Transfer within the RAM area (addresses 0040016 to 005FF16) using assembler instructions SMOVF and SMOVB.
Table 2.6.5 Serial I/O2 control register 3, SIO2CON3 (address 034816) setting example (with external
synchronous clock)
Serial I/O2 control register 3,
“n” cycles of transfer clocks
SIO2CON3 (address 034816);
Automatic transfer interval set bits
Not using FLDC
Gradation display mode OFF
Gradation display mode ON
Transfer clock ✕ n cycles ≥ 5 cycles of internal system clock
Transfer clock ✕ n cycles ≥ 17 cycles of internal system clock
Transfer clock ✕ n cycles ≥ 27 cycles of internal system clock
284
Serial I/O2
<How to set serial I/O2 transfer counter>
(a)
Write the value of the number of transfer-data decreased by 1 to the serial I/O2 transfer counter.
(b)
When using an external clock, after writing a value to the serial I/O2 register/transfer counter, wait for
5 or more cycles of the internal system clock before inputting the transfer clock to the serial I/O2
clock pin.
<Serial I/O initialization bit>
The serial I/O automatic transfer interrupt request occurs when “0” is written to the serial I/O initialization bit during an operation. Use software to set this interrupt priority level to level 0 (interrupt disabled), or any other methods which will disable it.
<Interrupt request bit>
The occurrence timing of serial I/O automatic transfer interrupt request may be delayed:
•Normally, the maximum delay is 17 cycles. In the FLD gradation display mode ON, the maximum
delay increases to 27 cycles.
•If the occurrence timing of the serial I/O2 interrupt request is delayed, the flags and the signals
which change simultaneously with the timing of the interrupt request, such as the serial transfer
status flag and the handshake signals, will also change in accordance to the delay.
285
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.7 FLD (VFD) Controller
2.7.1 Overview
The FLD controller drives and controls FLDs (fluorescent display). The following is the FLD controller
overview.
(1) FLDC port
There are a total of 56 ports, consisting of 52 high-breakdown-voltage (HBV) ports and 4 CMOS ports.
20 of the 52 HBV ports can be switched to normal ports, and all of the 4 CMOS ports can be switched
to general purpose ports. However, when using CMOS ports as display pins, external drivers must be
installed.
Ports P0, P1, P5 and P6, totaling 32 ports, have built-in pull-down resistors.
(2) Display pixel number
(a) Using all ports for FLD output
28 segments ✕ 28 digits (segment number + digit number ≤ 56)
(b) Using digit pulse output function
40 segments ✕ 16 digits (segment number + digit number ≤ 56, however, digit number ≤ 16)
(c) Using P44 to P47 expansion function
52 segments ✕ 16 digits (segment number ≤ 52, digit number ≤ 16)
(3) Selection function
The following selection functions can be applied to the FLD controller.
(a) Tscan control
Two types of interrupt sources can be selected, using the Tscan control bits (bits 2, 3 of address
035016):
•FLD digit interrupt
This is generated when the Toff1 time for each timing ends (at rising edge of digit output). Key
scanning, which makes use of FLD digits, can be applied by using each FLD digit interrupt.
•FLD blanking interrupt
This is generated when the FLD data pointer (address 0358 16) reaches FF 16.
The FLD automatic display output is turned off for a duration of 1 ✕ Tdisp, 2 ✕ Tdisp, or 3 ✕ Tdisp,
depending on post-interrupt settings. Key scanning, which makes use of FLD segments, can be
applied during this time.
(b) Timing number
The following two types of timing can be selected:
•16-timing
This timing is used when the display timing is 16 sets or less.
•32-timing
This timing is used when the display timing is more than 16 sets. This can be used for up to 32 sets.
286
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(c) Gradation display mode
The gradation display mode can apply bright/dark display for each segment when the display timing
is 16 or less.
Selection of gradation mode is as follows:
•Gradation display mode ON
Make sure to fix the timing number control bit (bit 4 of address 035016) to “0” as the maximum timing
is 16. Additionally, set the value to the Toff2 time set register (address 035616) so that Toff2 time
can be less than Tdisp time and more than Toff1 time.
•Gradation display mode OFF
(d) HBV port drivability
Two types of drivability, strong or weak, can be selected for HBV ports. This setting is also valid when
using HBV ports as general purpose ports.
(e) P44 to P47 FLD output reverse
Selecting this function enables the polarity reversal of the FLD output from P44 to P47. This function
is useful for adjusting the polarity when using an externally installed driver.
(f) P44 to P47 Toff invalid
Selecting this function disables Toff1 time and Toff2 time and outputs display data for the duration of
Tdisp.
(g) P97 dimmer signal output
Selecting this function outputs a signal from DIMOUT (P97) to the decoder which, in turn, sends out
the dimmer signal. The decoder controls this signal to enable the dimmer function.
(h) Toff section generate/not generate
This function can be applied to all of the HBV ports (P0, P1, P2, P3, P40 to P43, P5, P6) and CMOS
ports (P44 to P47). Two types can be selected:
•Generate Toff section
The Toff section is generated.
•No Toff section
This function reduces unwanted noises generated whenever a port switches due to the combined
capacity of the FLD ports. When continuous data is output to each FLD port, the Toff1 section of the
continuous parts is not generated.
(i) Toff2 SET/RESET change
In gradation display mode, this function specifies either output (SET) or “0” (RESET) depending on
Toff2 time for FLD output of dark display data (when gradation display control data is “1”). Two types
can be selected:
•Toff2SET
RAM data is output to the FLD output ports (SET) at the time set by Toff2 and is returned to “0”
(RESET) when the Tdisp time ends.
•Toff2RESET
RAM data is output to the FLD output ports (SET) at the time set by Toff1 and is returned to “0”
(RESET) at the time set by Toff2.
287
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Expansion function
The FLD controller is equipped with an expansion function.
(a) Digit pulses output function
Digit pulses can be output automatically from ports P5 and P6. When the same number of “1s” as the
timing number are consecutively written from P60 to the digit output set registers (addresses 035C16,
035D16), the contents of the FLD automatic display RAM for the ports that have been selected for
digit output are disabled. The digit pulses are then automatically output.
If a value exceeding the timing number for any port is set, the output of such port becomes “L” level.
(b) P44 to P47 expansion function
These ports have CMOS output structure. This function provides 16 lines of FLD digit outputs to
these four ports by connecting the decoder which converts 4-bit data to 16-bit data.
(5) Registers related to FLD controller
Figure 2.7.1 shows the memory map of FLDC related-registers. Figures 2.7.2 to 2.7.6 show FLDC
related-registers.
288
FLD controller
005016 FLD interrupt control register (FLDIC)
035016 FLDC mode register (FLDM)
035116 FLD output control register (FLDCON)
035216 Tdisp time set register (TDISP)
035316
035416 Toff1 time set register (TOFF1)
035516
035616 Toff2 time set register (TOFF2)
035716
035816 FLD data pointer (FLDDP)
035916 Port P2 FLD/port switch register (P2FPR)
035A16 Port P3 FLD/port switch register (P3FPR)
035B16 Port P4 FLD/port switch register (P4FPR)
035C16 Port P5 digit output set register (P5DOR)
035D16 Port P6 digit output set register (P6DOR)
Figure 2.7.1. Memory map of FLDC related-registers
289
FLD controller
FLDC mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
FLDM
Address
035016
Bit symbol
When reset
0016
Bit name
Function
FLDM0
Automatic display
control bit
0 : General-purpose mode
1 : Automatic display mode
FLDM1
Display start bit
0 : Stop display
1 : Display
RW
(start to display by switching “0” to “1”)
FLDM2
Tscan control bits
b3b2
00 : FLD digit interrupt
(at rising edge of each digit)
01 : 1 X Tdisp
FLD blanking
10 : 2 X Tdisp
interrupt (at falling
edge of last digit)
11 : 3 X Tdisp
}
FLDM3
Timing number control bit
0 : 16 timing mode
1 : 32 timing mode
FLDM5
Gradation display mode
selection control bit
0 : Not selecting
1 : Selecting (Note )
FLDM6
Tdisp counter
count source selection bit
0 : f(XIN)/32
1 : f(XIN)/128
FLDM7
High-breakdown voltage
port drivability select bit
0 : Drivability strong
1 : Drivability weak
FLDM4
Note : When a gradation display mode is selected, a number of timing is max. 16 timing.
(Set the timing number control bit to “0”.)
FLD output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FLDCON
Bit symbol
Address
035116
Bit name
FLDCON0 P44 to P47 FLD
output reverse bit
When reset
0016
Function
0 : Output normally
1 : Reverse output
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
FLDCON2
P44 to P47 FLD
Toff is invalid bit
0 : Perform normally
1 : Toff is invalid
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
P97 dimmer output
control bit
0 : Output normally
1 : Dimmer output
FLDCON5
CMOS ports: section of
Toff generate/not
generate bit
0 : section of Toff does NOT generate
1 : section of Toff generates
FLDCON6
High-breakdown-voltage ports: 0 : section of Toff does NOT generate
section of Toff
generate/not generate bit
1 : section of Toff generates
FLDCON7
Toff2
SET/RESET change bit
0 : gradation display data is reset at Toff2
(set at Toff1)
1 : gradation display data is set at Toff2
(reset at Toff1)
FLDCON4
Figure 2.7.2. FLDC related-registers (1)
290
RW
FLD controller
Tdisp time set register
b7
b0
Symbol
TDISP
Address
035216
When reset
0016
Function
Values that can be set R W
Counts Tdisp time. Count source is selected by Tdisp counter count source
select bit.
Supposing that the set value is “n”, the Tdisp time is expressed as
Tdisp = (n + 1) ✕ count source.
When reading this register, the value in the counter of Tdisp time set
register is read out.
016 to FF16
(Example)
Tdisp = (200 + 1) ✕ 3.2 µs = 643 µs
Conditions: •f(XIN) =10 MHz
•FLDC mode register FLDM6 = 0
( f(XIN)/32 selected as Tdisp counter count source)
•Tdisp time set register = 200 (C816)
Toff1 time set register
b7
b0
Symbol
Address
When reset
TOFF1
035416
FF 1 6
Function
Values that can be set R W
Counts Toff1 time. Count source is selected by Tdisp counter count source
select bit.
Supposing that the set value is “n1”, the Toff1 time is expressed as
Toff1 = n1 ✕ count source.
3 to FF16
(Example)
Toff1 = 30 ✕ 3.2 µs = 96 µs
Conditions: •f(XIN) =10 MHz
•FLDC mode register FLDM6 = 0
( f(XIN)/32 selected as Tdisp counter count source)
•Toff1 time set register = 30 (1E16)
Toff2 time set register
b7
b0
Symbol
Address
When reset
TOFF2
035616
FF 1 6
Function
Counts Toff2 time. Count source is selected by Tdisp counter count source
select bit.
Supposing that the set value is “n2”, the Toff2 time is expressed as
Toff2 = n2 ✕ count source.
This setting of Toff2 time applies only to the FLD ports as the following:
•Gradation display mode and
•The RAM value of gradation display control is “1” (= dark display).
(Example)
Toff2 = 180 ✕ 3.2 µs = 576 µs
Conditions: •f(XIN) =10 MHz
•FLDC mode register FLDM6 = 0
( f(XIN)/32 selected as Tdisp counter count source)
•Toff2 time set register = 180 (B416)
Figure 2.7.3. FLDC related-registers (2)
291
Values that can be set R W
3 to FF16
FLD controller
FLD data pointer
b7
b0
Symbol
Address
When reset
FLDDP
035816
indeterminate
Function
Values that can be set R W
Counts FLD output timing. Set this register to “FLD output data - 1 ”.
The set value is written into the FLD data pointer reload register.
When reading this register, the value of the FLD data pointer is read out.
1 to 1F16
Note: Reading the FLD data pointer takes out the count at that moment.
Port P2 FLD / port switch register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
P2FPR
035916
0016
Bit symbol
Bit name
Port P20 FLD/port switch bit
P2FPR0
P2FPR1
Port P21 FLD/port switch bit
Function
RW
Function
RW
0 : Normal port
1 : FLD output port
0 : Normal port
1 : FLD output port
P2FPR2
Port P22 FLD/port switch bit
0 : Normal port
1 : FLD output port
P2FPR3
Port P23 FLD/port switch bit
0 : Normal port
1 : FLD output port
P2FPR4
Port P24 FLD/port switch bit
0 : Normal port
1 : FLD output port
P2FPR5
Port P25 FLD/port switch bit
0 : Normal port
1 : FLD output port
P2FPR6
Port P26 FLD/port switch bit
0 : Normal port
1 : FLD output port
P2FPR7
Port P27 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P3 FLD / port switch register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
P3FPR
035A16
0016
Bit symbol
Bit name
P3FPR0
Port P30 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR1
Port P31 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR2
Port P32 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR3
Port P33 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR4
Port P34 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR5
Port P35 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR6
Port P36 FLD/port switch bit
0 : Normal port
1 : FLD output port
P3FPR7
Port P37 FLD/port switch bit
0 : Normal port
1 : FLD output port
Figure 2.7.4. FLDC related-registers (3)
292
FLD controller
Port P4 FLD / port switch register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
P4FPR
035B16
0016
Bit symbol
Bit name
P4FPR0
Port P40 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR1
Port P41 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR2
Port P42 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR3
Port P43 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR4
Port P44 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR5
Port P45 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR6
Port P46 FLD/port switch bit
0 : Normal port
1 : FLD output port
P4FPR7
Port P47 FLD/port switch bit
0 : Normal port
1 : FLD output port
Function
RW
Function
RW
Port P5 digit output set register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
P5DOR
035C16
0016
Bit symbol
Bit name
P5DOR0
Port P50 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR1
Port P51 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR2
Port P52 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR3
Port P53 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR4
Port P54 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR5
Port P55 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR6
Port P56 FLD/digit switch bit
0 : FLD output
1 : Digit output
P5DOR7
Port P57 FLD/digit switch bit
0 : FLD output
1 : Digit output
Figure 2.7.5. FLDC related-registers (4)
293
FLD controller
Port P6 digit output set register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
P6DOR
035D16
0016
Bit symbol
Bit name
Function
P6DOR0
Port P60 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR1
Port P61 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR2
Port P62 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR3
Port P63 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR4
Port P64 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR5
Port P65 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR6
Port P66 FLD/digit switch bit
0 : FLD output
1 : Digit output
P6DOR7
Port P67 FLD/digit switch bit
0 : FLD output
1 : Digit output
Figure 2.7.6. FLDC related-registers (5)
294
RW
FLD controller
This page kept blank for layout purposes.
295
FLD controller
2.7.2 FLD operation (FLD automatic display and key-scan using segments)
The FLD controller can choose functions from those listed in Table 2.7.1. The circled items are described
in detail below. Figure 2.7.7 shows the operation timing, and Figures 2.7.8 to 2.7.10 show the set-up
procedures.
Table 2.7.1. Selectable functions
Item
Tscan control
(Note 1)
Timing number
Set-up
Item
FLD digit interrupt
O
FLD blanking interrupt
O
16-timing
High-breakdown
voltage port drivability
P97 dimmer output
Set-up
Strong
O
Weak
O
Normal port
32-timing
Tdisp counter
count source
O
Dimmer output
High-breakdownvoltage ports:
Section of Toff generate/not generate
f(XIN)/32
f(XIN)/128
Gradation display
mode (Note 2)
Not selecting
O
T o ff2
SET/RESET
Selecting
Section of Toff does NOT
generate
O
Section of Toff generates
O
Reset at Toff2
Set at Toff2
Note 1: When selecting the FLD blanking interrupt, any one of 1 ✕ Tdisp, 2 ✕ Tdisp, or 3 ✕ Tdisp can be selected as
Tscan time.
Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number.
Operation (1) The FLD starts an automatic display when both the automatic display control bit and the
display start bit are set to “1”.
(2) The display data, the contents from the first address through the last address, in the FLD
automatic display RAM for each port is output to each port. The last address is the result of
decreasing the number indicated in the FLD data pointer from the first address. The gradation display control data is arranged at an address which is calculated by subtracting “7016”
from the stored address in the FLD automatic display RAM of the corresponding timing and
pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”.
However, the contents of the FLD automatic display RAM for ports P50, P51, and P60 to P67
are disabled by selection of the digit pulse output function, and the digit pulses are automatically output.
(3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF 16”, the
pointer is reloaded and starts counting over again.
(4) The FLD interrupt request bit is set to “1” simultaneously with the falling edge of the last
timing. The FLD automatic display output is turned off for a duration of 1 ✕ Tdisp, 2 ✕ Tdisp,
or 3 ✕ Tdisp, depending on post-interrupt settings. During this time, key scanning, which
makes use of FLD segments, can be applied.
(5) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to
the display start bit.
296
FLD controller
Connection example
SUN MON TUE WED THU FRI SAT
P60–P67 Digit
P50, P51
P30, P31 Segment
Segment
P20–P27
SP EP
RE C
■
LEVEL
●
●
●
●
AM
PM
L
R
Panel with fluorescent display (FLD)
P34–P37
M30218 Group
Key-matrix
Operation example
Tdisp
Tscan
FLD9 (P51)
Toff1
Toff2
FLD8 (P50)
FLD7 (P67)
•••
•••
FLD0 (P60)
FLD blanking interrupt request occur
FLD32–FLD41
(P20–P27,
P30, P31)
•••
Key-scan
Enlarged view of Tscan
FLD32 (P20)
FLD33 (P21)
FLD34 (P22)
•••
•••
FLD39 (P27)
Figure 2.7.7. Operation timing of FLD automatic display
297
CH
FLD controller
Port P3 direction register set-up
b7
b0
Port P3 direction register [Address 03E716]
PD3
0 0 0 0
Set P34 – P37 to input ports for key-scan input
Display pin/port switch of P2, P3, P5 and P6 set-up
b7
b0
Port P2 FLD/port switch register [Address 035916]
P2FPR
1 1 1 1 1 1 1 1
Set P20 – P27 to FLD output ports (FLD32 to FLD39)
b7
b0
Port P3 FLD/port switch register [Address 035A16]
P3FPR
0 0 0 0 0 0 1 1
Set P30 and P31 to FLD output ports (FLD40, FLD41)
Set P32 – P37 to normal I/O output ports
b7
b0
Port P5 digit output set register [Address 035C16]
P5DOR
0 0 0 0 0 0 1 1
Set P50 and P51 to digit output ports (FLD8, FLD9)
Set P52 – P57 to FLD output ports
b7
b0
1 1 1 1 1 1 1 1
Port P6 digit output set register [Address 035D16]
P6DOR
Set P60 – P67 to digit output ports (FLD0 to FLD7)
FLDC mode register set-up
b7
b0
1 0 1 0 1 1 0 1
FLDC mode register [Address 035016]
FLDM
Automatic display control bit
1 : Automatic display mode
Display start bit
0 : Stop display
Tscan control bits
b3 b2
1 1 : 3 X Tdisp; FLD blanking interrupt
Timing number control bit
0 : 16 timing mode
Gradation display mode selection control bit
1 : Selecting
Tdisp counter count source selection bit
0 : f(XIN)/32
High-breakdown voltage port drivability select bit
1 : Drivability weak
FLD output control register set-up
b7
0 1 0 0
b0
0
0
FLD output control re gist er [Address 035116]
FLDCON
P44 to P47 FLD output reverse bit
0 : Output normally
P44 to P47 FLD Toff is invalid bit
0 : Perform normally
P97 dimmer output control bit
0 : Output normally
CMOS ports: section of Toff generate/not generate bit
0 : Section of Toff does NOT generate
High-breakdown-voltage ports: section of Toff generate/not generate bit
1 : Section of Toff generates
Toff2 SET/RESET change bit
0 : gradation display data is reset at Toff2
(set at Toff1)
Continued to the next page
Figure 2.7.8. Set-up procedure for FLD automatic display (1)
298
FLD controller
Continued from the previous page
Tdisp, Toff1 and Toff2 time set-up
b7
b0
1 1 0
1 0
1 1 0
1 0
1 0
1
Tdisp time set register [Address 035216]
TDI SP
Set C816; Tdisp = (200 + 1) ✕ count source = 643 µs
Conditions: •f(XIN) =10 MHz
•Count source = f(XIN)/32 = 3.2 µs
b7
b0
1 0
0
1 0
1 1 1 1 1 0
1
Toff1 time set register [Address 035416]
T OF F 1
Set 1E16; Toff1 = 30 ✕ count source = 96 µs
Conditions: •f(XIN) =10 MHz
•Count source = f(XIN)/32 = 3.2 µs
b7
b0
1 0
1 1 1 0
1 1 0
1 0
1
Toff2 time set register [Address 035616]
T OF F 2
Set B416; Toff2 = 180 ✕ count source = 576 µs
Conditions: •f(XIN) =10 MHz
•Count source = f(XIN)/32 = 3.2 µs
FLD data pointer set-up
b7
b0
1 0
0
1 0
1 0
1 1 0
1 0
1 1
FLD data pointer [Ad dress 035816]
FLDDP
Set 9 = “digit number – 1”.
FLD interrupt control register set-up
b7
b0
FLD interrupt control register [ Addre ss 0 05016]
FLDI C
0
Interrupt priority level select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt request bit (Note)
0 : Interrupt not requested
Nothing is assigned.
Note: Only “0” can be written to this bit. (Do not write “1”.)
FLD display start
b7
b0
1
FLDC mode register [Address 035016]
FLDM
Display start bit
1 : Display
FLD display start
Figure 2.7.9. Set-up procedure for FLD automatic display (2)
299
FLD controller
FLD blanking interrupt routine
Push registers and any other set-up
FLDC mode register set-up
b7
b0
0
FLDC mode register [Address 035016]
FLDM
Automatic display control bit
0 : General-purpose mode
P2, P5 and P6 set-up
b7
b0
Port P5 [Address 03E916]
P5
1 1 1 1 1 1 0
1 0
1
Set “L” level to ports corresponding to digits
b7
b0
Port P6 [Address 03EC16]
P6
0 0 0 0 0 0 0 0
Set “L” level to ports corresponding to digits
b7
b0
Port P2 FLD/port switch register [Address 035916]
P2FPR
0 0 0 0 0 0 0 0
Set ports for key-scan to normal ports
b7
b0
Port P2 [Address 03E416]
P2
0 0 0 0 0 0 0 0
Output “L” level from ports for key-scan
Key-scan processing
P2 set-up
b7
b0
Port P2 [Address 03E416]
P2
0 0 0 0 0 0 0 0
Output “L” level from ports for key-scan
b7
b0
Port P2 FLD/port switch register [Address 035916]
P2FPR
1 1 1 1 1 1 1 1
Set normal ports to FLD output ports
FLDC mode register set-up
b7
b0
1
FLDC mode register [Address 035016]
FLDM
Automatic display control bit
1 : Automatic display mode
RTI
Figure 2.7.10. Set-up procedure for key-scan processing
300
FLD controller
This page kept blank for layout purposes.
301
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.7.3 FLD operation (FLD automatic display and key-scan using digits)
The FLD controller can choose functions from those listed in Table 2.7.2. The circled items are described
in detail below. Figure 2.7.11 shows the operation timing, and Figures 2.7.12 and 2.7.13 show the set-up
procedures.
Table 2.7.2. Selectable functions
Item
Set-up
Tscan control
(Note 1)
O
Timing number
O
Item
FLD digit interrupt
FLD blanking interrupt
High-breakdown
voltage port drivability
P97 dimmer output
16-timing
Set-up
Strong
O
Weak
O
Normal port
32-timing
Tdisp counter
count source
O
Dimmer output
High-breakdownvoltage ports:
Section of Toff generate/not generate
f(XIN)/32
f(XIN)/128
Gradation display
mode (Note 2)
Not selecting
O
T o ff2
SET/RESET
Selecting
Section of Toff does NOT
generate
O
Section of Toff generates
O
Reset at Toff2
Set at Toff2
Note 1: When selecting the FLD blanking interrupt, any one of 1 ✕ Tdisp, 2 ✕ Tdisp, or 3 ✕ Tdisp can be selected as
Tscan time.
Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number.
Operation (1) The FLD starts an automatic display when both the automatic display control bit and the
display start bit are set to “1”.
(2) The display data, the contents from the first address through the last address, in the FLD
automatic display RAM for each port is output to each port. The last address is the result of
decreasing the number indicated in the FLD data pointer from the first address. The gradation display control data is arranged at an address which is calculated by subtracting “7016”
from the stored address in the FLD automatic display RAM of the corresponding timing and
pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”.
However, the contents of the FLD automatic display RAM for ports P50, P51, and P60 to P67
are disabled by selection of the digit pulse output function, and the digit pulses are automatically output.
(3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF 16”, the
pointer is reloaded and starts counting over again.
(4) The FLD interrupt request bit is set to “1” simultaneously with the end of Toff1 time (at the
rising edge of a digit) for each timing. Key scanning, which makes use of FLD digits, can be
applied by using each FLD digit interrupt.
(5) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to
the display start bit.
302
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Connection example
P20–P27 Segment
P30, P31
P50, P51
P60–P67
Digit
SUN MON TUE WED THU FRI SAT
SP EP
RE C
■
Digit
LEVEL
●
●
●
●
AM
PM
L
R
Panel with fluorescent display (FLD)
P34–P37
M30218 Group
Key-matrix
Operation example
Tscan = 0 µs
Tdisp
FLD9 (P51)
Toff1
FLD digit interrupt request occur
Toff2
FLD8 (P50)
FLD digit interrupt request occur
FLD32–FLD41
(P20–P27,
P30, P31)
FLD digit interrupt request occur
•
•
FLD digit interrupt request occur
•
•
•
FLD7 (P67)
•
•
•
FLD0 (P60)
Figure 2.7.11. Operation timing of FLD automatic display
303
CH
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port P3 direction register set-up
b7
b0
Port P3 direction register [Address 03E716]
PD3
0 0 0 0
Set P34 – P37 to input ports for key-scan input
Display pin/port switch of P2, P3, P5 and P6 set-up
b7
b0
Port P2 FLD/port switch register [Address 035916]
P2FPR
1 1 1 1 1 1 1 1
Set P20 – P27 to FLD output ports (FLD32 to FLD39)
b7
b0
Port P3 FLD/port switch register [Address 035A16]
P3FPR
0 0 0 0 0 0 1 1
Set P30 and P31 to FLD output ports (FLD40, FLD41)
Set P32 – P37 to normal I/O output ports
b7
b0
Port P5 digit output set register [Address 035C16]
P5DOR
0 0 0 0 0 0 1 1
Set P50 and P51 to digit output ports (FLD8, FLD9)
Set P52 – P57 to FLD output ports
b7
b0
1 1 1 1 1 1 1 1
Port P6 digit output set register [Address 035D16]
P6DOR
Set P60 – P67 to digit output ports (FLD0 to FLD7)
FLDC mode register set-up
b7
b0
1 0 1 0 0 0 0 1
FLDC mode register [Address 035016]
FLDM
Automatic display control bit
1 : Automatic display mode
Display start bit
0 : Stop display
Tscan control bits
b3 b2
0 0 : FLD digit interrupt
Timing number control bit
0 : 16 timing mode
Gradation display mode selection control bit
1 : Selecting
Tdisp counter count source selection bit
0 : f(XIN)/32
High-breakdown voltage port drivability select bit
1 : Drivability weak
FLD output control register set-up
b7
0 1 0 0
b0
0
0
FLD output control re gist er [Address 035116]
FLDCON
P44 to P47 FLD output reverse bit
0 : Output normally
P44 to P47 FLD Toff is invalid bit
0 : Perform normally
P97 dimmer output control bit
0 : Output normally
CMOS ports: section of Toff generate/not generate bit
0 : Section of Toff does NOT generate
High-breakdown-voltage ports: section of Toff generate/not generate bit
1 : Section of Toff generates
Toff2 SET/RESET change bit
0 : Gradation display data is reset at Toff2
(set at Toff1)
Continued to the next page
Figure 2.7.12. Set-up procedure for FLD automatic display (1)
304
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Tdisp, Toff1 and Toff2 time set-up
b7
b0
1 1 0
1 0
1 1 0
1 0
1 0
1
Tdisp time set register [Address 035216]
TDI SP
Set C816; Tdisp = (200 + 1) ✕ count source = 643 µs
Conditions: •f(XIN) =10 MHz
•Count source = f(XIN)/32 = 3.2 µs
b7
b0
1 0
0
1 0
1 1 1 1 1 0
1
Toff1 time set register [Address 035416]
T OF F 1
Set 1E16; Toff1 = 30 ✕ count source = 96 µs
Conditions: •f(XIN) =10 MHz
•Count source = f(XIN)/32 = 3.2 µs
b7
b0
1 0
1 1 1 0
1 1 0
1 0
1
Toff2 time set register [Address 035616]
T OF F 2
Set B416; Toff2 = 180 ✕ count source = 576 µs
Conditions: •f(XIN) =10 MHz
•Count source = f(XIN)/32 = 3.2 µs
FLD data pointer set-up
b7
b0
1 0
0
1 0
1 0
1 1 0
1 0
1 1
FLD data pointer [Ad dress 035816]
FLDDP
Set 9 = “digit number – 1”.
FLD interrupt control register set-up
b7
b0
FLD interrupt control register [ Addre ss 0 05016]
FLDI C
0
Interrupt priority level select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt request bit (Note)
0 : Interrupt not requested
Nothing is assigned.
Note: Only “0” can be written to this bit. (Do not write “1”.)
FLD display start
b7
b0
1
FLDC mode register [Address 035016]
FLDM
Display start bit
1 : Display
FLD display start
Figure 2.7.13. Set-up procedure for FLD automatic display (2)
305
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.7.4 FLD operation (FLD display and key-scan using segment by software)
FLD display and key-scan using the Timer A0 interrupt are explained in detail below. Figure 2.7.14 shows
the operation timing, and Figures 2.7.15 to 2.7.17 show the set-up procedures.
Operation (1) Set both the automatic display control bit and the display start bit to “0”.
(2) Output segment data and digit data from each port during the Timer A0 interrupt processing.
(3) After finishing display of all digits, perform key-scan within during the Timer A0 interrupt
processing.
306
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Connection example
SUN MON TUE WED THU FRI SAT
P60–P67 Digit
P50, P51
P30, P31
P20–P27
Segment
SP EP
RE C
■
Segment
LEVEL
●
●
●
●
AM
PM
L
R
Panel with fluorescent display (FLD)
P34–P37
M30218 Group
Key-matrix
Operation example
P51
P50
P67
•••
•••
P60
Key-scan
P20–P27,
P30, P31
•••
Enlarged view of key-scan
P20
P21
P22
•••
•••
P27
Figure 2.7.14. Operation timing of FLD display
307
CH
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port P3 direction register set-up
b7
b0
1 1
0 0 0 0
Port P3 direction register [Address 03E716]
PD3
Set P30 and P31 to output ports for segment output
Set P34 – P37 to input ports for key-scan input
FLDC mode register set-up
b7
b0
1
0 0
FLDC mode register [Address 035016]
FLDM
Automatic display control bit
0 : General-purpose mode
Display start bit
0 : Stop display
High-breakdown voltage port drivability select bit
1 : Drivability weak
Timer mode (Timer A0) and functions set-up
b7
b0
0 0
0 0 0
Timer A0 mode register [Address 039616]
TA0MR
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TA0OUT pin is a normal port pin)
Gate function select bit
b4 b3
00:
01:
Gate function not available (TA0IN pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Count
source
0
0
0
1
f1
f8
1
0
f32
1
1
fC32
Count source period
f(XIN) : 10 MHZ f(XcIN) : 32.768 kHZ
100 ns
800 ns
3.2 µs
976.56 µs
Divide ratio set-up
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register [Address 038716, 038616]
TA0
Can be set to 000016 to FFFF16
Clock prescaler reset flag set-up
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by
dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Continued to the next page
Figure 2.7.15. Set-up procedure for FLD display (1)
308
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
TA0 interrupt control register set-up
b7
b0
TA0 interrupt control register [Ad dress 005516]
T A 0 IC
0
Interrupt priority level select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt request bit (Note)
0 : Interrupt not requested
Nothing is assigned.
Note: Only “0” can be written to this bit. (Do not write “1”.)
Count start flag set-up
b7
b0
1
Count start flag [Address 038016]
TABSR
Timer A0 count start flag
1 : Starts counting
Figure 2.7.16. Set-up procedure for FLD display (2)
309
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TA0 interrupt routine
Push registers and any other set-up
P2, P3, P5 and P6 set-up
b7
b0
1
1 0
1
0 1
0 1
0 1
0 1
0 1
0 0
Port P2 [Address 03E416]
P2
Set “0” to ports corresponding to segments
b7
b0
0 0
Port P3 [Address 03E516]
P3
Set “0” to ports corresponding to segments
b7
b0
0 0
Port P5 [Address 03E916]
P5
Set “0” to ports corresponding to digits
b7
b0
1 0
0
1 0
1 0
1 0
1 0
1 0
1 0
1
Port P6 [Address 03EC16]
P6
Set “0” to ports corresponding to digits
Segment data set-up
b7
b0
0 0 0 0 0 0 0 0
Port P2 [Address 03E416]
P2
Set segment data
b7
b0
0 0
Port P3 [Address 03E516]
P3
Set segment data
Digit data set-up
b7
b0
0 0
Port P5 [Address 03E916]
P2
Set digit data
b7
b0
0 0 0 0 0 0 0 0
Port P6 [Address 03EC16]
P6
Set digit data
RTI
Figure 2.7.17. Set-up procedure for key-scan processing
310
Mitsubishi microcomputers
M30218 Group
FLD controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This page kept blank for layout purposes.
311
FLD controller
2.7.5 FLD operation (Display with digit expander M35501FP)
The FLD controller can choose functions from those listed in Table 2.7.3. The circled items are described
in detail below. Figure 2.7.18 shows the connection example and Figure 2.7.19 shows the operation
timing, and Figures 2.7.20 and 2.7.21 show the set-up procedures.
Remarks: Also refer to the M35501FP data sheet on http://www.infomicom.mesc.co.jp
Table 2.7.3. Selectable functions
Item
Set-up
Tscan control
(Note 1)
O
FLD digit interrupt
Timing number
O
16-timing
Item
FLD blanking interrupt
High-breakdown
voltage port drivability
O
f(XIN)/32
Not selecting
O
O
T o ff2
SET/RESET
Selecting
Weak
Normal port
O
High-breakdownvoltage ports:
Section of Toff generate/not generate
f(XIN)/128
Gradation display
mode (Note 2)
Strong
P97 dimmer output
32-timing
Tdisp counter
count source
Set-up
Dimmer output
Section of Toff does NOT
generate
O
Section of Toff generates
O
Reset at Toff2
Set at Toff2
Note 1: When selecting the FLD blanking interrupt, any one of 1 ✕ Tdisp, 2 ✕ Tdisp, or 3 ✕ Tdisp can be selected as
Tscan time.
Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number.
Operation (1) The FLD starts an automatic display when both the automatic display control bit and the
display start bit are set to “1”.
(2) The display data, the contents from the first address through the last address, in the FLD
automatic display RAM for each port is output to each port. The last address is the result of
decreasing the number indicated in the FLD data pointer from the first address. The gradation display control data is arranged at an address which is calculated by subtracting “7016”
from the stored address in the FLD automatic display RAM of the corresponding timing and
pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”.
(3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF 16”, the
pointer is reloaded and starts counting over again.
(4) Supply signals to the RESET pin and SEL pin of the M35501FP from ports P70 and P71,
respectively. Supply the dimmer signal to the CLK pin from the DIMOUT (P97).
(5) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to
the display start bit.
312
FLD controller
Connection example
M30218 Group
P70
P71
DIMOUT
P00–P07
P10–P17
P20–P27
P30–P37
P40–P43
P50–P57
P60–P67
M35501FP
RESET
SEL OVFIN
CLK
OVFOUT
DIG0–DIG15
Digit (16)
Segment (52)
Fluorescent display (FLD)
Figure 2.7.18. Connection example of FLD automatic display (1)
313
FLD controller
Operation example
M35501FP
RESET
SEL
OVFIN
OVFOUT
CLK
DIG0
DIG1
DIG2
DIG3
•••
•••
DIG12
DIG13
DIG14
DIG15
M30218 Group
FLD0–FLD51
(P00–P07, P10–P17,
P20–P27, P30–P37,
P40–P43, P50–P57,
P60–P67)
Enlarged view
M35501FP
CLK
Tdisp
DIG0
DIG1
Toff1
DIG2
Toff2
•••
DIG15
M30218 Group
FLD0–FLD51
(P00–P07, P10–P17,
P20–P27, P30–P37,
P40–P43, P50–P57,
P60–P67)
•••
Figure 2.7.19. Operation timing of FLD automatic display
314
FLD controller
Display pin/port switch of P2, P3, P4, P5 and P6 set-up
b7
b0
Port P2 FLD/port switch register [Address 035916]
P2FPR
1 1 1 1 1 1 1 1
Set P20 – P27 to FLD output ports (FLD32 to FLD39)
b7
b0
Port P3 FLD/port switch register [Address 035A16]
P3FPR
1 1 1 1 1 1 1 1
Set P30 – P37 to FLD output ports (FLD40 to FLD47)
b7
b0
Port P4 FLD/port switch register [Address 035B16]
P4FPR
0 0 0 0 1 1 1 1
Set P40 – P43 to FLD output ports (FLD48 to FLD51)
Set P44 – P47 to normal I/O ports
b7
b0
Port P5 digit output set register [Address 035C16]
P5DOR
0 0 0 0 0 0 0 0
Set P50 – P57 to FLD output ports (FLD8 to FLD15)
b7
b0
0 0 0 0 0 0 0 0
Port P6 digit output set register [Address 035D16]
P6DOR
Set P60 – P67 to FLD output ports (FLD0 to FLD7)
M35501 initialization
b7
b0
Port P7 direction register [Address 03EF16]
PD7
1 1
Set P70 to output port (for RESET signal of M35501)
Set P71 to output port (for SEL signal of M35501)
b7
b0
Port P7 [Address 03ED16]
P7
0 0
Output RESET signal of M35501 (Note)
Output SEL signal “L” of M35501
Note: To remove reset state, after retaining “L” level for 2 µs or more, output “H” level when CLK signal = “L”.
FLDC mode register set-up
b7
b0
1 0 1 0 0 0 0 1
FLDC mode register [Address 035016]
FLDM
Automatic display control bit
1 : Automatic display mode
Display start bit
0 : Stop display
Tscan control bits
b3 b2
0 0 : FLD digit interrupt
Timing number control bit
0 : 16 timing mode
Gradation display mode selection control bit
1 : Selecting
Tdisp counter count source selection bit
0 : f(XIN)/32
High-breakdown voltage port drivability select bit
1 : Drivability weak
Continued to the next page
Figure 2.7.20. Set-up procedure for FLD automatic display (1)
315
FLD controller
Continued from the previous page
FLD output control register set-up
b7
0 1 0 1
b0
0
0
FLD output control re gist er [Address 035116]
FLDCON
P44 to P47 FLD output reverse bit
0 : Output normally
P44 to P47 FLD Toff is invalid bit
0 : Perform normally
P97 dimmer output control bit
1 : Dimmer output
CMOS ports: section of Toff generate/not generate bit
0 : Section of Toff does NOT generate
High-breakdown-voltage ports: section of Toff generate/not generate bit
1 : Section of Toff generates
Toff2 SET/RESET change bit
0 : Gradation display data is reset at Toff2
(set at Toff1)
Tdisp, Toff1 and Toff2 time set-up
b7
b0
1 1 0
1 0
1 1 0
1 0
1 0
1
Tdisp time set register [Address 035216]
TDI SP
Set C816; Tdisp = (200 + 1) ✕ count source = 643 µs
Conditions: •f(XIN) =10 MHz
•Count source = f(XIN)/32 = 3.2 µs
b7
b0
1 0
0
1 0
1 1 1 1 1 0
1
Toff1 time set register [Address 035416]
T OF F 1
Set 1E16; Toff1 = 30 ✕ count source = 96 µs
Conditions: •f(XIN) =10 MHz
•Count source = f(XIN)/32 = 3.2 µs
b7
b0
1 0
1 1 1 0
1 1 0
1 0
1
Toff2 time set register [Address 035616]
T OF F 2
Set B416; Toff2 = 180 ✕ count source = 576 µs
Conditions: •f(XIN) =10 MHz
•Count source = f(XIN)/32 = 3.2 µs
FLD data pointer set-up
b7
b0
1 0
0
1 0
1 0
1 1 1 1 1
FLD data pointer [Ad dress 035816]
FLDDP
Set 15 = “digit number – 1”.
FLD display start
b7
b0
1
FLDC mode register [Address 035016]
FLDM
Display start bit
1 : Display
FLD display start
Figure 2.7.21. Set-up procedure for FLD automatic display (2)
316
FLD controller
This page kept blank for layout purposes.
317
FLD controller
2.7.6 FLD operation (Display with digit expander M35501FP: column discrepancy)
The FLD controller can choose functions from those listed in Table 2.7.4. The circled items are described
in detail below. Figure 2.7.22 shows the connection example and Figure 2.7.23 shows the operation
timing, and Figures 2.7.24 and 2.7.27 show the set-up procedures.
Remarks: Also refer to the M35501FP data sheet on http://www.infomicom.mesc.co.jp
Table 2.7.4. Selectable functions
Item
Set-up
Tscan control
(Note 1)
O
FLD digit interrupt
Timing number
O
16-timing
Item
FLD blanking interrupt
High-breakdown
voltage port drivability
O
f(XIN)/32
Not selecting
O
O
T o ff2
SET/RESET
Selecting
Weak
Normal port
O
High-breakdownvoltage ports:
Section of Toff generate/not generate
f(XIN)/128
Gradation display
mode (Note 2)
Strong
P97 dimmer output
32-timing
Tdisp counter
count source
Set-up
Dimmer output
Section of Toff does NOT
generate
O
Section of Toff generates
O
Reset at Toff2
Set at Toff2
Note 1: When selecting the FLD blanking interrupt, any one of 1 ✕ Tdisp, 2 ✕ Tdisp, or 3 ✕ Tdisp can be selected as
Tscan time.
Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number.
Operation (1) The FLD starts an automatic display when both the automatic display control bit and the
display start bit are set to “1”.
(2) The display data, the contents from the first address through the last address, in the FLD
automatic display RAM for each port is output to each port. The last address is the result of
decreasing the number indicated in the FLD data pointer from the first address. The gradation display control data is arranged at an address which is calculated by subtracting “7016”
from the stored address in the FLD automatic display RAM of the corresponding timing and
pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”.
(3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF 16”, the
pointer is reloaded and starts counting over again.
(4) Supply signals to the RESET pin and SEL pin of the M35501FP from ports P70 and P71,
respectively. Supply the dimmer signal to the CLK pin from the DIMOUT (P97).
(5) Input the OVFOUT output of the M35501FP to TB2IN (P72) and count the input signals as a
count source with Timer B2. Generate the Timer A0 interrupt at FLD display intervals and
confirm the value of Timer B2. If the value is incorrect, reset the M35501FP.
(6) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to
the display start bit.
318
FLD controller
Connection example
M30218 Group
P70
P71
DIMOUT
TB2IN
P00–P07
P10–P17
P20–P27
P30–P37
P40–P43
P50–P57
P60–P67
M35501FP
RESET
SEL
CLK
OVFOUT
OVFIN
DIG0–DIG15
Digit (16)
Segment (52)
Fluorescent display (FLD)
Figure 2.7.22. Connection example of FLD automatic display
319
FLD controller
Correct operation example
M35501FP
RESET
SEL
OVFIN
OVFOUT
CLK
DIG0
DIG1
•••
•••
DIG14
DIG15
M30218 Group
FLD0–FLD51
(P00–P07, P10–P17,
P20–P27, P30–P37,
P40–P43, P50–P57,
P60–P67)
Incorrect operation example
M35501FP
RESET
SEL
OVFIN
Noise
OVFOUT
CLK
DIG0
DIG1
•••
•••
DIG14
DIG15
M30218 Group
FLD0–FLD51
(P00–P07, P10–P17,
P20–P27, P30–P37,
P40–P43, P50–P57,
P60–P67)
Column discrepancy occur
Figure 2.7.23. Operation timing of FLD automatic display
320
FLD controller
Display pin/port switch of P2, P3, P4, P5 and P6 set-up
b7
b0
Port P2 FLD/port switch register [Address 035916]
P2FPR
1 1 1 1 1 1 1 1
Set P20 – P27 to FLD output ports (FLD32 to FLD39)
b7
b0
Port P3 FLD/port switch register [Address 035A16]
P3FPR
1 1 1 1 1 1 1 1
Set P30 – P37 to FLD output ports (FLD40 to FLD47)
b7
b0
Port P4 FLD/port switch register [Address 035B16]
P4FPR
0 0 0 0 1 1 1 1
Set P40 – P43 to FLD output ports (FLD48 to FLD51)
Set P44 – P47 to normal I/O ports
b7
b0
Port P5 digit output set register [Address 035C16]
P5DOR
0 0 0 0 0 0 0 0
Set P50 – P57 to FLD output ports (FLD8 to FLD15)
b7
b0
0 0 0 0 0 0 0 0
Port P6 digit output set register [Address 035D16]
P6DOR
Set P60 – P67 to FLD output ports (FLD0 to FLD7)
M35501 initialization
b7
b0
Port P7 direction register [Address 03EF16]
PD7
1 1
Set P70 to output port (for RESET signal of M35501)
Set P71 to output port (for SEL signal of M35501)
b7
b0
Port P7 [Address 03ED16]
P7
0 0
Output RESET signal of M35501 (Note)
Output SEL signal “L” of M35501
Note: To remove reset state, after retaining “L” level for 2 µs or more, output “H” level when CLK signal = “L”.
FLDC mode register set-up
b7
b0
1 0 1 0 0 0 0 1
FLDC mode register [Address 035016]
FLDM
Automatic display control bit
1 : Automatic display mode
Display start bit
0 : Stop display
Tscan control bits
b3 b2
0 0 : FLD digit interrupt
Timing number control bit
0 : 16 timing mode
Gradation display mode selection control bit
1 : Selecting
Tdisp counter count source selection bit
0 : f(XIN)/32
High-breakdown voltage port drivability select bit
1 : Drivability weak
Continued to the next page
Figure 2.7.24. Set-up procedure for FLD automatic display (1)
321
FLD controller
Continued from the previous page
FLD output control register set-up
b7
0 1 0 1
b0
0
0
FLD output control re gist er [Address 035116]
FLDCON
P44 to P47 FLD output reverse bit
0 : Output normally
P44 to P47 FLD Toff is invalid bit
0 : Perform normally
P97 dimmer output control bit
1 : Dimmer output
CMOS ports: section of Toff generate/not generate bit
0 : Section of Toff does NOT generate
High-breakdown-voltage ports: section of Toff generate/not generate bit
1 : Section of Toff generates
Toff2 SET/RESET change bit
0 : Gradation display data is reset at Toff2
(set at Toff1)
Tdisp, Toff1 and Toff2 time set-up
b7
b0
1 1 0
1 0
1 1 0
1 0
1 0
1
Tdisp time set register [Address 035216]
TDI SP
Set C816; Tdisp = (200 + 1) ✕ count source = 643 µs
Conditions: •f(XIN) =10 MHz
•Count source = f(XIN)/32 = 3.2 µs
b7
b0
1 0
0
1 0
1 1 1 1 1 0
1
Toff1 time set register [Address 035416]
T OF F 1
Set 1E16; Toff1 = 30 ✕ count source = 96 µs
Conditions: •f(XIN) =10 MHz
•Count source = f(XIN)/32 = 3.2 µs
b7
b0
1 0
1 1 1 0
1 1 0
1 0
1
Toff2 time set register [Address 035616]
T OF F 2
Set B416; Toff2 = 180 ✕ count source = 576 µs
Conditions: •f(XIN) =10 MHz
•Count source = f(XIN)/32 = 3.2 µs
FLD data pointer set-up
b7
b0
1 0
0
1 0
1 0
1 1 1 1 1
FLD data pointer [Ad dress 035816]
FLDDP
Set 15 = “digit number – 1”.
Event counter mode (Timer B2) and functions set-up
b7
b0
0 0 0 0 0 1 0 1
Timer B2 mode register [Address 039D16]
TB2MR
Selection of event counter mode
Count polarity select bit
b3 b2
0 1 : Counts external signal’s rising edges
In an attempt to write to this bit, write “0”.
Invalid in event counter mode
Event clock select
0 : Input from TB2IN pin (Note)
Note: Set the corresponding port direction register to “0”.
Continued to the next page
Figure 2.7.25. Set-up procedure for FLD automatic display (2)
322
FLD controller
Continued from the previous page
Divide ratio (Timer B2) set-up
(b15)
b7
(b8)
b0 b7
b0
Timer B2 register [Address 039516, 039416]
TB2
Set FFFF16
Timer mode (Timer A0) and functions set-up
b7
b0
0 1 0 0
0 0 0
Timer A0 mode register [Address 039616]
TA0MR
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TA0OUT pin is a normal port pin)
Gate function select bit
b4 b3
00:
01:
Gate function not available (TA0IN pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source select bit
b7 b6
0 1 : f8
Divide ratio (Timer A0) set-up
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register [Address 038716, 038616]
TA0
Set 324016
Timer A0 interrupt control register set-up
b7
b0
TA0 interrupt control register [Ad dress 005516]
T A 0 IC
0
Interrupt priority level select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt request bit (Note)
0 : Interrupt not requested
Nothing is assigned.
Note: Only “0” can be written to this bit. (Do not write “1”.)
Count start flag set-up
b7
b0
1
1
Count start flag [Address 038016]
TABSR
Timer A0 count start flag
1 : Starts counting
Timer B2 count start flag
1 : Starts counting
FLD display start
b7
b0
1
FLDC mode register [Address 035016]
FLDM
Display start bit
1 : Display
FLD display start
Figure 2.7.26. Set-up procedure for FLD automatic display (3)
323
FLD controller
TA0 interrupt routine
Push registers and any other set-up
Timer B2 data check ?
Correct data (FE16)
Incorrect data (except FE16)
FLD display stop
b7
b0
FLDC mode register [Address 035016]
FLDM
0
Display start bit
0 : Stop display
M35501 initialization
b7
b0
Port P7 [Address 03ED16]
P7
0 0
Output RESET signal “L” of M35501
Output SEL signal “L”of M35501
b7
b0
Port P7 [Address 03ED16]
P7
0 1
Output RESET signal “H” of M35501 (Note)
Output SEL signal “L” of M35501
Note: To remove reset state, after retaining “L” level for 2 µs or more, output “H” level when CLK signal = “L”.
Set display data to FLD automatic display RAM
Count start flag set-up
b7
b0
1
Count start flag [Address 038016]
TABSR
Timer A0 count start flag
1 : Starts counting
FLD display start
b7
b0
1
FLDC mode register [Address 035016]
FLDM
Display start bit
1 : Display
Divide ratio (Timer B2) set-up
(b15)
b7
(b8)
b0 b7
b0
Timer B2 register [Address 039516, 039416]
TB2
Set FFFF16
Pop registers
RTI
Figure 2.7.27. Set-up procedure for FLD automatic display when detecting column discrepancy
324
FLD controller
2.7.7 Precautions for FLD controller
(1) Set a value of “0316” or more to the Toff1 time set register.
(2) When displaying in the gradation display mode, select the 16-timing mode with the timing number
control bit.
325
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.8 A-D Converter
2.8.1 Overview
The A-D converter used in the M30218 group operates on a successive conversion basis. The following
is an overview of the A-D converter.
(1) Mode
The A-D converter operates in one of five modes:
(a) One-shot mode
Carries out A-D conversion on input level of one specified pin only once.
(b) Repetition mode
Repeatedly carries out A-D conversion on input level of one specified pin.
(c) One-shot sweep mode
Carries out A-D conversion on input level of two or more specified pins only once.
(d) Repeated sweep mode 0
Repeatedly carries out A-D conversion on input level of two or more pins.
(e) Repeated sweep mode 1
Repeatedly carries out A-D conversion on input level of two or more pins. This mode is different from
the repeated sweep mode 0 in that weights can be assigned to specifing pins control the number of
conversion times.
(2) Operation clock
The operation clock can be selected from the following: fAD, divide-by-2 fAD, and divide-by-4 fAD. The
fAD frequency is equal to that of the CPU’s main clock.
(3) Conversion time
Number of conversion for A-D convertor varies depending on resolution as given. Table 2.8.1 shows
relation between the A-D converter operation clock and conversion time.
Sample & Hold function selected:
33 cycles for 10-bit resolution, or 28 cycles for 8-bit resolution
No Sample & Hold function:
59 cycles for 10-bit resolution, or 49 cycles for 8-bit resolution
Table 2.8.1. Conversion time every operation clock
Frequency selection bit 1
0
Frequency selection bit 0
A-D converter's operation clock
1
φAD =
Invalid
1
0
fAD
4
φAD =
fAD
2
φAD = fAD
Min. conversion
cycles (Note 1)
8-bit mode
28 X φAD
10-bit mode
33 X φAD
Min. conversion
time (Note 2)
8-bit mode
11.2µs
5.6µs
2.8µs
10-bit mode
13.2µs
6.6µs
3.3µs
Note 1: The number of conversion cycles per one analog input pin.
Note 2: The conversion time per one analog input pin (when fAD = f(XIN) = 10 MHz)
326
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Functions selection
(a) Sample & Hold function
Sample & Hold function samples input voltage when A-D conversion starts and carries out A-D
conversion on the voltage sampled. When A-D conversion starts, input voltage is sampled for 3
cycles of the operation clock. When the Sample & Hold function is selected, set the operation clock
for A-D conversion to 1 MHz or higher.
(b) 8-bit A-D to 10-bit A-D switching function
Either 8-bit resolution or 10-bit resolution can be selected. When 8-bit resolution is selected, the 8
higher-order bits of the 10-bit A-D are subjected to A-D conversion. The equations for 10-bit resolution and 8-bit resolution are given below:
10-bit resolution (Vref X n / 210 ) – (Vref X 0.5 / 1010 ) (n = 1 to 1023), 0 (n = 0)
8-bit resolution
(Vref X n / 28 ) – (Vref X 0.5 / 210 )
(n = 1 to 255), 0 (n = 0)
(c) Connecting or cutting Vref
Cutting Vref allows decrease of the current flowing into the A-D converter. To decrease the
microcomputer's power consumption, cut Vref. To carry out A-D conversion, start A-D conversion 1
µs or longer after connecting Vref.
The following are exsamples in which functions (a) through (c) are selected:
• One-shot mode ......................................................................................................................... P332
• Repeat mode, software trigger ................................................................................................. P334
• One-shot sweep mode, software trigger ................................................................................... P336
• Repeated sweep mode 0, software trigger ............................................................................... P338
• Repeated sweep mode 1, software trigger ............................................................................... P340
327
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Input to A-D converter and direction register
To use the A-D converter, set the direction register of the relevant port to input.
(6) Pins related to A-D converter
(a) AN0 pin through AN7 pin
(b) AVcc pin
(c) VREF pin
(d) AVss pin
Input pins of the A-D converter
Power source pin of the analog section
Input pin of reference voltage
GND pin of the analog section
(7) A-D converter and related registers
Figure 2.8.1 shows the memory map of A-D converter-related registers, and Figures 2.8.2 through
2.8.4 show A-D converter-related registers.
004E16
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D416
A-D conversion interrupt control register (ADIC)
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
A-D register 7 (AD7)
A-D control register 2 (ADCON2)
03D516
03D616
A-D control register 0 (ADCON0)
03D716
A-D control register 1 (ADCON1)
Figure 2.8.1. Memory map of A-D converter-related registers
328
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 0 (Note)
b7
b6
b5
0
b4
b3
b2
b1
b0
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000XXX2
Bit name
Function
RW
b2 b1 b0
CH0
Analog input pin select bit
CH1
CH2
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
b4 b3
M D0
M D1
A-D operation mode select 0 0 : One-shot mode
bit 0
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
Must always be “0”.
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Figure 2.8.2. A-D converter-related registers (1)
329
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 1 (Note)
b7
b6
0 0
b5
b4
b3
b2
b1
b0
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
0016
Bit name
A-D sweep pin select bit
SCAN0
Function
RW
When single sweep and repeat sweep
mode 0 are selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
When repeat sweep mode 1 is selected
SCAN1
b1 b0
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
M D2
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
BITS
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Vref connect bit
0 : Vref not connected
1 : Vref connected
VCUT
Must always be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Figure 2.8.3. A-D converter-related registers (2)
330
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 2 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
ADCON2
03D416
XXXXXXX02
Bit symbol
SMP
Bit name
A-D conversion method
select bit
Function
R W
0 Without sample and hold
1 With sample and hold
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
A-D register i
(b15)
b7
(b8)
b0 b7
ADi (i=0 to 7)
Address
When reset
03C016 to 03CF16 Indeterminate
b0
Function
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
When read, the content is indeterminate
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be “0”.
Figure 2.8.4. A-D converter-related registers (3)
331
R W
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.8.2 Operation of A-D converter (one-shot mode)
In one-shot mode, choose functions from those listed in Table 2.8.2. Operations of the circled items are
described below. Figure 2.8.5 shows the operation timing, and Figure 2.8.6 shows the set-up procedure.
Table 2.8.2. Choosed functions
Item
Set-up
Operation clock
φAD
O
Divided-by-4 f AD / dividedby-2 fAD / fAD
Resolution
O
8-bit / 10-bit
Analog input pin
O
One of AN 0 pin to AN7 pin
O
Not activated
Sample & Hold
Activated
Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to begin operating.
(2) After A-D conversion is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register i. At this time, the A-D conversion interrupt request bit goes to “1”. Also, the A-D conversion start flag goes to “0”, and the A-D converter
stops operating.
(1) Start A-D conversion
(2) A-D conversion is complete
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
φAD
Set to “1” by software
A-D conversion
start flag
“1”
“0”
A-D register i
A-D conversion
interrupt request
bit
Result
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: When φAD frequency is less than 1MH Z, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.8.5. Operation timing of one-shot mode
332
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting Sample and hold
b7
b0
1
A-D control register 2 [Address 03D4 16]
ADCON2
A-D conversion method select bit
1 : With sample and hold
Setting A-D control register 0 and A-D control register 1
b7
b0
0
0
0
b7
A-D control register 0 [Address 03D6 16]
ADCON0
0
0
b0
0
1
0
A-D control register 1 [Address 03D7 16]
ADCON1
Invalid in one-shot mode
Analog input pin select bit (Note)
b2 b1 b0
0 0 0 : AN 0
0 0 1 : AN 1
0 1 0 : AN 2
0 1 1 : AN 3
1 0 0 : AN 4
1 0 1 : AN 5
1 1 0 : AN 6
1 1 1 : AN 7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
A-D operation mode select bit 1 (Note)
0 (Must always be “0” in one-shot mode)
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1
0 : f AD/2 or f AD/4 is selected
1 : f AD is selected
One-shot mode is selected (Note)
Nothing is arranged for this bit.
Fix “0” to this bit.
Vref connect bit
1 : Vref connected
A-D conversion start flag
0 : A-D conversion disabled
Nothing is arranged for these bits.
Fix “0” to these bits.
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: Rewrite to analog input pin select bit after changing A-D operation mode.
Setting A-D conversion start flag
b7
b0
1
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
1 : A-D conversion started
Start A-D conversion
Stop A-D conversion
Reading conversion result
(b15)
b7
(b8)
b0 b7
b0
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
[Address 03C1 16, 03C016]
[Address 03C3 16, 03C216]
[Address 03C5 16, 03C416]
[Address 03C7 16, 03C616]
[Address 03C9 16, 03C816]
[Address 03CB 16, 03CA16]
[Address 03CD 16, 03CC 16]
[Address 03CF 16, 03CE16]
Eight low-order bits of A-D conversion result
During 10-bit mode
Two high-order bits of A-D conversion result
During 8-bit mode
When read, the content is indeterminate
Figure 2.8.6. Set-up procedure of one-shot mode
333
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.8.3 Operation of A-D Converter (in repeat mode)
In repeat mode, choose functions from those listed in Table 2.8.3. Operations of the circled items are
described below. Figure 2.8.7 shows timing chart, and Figure 2.8.8 shows the set-up procedure.
Table 2.8.3. Choosed functions
Item
Set-up
Operation clock
φAD
O
Divided-by-4 f AD / dividedby-2 fAD / fAD
Resolution
O
8-bit / 10-bit
Analog input pin
O
One of AN0 pin to AN7 pin
Sample & Hold
Not activated
O
Activated
Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start operating.
(2) After the first conversion is completed, the content of the successive comparison register
(conversion result) is transmitted to A-D register i. The A-D conversion interrupt request bit
does not go to “1”.
(3) The A-D converter continues operating until the A-D conversion start flag is set to “0” by
software. The conversion result is transmitted to A-D register i every time a conversion is
completed.
(1) Start A-D conversion
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
(2) Conversion result is transferred to the A-D register
(3) A-D conversion
8-bit resolution : 28 φAD cycles
is complete
10-bit resolution : 33 φAD cycles
φAD
Set to “1” by software
Cleared to “0” by software
A-D conversion “1”
start flag
“0”
A-D register i
A-D conversion
Result
Result
Stop
Convert
Convert
Convert
Stop
Note: When φAD frequency is less than 1MHz, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles
for 10-bit resolution.
Figure 2.8.7. Operation timing of repeat mode
334
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting Sample and hold
b7
b0
1
A-D control register 2 [Address 03D4 16]
ADCON2
A-D conversion method select bit
1 : With sample and hold
Setting A-D control register 0 and A-D control register 1
b7
b0
0
0
0
b7
A-D control register 0 [Address 03D6 16]
ADCON0
1
0
b0
0
1
0
A-D control register 1 [Address 03D7 16]
ADCON1
Invalid in Repeat mode
Analog input pin select bit (Note)
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : AN 0 is selected
1 : AN 1 is selected
0 : AN 2 is selected
1 : AN 3 is selected
0 : AN 4 is selected
1 : AN 5 is selected
0 : AN 6 is selected
1 : AN 7 is selected
A-D operation mode select bit 1 (Note)
0 (Must always be “0” in repeat mode)
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1
0 : f AD/2 or f AD/4 is selected
1 : f AD is selected
Repeat mode is selected (Note)
Nothing is arranged for this bit.
Fix “0” to this bit.
Vref connect bit
1 : Vref connected
A-D conversion start flag
0 : A-D conversion disabled
Frequency select bit 0
0 : f AD/4 is selected
1 : fAD/2 is selected
Nothing is arranged for these bits.
Fix “0” to these bits
Note: Rewrite to analog input pin select bit after changing A-D operation mode.
Setting A-D conversion start flag
b7
b0
1
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
1 : A-D conversion started
Start A-D conversion
Transmitting conversion result to A-D register i
(b15)
b7
(b8)
b0 b7
b0
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
[Address 03C1 16, 03C016]
[Address 03C3 16, 03C216]
[Address 03C5 16, 03C416]
[Address 03C7 16, 03C616]
[Address 03C9 16, 03C816]
[Address 03CB 16, 03CA16]
[Address 03CD 16, 03CC 16]
[Address 03CF 16, 03CE16]
Eight low-order bits of A-D conversion result
During 10-bit mode
Two high-order bits of A-D conversion result
During 8-bit mode
When read, the content is indeterminate
Setting A-D conversion start flag
b7
b0
0
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
0 : A-D conversion disabled
Stop A-D conversion
Figure 2.8.8. Set-up procedure of repeat mode
335
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.8.4 Operation of A-D Converter (in single sweep mode)
In single sweep mode, choose functions from those listed in Table 2.8.4. Operations of the circled items
are described below. Figure 2.8.9 shows timing chart, and Figure 2.8.10 shows the set-up procedure.
Table 2.8.4. Choosed functions
Item
Operation clock φAD
Resolution
Set-up
Item
O
Divided-by-4 f AD / dividedby-2 fAD / fAD
O
8-bit / 10-bit
O
AN0 and AN1 (2 pins) / AN 0
to AN3 (4 pins) / AN 0 to AN 5
(6 pins) / AN 0 to AN7 (8 pins)
Set-up
Sample & Hold
Not activated
O
Activated
Analog input pin
Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion
on voltage input to the AN0 pin.
(2) After the A-D conversion of voltage input to the AN0 pin is completed, the content of the
successive comparison register (conversion result) is transmitted to A-D register 0. The A-D
converter converts all analog input pins selected by the user. The conversion result is transmitted to A-D register i corresponding to each pin, every time conversion on one pin is completed.
(3) When the A-D conversion on all the analog input pins selected is completed, the A-D conversion interrupt request bit goes to “1”. At this time, the A-D conversion start flag goes to “0”.
The A-D converter stops operating.
(1) Start A-D conversion
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
(2) After A-D conversion on AN0 pin is complete,
A-D converter begins converting all pins selected
(3) A-D conversion
is complete
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
φAD
Set to “1” by software
A-D conversion “1”
start flag
“0”
A-D register 0
Result
A-D register 1
Result
A-D register i
Result
A-D conversion “1”
interrupt request
“0”
bit
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.8.9. Operation timing of single sweep mode
336
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting Sample and hold
b7
b0
1
A-D control register 2 [Address 03D4 16]
ADCON2
A-D conversion method select bit
1 : With sample and hold
Setting A-D control register 0 and A-D control register 1
b7
b0
0
0
1
b7
A-D control register 0
[Address 03D6 16] ADCON0
0
0
b0
0
1
0
A-D control register 1 [Address 03D7 16]
ADCON1
A-D sweep pin select bit (Note)
Invalid in single sweep mode
b1 b0
0 0 : AN 0, AN1 (2 pins)
0 1 : AN 0 to AN 3 (4 pins)
1 0 : AN 0 to AN 5 (6 pins)
1 1 : AN 0 to AN 7 (8 pins)
Single sweep mode is selected
(Note)
Nothing is arranged for this bit.
Fix “0” to this bit.
A-D operation mode select bit 1 (Note)
0 (Must always be “0” in Single sweep mode)
A-D conversion start flag
0 : A-D conversion disabled
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Frequency select bit 1
0 : f AD/2 or f AD/4 is selected
1 : f AD is selected
Vref connect bit
1 : Vref connected
Nothing is arranged for these bits.
Fix “0” to these bits.
Note: Rewrite to analog input pin select bit after changing A-D operation mode.
Setting A-D conversion start flag
b7
b0
1
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
1 : A-D conversion started
Start A-D conversion
Stop A-D conversion
Reading conversion result
(b15)
b7
(b8)
b0 b7
b0
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
[Address 03C1 16, 03C016]
[Address 03C3 16, 03C216]
[Address 03C5 16, 03C416]
[Address 03C7 16, 03C616]
[Address 03C9 16, 03C816]
[Address 03CB 16, 03CA16]
[Address 03CD 16, 03CC 16]
[Address 03CF 16, 03CE16]
Eight low-order bits of A-D conversion result
During 10-bit mode
Two high-order bits of A-D conversion result
During 8-bit mode
When read, the content is indeterminate
Figure 2.8.10. Set-up procedure of single sweep mode
337
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.8.5 Operation of A-D Converter (in repeat sweep mode 0)
In repeat sweep mode 0, choose functions from those listed in Table 2.8.5. Operations of the circled items
are described below. Figure 2.8.11 shows timing chart, and Figure 2.8.12 shows the set-up procedure.
Table 2.8.5. Choosed functions
Item
Operation clock φAD
Resolution
Set-up
Item
O
Divided-by-4 f AD / dividedby-2 f AD / fAD
O
8-bit / 10-bit
O
AN 0 and AN1 (2 pins) / AN 0
to AN 3 (4 pins) / AN 0 to AN 5
(6 pins) / AN 0 to AN7 (8 pins)
Set-up
Sample & Hold
Not activated
O
Activated
Analog input pin
Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion
on voltage input to the AN0 pin.
(2) After the A-D conversion of voltage input to the AN0 pin is completed, the content of the
successive comparison register (conversion result) is transmitted to A-D register 0.
(3) The A-D converter converts all pins selected by the user. The conversion result is transmitted
to A-D register i corresponding to each pin every time A-D conversion on the pin is completed. The A-D conversion interrupt request bit does not go to “1”.
(4) The A-D converter continues operating until the A-D conversion start flag is set to “0” by
software.
(1) Start A-D conversion
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
(2) AN1 conversion begins after AN0
conversion is complete
(3) Consecutive conversion
(4) A-D conversion
is complete
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
φAD
Cleared to “0” by software
Set to “1” by software.
A-D
conversion
start flag
A-D register 0
“1”
“0”
Result
A-D register 1
Result
A-D register i
Result
Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.8.11. Operation timing of repeat sweep mode 0
338
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting Sample and hold
b7
b0
1
A-D control register 2 [Address 03D4 16]
ADCON2
A-D conversion method select bit
1 : With sample and hold
Setting A-D control register 0 and A-D control register 1
b7
b7
b0
0
0
1
A-D control register 0
[Address 03D6 16] ADCON0
1
0
b0
0
1
0
Invalid in repeat sweep mode 0
A-D control register 1 [Address 03D7 16]
ADCON1
A-D sweep pin select bit (Note)
b1 b0
0 0 : AN 0, AN1 (2 pins)
0 1 : AN 0 to AN 3 (4 pins)
1 0 : AN 0 to AN 5 (6 pins)
1 1 : AN 0 to AN 7 (8 pins)
Repeat sweep mode 0 is selected
(Note)
Nothing is arranged for this bit.
Fix “0” to this bit.
A-D operation mode select bit 1 (Note)
0 (Must always be “0” in repeat sweep mode 0)
A-D conversion start flag
0 : A-D conversion disabled
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 0
0 : f AD/4 is selected
1 : fAD/2 is selected
Frequency select bit 1
0 : fAD/2 or f AD/4 is selected
1 : fAD is selected
Vref connect bit
1 : Vref connected
Nothing is arranged for these bits.
Fix “0” to these bits.
Note: Rewrite to analog input pin select bit after changing A-D operation mode.
Setting A-D conversion start flag
b7
b0
1
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
1 : A-D conversion started
Repeatedly carries out A-D conversion on pins
selected through the A-D sweep pin select bit.
Start A-D conversion
Transmitting conversion result to A-D register i
(b15)
b7
(b8)
b0 b7
b0
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
[Address 03C1 16, 03C0 16]
[Address 03C3 16, 03C2 16]
[Address 03C5 16, 03C4 16]
[Address 03C7 16, 03C6 16]
[Address 03C9 16, 03C8 16]
[Address 03CB 16, 03CA 16]
[Address 03CD 16, 03CC16]
[Address 03CF 16, 03CE 16]
Eight low-order bits of A-D conversion result
During 10-bit mode
Two high-order bits of A-D conversion result
During 8-bit mode
When read, the content is indeterminate
Setting A-D conversion start flag
b7
b0
0
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
0 : A-D conversion disabled
Stop A-D conversion
Figure 2.8.12. Set-up procedure of repeat sweep mode 0
339
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.8.6 Operation of A-D Converter (in repeat sweep mode 1)
In repeat sweep mode 1, choose functions from those listed in Table 2.8.6. Operations of the circled items are
described below. Figure 2.8.13 shows ANi pin's sweep sequence, Figure 2.8.14 shows timing chart, and Figure
2.8.15 shows the set-up procedure.
Table 2.8.6. Choosed functions
Item
Set-up
Operation clock φAD
Resolution
Set-up
Sample & Hold
O
Divided-by-4 f AD / dividedby-2 f AD / fAD
O
8-bit / 10-bit
O
An0 (1 pin) / AN 0 and AN1 (2
pins) / AN 0 to AN2 (3 pins) /
AN 0 to AN3 (4 pins)
Analog input pin
Operation
Item
Not activated
O
Activated
(1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage
input to the AN0 pin.
(2) After the A-D conversion on voltage input to the AN 0 pin is completed, the content of the successive
comparison register (conversion result) is transmitted to A-D register 0.
(3) Every time the A-D converter carries out A-D conversion on a selected analog input pin, the A-D converter
carries out A-D conversion on only one unselected pin, and then the A-D converter carries out A-D conversion from the AN0 pin again. (See Figure 2.8.13.) The conversion result is transmitted to A-D register i
every time conversion on a pin is completed. The A-D conversion interrupt request bit does not go to “1”.
(4) The A-D converter continues operating until software goes the A-D conversion start flag to “0”.
0
0
0
0
0
0
0
0
1
1
2
2
3
4
5
6
7
0
.
.
.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
2
3
4
5
6
7
0
.
.
.
When AN 0 to AN 2 are selected
Time
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
3
3
4
5
6
7
0
.
.
.
When AN 0 to AN3 are selected
Time
Converted analog input pin
0
Time
Converted analog input pin
When AN 0, AN 1 are selected
Time
Converted analog input pin
Converted analog input pin
When AN 0 is selected
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
.
.
.
4
4
5
6
7
Figure 2.8.13. ANi pin's sweep sequence in repeat sweep mode 1
(2) Conversion result is
transfered to A-D
(3) Consecutive conversion
conversion register 0
(1) Start AN0 pin conversion
8-bit resolution :
8-bit resolution :
8-bit resolution :
28 φAD cycles
28 φAD cycles
28 φAD cycles
10-bit resolution :
10-bit resolution :
10-bit resolution :
33 φAD cycles
33 φAD cycles
33 φAD cycles
8-bit resolution :
28 AD cycles
10-bit resolution :
33 AD cycles
(4) A-D
conversion
is complete
φAD
Cleared to “0” by software
Set to “1” by software
A-D
conversion
start flag
A-D register 0
“1”
“0”
Result
Result
Result
A-D register 1
A-D register 2
Result
Note: When φAD frequency is less than 1MHz, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.8.14. Operation timing of repeat sweep mode 1
340
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting Sample and hold
b7
b0
1
A-D control register 2 [Address 03D4 16]
ADCON2
A-D conversion method select bit
1 : With sample and hold
Setting A-D control register 0 and A-D control register 1
b7
b0
0
0
1
b7
A-D control register 0
[Address 03D6 16] ADCON0
1
0
b0
0
1
1
Invalid in repeat sweep mode 1
A-D control register 1 [Address 03D7 16]
ADCON1
A-D sweep pin select bit (Note)
b1 b0
0 0 : AN 0 (1 pin)
0 1 : AN 0, AN1 (2 pins)
1 0 : AN 0 to AN 2 (3 pins)
1 1 : AN 0 to AN 3 (4 pins)
Repeat sweep mode 1 is selected
(Note)
Nothing is arranged for this bit.
Fix “0” to this bit.
A-D operation mode select bit 1 (Note)
0 (Must always be “0” in repeat sweep mode 1)
A-D conversion start flag
0 : A-D conversion disabled
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 0
0 : f AD/4 is selected
1 : fAD/2 is selected
Frequency select bit 1
0 : f AD/2 or f AD/4 is selected
1 : fAD is selected
Vref connect bit
1 : Vref connected
Nothing is arranged for these bits.
Fix “0” to these bits.
Note: Rewrite to analog input pin select bit after changing A-D operation mode.
Setting A-D conversion start flag
b7
b0
1
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
1 : A-D conversion started
Start A-D conversion
Converts non-selected pin after converting pins
selected through the A-D sweep pin select bit.
Transmitting conversion result to A-D register i
(b15)
b7
(b8)
b0 b7
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
b0
[Address 03C1 16, 03C016]
[Address 03C3 16, 03C216]
[Address 03C5 16, 03C416]
[Address 03C7 16, 03C616]
[Address 03C9 16, 03C816]
[Address 03CB 16, 03CA16]
[Address 03CD 16, 03CC 16]
[Address 03CF 16, 03CE16]
Eight low-order bits of A-D conversion result
During 10-bit mode
Two high-order bits of A-D conversion result
During 8-bit mode
When read, the content is indeterminate
Setting A-D conversion start flag
b7
b0
0
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
0 : A-D conversion disabled
Stop A-D conversion
Figure 2.8.15. Set-up procedure of repeat sweep mode 1
341
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.8.7 Precautions for A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1,
and to bit 0 of A-D control register 2 when A-D conversion is stopped.
In particular, when the Vref connection bit is changed from 0 to 1, start A-D conversion after
an elapse of 1 µs or longer.
(2) To reduce conversion error due to noise, connect a voltage to the AVcc pin and to the V REF
pin from an independent source. It is recommended to connect a capacitor between the AVss
pin and the AVcc pin, between the AVss pin and the VREF pin, and between the AVss pin and
the analog input pin (ANi). Figure 2.8.16 shows an example of connecting the capacitors to
these pins.
Microcomputer
VCC
AVCC
VREF
C1
C2
AVSS
Note 1: C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF
(for reference)
Note 2: Use thick and shortest possible wiring
to connect capacitors.
C3
ANi
Figure 2.8.16. Use of capacitors to reduce noice
(3) Set the direction register of the the port corresponding to a pin to be used as an analog input
pin to input.
(4) Rewrite to analog input pin after changing A-D operation mode. The two cannot be set at the
same time.
(5) When using the one-shot or single sweep mode
Confirm that A-D conversion is complete before reading the A-D register.
(Note: When A-D conversion interrupt request bit is set, it shows that A-D conversion is completed.)
(6) When using the repeat mode or repeat sweep mode 0 or 1
Use the undivided main clock as the internal CPU clock.
342
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.8.8 Method of A-D Conversion (10-bit mode)
(1) The A-D converter compares the reference voltage (Vref) generated internally based on the
contents of the successive comparison register with the analog input voltage (VIN) input from
the analog input pin. Each bit of the comparison result is stored in the successive comparison
register until analog-to-digital conversion (successive comparison method) is complete. If a
trigger occurs, the A-D converter carries out the following:
1. Fixes bit 9 of the successive comparison register.
Compares Vref with VIN: [In this instance, the contents of the successive comparison
register are “10000000002” (default).]
Bit 9 of the successive comparison register varies depending on the comparison result as follows.
If Vref < VIN, then “1” is assigned to bit 9.
If Vref > VIN, then “0” is assigned to bit 9.
2. Fixes bit 8 of the successive comparison register.
Sets bit 8 of the successive comparison register to “1”, then compares Vref with VIN.
Bit 8 of the successive comparison register varies depending on the comparison
result as follows:
If Vref < VIN, then “1” is assigned to bit 8.
If Vref > VIN, then “0” is assigned to bit 8.
3. Fixes bit 7 through bit 0 of the successive comparison register.
Carries out step 2 above on bit 7 through bit 0.
After bit 0 is fixed, the contents of the successive comparison register (conversion
result) are transmitted to A-D register i.
Vref is generated based on the latest content of the successive comparison register. Table
2.8.7 shows the relationship of the successive comparison register contents and Vref. Table
2.8.8 shows how the successive comparison register and Vref vary while A-D conversion is in
progress. Figure 2.8.17 shows theoretical A-D conversion characteristics.
Table 2.8.7. Relationship of the successive comparison register contents and Vref
Successive approximation register : n
Vref (V)
0
0
VREF
1024
1 to1023
343
x
n
–
VREF
2048
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 2.8.8. Variation of the successive comparison register and Vref while A-D conversion is in
progress (10-bit mode)
Successive approximation register
b9
Vref change
b0
A-D converter stopped
1 0 0 0 0 0 0 0 0 0
VREF [V]
2
1st comparison
1 0 0 0 0 0 0 0 0 0
VREF VREF
[V]
–
2048
2
2nd comparison
n9 1 0 0 0 0 0 0 0 0
VREF
VREF
VREF
[V]
–
±
2048
4
2
1st comparison result
3rd comparison
n9 n8 1 0 0 0 0 0 0 0
2nd comparison result
10th comparison
n9 n8 n7 n6 n5 n4 n3 n2 n1 0
Conversion complete
n9 n8 n7 n6 n5 n4 n3 n2 n1 n0
n9 = 1
n9 = 0
VREF ± VREF ± VREF – VREF [V]
4
8
2048
2
VREF
4
– VREF
4
n8 = 1
+
+
n8 = 0
–
VREF
8
VREF
8
VREF
VREF
VREF
VREF
VREF
[V]
± ...... ±
–
±
±
2
4
8
1024
2048
This data transfers to the bit 0
to bit 9 of A-D register.
Result of A-D conversion
Theoretical A-D
conversion characteristic
3FF16
3FE16
00316
Ideal A-D conversion
characteristic
00216
00116
00016
0
VREF x 1
1024
VREF x 2
1024
VREF x 3
1024
VREF x 1021 VREF x 1022 VREF x 1023
1024
1024
1024
VREF x 0.5
1024
VREF
Analog input voltage
Figure 2.8.17. Theoretical A-D conversion characteristics (10-bit mode)
344
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.8.9 Method of A-D Conversion (8-bit mode)
(1) In 8-bit mode, 8 higher-order bits of the 10-bit successive comparison register becomes A-D
conversion result. Hence, if compared to a result obtained by using an 8-bit A-D converter,
the voltage compared is different by 3 VREF/2048 (see what are underscored in Table 2.8.9),
and differences in stepping points of output codes occur as shown in Figure 2.8.18.
Table 2.8.9. The comparison voltage in 8-bit mode compared to 8-bit A-D converter
8-bit mode
8-bit A-D converter
0
0
n=0
Comparison
voltage
Vref
n = 1 to 255
VREF
28
x n
–
VREF
210
x 0.5
VREF
28
x
n –
VREF
28
Optimal conversion characteristics of 8-bit A-D converter (VREF = 5.12 V)
Output code
(Result of A-D conversion)
02
01
00
10
30
Analog input voltage (mV)
Optimal conversion characteristics in 8-bit mode (VREF = 5.12 V)
Output code
(Result of A-D conversion)
8-bit
mode
10-bit
mode
(Note)
10bit-mode
02
01
00
09
08
07
06
05
04
03
02
01
00
8bit-mode
17.5
37.5
Analog input voltage (mV)
Note: Differences in stepping points of output code for analog input voltage.
Figure 2.8.18. The level conversion characteristics of 8-bit mode and 8-bit A-D converter
345
x 0.5
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 2.8.10. Variation of the successive comparison register and Vref while A-D conversion is in
progress (8-bit mode)
Vref change
Successive approximation register
b9
b0
A-D converter stopped
1 0 0 0 0 0 0 0 0 0
VREF
[V]
2
1st comparison
1 0 0 0 0 0 0 0 0 0
VREF VREF
[V]
–
2
2048
2nd comparison
n9 1 0 0 0 0 0 0 0 0
VREF
VREF
VREF
[V]
–
±
2
4
2048
1st comparison result
3rd comparison
2nd comparison result
n9 n8 n7 n6 n5 n4 n3 1 0 0
Conversion
complete
n9 n8 n7 n 6 n 5 n 4 n3 n 2 0 0
n9 = 0
VREF VREF
VREF
VREF
[V]
–
±
±
2
2048
4
8
n9 n 8 1 0 0 0 0 0 0 0
8th comparison
n9 = 1
VREF
4
VREF
–
4
n8 = 1
+
n8 = 0
–
+
VREF
VREF
VREF
VREF
VREF
[V]
±
±
± ...... ±
–
2048
2
4
8
256
This data transfers to bit 0 to
bit 7 of A-D register.
Result of A-D conversion
Theoretical A-D conversion
characteristic of general 8-bit
A-D converter
FF16
FE16
0316
Theoretical A-D conversion
characteristic in the 8-bit mode
0216
0116
0016
0
VREF x 1
256
VREF x 2
256
VREF
8
VREF
8
VREF x 3
256
VREF x 4
256
VREF x 254
256
VREF x 255
256
VREF
Analog input voltage
VREF x 3
2048
Figure 2.8.19. Theoretical A-D conversion characteristics (8-bit mode)
346
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.8.10 Absolute Accuracy and Differential Non-Linearity Error
• Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A-D conversion
characteristics, and actual A-D conversion result. When measuring absolute accuracy, the voltage at
the middle point of the width of analog input voltage (1-LSB width), that can meet the expectation of
outputting an equal code based on the theoretical A-D conversion characteristics, is used as an analog input voltage. For example, if 10-bit resolution is used and if VREF (reference voltage) = 5.12 V,
then 1-LSB width becomes 5 mV, and 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, ···· are used as analog input
voltages. If analog input voltage is 25 mV, “absolute accuracy = ± 3LSB” refers to the fact that actual
A-D conversion falls on a range from “00216” to “00816” though an output code, “00516”, can be expected from the theoretical A-D conversion characteristics. Zero error and full-scale error are included
in absolute accuracy.
Also, all the output codes for analog input voltage between VREF and AVcc becomes “3FF16”.
Output code
(result of A-D conversion)
00B16
00A16
00916
+3LSB
00816
Theoretical A-D conversion
characteristic
00716
00616
00516
00416
00316
00216
–3LSB
00116
00016
0
5
10
15
20
25
30
35
Analog input voltage (mV)
Figure 2.8.20. Absolute accuracy (10-bit resolution)
347
40
45
50
55
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Differential non-linearity error
Differential non-linearity error refers to the difference between 1-LSB width based on the theoretical AD conversion characteristics (an analog input width that can meet the expectation of outputting an
equal code) and an actually measured 1-LSB width (analog input voltage width that outputs an equal
code). If 10-bit resolution is used and if VREF (reference voltage) = 5.12 V, “differential non-linearity
error = ± 1LSB” refers to the fact that 1-LSB width actually measured falls on a range from 0 mV to 10
mV though 1-LSB width based on the theoretical A-D conversion characteristics is 5 mV (see 5.2 A-D
converter's standard characteristics).
Output code
(result of A-D conversion)
00916
1LSB width for theoretical A-D
conversion characteristic
00816
00716
00616
00516
00416
00316
00216
00116
Differential non-linear error
00016
0
5
10
15
20
25
30
35
Analog input voltage (mV)
Figure 2.8.21. Differential non-linearity error (10-bit resolution)
348
40
45
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.8.11 Internal Equivalent Circuit of Analog Input
Figure 2.8.22 shows the internal equivalent circuit of analog input.
Vcc
Vcc Vss
AVcc
Parasitic
diode
ON resistor
approx. 2kΩ
AN0
ON resistor
approx. 0.6kΩ
Wiring resistor
approx. 0.2kΩ
Analog input voltage
SW1
SW2
Parasitic
diode
C = Approx. 3.0pF
AMP
VIN
ON resistor,
approx. 5kΩ
Sampling
control signal
Vss
SW3
SW4
i ladder-type
switches
(i = 8)
i ladder-type wiring
resistors
(i = 8)
AVss
Chopper-type
amplifier
AN i
SW1
b2 b1 b0
Reference control
signal
A-D control register 0
A-D successive conversion
register
Vref
VREF
Resistor
ladder
SW2
Comparison voltage
ON resistor
approx. 0.6kΩ
A-D conversion
interrupt request
AVss
Comparison reference voltage (Vref) generator
Sampling
Comparison
SW1 conducts only on the ports selected for analog input.
Connect to
Control signal
for SW2
Connect to
SW2 and SW3 are open when A-D conversion is not in
progress; their status varies as shown by the waveforms in
the diagrams on the left.
Connect to
SW4 conducts only when A-D conversion is not in progress.
Control signal
for SW3
Connect to
Warning: Use only as a standard for designing this data.
Mass production may cause some changes in device characteristics.
Figure 2.8.22. Internal equivalent circuit to analog input
349
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.8.12 Sensor’s Output Impedance under A-D Conversion
To carry out A-D conversion properly, charging the internal capacitor C shown in Figure 2.8.23 has to be
completed within a specified period of time. With T as the specified time, time T is the time that switches
SW2 and SW3 are connected to O in Figure 2.8.22. Let output impedance of sensor equivalent circuit be
R0, microcomputer’s internal resistance be R, precision (error) of the A-D converter be X, and the A-D
converter’s resolution be Y.
–
Vc is generally VC = VIN {1 – e
And when t = T,
VC=VIN –
e
–
t
C (R0 + R)
X
X
VIN=VIN(1 –
)
Y
Y
T
C (R0 + R)
=
T
=ln
C (R0 +R)
T
–R
X
C • ln
Y
–
Hence, R0 = –
}
X
Y
X
Y
Each value is R = 7.8 kΩ, C = 3 pF, T = 0.3 us in the A-D conversion mode with sample & hold. For
example, when the A-D converter’s resolution is 10 bits and precision (error) of the A-D converter is 0.1
LSB, Y = 10, X = 0.1LSB. Hence,
0.3 X 10-6
R0 = –
3.0 X 10
–12
• ln
0.1
–7.8 X103
3.0 X 103
1024
Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A-D converter turns out to be approximately 3.0 kΩ. Tables 2.8.11 and 2.8.12 show output impedance values
based on the LSB values.
Microprocessor's inside
Sensor-equivalent circuit
R0
VIN
R (7.8kW)
C (3.0pF)
VC
Figure 2.8.23 A circuit equivalent to the A-D conversion terminal
350
Mitsubishi microcomputers
M30218 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 2.8.11. Output impedance values based on the LSB values (1)
f(XIN)
(MHz)
Cycle
(µs)
Sampling time
(µs)
10
0.1
10
0.1
R (kohm)
C (pF)
0.3
(3 ✕ cycle, sample &
hold bit is enabled)
7.8
3.0
0.2
(2 ✕ cycle, sample &
hold bit is disabled)
7.8
3.0
Accuracy
(LSB)
R0 (kohm)
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
3.0
4.5
5.3
5.9
6.4
6.8
7.2
7.5
7.8
8.1
0.4
0.9
1.3
1.7
2.0
2.2
2.4
2.6
2.8
Accuracy
(LSB)
R0 (kohm)
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
4.9
7.0
8.2
9.1
9.9
10.5
11.1
11.7
12.1
12.6
0.7
2.1
2.9
3.5
4.0
4.4
4.8
5.2
5.5
5.8
Table 2.8.12. Output impedance values based on the LSB values (2)
f(XIN)
(MHz)
Cycle
(µs)
Sampling time
(µs)
10
0.1
10
0.1
R (kohm)
C (pF)
0.3
(3 ✕ cycle, sample &
hold bit is enabled)
7.8
3.0
0.2
(2 ✕ cycle, sample &
hold bit is disabled)
7.8
3.0
351
Mitsubishi microcomputers
M30218 Group
D-A Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.9 D-A Converter
2.9.1 Overview
The D-A converter used in the M30218 group is based on the 8-bit R-2R technique.
(1) Output voltage
The D-A converter outputs voltage within a range from 0 V to VREF. The output voltage is determined
by VREF/(256) X the D-A register contents.
The D-A converter is not effected by the Vref connection bit of the A-D converter.
(2) Conversion time
tsu = 3 µs
(3) Output from the D-A converter and the direction register
To use the D-A converter, do not set the direction register of the relevant port to output.
(4) Pins related to the D-A converter
• DA0 pin, DA1 pin
Output pins of the D-A converter
• AVcc pin
The power source pin of the analog section
• VREF pin
Input pin of the reference voltage
• AVss pin
The GND pin of the analog section
(5) Registers related to the D-A converter
Figure 2.9.1 shows the memory map of D-A converter-related registers, and Figure 2.9.2 shows D-A
converter-related registers.
(6) Note
D-A output pins shared with P97 and P96. The two pins are input ports and floating at the reset.
03D816
D-A register 0 (DA0)
03D916
03DA16
D-A register 1 (DA1)
03DB16
03DC16
D-A control register (DACON)
Figure 2.9.1. Memory map of D-A converter-related registers
D-A control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DACON
Address
03DC16
Bit symbol
When reset
0016
Bit name
Function
DA0E
D-A0 output enable bit
0 : Output disabled
1 : Output enabled
DA1E
D-A1 output enable bit
0 : Output disabled
1 : Output enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
D-A register
b7
b0
Symbol
DAi (i = 0,1)
Address
03D816, 03DA16
Function
Output value of D-A conversion
Figure 2.9.2. D-A converter-related registers
352
When reset
Indeterminate
R
RW
W
Mitsubishi microcomputers
M30218 Group
D-A Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.9.2 D-A Converter Operation
The following is the D-A converter operation. Figure 2.9.3 shows the set-up procedure.
Operation (1) Writing a value to the D-A register i starts D-A conversion.
(2) Setting the D-Ai output enable bit to “1” outputs an analog signal on the DAi pin.
(3) The D-A converter continues outputting an analog signal until the D-A output enable bit is set
to “0”.
Setting D-A register
b7
b0
D-A register 0 [Address 03D816] DA0
D-A register 1 [Address 03DA16] DA1
Output value of D-A conversion
Setting D-A control register
b7
b0
D-A Control register [Address 03DC16]
DACON
D-A0 output enable bit
1 : Output enabled
D-A1 output enable bit
1 : Output enabled
Figure 2.9.3. Set-up procedure of D-A converter
353
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.10 DMAC
2.10.1 Overview
DMAC transfers one data item held in the source address to the destination address every time a transfer
request is generated. The following is a DMAC overview.
(1) Source address and destination address
Both the register which indicates a source and the register which indicates a destination comprise of
24 bits, so that each can cover a 1M bytes space. After transfer of one bit of data is completed, the
address in either the source register or the destination register can be incremented. However, both
registers cannot be incremented. The links between the source and destination are as follows:
(a) A fixed address from an arbitrary 1M bytes space
(b) An arbitrary 1M bytes space from a fixed address
(c) A fixed address from another fixed address
(2) The number of bits of data transferred
The number of bit of data indicated by the transfer counter is transferred. If a 16-bit transfer is selected, up to 128 K bytes can be transferred. If an 8-bit transfer is selected, up to 64K bytes can be
transferred. The transfer counter is decremented each time one bit of data is transferred, and a DMA
interrupt occurs when the transfer counter underflows.
(3) DMA transfer factor
________ ________
The DMA transfer factor can be selected from the following 15 factors: falling edge of INT0/INT1 pin,
timer A0 interrupt request through timer A4 interrupt request, timer B0 interrupt request through timer
B2 interrupt request, UART0 transmission interrupt request, UART0 reception interrupt request,
UART1 transmission interrupt request, UART1 reception interrupt request, A-D conversion interrupt
request, and software trigger.
When software trigger is selected, DMA transfer is generated by writing “1” to software DMA interrupt
request bit. When other factor is selected, DMA transfer is generated by generating corresponding
interrupt request.
(4) Channel priority
If DMA0 transfer request and DMA1 transfer request occur simultaneously, priority is given to DMA0.
(5) Writing to a register
When writing to the source register or the destination register with DMA enabled, the content of the
register with a fixed address will change at the time of writing. Therefore, the user should not write to
a register with a fixed address when the DMA enable bit is set to “1”. The contents of the register with
‘forward direction’ selected, and the transfer counter, are changed when reloaded. A reload occurs
either when the transfer counter underflows, or when the DMA enable bit is re-enabled, after having
been disabled.
The reload register can be written to, as in normal conditions.
(6) Reading to a register
The reload register can be read to, as in normal conditions.
354
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(7) Switching function
(a) Switching between one-shot transfer and repeated transfer
'One-shot transfer' refers to a mode in which DMA is disabled after the transfer counter underflows.
'Repeated transfer' refers to a mode in which a reload is carried out after the transfer counter
underflows. The reload is carried out for the transfer counter and on the address pointer subjected to
forward direction.
The following are examples of operation in which the options listed are selected.
• A fixed address from an arbitrary 1M byte space, one-shot transfer ........................................ P358
• An arbitrary 1M byte space from a fixed address, repeated transfer ........................................ P360
(8) Registers related to DMAC
Figure 2.10.1 shows the memory map of DMAC-related registers, and Figures 2.10.2 and 2.10.3 show
DMAC-related registers.
002016
002116
DMA0 source pointer (SAR0)
002216
002316
002416
002516
DMA0 destination pointer (DAR0)
002616
002716
002816
DMA0 transfer counter (TCR0)
002916
002C15
DMA0 control register (DM0CON)
003016
003116
DMA1 source pointer (SAR1)
003216
003316
003416
003516
DMA1 destination pointer (DAR1)
003616
003716
003816
003916
DMA1 transfer counter (TCR1)
003C16
DMA1 control register (DM1CON)
004B16
DMA0 interrupt control register (DM0IC)
004C16
DMA1 interrupt control register (DM1IC)
03B816
DMA0 cause select register (DM0SL)
03B916
03BA16
DMA1 cause select register (DM1SL)
Figure 2.10.1. Memory map of DMAC-related registers
355
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DMiSL(i=0,1)
Function
Bit name
Bit symbol
DSEL0
When reset
0016
Address
03B816,03BA16
DMA request cause
select bit
DSEL1
DSEL2
DSEL3
R
W
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT0 / INT1
pin (Note)
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4
0 1 1 1 : Timer B0
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART1 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : A-D conversion
1 1 1 1 : Inhibited
Nothing is assigned. In an attempt to write to these bits, write “0”.
The value, if read, turns out to be “0”.
DSR
Software DMA request bit
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
Note: Address 03B816 is for INT0; address 03BA16 is for INT1.
DMAi control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DMiCON(i=0,1)
Address
002C16, 003C16
When reset
00000X002
Function
Bit name
Bit symbol
DMBIT
Transfer unit bit select bit
0 : 16 bits
1 : 8 bits
DMASL
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMAS
DMA request bit (Note 1)
0 : DMA not requested
1 : DMA requested
DMA enable bit
0 : Disabled
1 : Enabled
DMAE
DSD
Source address direction
0 : Fixed
select bit (Note 3) 1 : Forward
DAD
Destination address
0 : Fixed
direction select bit (Note 3) 1 : Forward
W
R
(Note 2)
Nothing is assigned. In an attempt to write to these bits, write “0”.
The value, if read, turns out to be “0”.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
Figure 2.10.2. DMAC-related registers (1)
356
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi source pointer (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
Transfer count
specification
Function
• Source pointer
Stores the source address
When reset
Indeterminate
Indeterminate
AA
R W
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi destination pointer (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
Transfer count
specification
Function
• Destination pointer
Stores the destination address
When reset
Indeterminate
Indeterminate
AA
R W
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
Function
• Transfer counter
Set a value one less than the transfer count
Figure 2.10.3. DMAC-related registers (2)
357
When reset
Indeterminate
Indeterminate
Transfer count
specification
AA
000016 to FFFF16
R W
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.10.2 Operation of DMAC (one-shot transfer mode)
In one-shot transfer mode, choose functions from the items shown in Table 2.10.1. Operations of the
circled items are described below. Figure 2.10.4 shows an example of operation and Figure 2.10.5
shows the set-up procedure.
Table 2.10.1. Choosed functions
Item
Transfer space
Set-up
O
Fixed address from an arbitrary 1 M bytes space
Arbitrary 1 M bytes space from a fixed address
Fixed address from fixed address
Unit of transfer
O
8 bits
16 bits
Operation (1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA
transfer request signal.
(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi
forward-direction address pointer are transferred to the address indicated by the DMAi destination pointer. When data transfer starts directly after DMAC becomes active, the value of
the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the
value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.
Each time a DMA transfer request signal is generated, 1 byte of data is transferred. The
DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up
counted.
(3) If the DMA transfer counter underflows, the DMA enable bit changes to “0” and DMA transfer
is completed. The DMA interrupt request bit changes to “1” simultaneously.
(1) Request signal for a DMA transfer occurs
(2) Data transfer begins
(3) Underflow
BCLK
Destination
Destination
Address bus
CPU use
Dummy
cycle
Source
CPU use
Source
Dummy
cycle
CPU use
RD signal
WR signal
Destination
Data bus
CPU use
Source
Destination
Dummy
cycle
CPU use
Source
Dummy
cycle
CPU use
Write signal to
software DMAi
request bit
DMAi
request bit
DMA transfer
counter
DMAi
interrupt
request bit
Indeterminate
0016
FF16
0116
Cleared to “0” when interrupt request is
accepted, or cleared by software
DMAi
enable bit
• In the case in which the number of transfer times is set to 2.
Figure 2.10.4. Example of operation of one-shot transfer mode
358
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting DMAi request cause select register
b7
b0
0
0
0
0
DMAi request cause select register (i = 0, 1) [Address 03B816, 03BA16]
DMiSL(i = 0, 1)
1
DMA request cause select bit
b3 b2 b1 b0
0 0 0 1 : Software trigger
Software DMA request bit
Set to “0”
Setting DMAi control register
b7
b0
0 1
0 0
0
DMAi control register (i = 0, 1) [Address 002C16, 003C16]
DMiCON(i = 0, 1)
1
Transfer unit bit select bit
1 : 8 bits
Repeat transfer mode select bit
0 : Single transfer
DMA request bit
0 : DMA not requested
DMA enable bit
0 : Disabled
Source address direction select bit
1 : Forward (Bit 4 and bit 5 cannot be set to “1” simultaneously)
Destination address direction select bit
0 : Fixed (Bit 4 and bit 5 cannot be set to “1” simultaneously)
Setting DMAi source pointer
(b23)
b7
(b19)
b3
DMA0 source pointer [Address 002216 to 002016] SAR0
DMA1 source pointer [Address 003216 to 003016] SAR1
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Source pointer
Stores the source address
Setting DMAi destination pointer
(b23)
b7
(b19)
b3
DMA0 destination pointer [Address 002616 to 002416] DAR0
DMA1 destination pointer [Address 003616 to 003416] DAR1
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Destination pointer
Stores the destination address
Setting DMAi transfer counter
(b15)
b0
(b8)
b0 b7
b0
DMA0 transfer counter [Address 002916, 002816] TCR0
DMA1 transfer counter [Address 003916, 003816] TCR1
Transfer counter
Set a value one less than the transfer count
Setting DMAi control register
b7
b0
1
DMAi control register (i = 0, 1) [Address 002C16, 003C16]
DMiCON(i = 0, 1)
DMA enable bit
1 : Enabled
Note: Clear DMA request bit simultaneously again.
When software DMA request bit = “1”
Start DMA transmission
Figure 2.10.5. Set-up procedure of one-shot transfer mode
359
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.10.3 Operation of DMAC (repeated transfer mode)
In repeat transfer mode, choose functions from the items shown in Table 2.10.2. Operations of the circled
items are described below. Figure 2.10.6 shows an example of operation and Figure 2.10.7 shows the
set-up procedure.
Table 2.10.2. Choosed functions
Item
Set-up
Transfer space
Fixed address from an arbitrary 1 M bytes space
O
Arbitrary 1 M bytes space from a fixed address
Fixed address from fixed address
Unit of transfer
8 bits
O
16 bits
Operation (1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA
transfer request signal.
(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi
forward-direction address pointer are transferred to the address indicated by the DMAi destination pointer. When data transfer starts directly after DMAC becomes active, the value of
the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the
value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.
Each time a DMA transfer request signal is generated, 2 byte of data is transferred. The
DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up
counted.
(3) Though DMAi transfer counter is underflowed, DMA enable bit is still “1”. The DMA interrupt
request bit changes to “1” simultaneously.
(4) After DMAi transfer counter is underflowed, when the next DMA request is generated, DMA
transfer is repeated from (1).
(1) Request signal for a DMA transfer occurs
(2) Data transfer begins
(3) Underflow
BCLK
Destination
Address bus
CPU use
Dummy cycle
Destination
CPU use
Source
Dummy cycle
Source
Destination
CPU use
Source
Dummy cycle
CPU use
RD signal
WR signal
Destination
Data bus
CPU use
Destination
Dummy cycle
Source
CPU use
Dummy cycle
Source
CPU use
Destination
Source
Dummy cycle
CPU use
Write signal to
software DMAi
request bit
DMAi
request bit
0116
DMA transfer
counter
DMAi
interrupt
request bit
DMAi
enable bit
0116
Indeterminate
0016
FF16
Cleared to “0” when interrupt request is accepted, or cleared by software
“1”
• In the case in which the number of transfer times is set to 2.
Figure 2.10.6. Example of operation of repeated transfer mode
360
0016
Mitsubishi microcomputers
M30218 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting DMAi request cause select register
b7
b0
0
0
0
0
DMAi request cause select register (i = 0, 1) [Address 03B8
DMiSL(i = 0, 1)
1
16,
03BA 16]
DMA request cause select bit
b3 b2 b1 b0
0 0 0 1 : Software trigger
Software DMA request bit
Set to “0”
Setting DMAi control register
b7
b0
1 0
0
0
1
DMAi control register (i = 0, 1) [Address 002C 16, 003C 16]
DMiCON(i = 0, 1)
0
Transfer unit bit select bit
0 : 16 bits
Repeat transfer mode select bit
1 : Repeat transfer
DMA request bit
0 : DMA not requested
DMA enable bit
0 : Disabled
Source address direction select bit
0 : Fixed (Bit 4 and bit 5 cannot be set to “1” simultaneously)
Destination address direction select bit
1 : Forward (Bit 4 and bit 5 cannot be set to “1” simultaneously)
Setting DMAi source pointer
(b23)
b7
(b19)
b3
DMA0 source pointer [Address 0022 16 to 0020 16] SAR0
DMA1 source pointer [Address 0032 16 to 0030 16] SAR1
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Source pointer
Stores the source address
Setting DMAi destination pointer
(b23)
b7
(b19)
b3
DMA0 destination pointer [Address 0026 16 to 0024 16] DAR0
DMA1 destination pointer [Address 0036 16 to 0034 16] DAR1
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Destination pointer
Stores the destination address
Setting DMAi transfer counter
(b8)
b0 b7
(b15)
b0
b0
DMA0 transfer counter [Address 0029 16, 0028 16] TCR0
DMA1 transfer counter [Address 0039 16, 0038 16] TCR1
Transfer counter
Set a value one less than the transfer count
Setting DMAi control register
b7
b0
1
DMAi control register (i = 0, 1) [Address 002C 16, 003C 16]
DMiCON(i = 0, 1)
DMA enable bit
1 : Enabled
Note: Clear DMA request bit simultaneously again.
When software DMA request bit = “1”
Start DMA transmission
Figure 2.10.7. Set-up procedure of repeated transfer mode
361
Mitsubishi microcomputers
M30218 Group
CRC Calculation Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.11 CRC Calculation Circuit
2.11.1 Overview
Cyclic Redundancy Check (CRC) is a method that compares CRC code formed from transmission data
by use of a polynomial generation with CRC check data so as to detect errors in transmission data. Using
the CRC calculation circuit allows generation of CRC code. A polynomial counter is used for the polynomial generation.
(1) Registers related to CRC calculation circuit
Figure 2.11.1 shows the memory map of CRC-related registers, and Figure 2.11.2 shows CRC- related registers.
03BC16
03BD16
03BE16
CRC data register (CRCD)
CRC input register (CRCIN)
Figure 2.11.1. Memory map of CRC-related registers
CRC data register
(b15)
b7
(b8)
b0 b7
b0
Symbol
CRCD
Address
03BD16, 03BC16
When reset
Indeterminate
Values that
can be set
Function
CRC calculation result output register
RW
000016 to FFFF16
CRC input register
b7
Symbo
CRCIN
b0
Function
Data input register
Address
03BE16
When reset
Indeterminate
Values that
can be set
0016 to FF16
Figure 2.11.2. CRC-related registers
362
RW
Mitsubishi microcomputers
M30218 Group
CRC Calculation Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.11.2 Operation of CRC Calculation Circuit
The following describes the operation of the CRC calculation. Figure 2.11.3 shows an example of calculation data 012316 using the CRC calculation circuit.
Operation (1) The CRC calculation circuit sets an initial value in the CRC data register.
(2) Writing 1 byte data to the CRC input register generates CRC code based on the data register.
CRC code generation for 1 byte data finishes in two machine cycles.
(3) The CRC calculation circuit detects an error by means of comparing the CRC-checking data
with the content of the CRC data register, after the next data is written to the CRC input
register.
(4) The content of CRC data register after all data is written becomes CRC code.
b15
b0
CRC data register
(1) Setting 000016
b7
CRCD
[03BD16, 03BC16]
b0
CRC input register
(2) Setting 0116
CRCIN
[03BE16]
2 cycles
After CRC calculation is complete
b15
b0
CRC data register
118916
CRCD
[03BD16, 03BC16]
Stores CRC code
The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
(X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
LSB
MSB
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
1 0001 0000 0010 0001
9
1000 0000 0000
1000 1000 0001
1000 0001
1000 1000
1001
LSB
8
1
0000
0000
0000
0001
0001
0000
1
1000
0000
1000
0000
0+0=0
0+1=1
1+0=1
1+1=0
-1 = 1
0
1
1000
MSB
1
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
b7
b0
CRC input register
(3) Setting 2316
CRCIN
[03BE16]
After CRC calculation is complete
b15
b0
CRC data register
0A4116
CRCD
[03BD16, 03BC16]
Stores CRC code
Figure 2.11.3. Calculation example using the CRC calculation circuit
363
Mitsubishi microcomputers
M30218 Group
Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.12 Watchdog Timer
2.12.1 Overview
The watchdog timer can detect a runaway program using its 15-bit timer prescaler. The following is an
overview of the watchdog timer.
(1) Watchdog timer start procedure
When reset, the watchdog timer is in stopped state. Writing to the watchdog timer start register
initializes the watchdog timer to 7FFF16 and causes it to start performing a down count. The watchdog
timer, once started operating, cannot be stopped by any means other than stopping conditions.
(2) Watchdog timer stop conditions
The watchdog timer stops in any one of the following states:
(a) Period in which the CPU is in stopped state
(b) Period in which the CPU is in waiting state
(c) Period in which the microcomputer is in hold state
(3) Watchdog timer initialization
The watchdog timer is initialized to 7FFF16 in the cases given below, and begins a down count.
(a) When the watchdog timer writes to the watchdog timer start register while a count is in progress
(b) When the watchdog timer underflows
(4) Runaway detection
When the watchdog timer underflows, a watchdog timer interrupt occurs. In writing a program, write to
the watchdog timer start register before the watchdog timer underflows. The watchdog timer interrupt
occurs regardless of the status of the interrupt enable flag (I flag). In processing a watchdog timer
interrupt, set the software reset bit to “1” to reset software.
(5) Watchdog timer cycle
The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the
prescaler selected.
Table 2.12.1. The watchdog timer cycle
CM07
CM06
CM17
CM16
BCLK
0
0
0
0
10MHz
0
0
0
1
5MHz
0
0
0
0
1
1
0
1
2.5MHz
0.625MHz
0
1
Invalid
Invalid
1.25MHz
1
Invalid
Invalid
Invalid
32kHz
Note: An error due to the prescaler occurs.
364
WDC7
Period
0
Approx. 52.4ms (Note)
1
Approx. 419.4ms (Note)
0
Approx. 104.9ms (Note)
1
Approx. 838.9ms (Note)
0
Approx. 209.7ms (Note)
1
Approx. 1.68s (Note)
0
Approx. 838.9ms (Note)
1
Approx. 6.71s (Note)
0
Approx. 419.4ms (Note)
1
Approx. 3.36s (Note)
Invalid
Approx. 2s (Note)
Mitsubishi microcomputers
M30218 Group
Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(6) Registers related to the watchdog timer
Figure 2.12.1 shows the memory map of watchdog timer-related registers, and Figure 2.12.2 shows
watchdog timer-related registers.
000E16
Watchdog timer start register (WDTS)
000F16
Watchdog timer control register (WDC)
Figure 2.12.1. Memory map of watchdog timer-related registers
Watchdog timer control register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
WDC
Bit symbol
Address
000F16
When reset
000XXXXX2
Bit name
Function
High-order bit of watchdog timer
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “0”
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
AA
AA
A
AA
A
AA
A
R W
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of whatever value is written.
Figure 2.12.2. Watchdog timer-related registers
365
A
A
R W
Mitsubishi microcomputers
M30218 Group
Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.12.2 Operation of Watchdog Timer
The following is an operation of the watchdog timer. Figure 2.12.3 shows the operation timing, and Figure
2.12.4 shows the set-up procedure.
Operation (1) Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and
causes it to start a down count.
(2) With a count in progress, writing to the watchdog timer start register again initializes the
watchdog timer to 7FFF16 and causes it to resume counting.
(3) Either executing the WAIT instruction or going to the stopped state causes the watchdog
timer to hold the count in progress and to stop counting. The watchdog timer resumes counting after returning from the execution of the WAIT instruction or from the stopped state.
(4) If the watchdog timer underflows, it is initialized to 7FFF16 and continues counting. At this
time, a watchdog timer interrupt occurs.
(3) In stopped state, or WAIT
instruction is executing, etc
(2) Write operation
(1) Start count
7FFF16
000016
Write signal to the “H”
watchdog timer
start register
“L”
Figure 2.12.3. Operation timing of watchdog timer
366
(4) Generate
watchdog timer
interrupt
Mitsubishi microcomputers
M30218 Group
Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting watchdog timer control register
b7
b0
0 0
Watchdog timer control register [Address 000F16]
WDC
Reserved bit
Must always be “0”
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
Setting watchdog timer start register
b7
b0
Watchdog timer start register [Address 000E16]
WDTS
The watchdog timer is initialized and starts counting with a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of the value written.
Generating watchdog
timer interrupt
Software reset
b7
b0
1
Processor mode register 0 [Address 000416]
PM0
Software reset bit
The device is reset when this bit is set to “1”. The value of this bit
is “0” when read.
Figure 2.12.4. Set-up procedure of watchdog timer
367
Mitsubishi microcomputers
M30218 Group
Address Match Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.13 Address Match Interrupt
2.13.1 Overview
The address match interrupt is used for correcting a ROM or for a simplified debugging-purpose monitor.
The following is an overview of the address match interrupt.
(1) Enabling/disabling the address match interrupt
The address match interrupt enable bit can be used to enable and disable an address match interrupt.
It is affected neither by the processor interrupt priority level (IPL) nor the interrupt enable flag (I flag).
(2) Timing of the address match interrupt
An interrupt occurs immediately before executing the instruction in the address indicated by the address match interrupt register. Set the first address of the instruction in the address match interrupt
register. Setting a half address of an instruction or an address of tabulated data does not generate an
address match interrupt.
The first instruction of an interrupt routine does not generate an address match interrupt either.
(3) Returning from an address match interrupt
The return address put in the stack when an address match interrupt occurs depends on the instruction not yet executed (the instruction the address match interrupt register indicates). The return address is not put in the stack. For this reason, to return from an address match interrupt, either rewrite
the content of the stack and use the REIT instruction or use the POP instruction to restore the stack to
the state as it was before the interrupt occurred and return by use of a jump instruction.
Figure 2.13.1 shows unexecuted instructions and corresponding the stacked addresses.
<Instructions whose address is added to by 2 when an address match interrupt occurs>
• 16-bit operation code instructions
• 8-bit operation code instructions given below
ADD.B:S
OR.B:S
#IMM8,dest
#IMM8,dest
SUB.B:S
MOV.B:S
#IMM8,dest
#IMM8,dest
AND.B:S
STZ.B:S
STNZ.B:S
#IMM8,dest
STZX.B:S
#IMM81,#IMM82,dest
CMP.B:S
#IMM8,dest
PUSHM
src
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S
#IMM,dest (However, dest = A0/A1)
POPM
#IMM8,dest
#IMM8,dest
dest
<Instructions whose address is added to by 1 when an address match interrupt occurs>
• Instructions other than those listed above
Figure 2.13.1. Unexecuted instructions and corresponding stacked addresses
(4) How to determine an address match interrupt
Address match interrupts can be set at two different locations. However, both location will have the
same vector address. Therefore, it is necessary to determine which interrupt has occurred; address
match interrupt 0 or address match interrupt 1. Using the content of the stack, etc., determine which
interrupt has occurred according to the first part of the address match interrupt routine.
368
Mitsubishi microcomputers
M30218 Group
Address Match Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Registers related to the address match interrupt
Figure 2.13.2 shows the memory map of address match interrupt-related registers, and Figure 2.13.3
shows address match interrupt-related registers.
000916
Address match interrupt enable register (AIER)
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
Address match interrupt register 0 (RMAD0)
001216
001316
001416
001516
Address match interrupt register 1 (RMAD1)
001616
Figure 2.13.2. Memory map of address match interrupt-related registers
Address match interrupt enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER
Bit symbol
Address
000916
When reset
XXXXXX002
Bit name
Function
AIER0
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
Function
Address setting register for address match interrupt
When reset
X0000016
X0000016
Values that can be set R W
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Figure 2.13.3. Address match interrupt-related registers
369
Mitsubishi microcomputers
M30218 Group
Address Match Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.13.2 Operation of Address Match Interrupt
The following is an operation of address match interrupt. Figure 2.13.4 shows the set-up procedure of
address match interrupt, and Figure 2.13.5 shows the overview of the address match interrupt handling
routine.
Operation (1) The address match interrupt handling routine sets an address to be used to cause the address match interrupt register to generate an interrupt.
(2) Setting the address match enable flag to “1” enables an interrupt to occur.
(3) An address match interrupt occurs immediately before the instruction in the address indicated
by the address match interrupt register as a program is executed.
Setting address match interrupt register
Address match interrupt register 0 [Address 001216 to 001016]
RMAD0
Address match interrupt register 1 [Address 001616 to 001416]
RMAD1
(b23)
b7
(b20) (b19)
b4 b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Can be set to “0000016” to “FFFFF16”
Setting address match interrupt enable register
b7
b0
Address match interrupt enable register [Address 000916]
AIER
Address match interrupt 0 enable bit
1: Interrupt enabled
Address match interrupt 1 enable bit
1: Interrupt enabled
Figure 2.13.4. Set-up procedure of address match interrupt
370
Mitsubishi microcomputers
M30218 Group
Address Match Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address match interrupt routine
[1] Storing registers
[2] Determining the interrupt address
Address match 0?
No
Yes
Address match 0 program
Address match 1?
No
Yes
Address match 1 program
[3] Rewriting the stack
Restoring registers
REIT
Handling an error
Explanation:
[1] Storing the contents of the registers holding the main program status to be kept.
[2] Determining the interrupt address
Determining which factor generated the interrupt.
[3] Rewriting the stack
Rewriting the return address.
Figure 2.13.5. Overview of the address match interrupt handling routine
371
Mitsubishi microcomputers
M30218 Group
Power Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.14 Power Control
2.14.1 Overview
‘Power Control’ refers to the reduction of CPU power consumption by stopping the CPU and oscillators,
or decreasing the operation clock. The following is a description of the three available power control
modes:
(1) Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK
selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the BCLK selected. Each peripheral function operates
according to its assigned clock.
• Low-speed mode
fc becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the
secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fc
clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate
are those with the sub-clock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 2.14.1 shows the state transition diagram of the above modes.
372
Mitsubishi microcomputers
M30218 Group
Power Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transition of stop mode, wait mode
Reset
All oscillators stopped
Stop mode
CM10 = “1”
Interrupt
CM10 = “1”
Stop mode
Interrupt
CPU operation stopped
WAIT
instruction
High-speed/mediumspeed mode
Wait mode
Interrupt
All oscillators stopped
CM10 = “1”
Wait mode
Interrupt
All oscillators stopped Interrupt
Stop mode
CPU operation stopped
WAIT
instruction
Medium-speed mode
(divided-by-8 mode)
CPU operation stopped
WAIT
instruction
Low-speed/low power
dissipation mode
Wait mode
Interrupt
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
(divided-by-8 mode)
CM06 = “1”
BCLK : f(XIN)/8
CM07 = “0” CM06 = “1”
Main clock is oscillating CM04 = “0”
Sub clock is oscillating
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM04 = “1”
(Notes 1, 3)
High-speed mode
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-8 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/8
CM07 = “0”
CM06 = “1”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Main clock is oscillating
Sub clock is oscillating
Low-speed mode
CM07 = “0”
(Note 1, 3)
BCLK : f(XCIN)
CM07 = “1”
CM07 = “1”
(Note 2)
CM05 = “0”
CM04 = “0”
CM06 = “0”
(Notes 1,3)
Main clock is oscillating
Sub clock is stopped
CM05 = “1”
CM04 = “1”
High-speed mode
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Main clock is stopped
Sub clock is oscillating
Low power dissipation mode
CM07 = “1” (Note 2)
CM05 = “1”
CM07 = “1”
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
Figure 2.14.1. State transition diagram of power control mode
373
BCLK : f(XCIN)
Mitsubishi microcomputers
M30218 Group
Power Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Switching the driving capacity of the oscillation circuit
Both the main clock and the secondary clock have the ability to switch the driving capacity. Reducing
the driving capacity after the oscillation stabilizes allows for further reduction in power consumption.
(3) Clearing stop mode and wait mode
The stop mode and wait mode can be cleared by generating an interrupt request, or by resetting
hardware. Set the priority level of the interrupt to be used for clearing, higher than the processor
interrupt priority level (IPL), and enable the interrupt enable flag (I flag). When an interrupt clears a
mode, that interrupt is processed. Table 2.14.1 shows the interrupts that can be used for clearing a
stop mode and wait mode.
(4) BCLK in returning from wait mode or stop mode
(a) Returning from wait mode
The processor immediately returns to the BCLK, which was in use before entering wait mode.
(b) Returning from stop mode
CM06 is set to “1” when the device enters stop mode after selecting the main clock for BCLK. CM17,
CM16, and CM07 do not change state. In this case, when restored from stop mode, the device starts
operating in divided-by-8 mode.
When the device enters stop mode after selecting the subclock for BCLK, CM06, CM17, CM16, and
CM07 all do not change state. In this case, when restored from stop mode, the device starts operating in low-speed mode.
Table 2.14.1. Interrupts available for clearing stop mode and wait mode
Wait mode
Interrupt for clearing
Stop mode
CM02 = 0
CM02 = 1
DMA0 interrupt
Impossible
Impossible
Impossible
DMA1 interrupt
Impossible
Impossible
Impossible
Note 3
Impossible
Impossible
UART0 transmit interrupt
Possible
Note 1
Note 1
UART0 receive interrupt
Possible
Note 1
Note 1
UART1 transmit interrupt
Possible
Note 1
Note 1
UART1 receive interrupt
Possible
Note 1
Note 1
SI/O automatic transfer interrupt
Possible
Impossible
Impossible
FLD interrupt
Possible
Impossible
Impossible
Timer A0 interrupt
Possible
Note 2
Note 2
Timer A1 interrupt
Possible
Note 2
Note 2
Timer A2 interrupt
Possible
Note 2
Note 2
Timer A3 interrupt
Possible
Note 2
Note 2
Timer A4 interrupt
Possible
Note 2
Note 2
Timer B0 interrupt
Possible
Note 2
Note 2
Timer B1 interrupt
Possible
Note 2
Note 2
Timer B2 interrupt
Possible
Note 2
Note 2
INT0 interrupt
Possible
Possible
Possible
INT1 interrupt
Possible
Possible
Possible
INT2 interrupt
Possible
Possible
Possible
INT3 interrupt
Possible
Possible
Possible
INT4 interrupt
Possible
Possible
Possible
A-D interrupt
INT5 interrupt
Possible
Possible
Possible
Note 1: Can be used when an external clock in clock synchronous serial I/O mode is selected.
Note 2: Can be used when the external signal is being counted in event counter mode.
Note 3: Can be used in one-shot mode and one-shot sweep mode.
374
Mitsubishi microcomputers
M30218 Group
Power Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Sequence of returning from stop mode
Sequence of returning from stop mode is oscillation start-up time and interrupt sequence.
When interrupt is generated in stop mode, CM10 becomes “0” and clearing stop mode.
Starting oscillation and supplying BCLK execute the interrupt sequence as follow:
In the interrupt sequence, the processor carries out the following in sequence given:
(a) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. The interrupt request bit of the interrupt written in address 0000016 will
then be set to “0”.
(b) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
sequence in the temporary register (Note) within the CPU.
(c) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer assignment
flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software
interrupt numbers 32 through 63, is executed)
(d) Saves the content of the temporary register (Note) within the CPU in the stack area.
(e) Saves the content of the program counter (PC) in the stack area.
(f) Sets the interrupt priority level of the accepted instruction in the IPL.
Note: This register cannot be utilized by the user.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Figure 2.14.2 shows the sequence of returning from stop mode.
Writing “1” to CM10
(all clock stop control bit)
Operated by divided-by-8 mode
BCLK
Address
00000
Address bus
Interrupt
information
Data bus
Indeterminate
Indeterminate
SP-2
SP-4
vec
vec+2
SP-2
SP-4
vec
contents contents contents
PC
vec+2
contents
Indeterminate
RD
WR
INTi
Stop mode Oscillation start-up
Interrupt sequence approximately 20 cycle (16µ sec)
(Single-chip mode, f(XIN) = 10MHz)
Note: Shown above is the case where the main clock is selected for BCLK. If the sub-clock is selected for BCLK,
the sub-clock functions as BCLK when restored from stop mode, with the main clock's divide ratio
unchanged.
Figure 2.14.2. Sequence of returning from stop mode
(6) Registers related to power control
Figure 2.14.3 shows the memory map of power control-related registers, and Figure 2.14.4 shows
power control-related registers.
375
Mitsubishi microcomputers
M30218 Group
Power Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
000616
System clock control register 0 (CM0)
000716
System clock control register 1 (CM1)
Figure 2.14.3. Memory map of power control-related registers
System clock control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM0
Address
000616
Bit symbol
CM00
When reset
48 16
Bit name
Function
0 0 : I/O port P9 7/DA 0
0 1 : f C output
1 0 : f 8 output
1 1 : f 32 output
CM01
CM02
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
CM03
XCIN-XCOUT drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
Port X C select bit
0 : I/O port
1 : XCIN-XCOUT generation
CM05
Main clock (X IN-XOUT)
stop bit (Note 3, 4, 5)
0 : On
1 : Off
CM06
Main clock division select
bit 0 (Note 7)
0 : CM16 and CM17 valid
1 : Division by 8 mode
CM07
System clock select bit
(Note 6)
0 : XIN, XOUT
1 : XCIN, XCOUT
CM04
RW
b1 b0
Clock output function
select bit
Note 1: Set bit 0 of the protect register (address 000A 16) to “1” before writing to this register.
Note 2: Changes to “1” when shifting to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and
operating with X IN, set this bit to “0”. When main clock oscillation is operating by itself, set system clock select
bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, X OUT turns “H”. The built-in feedback resistor remains being connected, so X IN turns
pulled up to X OUT (“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the
main clock oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: f C32 is not included.
System clock control register 1 (Note 1)
b7
b6
b5
b4
b3
b2
b1
0
0
0
0
b0
Symbol
CM1
Address
000716
Bit symbol
CM10
When reset
20 16
Bit name
All clock stop control bit
(Note4)
Function
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
CM15
XIN-XOUT drive capacity
select bit (Note 2)
RW
0 : Clock on
1 : All clocks off (stop mode)
0 : LOW
1 : HIGH
b7 b6
CM16
Main clock division
select bit 1 (Note 3)
CM17
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A 16) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 0006 16) is “0”. If “1”, division mode is
fixed at 8.
Note 4: If this bit is set to “1”, X OUT turns “H”, and the built-in feedback resistor is cut off. X CIN and X COUT turn highimpedance state.
Figure 2.14.4. Power control-related registers
376
Mitsubishi microcomputers
M30218 Group
Power Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.14.2 Stop Mode Set-Up
Settings and operation for entering stop mode are described here.
Operation (1) Enables the interrupt used for returning from stop mode.
(2) Sets the interrupt enable flag (I flag) to “1”.
(3) Clearing the protection and setting every-clock stop bit to “1” stops oscillation and causes the
processor to go into stop mode.
(1) Setting interrupt to cancel stop mode
Interrupt control register
SiTIC(i=0, 1)
SiRIC(i=0, 1)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
b7
[Address 0051 16, 0053 16]
[Address 0052 16, 0054 16]
[Address 0055 16 to 0059 16]
[Address 005A 16 to 005C 16]
b0
INTiIC(i=0 to 2)
INTiIC(i=3 to 5)
b7
[Address 005D 16 to 005F 16]
[Address 0047 16 to 0049 16]
b0
0
Interrupt priority level select bit
Make sure that the interrupt priority
level of the interrupt which is used to
cancel the stop mode is higher than
the processor interrupt priority(IPL).
Interrupt priority level select bit
Make sure that the interrupt priority level of the
interrupt which is used to cancel the stop mode is
higher than the processor interrupt priority(IPL).
Reserved bit
Must be set to “0”
(2) Interrupt enable flag (I flag)
“1”
(3) Canceling protect
b7
b0
1
Protect register [Address 000A 16]
PRCR
Enables writing to system clock control registers 0 and 1
(addresses 0006 16 and 0007 16)
1 : Write-enabled
(3) Setting operation clock after returning from stop mode
(When operating with X IN after returning)
b7
0
b0
0
(When operating with X CIN after returning)
System clock control register 0
b7
[Address 0006 16] CM0
1
b0
1
System clock control register 0
[Address 0006 16] CM0
Main clock (X IN-XOUT) stop bit
On
Port X C select bit
XCIN-XCOUT generation
System clock select bit
XIN, XOUT
System clock select bit
XCIN, XCOUT
As this register becomes setting mentioned above when
operating with X IN (count source of BCLK is X IN),
the user does not need to set it again.
As this register becomes setting mentioned above when operating with X CIN
(count source of BCLK is X CIN), the user does not need to set it again.
When operating with X IN, set port Xc select bit to “1” before setting system clock
select bit to “1”. The both bits cannot be set at the same time.
(3) All clocks off (stop mode)
b7
b0
0
0
0
0
1
System clock control register 1 [Address 0007 16]
CM1
All clock stop control bit
1 : All clocks off (stop mode)
Reserved bit
Must be set to “0”
All clocks off (stop mode)
Figure 2.14.5. Example of stop mode set-up
377
Mitsubishi microcomputers
M30218 Group
Power Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.14.3 Wait Mode Set-Up
Settings and operation for entering wait mode are described here.
Operation (1) Enables the interrupt used for returning from wait mode.
(2) Sets the interrupt enable flag (I flag) to “1”.
(3) Clears the protection and changes the content of the system clock control register.
(4) Executes the WAIT instruction.
(1) Setting interrupt to cancel wait mode
Interrupt control register
ADIC
ASIOC
FLDIC
SiTIC(i=0, 1)
SiRIC(i=0, 1)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
b7
[Address 004E 16]
[Address 004F 16]
[Address 0050 16]
[Address 0051 16, 0053 16]
[Address 0052 16, 0054 16]
[Address 0055 16 to 0059 16]
[Address 005A 16 to 005C 16]
b0
INTiIC(i=0 to 2)
INTiIC(i=3 to 5)
b7
[Address 005D 16 to 005F 16]
[Address 0047 16 to 0049 16]
b0
0
Interrupt priority level select bit
Make sure that the interrupt priority
level of the interrupt which is used
to cancel the wait mode is higher
than the processor interrupt priority
(IPL) of the routine where the
WAIT instruction is executed.
(2) Interrupt enable flag (I flag)
Interrupt priority level select bit
Make sure that the interrupt priority level of the
interrupt which is used to cancel the wait mode is
higher than the processor interrupt priority (IPL) of
the routine where the WAIT instruction is executed.
Reserved bit
Must be set to “0”
“1”
(3) Canceling protect
b7
b0
1
Protect register [Address 000A 16]
PRCR
Enables writing to system clock control registers 0 and 1
(addresses 0006 16 and 0007 16)
1 : Write-enabled
(3) Control of CPU clock
b7
b0
0
0
0
0
System clock control register 1
[Address 0007 16] CM1
b7
Reserved bit
Must be set to “0”
b0
System clock control register 0
[Address 0006 16] CM0
WAIT peripheral function clock stop bit
0 : Do not stop f 1, f8, f 32 in wait mode
1 : Stop f 1, f8, f32 in wait mode
Main clock division select bit
b7 b6
Port X C select bit
0 : I/O port
1 : X CIN-XCOUT generation
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
Main clock (X IN-XOUT) stop bit
0 : On
1 : Off
Main clock division select bit 0
0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit (Note)
0 : X IN, XOUT
1 : X CIN, XCOUT
Note: When switching the system clock, it is necessary
to wait for the oscillation to stabilize.
(4) WAIT instruction
Wait mode
Figure 2.14.6. Example of wait mode set-up
378
Mitsubishi microcomputers
M30218 Group
Power Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.14.4 Precautions in Power Control
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until
main clock oscillation is stabilized.
(2) When switching to either wait mode or stop mode, instructions occupying four bytes either
from the WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within
the instruction queue are prefetched and then the program stops. So put at least four NOPs
in succession either to the WAIT instruction or to the instruction that sets the every-clock stop
bit to 1.
(3) Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to
which the count source is going to be switched must be oscillating stably. Allow a wait time in
software for the oscillation to stabilize before switching over the clock.
(4) Suggestions to reduce power consumption
• Ports
The processor retains the state of each programmable I/O port even when it goes to
wait mode or to stop mode. A current flows in active I/O ports. A pass current flows in
input ports that float. When entering wait mode or stop mode, set non-used ports to
input and stabilize the potential.
(a) A-D converter
A current always flows in the VREF pin. When entering wait mode or stop mode, set
the Vref connection bit to “0” so that no current flows into the VREF pin.
(b) D-A converter
The processor retains the D-A state even when entering wait mode or stop mode.
Disable the output from the D-A converter then work on the programmable I/O ports.
(c) Stopping peripheral functions
In wait mode, stop non-used wait peripheral functions using the peripheral function
clock stop bit.
(d) Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
(e) External clock
When using an external clock input for the CPU clock, set the main clock stop bit to
“1”. Setting the main clock stop bit to “1” causes the XOUT pin not to operate and the
power consumption goes down (when using an external clock input, the clock signal
is input regardless of the content of the main clock stop bit).
379
Mitsubishi microcomputers
M30218 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.15 Programmable I/O Ports
2.15.1 Overview
Forty-eight programmable I/O ports and forty high-breakdown-voltage output ports are available. I/O pins
also serve as I/O pins for built-in peripheral functions.
Each port has a direction register that defines the I/O direction and also has a port register for I/O data. In
addition, each port has a pull-up control register that defines pull-up in terms of 4 bits. Ports P2, P3, and
P40–P43 are high-breakdown-voltage P-channel open-drain output structure. These ports have no pullup resistance.
The following is an overview of the programmable I/O ports:
(1) Writing to a port register
With the direction register set to output, the level of the written values from each relevant pin is output
by writing to a port register. The output level conforms to CMOS output or P-channel open-drain
output. “L” level of port which is built-in pull-down resistor is apply voltage to the V EE pin. Writing to the
port register, with the direction register set to input, inputs a value to the port register, but nothing is
output to the relevant pins. The output level remains floating.
(2) Reading a port register
With the direction register set to output, reading a port register takes out the content of the port register, not the content of the pin. When the FLD controller is used, reading the port register takes out FLD
output. With the direction register set to input, reading the port register takes out the content of the pin.
(3) Exclusive high-breakdown-voltage output port
There are 40 exclusive output Ports: P0 to P2, P5 and P6.
All ports have structure of high-breakdown-voltage P-channel open drain output. Exclusive output
ports except P2 have built-in pull-down resistance.
(4) Setting pull-up
The pull-up control bit allows setting of the pull-up, in terms of 4 bits, either in use or not in use. For the
four bits chosen, pull-up is effective only in the ports whose direction register is set to input. Pull-up is
not effective in ports whose direction register is set to output.
Do not set pull-up of corresponding pin when XCIN/XCOUT is set or a port is used as A-D input.
380
Mitsubi shi microcomputers
M30218 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) I/O functions of built-in peripheral devices
Table 2.15.1 shows relation between ports and I/O functions of built-in peripheral devices.
Table 2.15.1. Relation between ports and I/O functions of built-in peripheral devices
Port
Internal peripheral device I/O pins
P0 to P3
FLD controller output pins
P40 to P4 3
FLD controller output pins
P44 to P4 7
FLD controller output pins/UART0 I/O pins
P5, P6
FLD controller output pins
P70 to P7 2
Timer B0 to B2 input pins
P73
Timer A0 I/O pin
P74 to P7 7
Timer A1 to A4 input pins/UART1 I/O pins
P80 to P8 5
External interrupt input pins
P86, P87
Sub-clock input pins
P90 to P9 5
I/O pins of serial I/O with automatic transfer function
P96
D-A converter output pin/Clock I/O pin of serial I/O with automatic transfer function
P97
D-A converter output pin/ X IN division clock output pin
/ DIM signal output pin of FLD controller
P100 to P10 7
A-D converter input pins
(6) Examples of working on non-used pins
Table 2.15.2 contains examples of working on non-used pins. There are shown here for mere examples. In practical use, make suitable changes and perform sufficient evaluation in compliance with
you application.
(a) Single-chip mode
Table 2.15.2. Examples of working on unused pins in single-chip mode
Pin name
Connection
Ports P3, P4, P7 to P10
After setting for input mode, connect every pin to V SS or VCC via a
resistor; or after setting for output mode, leave these pins open.
(Note 1)
Ports P0 to P2, P5, P6
Open
XOUT (Note 2), V EE
Open
AV SS, VREF
Connect to V SS
Note 1: If setting these pins in output mode and opening them, ports are in input mode until switched into
output mode by use of software after reset. Thus the voltage levels of the pins become unstable,
and there can be instances in which the power source current increases while the ports are in
input mode.
In view of an instance in which the contents of the direction registers change due to a runaway
generated by noise or other causes, setting the contents of the direction registers periodically by
use of software increases program reliability.
Note 2: When an external clock is input to the X IN pin.
381
Mitsubishi microcomputers
M30218 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(7) Registers related to the programmable I/O ports
Figure 2.15.1 shows the memory map of programmable I/O ports-related registers, and Figures
2.15.2 to 2.15.4 show programmable I/O ports-related registers.
035916
P2 FLD/port switch register (P2FPR)
035A16
P3 FLD/port switch register (P3FPR)
035B16
P4 FLD/port switch register (P4FPR)
035C16
P5 digit output set register (P5DOR)
035D16
P6 digit output set register (P6DOR)
03E016
Port P0 (P0)
03E116
Port P1 (P1)
03E216
03E316
03E416
Port P2 (P2)
03E516
Port P3 (P3)
03E616
03E716
Port P3 direction register (PD3)
03E816
Port P4 (P4)
03E916
Port P5 (P5)
03EA16
Port P4 direction register (PD4)
03EB16
03EC16
Port P6 (P6)
03ED16
Port P7 (P7)
03EE16
03EF16
Port P7 direction register (PD7)
03F016
Port P8 (P8)
03F116
Port P9 (P9)
03F216
Port P8 direction register (PD8)
03F316
Port P9 direction register (PD9)
03F416
Port P10 (P10)
03F516
03F616
Port P10 direction register (PD10)
03FC16
03FD16
Pull-up control register 0 (PUR0)
03FE16
Pull-up control register 1 (PUR1)
03FF16
Figure 2.15.1. Memory map of programmable I/O ports-related registers
382
Mitsubi shi microcomputers
M30218 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port Pi direction register
b7
b6
b5
b4
b3
b2
b1
Symbol
PDi (i = 3 to 10, except 5, 6)
b0
Bit symbol
Address
03E716, 03EA16, 03EF16
03F216, 03F316, 03F616
Bit name
When reset
0016
0016
Function
PDi_0
Port Pi0 direction register
PDi_1
Port Pi1 direction register
PDi_2
Port Pi2 direction register
PDi_3
Port Pi3 direction register
PDi_4
Port Pi4 direction register
PDi_5
Port Pi5 direction register
PDi_6
Port Pi6 direction register
PDi_7
Port Pi7 direction register
RW
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 3 to 10 except 5, 6)
Figure 2.15.2. Programmable I/O ports-related registers (1)
Port Pi register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Pi (i = 0 to 10)
Bit symbol
Addres
03E016, 03E116, 03E416, 03E516, 03E816
03E916, 03EC16, 03ED16, 03F016, 03F116, 03F416
Bit name
Pi_0
Port Pi0 register
Pi_1
Port Pi1 register
Pi_2
Port Pi2 register
Pi_3
Port Pi3 register
Pi_4
Port Pi4 register
Pi_5
Port Pi5 register
Pi_6
Port Pi6 register
Pi_7
Port Pi7 register
Function
Data is input and output to and from
each pin by reading and writing to and
from each corresponding bit
0 : “L” level data
1 : “H” level data
(i = 0 to 10)
Figure 2.15.3. Programmable I/O ports-related registers (2)
383
When reset
Indeterminate
Indeterminate
RW
Mitsubishi microcomputers
M30218 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR0
Bit symbol
Address
03FD16
Bit name
When reset
0016
Function
RW
Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if
read, turns out to be indeterminate.
PU01
P44 to P47 pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
PU06
P70 to P73 pull-up
PU07
P74 to P77 pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Pull-up control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR1
Bit symbol
Address
03FE16
Bit name
PU10
P80 to P83 pull-up
PU11
P84 to P87 pull-up
PU12
PU13
P90 to P93 pull-up
P94 to P97 pull-up
PU14
P100 to P103 pull-up
PU15
P104 to P107 pull-up
When reset
0016
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if
read, turns out to be indeterminate.
Figure 2.15.4. Programmable I/O ports-related registers (3)
384
R W
Chapter 3
Examples of Peripheral functions Applications
Mitsubishi microcomputers
M30218 Group
Applications
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This chapter presents applications in which peripheral functions built in the M30218 are used. They are
shown here as examples. In practical use, make suitable changes and perform sufficient evaluation. For
basic use, see Chapter 2 Peripheral Functions Usage.
Here follows the list of applications that appear in this chapter.
• 3.1 Long-period timers .............................................................................................................. P388
• 3.2 Variable-period variable-duty PWM output ......................................................................... P392
• 3.3 Delayed one-shot output .................................................................................................... P396
• 3.4 Buzzer output ..................................................................................................................... P400
• 3.5 Solution for external interrupt pins shortage ....................................................................... P402
• 3.6 Memory to memory DMA transfer ...................................................................................... P404
• 3.7 Controlling power using stop mode .................................................................................... P408
• 3.8 Controlling power using wait mode ..................................................................................... P412
386
Mitsubishi microcomputers
M30218 Group
Applications
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This page kept blank for layout purposes.
387
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3.1 Long-Period Timers
Overview In this process, Timer A0 and Timer A1 are connected to make a 16-bit timer with a 16-bit
prescaler. Figure 3.1.1 shows the operation timing, Figure 3.1.2 shows the connection diagram, and Figures 3.1.3 and 3.1.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer A
• Event counter mode of timer A
Specifications
(1) Set timer A0 to timer mode, and set timer A1 to event counter mode.
(2) Perform a count on count source f1 using timer A0 to count for 1 ms, and perform a count
on timer A0 using timer A1 to count for 1 second.
(3) Connect a 10-MHz oscillator to XIN.
Operation (1) Setting the count start flag to “1” causes the counter to begin counting. The counter of
timer A0 performs a down count on count source f1.
(2) If the counter of timer A0 underflows, the counter reloads the content of the reload register
and continues counting. At this time, the timer A0 interrupt request bit goes to “1”. The
counter of timer A1 performs a down count on underflows in timer A0.
(3) If the counter of timer A1 underflows, the counter reloads the content of the reload register
and continues counting. At this time, the timer A1 interrupt request bit goes to “1”.
Timer A0 counter
content (hex)
l = reload register content
FFFF16
(1) Start count (2) Timer A0 underflow
(3) Timer A1 underflow
l
Timer A1 counter
content (hex)
000016
Time
n = reload register content
FFFF16
Start count.
n
000016
Cleard “0” by software
Set to “1” by software
Timer A0 count
start flag
“1”
“0”
Timer A1 count
start flag
“1”
“0”
Time
Set to “1” by software
Timer A0 interrupt “1”
“0”
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer A1 interrupt “1”
request bit
“0”
Figure 3.1.1. Operation timing of long-period timers
388
Mitsubishi microcomputers
M30218 Group
Timer A Applications
f1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Used for timer mode
f8
f32
fC32
Timer A0
Timer A0 interrupt request bit
Timer A1
Timer A1 interrupt request bit
Used for event counter mode
Figure 3.1.2. Connection diagram of long-period timers
389
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting timer A0
Selecting timer mode and functions
b7
0
b0
0
0
0
0
0
0
0
Timer A0 mode register [Address 0396 16]
TA0MR
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TA0 OUT pin is a normal port pin)
Gate function select bit
b4 b3
0 0 : Gate function not available (TA0 IN pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
Count
source
Count source period
0
0
f1
f(XIN) : 10MH Z f(XcIN) : 32.768kH Z
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
0F16
2716
Timer A0 register [Address 0387 16, 0386 16]
TA0
Setting timer A1
Selecting event counter mode and each function
b7
0
b0
0
0
0
0
0
0
1
Timer A1 mode register [Address 0397 16]
TA1MR
Selection of event counter mode
Pulse output function select bit
0 : Pulse is not output (TA1 OUT pin is a normal port pin)
Count polarity select bit
Up/down switching cause select bit
0 : Up/down flag content
0 (Must always be “0” in event counter mode)
Count operation type select bit
0 : Reload type
Fix to “0” when counting timer overflow flag
Continued to the next page
Figure 3.1.3. Set-up procedure of long-period timers (1)
390
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Setting trigger select register
b7
b0
1
Trigger select register [Address 0383 16]
TRGSR
0
Timer A1 event/trigger select bit
b1 b0
1 0 : TA0 overflow is selected
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
E716
0316
Timer A1 register [Address 0389 16, 0388 16]
TA1
Setting count start flag
b7
b0
1
1
Count start flag [Address 0380 16]
TABSR
Timer A0 count start flag
1 : Starts counting
Timer A1 count start flag
1 : Starts counting
Start counting
Figure 3.1.4. Set-up procedure of long-period timers (2)
391
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3.2 Variable-Period Variable-Duty PWM Output
Overview In this process, Timer A0 and A1 are used to generate variable-period, variable-duty PWM output. Figure 3.2.1 shows the operation timing, Figure 3.2.2 shows the connection diagram, and
Figures 3.2.3 and 3.2.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer A
• One-shot timer mode of timer A
Specifications
(1) Set timer A0 in timer mode, and set timer A1 in one-shot timer mode with pulse-output function.
(2) Set 1 ms, the PWM period, to timer A0. Set 500 µs, the width of PWM “H” pulse, to timer A1.
Both timer A0 and timer A1 use f1 for the count source.
(3) Connect a 10-MHz oscillator to XIN.
Operation (1) Setting the count start flag to “1” causes the counter of timer A0 to begin counting. The
counter of timer A0 performs a down count on count source f1.
(2) If the counter of timer A0 underflows, the counter reloads the content of the reload register
and continues counting. At this time, the timer A0 interrupt request bit gose to “1”.
(3) An underflow in timer A0 triggers the counter of timer A1 and causes it to begin counting. When
the counter of timer A1 begins counting, the output level of the TA1OUT pin gose to “H”.
(4) As soon as the count of the counter of timer A1 becomes “000016”, the output level of TA1OUT
pin gose to “L”, and the counter reloads the content of the reload register and stops counting.
At the same time, the timer A1 interrupt request bit gose to “1”.
392
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
l = reload register content
(1) Timer A0 start count
Timer A0 counter
content (hex)
FFFF16
(2) Timer A0 underflow
l
000016
Time
Timer A1 counter
content (hex)
n = reload register content
FFFF16
(3) Timer A1 start count
(4) Timer A1 stop count
n
000116
Set to “1” by software
Timer A0 count
start flag
“1”
“0”
Timer A1 count
start flag
“1”
“0”
Time
Set to “1” by software
500µs
1ms
PWM pulse output “H”
from TA1OUT pin
“L”
Timer A0 interrupt “1”
request bit
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer A1 interrupt “1”
request bit
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 3.2.1. Operation timing of variable-period variable-duty PWM output
f1
Used for timer mode (Set to period)
f8
Timer A0
Timer A0 interrupt request bit
Timer A1
Timer A1 interrupt request bit
f32
fC32
Used for one-shot timer mode (Set to “H” width)
Figure 3.2.2. Connection diagram of variable-period variable-duty PWM output
393
AAA
AAA
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting timer A0
Selecting timer mode and functions
b7
0
b0
0
0
0
0
0
0
0
Timer A0 mode register [Address 0396 16 ]
TA0MR
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TA0 OUT pin is a normal port pin)
Gate function select bit
b4 b3
0 0 : Gate function not available (TA0 IN pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
Count source period
Count
source f(XIN) : 10MH Z f(XcIN) : 32.768kH Z
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
0F16
2716
Timer A0 register [Address 0387 16, 0386 16]
TA0
Setting timer A1
Selecting one-shot timer mode and functions
b7
0
b0
0
0
1
0
1
1
0
Timer A1 mode register [Address 0397 16 ]
TA1MR
Selection of one-shot timer mode
Pulse output function select bit
1 : Pulse is output
External trigger select bit (Invalid when choosing timer's overflow as trigger)
Trigger select bit
1 : Selected by event/trigger select register
0 (Must always be “0” in one-shot timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
Count source period
Count
source f(XIN) : 10MH Z f(XcIN) : 32.768kH Z
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Continued to the next page
Figure 3.2.3. Set-up procedure of variable-period variable-duty PWM output (1)
394
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Setting trigger select register
b7
b0
1
Trigger select register [Address 0383 16]
TRGSR
0
Timer A1 event/trigger select bit
b1 b0
1 0 : TA0 overflow is selected
Setting one-shot timer's time
(b15)
b7
(b8)
b0 b7
b0
8816
1316
Timer A1 register [Address 0389 16, 0388 16]
TA1
Setting count start flag
b7
b0
1
1
Count start flag [Address 0380 16]
TABSR
Timer A0 count start flag
1 : Starts counting
Timer A1 count start flag
1 : Starts counting
Start counting
Figure 3.2.4. Set-up procedure of variable-period variable-duty PWM output (2)
395
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3.3 Delayed One-Shot Output
Overview The following are steps of outputting a pulse only once after a specified elapse since an external
trigger is input. Figure 3.3.1 shows the operation timing, Figure 3.3.2 shows the connection diagram, and Figures 3.3.3 and 3.3.4 show the set-up procedure.
Use the following peripheral function:
• One-shot timer mode of timer A
Specifications
(1) Set timer A0 in one-shot timer mode, and set timer A1 in one-shot timer mode with pulseoutput function.
(2) Set 1 ms, an interval before a pulse is output, in timer A0; and set 50 µs, a pulse width, in timer
A1. Both timer A0 and timer A1 use f1 for the count source.
(3) Connect a 10-MHz oscillator to XIN.
Operation (1) Setting the trigger select bit to “1” and setting the count start flag to “1” enables the counter of
timer A0 to count.
(2) If an effective edge, selected by use of the external trigger select bit, is input to the TA0 IN pin,
the counter begins a down count. The counter of timer A0 performs a down count on count
source f1.
(3) As soon as the counter of timer A0 becomes “000016”, the counter reloads the content of the
reload register and stops counting. At this time, the timer A0 interrupt request bit gose to “1”.
(4) An underflow in timer A0 triggers the counter of timer A1 and causes it to begin counting.
When timer A1 begins counting, the output level of the TA1OUT pin gose to “H”.
(5) As soon as the counter of timer A1 becomes “000016”, the output level of the TA1OUT pin
gose to “L”, the counter reloads the content of the reload register, and stops counting. At this
time, timer A1 interrupt request bit gose to “1”.
396
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
l = reload register content
Timer A0 counter
content (hex)
(1) Count enabled
(2) Timer A0 start count
FFFF16
(3) Timer A0 stop count
l
Timer A1 counter
content (hex)
000116
Time
n = reload register content
(4) Timer A1 start count
FFFF16
(5) Timer A1 stop count
n
000116
Set to “1” by software
Timer A0 count
start flag
“1”
“0”
Timer A1 count
start flag
“1”
“0”
Input signal from
TA0IN pin
“H”
“L”
Time
Set to “1” by software
1ms
50µs
PWM pulse output “H”
from TA1OUT pin
“L”
Timer A0 interrupt “1”
“0”
request bit
Timer A1 interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 3.3.1. Operation timing of delayed one-shot output
TA0IN pin input
f1
f8
Used for one-shot timer mode
Timer A0
Timer A0 interrupt request bit
Timer A1
Timer A1 interrupt request bit
f32
fC32
Used for one-shot timer mode
Figure 3.3.2. Connection diagram of delayed one-shot output
397
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting timer A0
Selecting one-shot timer mode and functions
b7
0
b0
0
0
1
0
0
1
0
Timer A0 mode register [Address 0396 16]
TA0MR
Selection of one-shot timer mode
Pulse output function select bit
0 : Pulse is not output (TA0 OUT pin is normal port pin)
External trigger select bit
0 : Falling edge of TA0 IN pin's input signal
Trigger select bit
1 : Selected by event/trigger select register
0 (Must always be “0” in one-shot timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
Count source period
Count
source f(XIN) : 10MH Z f(XcIN) : 32.768kH Z
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Setting one-shot start flag
(Select TA0 IN pin to input TA0 trigger)
b7
b0
One-shot start flag [Address 0382 16]
ONSF
Timer A0 event/trigger select bit
b7 b6
0 0 : Input on TA0 IN is selected (Note)
Note: Set the corresponding port direction register to “0”.
Setting delay time
(b15)
b7
(b8)
b0 b7
2716
b0
Timer A0 register [Address 0387 16, 0386 16]
TA0
1016
Continued to the next page
Figure 3.3.3. Set-up procedure of delayed one-shot output (1)
398
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Setting timer A1
Selecting one-shot timer mode and functions
b7
0
b0
0
0
1
0
1
1
Timer A1 mode register [Address 0397 16]
TA1MR
0
Selection of one-shot timer mode
Pulse output function select bit
1 : Pulse is output (TA1 OUT pin is pulse output pin)
External trigger select bit
Invalid when choosing timer's overflow
Trigger select bit
1 : Selected by event/trigger select register
0 (Must always be “0” in one-shot timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
Count source period
Count
source f(XIN) : 10MHZ f(XcIN) : 32.768kH Z
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
3.2µs
976.56µs
Setting trigger select register
(Set timer A0 to trigger timer A1)
b7
b0
1
Trigger select register [Address 0383 16]
TRGSR
0
Timer A1 event/trigger select bit
b1 b0
1 0 : TA0 overflow is selected
Setting one-shot timer's time
(b15)
b7
(b8)
b0 b7
0116
b0
F416
Timer A1 register [Address 0389 16, 0388 16]
TA1
Setting count start flag
b7
b0
1
1
Count start flag [Address 0380 16]
TABSR
Timer A0 count start flag
1 : Starts counting
Timer A1 count start flag
1 : Starts counting
Start counting
Figure 3.3.4. Set-up procedure of delayed one-shot output (2)
399
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3.4 Buzzer Output
Overview The timer mode is used to make the buzzer ring. Figure 3.4.1 shows the operation timing, and
Figure 3.4.2 shows the set-up procedure.
Use the following peripheral function:
• The pulse-outputting function in timer mode of timer A.
Specifications
(1) Sound a 2-kHz buzz beep by use of timer A0.
(2) Effect pull-up in the relevant port by use of a pull-up resistor. When the buzzer is off, set the
port high-impedance, and stabilize the potential resulting from pulling up.
(3) Connect a 10-MHz oscillator to XIN.
Operation (1) The microcomputer begins performing a count on timer A0. Timer A0 has disabled interrupts.
(2) The microcomputer begins pulse output by setting the pulse output function select bit to
“Pulse output effected”. P75 changes into TA0OUT pin and outputs 2-kHz pulses.
(3) The microcomputer stops outputting pulses by setting the pulse output function select bit to
“Pulse output not effected”. P75 goes to an input pin, and the output from the pin becomes
high-impedance.
(1) Start count
(2) Buzzer output ON
(3) Buzzer output OFF
Timer A0
overflow timing
“1”
Count start flag
“0”
Pulse output
function select bit
“1”
“0”
“1”
P75 output
“0”
High-impedance
High-impedance
Figure 3.4.1. Operation timing of buzzer output
400
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Initialization of timer A0
b7
0 0
b0
0
0
0
0 0
Timer A0 mode register
TA0MR [Address 0396 16 ]
0
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TA0 OUT pin is a normal port pin)
Gate function select bit
b4 b3
0 0 : Gate function not available (TA0 IN pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
b15
b8
b7
0916
b7
b0
C416
Count source period
Count
source f(XIN) : 10MH Z f(XcIN) : 32.768kH Z
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
Timer A0 register
TA0 [Address 0387 16, 0386 16]
b0
b7
b0
1
Count start flag [Address 0380 16]
TABSR
Timer A0 count start flag
1 : Starts counting
Initialization of port P7 direction register
b7
b0
0
Port P7 direction register [Address 03EF 16]
PD7
Port P7 5 direction register
0 : Input mode
Buzzer ON
b7
b0
Timer A0 mode register [Address 0396 16 ]
TA0MR
1
Pulse output function select bit
1 : Pulse is output (Port P7 5 is TA0 OUT output pin)
Buzzer OFF
b7
b0
0
Timer A0 mode register [Address 0396 16 ]
TA0MR
Pulse output function select bit
0 : Pulse is not output
Figure 3.4.2. Set-up procedure of buzzer output
401
3.2µs
976.56µs
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3.5 Solution for External Interrupt Pins Shortage
Overview The following are solution for external interrupt pins shortage. Figure 3.5.1 shows the set-up
procedure.
Use the following peripheral function:
• Event counter mode of timer A
Specifications
(1) Inputting a falling edge to the TA0IN pin generates a timer A0 interrupt.
Operation (1) Set timer A0 to event counter mode, set timer to “0”, and set interrupt priority levels in timer A0.
(2) Inputting a falling edge to the TA0IN pin generates a timer A0 interrupt.
402
Mitsubishi microcomputers
M30218 Group
Timer A Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Initialization of timer A0
b7
b0
0
0
0
0
0
0
0
Timer A0 mode register
TA0MR [Address 0396 16 ]
1
Selection of event counter mode
Pulse output function select bit
0 : Pulse is not output (TA0 OUT pin is a normal port pin)
Count polarity select bit
0 : Counts external signal's falling edge
Up/down switching cause select bit
0 : Up/down flag's content
0 (Must always be “0” in event counter mode)
Count operation type select bit
0 : Reload type
0 (Must always be “0” in event counter mode)
b15
b8
b7
b0
0016
0016
b7
Timer A0 register
TA0 [Address 0387 16, 0386 16]
b0
b7
b0
0
Up/down flag [Address 0384 16]
UDF
Timer A0 up/down flag
0 : Down count
b7
b0
1
Count start flag [Address 0380 16]
TABSR
Timer A0 count start flag
1 : Starts counting
Setting interrupt priority levels in timer A0
b7
b0
Timer A0 interrupt control register [Address 0055 16]
TA0IC
Interrupt control level (set a value 1 to 7)
Initialization of port P7 direction register
b7
b0
0
Port P7 direction register [Address 03EF 16]
PD7
Port P7 3 direction register
0 : Input mode
Setting interrupt enable flag (I flag)
Figure 3.5.1. Set-up procedure of solution for a shortage of external interrupt pins
403
Mitsubishi microcomputers
M30218 Group
DMAC
Timer AApplications
Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3.6 Memory to Memory DMA Transfer
Overview The following are steps for changing both source address and destination address to transfer
data from memory to another. The DMA transfer utilizes the workings that assign a higher priority
to the DMA0 transfer if transfer requests simultaneously occur in two DMA channels. Figure
3.6.1 shows the operation timing, Figure 3.6.2 shows the block diagram, and Figures 3.6.3 and
3.6.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer A
• Two DMAC channels
• One-byte temporary RAM (address 080016)
Specifications
(1) Transfer the content of memory extending over 128 bytes from address F800016 to a 128byte area starting from address 0040016. Transfer the content every time a timer A0 interrupt
request occurs.
(2) Use DMA0 for a transfer from the source to built-in memory, and DMA1 for a transfer from
built-in memory to the destination.
Operation (1) A timer A interrupt request occurs. Though both a DMA0 transfer request and a DMA1 transfer request occur simultaneously, the former is executed first.
(2) DMA0 receives a transfer request and transfers data from the source to the built-in memory.
At this time, the source address is incremented.
(3) Next, DMA1 receives a transfer request and transfers data involved from built-in memory to
the destination. At this time, the destination address is incremented.
(3) Start DMA1 transferring
(1) Transfer request generation
(2) Start DMA0 transferring
Timer A0
transfer request
“1”
“0”
Source address
F800016
Address bus
Source address
080016
080016
Destination address
00400 16
Destination address
“1”
RD signal
“0”
“1”
WR signal
“0”
Instruction cycle
DMA0 operation
DMA1 operation
Note 1: The DMA0 operation and DMA1 operation are not necessarily executed in succession
due to the a cycle steal operation.
Note 2: The instruction cycle varies from instruction to instruction.
Note 3: Since the parts of the RD and WR signals shown in short-dash lines vary in step with
writing to the internal RAM, waveforms are not output to the RD and WR pins.
Figure 3.6.1. Operation timing of memory to memory DMA transfer
404
Mitsubishi microcomputers
M30218 Group
DMAC
Timer AApplications
Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Source area
Destination area
F8000 16
F8000 16 content
00400 16
F8001 16 content
F8002 16 content
Temporary RAM
F807F 16
80016
Data transfer by DMA0
Data transfer by DMA1
Figure 3.6.2. Block diagram of memory to memory DMA transfer
405
F807F 16 content
0047F 16
Mitsubishi microcomputers
M30218 Group
DMAC
Timer Aapplications
Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Initialization of DMA0
b7
b0
0
0
0
1
0
b7
DMA0 request cause select register
DM0SL [Address 03B8 16]
b0
0
1
1
0
1
1
DMA0 control register
DM0CON [Address 002C 16]
Transfer unit bit select bit
1 : 8 bits
DMA request cause select bit
b3 b2 b1 b0
0 0 1 0 : Timer A0
Repeat transfer mode select bit
1 : Repeat transfer
Software DMA request bit
0 : Software is not generated
DMA request bit
0 : DMA not requested
DMA enable bit
1 : Enabled
Source address direction select bit
1 : Forward
Destination address direction
select bit
0 : Fixed
b23
b16 b15
b8 b7
0F16
b7
8016
b0 b7
b23
DMA0 source pointer
SAR0
[Address 0022 16, 0021 16, 002016]
DMA0 destination
pointer
DAR0
[Address 0026 16, 0025 16, 002416]
DMA0 transfer counter
TCR0
[Address 0029 16, 0028 16]
b0
b16 b15
b8 b7
0016
b7
b0
0016
0816
b0 b7
b0
0016
b0
b15
b8 b7
0016
b7
b0
7F16
b0
Initialization of DMA1
b7
b0
0
0 0 1 0
DMA0 request cause select register
DM1SL [Address 03BA 16]
b7
b0
1 0 1 0 1 1
DMA1 control register
DM1CON [Address 003C 16]
Transfer unit bit select bit
1 : 8 bits
DMA request cause select bit
b3 b2 b1 b0
0 0 1 0 : Timer A0
Repeat transfer mode select bit
1 : Repeat transfer
Software DMA request bit
0 : Software is not generated
DMA request bit
0 : DMA not requested
DMA enable bit
1 : Enabled
Source address direction select bit
0 : Fixed
Destination address direction
select bit
1 : Forward
b23
b16 b15
0016
b7
b23
b0 b7
b16 b15
0016
b7
b8 b7
0816
b0
b8 b7
0416
b0 b7
b8 b7
0016
DMA1 source pointer
SAR1 [Address 0032 16, 0031 16, 003016]
DMA1 destination
pointer
DAR1 [Address 0036 16, 0035 16, 003416]
DMA1 transfer counter
TCR1
b0
0016
b0
b15
b7
b0
0016
b0
7F16
[Address 0039 16, 0038 16]
b0
Continued to the next page
Figure 3.6.3. Set-up procedure of memory to memory DMA transfer (1)
406
Mitsubishi microcomputers
M30218 Group
DMAC
Timer Aapplications
Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Initialization of timer A0
b7
0
b0
0
0
0
0
0
0
0
Timer A0 mode register
TA0MR [Address 039616 ]
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TA0OUT pin is a normal port pin)
Gate function select bit
b4 b3
0 0 : Gate function not available (TA0IN pin is a normal port pin)
0 (Must always be fixed to “0” in timer mode)
Count source select bit
b7 b6
b7 b6
0 0 : f1
b15
b8
2716
b7
b7
b7
Count source period
Count
source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
0
0
f1
100ns
0
1
f8
800ns
1
0
f32
1
1
fC32
b0
0F16
b0
Timer A0 register
TA0 [Address 0387, 038616 ]
b0
1
Count start flag [Address 038016]
TABSR
Timer A0 count start flag
1 : Starts counting
Figure 3.6.4. Set-up procedure of memory to memory DMA transfer (2)
407
3.2µs
976.56µs
Mitsubishi microcomputers
M30218 Group
Controlling Power Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3.7 Controlling Power Using Stop Mode
Overview
The following are steps for controlling power using stop mode. Figure 3.7.1 shows the operation
timing, Figure 3.7.2 shows an example of circuit, and Figures 3.7.3 and 3.7.4 show the set-up
procedure.
Use the following peripheral functions:
________
• INT5 interrupt
• Stop mode
Specifications
(1) Use INT5 for the INT interrupt. Use the P85/INT5 pin as an input pin.
________
(2) When a INT5 interrupt request occurs, the stop mode is cleared.
________
Operation (1) Enable INT5 interrupt and set the pull-up function to the P85 pin.
________
(2) Stop XIN to enter the stop mode. Enable INT5 interrupt at this time.
________
(3) When a INT5 interrupt request occurs by falling edge input to the P85 pin, the stop mode is
cleared. Execute the return processing for the other interrupts, which are stopped, in the
________
INT5 interrupt processing and others.
(1) Enter stop mode
(2) Clear stop mode
(3) Return processing
INT5 input
INT5 interrupt processing
CPU clock
Stop mode
Figure 3.7.1. Operation timing of controlling power using stop mode
408
Mitsubishi microcomputers
M30218 Group
Controlling Power Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VREF
I/O port
P85 / INT5
Key input
Figure 3.7.2. Example of circuit of controling power using stop mode
409
Mitsubishi microcomputers
M30218 Group
Controlling Power Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Main
Initial condition
b7
Pull-up control register 2
[Address 03FE 16]
PUR2
b0
1
b7
b0
0
0
0
0
1
P84 to P8 7 pulled high
b7
Interrupt priority level select bit
Set higher value than the present IPL
Port P8 direction register
[Address 03F2 16]
PD8
Set P85 to input port
b0
0
INT5 interrupt control register
[Address 0049 16]
INT5IC
Polarity select bit
0 : Selects falling edge
Reserved bit
Always set to “0”
Interrupt enable level (IPL) = 0
Interrupt enable flag (I) = 1
Setting interrupt except stop mode cancel
Interrupt control register DMiIC(i=0, 1)
ADIC
ASIOIC
FLDIC
SiTIC(i=0, 1)
SiRIC(i=0, 1)
b0
TAiIC(i=0 to 4)
0 0 TBiIC(i=0 to 2)
b7
0
[Address 004B 16, 004C 16]
[Address 004E 16]
[Address 004F 16]
[Address 0050 16]
[Address 0051 16, 0053 16]
[Address 0052 16, 0054 16]
[Address 0055 16 to 0059 16]
[Address 005A 16 to 005C 16]
b7
b0
0
0
0
0
Interrupt priority level select bit
000 : Interrupt disabled
INTiIC(i=0 to 4) [Address 0047 16 to 0048 16]
[Address 005D 16 to 005F 16]
Interrupt priority level select bit
000 : Interrupt disabled
Reserved bit
Always set to “0”
Canceling protect
b7
b0
1
Protect register [Address 000A 16]
PRCR
Enables writing to system clock control registers 0 and 1
(addresses 0006 16 and 0007 16)
1 : Write-enabled
Setting operation clock after returning from stop mode
(When operating with X IN after returning)
b7
b0
0
System clock control register 0
[Address 0006 16]
CM0
Main clock (X IN-XOUT) stop bit
On
0
(When operating with X CIN after returning)
b7
1
b0
1
System clock select bit
XIN, XOUT
As this register becomes setting mentioned above when
operating with X IN (count source of BCLK is X IN),
the user does not need to set it again.
System clock control register 0
[Address 0006 16]
CM0
Port X C select bit
XCIN-XCOUT generation
System clock select bit
XCIN, XCOUT
As this register becomes setting mentioned above when operating with X CIN
(count source of BCLK is X CIN), the user does not need to set it again.
When operating with X IN, set port Xc select bit to “1” before setting system
clock select bit to “1”. The both bits cannot be set at the same time.
All clocks off (stop mode)
b7
b0
0
0
0
0
1
System clock control register 1 [Address 0007 16]
CM1
All clock stop control bit
1 : All clocks off (stop mode)
Reserved bit
Always set to “0”
NOP instruction X 5
INT5 interrupt request generation
Figure 3.7.3. Set-up procedure of controlling power using stop mode (1)
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INT5 interrupt
Store the registers
Returning interrupt except stop mode cancel
Interrupt control register DMiIC(i=0, 1)
b7
b0
ADIC
ASIOIC
FLDIC
SiTIC(i=0, 1)
SiRIC(i=0, 1)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
[Address 004B 16, 004C16]
[Address 004E 16]
[Address 004F 16]
[Address 0050 16]
[Address 0051 16, 0053 16]
[Address 0052 16, 0054 16]
[Address 0055 16 to 0059 16]
[Address 005A 16 to 005C 16]
Interrupt priority level select bit
Set interrupt priority level of used interrupt to
these bits again
b7
b0
0
0
0
0
INTiIC(i=0 to 4)
[Address 0047 16 to 0048 16]
[Address 005D 16 to 005F 16]
Interrupt priority level select bit
Set interrupt priority level of used
interrupt to these bits again
Always set to “0”
Restore the registers
REIT instruction
Figure 3.7.4. Set-up procedure of controlling power using stop mode (2)
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3.8 Controling Power Using Wait Mode
Overview The following are steps for controling power using wait mode. Figure 3.8.1 shows the operation
timing, and Figures 3.8.2 to 3.8.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer B
• Wait mode
A flag named “F-WIT” is used in the set-up procedure. The purpose of this flag is to decide
whether or not to clear wait mode. If F_WIT = “1” in the main program, the wait mode is entered;
if F_WIT = “0”, the wait mode is cleared.
Specifications
(1) Connect a 32.768-kHz oscillator to XCIN to serve as the timer count source. As interrupts
occur every one second, which is a count the timer reaches, the controller returns from wait
mode and count the clock using a program.
________
(2) Clear wait mode if a INT0 interrupt request occurs.
Operation (1) Switch the system clock from XIN to XCIN to get low-speed mode.
_______
(2) Stop XIN and enter wait mode. In this instance, enable the timer B2 interrupt and the INT0 interrupt.
(3) When a timer B2 interrupt request occurs (at 1-second intervals), start supplying the BCLK
from XCIN.
At this time, count the clock within the routine that handles the timer B2 interrupts and enter
wait mode again.
_______
(4) If a INT0 interrupt occurs, start supplying the BCLK from X CIN. Start the XIN oscillation within
_______
the INT0 interrupt, and switch the BCLK count source to XIN after oscillation is stabilized.
(1) Shift to low-speed mode
(2) Stop XIN
(3) Timer B2 interrupt
(4) INT0 interrupt
XOUT
XCIN
Timer B overflow
Timer B2
interrupt processing
INT0
“H”
“L”
BCLK
High-speed
Low-speed
High-speed
Low-speed
Low-speed
Figure 3.8.1. Operation timing of controling power using wait mode
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Main
Initial condition
b7
b0
0
0
System clock control register 0 [Address 0006 16]
CM0
1
WAIT state internal clock stop bit
XCIN-XCOUT drive capacity select bit
Port Xc select bit
1 : Functions as X CIN-XCOUT oscillator
Main clock (X IN-XOUT) stop bit
0 : Oscillating
Main clock divide ratio select bit 0
System clock select bit
0 : X IN-XOUT
b7
1
b0
0
1
Timer B2 mode register [Address 039D 16]
TB2MR
0
Operation mode select bit
b1 b0
0 0 : Timer mode
Count source select bit
b7 b6
1 1 : f C32 (f(XCIN) divided by 32)
b15
b8
b7
b0
0316
Timer B2 register [Address 0395 16, 0394 16]
TB2
FF16
b7
b0
Clock prescaler reset flag [Address 0381 16]
CPSRF
1
Rrescaler is reset
b7
b0
Count start flag [Address 0380 16]
TABSR
1
TB2 start counting
b7
b0
0
0
0
0 1
b7
1
b0
0
Timer B2 interrupt control register [Address 005C 16]
TB2IC
TB2 interrupt priority level
INT0 interrupt control register [Address 005D 16]
INT0IC
INT0 interrupt priority level
Interrupt priority level (IPL) = 0
Interrupt enable flag (I) = 1
Setting interrupt except clearing wait mode
Interrupt control register
b7
b0
0
0
0
Interrupt priority level select bit
DMiIC (i = 0, 1)
ADIC
ASIOIC
FLDIC
SiTIC (i = 0, 1)
SiRIC (i = 0, 1)
TAiIC (i = 0 to 4)
TBiIC (i = 0 to 2)
INTiIC (i =1 to 5)
b2 b1 b0
[Address 004B 16, 004C 16]
[Address 004E 16]
[Address 004F 16]
[Address 0050 16]
[Address 0051 16, 0053 16]
[Address 0052 16, 0054 16]
[Address 0055 16 to 0059 16]
[Address 005A 16 to 005C 16]
[Address 0047 16 to 0049 16]
[Address 005E 16, 005F16]
0 0 0 : Interrupt disabled
Continued to the next page
Figure 3.8.2. Set-up procedure of controlling power using wait mode (1)
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Continued from the previous page
Canceling protect
b7
b0
Protect register [Address 000A 16]
PRCR
1
Enables writing to system clock control registers 0 and 1 (address 0006
1 : write-enabled
16
and 0007 16)
Switching system clock
b7
b0
System clock control register 0 [Address 0006 16]
CM0
1
System clock select bit
1 : X CIN-XCOUT
Stopping main clock
b7
b0
System clock control register 0 [Address 0006 16]
CM0
1
Main clock (X IN-XOUT) stop bit
1 : Off
[F_WIT] = 1
WAIT instruction
NOP instruction X 5
INT0 interrupt request generated
TB2 interrupt request generated
=
[F_WIT] : 1
≠
Starting main clock oscillator
b7
b0
System clock control register 0 [Address 0006 16]
CM0
0
Main clock (X IN-XOUT) stop bit
0 : On
Wait until the main clock has stabilized
Switching system clock
b7
0
b0
System clock control register 0 [Address 0006 16]
CM0
System clock select bit
0 : X IN-XOUT
Figure 3.8.3. Set-up procedure of controlling power using wait mode (2)
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INT0 interrupt
Timer B2 interrupt
Store the registers
Store the registers
[F_WIT] = 0
Counting clock
Restore the registers
Restore the registers
REIT instruction
REIT instruction
Figure 3.8.4. Set-up procedure of controlling power using wait mode (3)
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This page kept blank for layout purposes.
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Chapter 4
Interrupt
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Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
4.1 Overview of Interrupt
4.1.1 Type of Interrupts
Figure 4.1.1 lists the types of interrupts.
Hardware
Special
Peripheral I/O (Note)
Interrupt
Software
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
DBC
Watchdog timer
Single step
Address matched
________
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 4.1.1. Classification of interrupts
• Maskable interrupt :
• Non-maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
An interrupt which cannot be enabled (disabled) by the interrupt enable
flag (I flag) or whose interrupt priority cannot be changed by priority level.
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4.1.2 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing
the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts,
so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O
interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
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4.1.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
____________
Reset occurs if an “L” is input to the RESET pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs. For address match interrupt, see 2.13 Address match Interrupt.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• DMA0 interrupt, DMA1 interrupt
These are interrupts DMA generates.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0 and UART1 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt
These are interrupts that the serial I/O reception generates.
• SI/O automatic transfer interrupt
This is an interrupt that the SI/O automatic transfer generates.
• FLD interrupt
This is an interrupt that FLD generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates.
• Timer B0 interrupt through timer B2 interrupt
These are interrupts that timer B generates.
________
________
• INT0 interrupt through INT5 interrupt
______
______
An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.
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4.1.4 Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt
vector table. Set the first address of the interrupt routine in each vector table. Two types of interrupt
vector tables are available — fixed vector table in which addresses are fixed and variable vector
table in which addresses can be varied by the setting.
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 4.1.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 4.1.1. Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt source
Undefined instruction
Overflow
BRK instruction
Vector table addresses
Address (L) to address (H)
FFFDC16 to FFFDF16
FFFE016 to FFFE316
FFFE416 to FFFE716
Remarks
Interrupt on UND instruction
Interrupt on INTO instruction
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Address match
FFFE816 to FFFEB16
Single step (Note)
FFFEC16 to FFFEF16
Watchdog timer
FFFF016 to FFFF316
________
DBC (Note)
FFFF416 to FFFF716
Do not use
FFFF816 to FFFFB16
Reset
FFFFC16 to FFFFF16
Note: Interrupts used for debugging purposes only.
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• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 4.1.2 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
Table 4.1.2. Interrupts assigned to the variable vector tables and addresses of vector tables
Software interrupt number
Vector table address
Interrupt source
Remarks
Address (L) to address (H)
Software interrupt number 0
+0 to +3 (Note)
BRK instruction
Software interrupt number 7
+28 to +31 (Note)
INT3
Software interrupt number 8
+32 to +35 (Note)
INT4
Software interrupt number 9
+36 to +39 (Note)
INT5
Software interrupt number 11
+44 to +47 (Note)
DMA0
Software interrupt number 12
+48 to +51 (Note)
DMA1
Software interrupt number 14
+56 to +59 (Note)
A-D
Software interrupt number 15
+60 to +63 (Note)
SI/O automatic transfer
Software interrupt number 16
+64 to +67 (Note)
FLD
Software interrupt number 17
+68 to +71 (Note)
UART0 transmit
Software interrupt number 18
+72 to +75 (Note)
UART0 receive
Software interrupt number 19
+76 to +79 (Note)
UART1 transmit
Software interrupt number 20
+80 to +83 (Note)
UART1 receive
Software interrupt number 21
+84 to +87 (Note)
Timer A0
Software interrupt number 22
+88 to +91 (Note)
Timer A1
Software interrupt number 23
+92 to +95 (Note)
Timer A2
Software interrupt number 24
+96 to +99 (Note)
Timer A3
Software interrupt number 25
+100 to +103 (Note)
Timer A4
Software interrupt number 26
+104 to +107 (Note)
Timer B0
Software interrupt number 27
+108 to +111 (Note)
Timer B1
Software interrupt number 28
+112 to +115 (Note)
Timer B2
Software interrupt number 29
+116 to +119 (Note)
INT0
Software interrupt number 30
+120 to +123 (Note)
INT1
Software interrupt number 31
+124 to +127 (Note)
INT2
Software interrupt number 32
+128 to +131 (Note)
to
Software interrupt number 63
to
+252 to +255 (Note)
Software interrupt
Note : Address relative to address in interrupt table register (INTB).
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Cannot be masked I flag
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
4.2 Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level
selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is
indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit
are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the
IPL are located in the flag register (FLG).
Figure 4.2.1 shows the memory map of the interrupt control registers, and Figure 4.2.2 shows the interrupt
control registers.
004716
004816
004916
INT3 interrupt control register (INT3IC)
INT4 interrupt control register (INT4IC)
INT5 interrupt control register (INT5IC)
004A16
004B16
004C16
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
A-D conversion interrupt control register (ADIC)
SI/O2 transmit interrupt control register (ASIOIC)
FLD interrupt control register (FLDIC)
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control regster(S1TIC)
UART1 receive interrupt control register(S1RIC)
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
INT2 interrupt control register (INT2IC)
Figure 4.2.1. Memory map of the interrupt control registers
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Interrupt control register(Note2)
AAA
A
AA
AAA
AA
A
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DMiIC(i=0, 1)
ADIC
ASIOIC
FLDIC
SiTIC(i=0, 1)
SiRIC(i=0, 1)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
Bit symbol
ILVL0
Address
004B16 to 004C16
004E16
004F16
005016
005116, 005316
005216, 005416
005516 to 005916
005A16 to 005C16
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
When reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Interrupt request bit
Function
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
AAA
A
AA
b7 b6 b5 b4 b3 b2 b1 b0
0
AA
AA
AA
AA
R
W
(Note1)
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
Symbol
INTiIC(i=0 to 5)
Bit symbol
ILVL0
Address
005D16 to 005F16
004716 to 004916
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
POL
When reset
XX00X0002
Interrupt request bit
Polarity select bit
Function
b2 b1 b0
W
AA
AA
AA
AA
AA
A
A
AA
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
Reserved bit
R
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
(Note1)
Note1 : This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
Figure 4.2.2. Interrupt control registers
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4.2.1 Interrupt Enable Flag
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
The content is changed when the I flag is changed causes the acceptance of the interrupt request in the
following timing:
• When changing the I flag using the REIT instruction, the acceptance of the interrupt takes
effect as the REIT instruction is executed.
• When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, the
acceptance of the interrupt is effective as the next instruction is executed.
When changed by REIT instruction
Interrupt request generated
Determination whether or not to
accept interrupt request
Time
Previous
instruction
REIT
Interrupt sequence
(If I flag is changed from 0 to 1 by REIT instruction)
When changed by FCLR, FSET, POPC, or LDC instruction
Determination whether or not to
accept interrupt request
Interrupt request generated
Time
Previous
instruction
FSET I
Next instruction
Interrupt sequence
(If I flag is changed from 0 to 1 by FSET instruction)
Figure 4.2.3. The timing of reflecting the change in the I flag to the interrupt
4.2.2 Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
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4.2.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 4.2.1 shows the settings of interrupt priority levels and Table 4.2.2 shows the interrupt levels enabled, according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 4.2.1. Settings of interrupt priority levels
Interrupt priority
level select bit
Interrupt priority
level
Priority
order
Table 4.2.2. Interrupt levels enabled according
to the contents of the IPL
IPL
b2 b1 b0
Enabled interrupt priority levels
IPL2 IPL1 IPL0
0
0
0
Level 0 (interrupt disabled)
0
0
0
Interrupt levels 1 and above are enabled
0
0
1
Level 1
0
0
1
Interrupt levels 2 and above are enabled
0
1
0
Level 2
0
1
0
Interrupt levels 3 and above are enabled
0
1
1
Level 3
0
1
1
Interrupt levels 4 and above are enabled
1
0
0
Level 4
1
0
0
Interrupt levels 5 and above are enabled
1
0
1
Level 5
1
0
1
Interrupt levels 6 and above are enabled
1
1
0
Level 6
1
1
0
Interrupt levels 7 and above are enabled
1
1
1
Level 7
1
1
1
All maskable interrupts are disabled
Low
High
When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt in
the following timing:
• When changing the IPL using the REIT instruction, the reflection takes effect as of the instruction
that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction.
• When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes
effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the
instruction used.
• When changing the interrupt priority level using the MOV or similar instruction, the reflection takes
effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in
the instruction used.
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4.2.4 Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
;
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
;
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is
to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to
effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
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4.3 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note 1) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
4.3.1 Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 4.3.1 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
(a)
Interrupt sequence
Instruction in
interrupt routine
(b)
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the interrupt sequence is executed.
Figure 4.3.1. Interrupt response time
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Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 4.3.1.
Table 4.3.1. Time required for executing the interrupt sequence
Interrupt vector address
Stack pointer (SP) value
16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
18 cycles (Note 1)
20 cycles (Note 1)
Even
Odd
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Even
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Odd
20 cycles (Note 1)
20 cycles (Note 1)
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address bus
Data bus
R
Address
0000
Interrupt
information
Indeterminate
SP-2
Indeterminate
SP-2
contents
SP-4
SP-4
contents
vec
vec+2
vec
contents
PC
vec+2
contents
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 4.3.2. Time required for executing the interrupt sequence
4.3.2 Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 4.3.2 is set in the IPL.
Table 4.3.2. Relationship between interrupts without interrupt priority levels and IPL
Value set in the IPL
Interrupt sources without priority levels
Watchdog timer
7
Reset
0
Not changed
Other
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4.3.3 Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 4.3.3 shows the state of the stack as it was before the acceptance of the
interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
MSB
Stack area
Address
MSB
LSB
Stack area
LSB
m–4
m–4
Program counter (PCL)
m–3
m–3
Program counter (PCM)
m–2
m–2
Flag register (FLGL)
m–1
m–1
m
Content of previous stack
m+1
Content of previous stack
[SP]
Stack pointer
value before
interrupt occurs
Stack status before interrupt request
is acknowledged
Flag register
(FLGH)
Program
counter (PCH)
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
Figure 4.3.3. State of stack before and after acceptance of interrupt request
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[SP]
New stack
pointer value
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The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 4.3.4 shows the operation of the saving registers.
Note: Stack pointer indicated by U flag.
(1) Stack pointer (SP) contains even number
Address
Sequence in which order
registers are saved
Stack area
[SP] – 5 (Odd)
[SP] – 4 (Even)
Program counter (PCL)
[SP] – 3(Odd)
Program counter (PCM)
[SP] – 2 (Even)
Flag register (FLGL)
[SP] – 1(Odd)
[SP]
Flag register
(FLGH)
Program
counter (PCH)
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
Program counter (PCL)
(3)
[SP] – 3 (Even)
Program counter (PCM)
(4)
[SP] – 2(Odd)
Flag register (FLGL)
[SP] – 1 (Even)
[SP]
Flag register
(FLGH)
Saved simultaneously,
all 8 bits
(1)
Program
counter (PCH)
(2)
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 4.3.4. Operation of saving registers
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4.4 Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter
(PC), both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
4.5 Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware
priority is accepted (see Figure 4.5.1).
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 4.5.2 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
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High
INT1
Timer B2
Timer B0
Timer A3
Timer A1
INT4
INT2
INT0
Timer B1
Timer A4
Timer A2
Priority of peripheral I/O interrupts
(if priority levels are same)
INT5
INT3
UART1 reception
UART0 reception
FLD
A-D conversion
DMA1
Timer A0
UART1 transmission
UART0 transmission
SI/O2 automatic transfer
DMA0
Low
Figure 4.5.1. Maskable interrupts priorities (peripheral I/O interrupts)
________
Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 4.5.2. Hardware interrupts priorities
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4.6 Multiple Interrupts
The state when control branched to an interrupt routine is described below:
· The interrupt enable flag (I flag) is set to “0” (the interrupt is disabled).
· The interrupt request bit of the accepted interrupt is set to “0”.
· The processor interrupt priority level (IPL) is assigned to the same interrupt priority level as assigned to
the accepted interrupt.
Setting the interrupt enable flag (I flag) to “1” within an interrupt routine allows an interrupt request assigned
a priority higher than the IPL to be accepted. Figure 4.6.1 shows the scheme of multiple interrupts.
An interrupt request that is not accepted because of low priority will be held. If the condition following is met
when the REIT instruction returns the IPL and the interrupt priority is determined, then the interrupt request
being held is accepted.
Interrupt priority level of the interrupt request being held
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Interrupt request
generated
Time
Reset
Nesting
Main routine
I=0
IPL = 0
Interrupt 1
I=1
Interrupt priority level = 3
Interrupt 1
I=0
Interrupt 2
IPL = 3
Multiple interrupts
I=1
Interrupt priority level = 5
Interrupt 2
I=0
IPL = 5
Interrupt 3
REIT
Interrupt priority level = 2
I=1
IPL = 3
Interrupt 3
REIT
I=1
Not acknowledged because
of low interrupt priority
IPL = 0
Main routine instructions
are not executed.
Interrupt 3
I=0
IPL = 2
REIT
I=1
IPL = 0
I : Interrupt enable flag
IPL : Processor interrupt priority level
: Automatically executed.
: Be sure to set in software.
Figure 4.6.1. Multiple interrupts
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4.7 Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 0000 16. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
the stack pointer before accepting an interrupt.
(3) External interrupt
_______
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
_______
through INT5 regardless of the CPU operation clock.
________
________
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to “1”.
After changing the polarity, set the interrupt request bit to “0”. Figure 4.7.1 shows the procedure for
______
changing the INT interrupt generate factor.
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
______
Figure 4.7.1. Switching condition of INT interrupt request
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(4) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
;
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
;
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is
to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to
effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
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This page kept blank for layout purposes.
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Chapter 5
Standard Characteristics
Mitsubishi microcomputers
M30218 Group
Standard Characteristics
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
5.1 Standard DC Characteristics
The standard characteristics given in this section are examples of M30218MC-AXXXFP. The contents of
these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.
5.1.1 Standard Ports Characteristics
Figures 5.1.1 through 5.1.6 show the standard ports characteristics.
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CMOS ports
VCC = 5 V
IOH [mA]
–50
Ta = –20 °C
Ta = 25 °C
–25
Ta = 90 °C
0
1
2
3
4
5
VOH [V]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Figure 5.1.1. IOH - VOH standard characteristics of ports P44 to P47, P7 to P10 (VCC = 5V)
CMOS ports
VCC = 5 V
IOL [mA]
50
Ta = –20 °C
Ta = 25 °C
25
Ta = 90 °C
0
1
2
3
4
5
VOL [V]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Figure 5.1.2. IOL - VOL standard characteristics of ports P44 to P47, P7 to P10 (VCC = 5V)
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CMOS ports
VCC = 3 V
IOH [mA]
–20
Ta = 25 °C
Ta = –20 °C
–10
Ta = 90 °C
0
1.5
3
VOH [V]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Figure 5.1.3. IOH - VOH standard characteristics of ports P44 to P47, P7 to P10 (VCC = 3V)
CMOS ports
VCC = 3 V
IOL [mA]
–20
Ta = 25 °C
Ta = –20 °C
–10
Ta = 90 °C
0
1.5
3
VOL [V]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Figure 5.1.4. IOL - VOL standard characteristics of ports P44 to P47, P7 to P10 (VCC = 3V)
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High-breakdown-voltage ports
VCC = 5 V
–100
Ta = –20 °C
IOH [mA]
Ta = 90 °C
Ta = 25 °C
–50
0
1
2
3
4
5
VOH [V]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Figure 5.1.5. IOH - VOH standard characteristics of ports P0 to P3, P40 to P43, P5, P6 (VCC = 5V)
High-breakdown-voltage ports
VCC = 3 V
–50
Ta = –20 °C
IOH [mA]
Ta = 25 °C
–25
Ta = 90 °C
0
1.5
3
VOH [V]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Figure 5.1.6. IOL - VOL standard characteristics of ports P0 to P3, P40 to P43, P5, P6 (VCC = 3V)
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5.1.2 Characteristics of ICC-f(XIN)
Figures 5.1.7 and 5.1.8 show the Characteristics of ICC-f(XIN).
• Measurement conditions :
VCC = 5V, Ta = 25˚C, f(X IN) : square waveform input, single-chip mode
When access to ROM and RAM
• Register setting condition
XIN - XOUT drive capacity select bit = “1” (HIGH)
= “0” (On)
Main clock (X IN - XOUT ) stop bit
VCC = 5 V
25
XIN / 1
XIN / 2
20
XIN / 4
XIN / 8
ICC [mA]
XIN / 16
15
10
5
0
0
2
4
6
8
10
12
f(XIN) [MHz]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Figures 5.1.7. Characteristics of ICC-f(XIN) (VCC = 5V)
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• Measurement conditions :
VCC = 3V, Ta = 25˚C, f(X IN) : square waveform input, single-chip mode
When access to ROM and RAM
• Register setting condition
XIN - XOUT drive capacity select bit = “1” (HIGH)
= “0” (On)
Main clock (X IN - XOUT) stop bit
VCC = 3 V
20
XIN
XIN / 2
XIN / 4
15
XIN / 8
ICC [mA]
XIN / 16
10
5
0
0
2
4
6
8
10
12
f(XIN) [MHz]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Figures 5.1.8. Characteristics of ICC-f(XIN) (VCC = 3V)
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5.2 Standard Characteristics of A-D Converter
The standard characteristics given in this section are an example of M30218MC-AXXXFP. The contents
of these examples cannot be guaranteed. For standardize values, see “Electric characteristics”.
Figures 5.2.1 and 5.2.2 show the standard characteristics of the A-D converter.
The line on the top side of the graph represents absolute errors.
The line on the bottom side of the graph represents the width of input voltage bearing the equal output code.
Measurement conditions (VCC = 5.12V, VREF = 5.12V, f(XIN ) = 10MHz, Ta˚C)
M30218MC with sample & hold, 10 bit characteristics of A-D conversion
AVcc = Vcc = Vref = 5.12 V
1 LSB = 5 mV
φAD = XIN = 10 MHz
Absolute error [LSB]
3.0
3.0
2.0
2.0
1.0
1.0
0.0
0.0
-1.0
-1.0
Absolute error [LSB] (without a quantization error)
Differential non-linearity error [LSB]
-2.0
-2.0
-3.0
-3.0
0
256
512
768
1024
A-D conversion output code
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Figure 5.2.1. Standard characteristics of the A-D converter
446
Standard Characteristics
Measurement conditions (VCC = 3.072V, VREF = 3.072V, f(XIN ) = 3.5MHz, Ta = 25˚C)
M30218MC 8 bit, characteristics of A-D conversion
Absolute error [LSB]
AVcc = Vcc = Vref = 3.072V
1 LSB = 12 mV
φAD = XIN/2, XIN = 3.5 MHz
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
0.0
-0.5
-0.5
-1.0
-1.0
Absolute error [LSB] (without a quantization error)
-1.5
-1.5
Differential non-linearity error [LSB]
-2.0
-2.0
0
64
128
192
256
A-D conversion output code
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Figure 5.2.2. Standard characteristics of the A-D converter
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5.3 Standard Characteristics of D-A Converter
The standard characteristics given in this section are an example of M30218MC-AXXXFP. The contents of
these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.
Figures 5.3.1 and 5.3.2 show the standard characteristics of the D-A converter.
The line on the bottom side of the graph represents absolute errors. This indicates the difference between
the measurement and the ideal analog value corresponding to the input code.
The line on the top side of the graph represents the variation width of analog output value corresponding to
1-bit variation in the input code.
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Measurement conditions (VCC = 5.12V, VREF = 5.12V, f(XIN) = 10MHz, Ta = 25˚C)
M30218MC 8 bit, characteristics of D-A conversion
AVcc = Vcc = Vref = 5.12V
1LSB = 20mV
XIN = 10 MHz
Absolute accuracy [mV]
30
30
20
20
10
10
0
0
-10
-10
-20
-20
Absolute accuracy [mV]
1 LSB WIDTH = 20mV
-30
-30
0
32
64
96
128
Absolute accuracy [mV]
D-A input code
30
30
20
20
10
10
0
0
-10
-10
-20
-20
-30
-30
128
160
192
224
256
D-A input code
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Figure 5.3.1. Characteristics of the D-A converter
449
Standard Characteristics
Measurement conditions (VCC = 3.072V, VREF = 3.072V, f(X IN) = 3.5MHz, Ta = 25˚C)
M30218FC/MC 8 bit, characteristics of D-A conversion
Absolute accuracy [mV]
AVcc = Vcc = Vref = 3.072V
1LSB = 12mV
XIN = 3.5 MHz
50
50
40
40
30
30
20
20
10
10
0
0
-10
-10
-20
-20
-30
Absolute accuracy [mV]
1 LSB WIDTH = 20mV
-40
-50
Absolute accuracy [mV]
0
32
64
D-A input code
96
-30
-40
-50
128
50
50
40
40
30
30
20
20
10
10
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
128
160
192
224
-50
256
D-A input code
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Figure 5.3.2. Characteristics of the D-A converter
450
Mitsubishi microcomputers
M30218 Group
Standard Characteristics
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
5.4 Standard Characteristics of Pull-Up Resistor
Figure 5.4.1 shows an example of the standard characteristics of the pull-up resistor.
–200.0
II (µA)
–160.0
Vcc = 5 V
–100.0
–40.0
Vcc = 3 V
0
1.0
2.0
3.0
4.0
5.0
VI (V)
Note: Data described here are characteristic examples. The data values are not guaranteed.
Figure 5.4.1. Example of the standard characteristics of the pull-up resistor
451
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
M30218 Group
REV.B Jun. 2001
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©2001 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
M30218 Group
REVISION DESCRIPTION LIST
Rev.
No.
A
A1
M30218 GROUP USER’S MANUAL
Revision Description
Rev.
date
First Edition
991125
The followings are updated:
991221
Page 56 Figure 39:
FLDC mode register
b3b2
(at rising edge of each digit)
10 : 2 X Tdisp
Page 447 Figure 5.2.2, Page 450 Figure 5.3.2 : Measurement conditions....f(XIN)=3.5MHz
B
The followings are updated:
010627
Pages 3, 6, 7, 8, 9, 129, 134, 135, 141, 143, 147, 286, 440, 446, and 448:
Delete about mask option specification of pull-down resistor
Page 151 Table 71 Automatic transfer serial I/O:
Decided electrical standard values (at V CC = 3 V)
Page 154 Figure 125 Block diagram of flash memory version:
User ROM area block number
E000016 to E7FFF16 Block 0 ---> Block 3
E800016 to EFFFF16 Block 1 ---> Block 2
F000016 to F7FFF16 Block 2 ---> Block 1
F800016 to FFFFF16 Block 3 ---> Block 0
Page 155 Figure 126 Flash memory control register
bit6 bit5 bit4
0 0 0 : Block 0 program/erase ---> Block 3 program/erase
0 0 1 : Block 1 program/erase ---> Block 2 program/erase
0 1 0 : Block 2 program/erase ---> Block 1 program/erase
0 1 1 : Block 3 program/erase ---> Block 0 program/erase
Page 225 2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode) Line 7
....This flag cannot be set to “0” by.... ---> ....This flag can be set to “0” by....
(1/1)