Fairchild MM74C90 4-bit decade counter â ¢ 4-bit binary counter Datasheet

Revised May 2002
MM74C90 • MM74C93
4-Bit Decade Counter • 4-Bit Binary Counter
General Description
Features
The MM74C90 decade counter and the MM74C93 binary
counter and complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement
mode transistors. The 4-bit decade counter can reset to
zero or preset to nine by applying appropriate logic level on
the R01, R02, R91 and R92 inputs. Also, a separate flip-flop
on the A-bit enables the user to operate it as a divide-by-2,
5 or 10 frequency counter. The 4-bit binary counter can be
reset to zero by applying high logic level on inputs R01 and
R02, and a separate flip-flop on the A-bit enables the user
to operate it as a divide-by-2, -8, or -16 divider. Counting
occurs on the negative going edge of the input pulse.
■ Wide supply voltage range:
3V to 15V
■ Guaranteed noise margin: 1V
■ High noise immunity: 0.45 VCC (typ.)
■ Low power compatibility:
Fan out of 2 TTL driving 74L
■ The MM74C93 follows the MM74L93 Pinout
All inputs are protected against static discharge damage.
Ordering Code:
Order Number
Package Number
Package Description
MM74C90N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74C93N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Connection Diagrams
MM74C90
MM74C93
Top View
Top View
© 2002 Fairchild Semiconductor Corporation
DS005889
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MM74C90 • MM74C93 4-Bit Decade Counter • 4-Bit Binary Counter
October 1987
MM74C90 • MM74C93
Logic Diagrams
MM74C90
MM74C93
MM74C90 4-Bit Decade Counter BCD Count Sequence
MM74C93 4-Bit Binary Counter Binary Count Sequence
Truth Tables
Count
Output
Count
QD
QC
QB
QA
0
L
L
L
L
1
L
L
L
2
L
L
3
L
L
4
L
H
5
L
H
6
L
H
7
L
H
8
H
L
9
H
L
Output
QD
QC
QB
0
L
L
L
L
H
1
L
L
L
H
H
L
2
L
L
H
L
H
H
3
L
L
H
H
L
L
4
L
H
L
L
L
H
5
L
H
L
H
H
L
6
L
H
H
L
H
H
7
L
H
H
H
L
L
8
H
L
L
L
L
H
9
H
L
L
H
10
H
L
H
L
11
H
L
H
H
12
H
H
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
Output QA is connected to Input B for BCD count.
H = HIGH Level
L = LOW Level
X = Irrelevant
QA
Output QA is connected to input B for binary count sequence.
H = HIGH Level
L = LOW Level
X = Irrelevant
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MM74C90 • MM74C93
Function Tables
Reset/Count Function Table
Reset Inputs
Output
R01
R02
R91
R92
QD
QC
QB
QA
H
H
L
X
L
L
L
L
H
H
X
L
L
L
L
L
X
X
H
H
H
L
L
H
X
L
X
L
Count
L
X
L
X
Count
L
X
X
L
Count
X
L
L
X
Count
Reset/Count Function Table
Reset
Output
Inputs
R01
R02
QD
QC
QB
QA
H
H
L
L
L
L
L
X
Count
X
L
Count
3
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MM74C90 • MM74C93
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin (Note 1)
−0.3V to VCC +0.3V
Operating Temperature Range (TA)
MM74C90, MM74C93
−55°C to +125 °C
Power Dissipation (PD)
Dual-In-Line
700 mW
Small Outline
500 mW
Operating VCC Range
3V to 15V
Absolute Maximum VCC
Storage Temperature Range (TS)
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Temperature Range”, they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
18V
−65°C to +150 °C
Lead Temperature (TL)
260 °C
(Soldering, 10 seconds)
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
VIN(1)
VIN(0)
VOUT(1)
VOUT(0)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
VCC = 5V
3.5
VCC = 10V
8.0
V
VCC = 5V
1.5
VCC = 10V
2.0
VCC = 5V, IO = −10 µA
4.5
VCC = 10V, IO = −10 µA
9.0
V
VCC = 5V, IO = +10 µA
0.5
VCC = 10V, IO = +10 µA
1.0
IIN(1)
Logical “1” Input Current
VCC = 15V, VIN = 15V
IIN(0)
Logical “0” Input Current
VCC = 15V, VIN = 0V
ICC
Supply Current
VCC = 15V
0.005
−1.0
V
1.0
µA
300
µA
−0.005
0.05
V
µA
CMOS/LPTTL INTERFACE
VIN(1)
Logical “1” Input Voltage
MM74C90, MM74C93
VIN(0)
MM74C90, MM74C93
VOUT(1)
VCC−1.5
V
VCC = 4.75V
0.8
V
Logical “1” Output Voltage
MM74C90, MM74C93
VOUT(0)
VCC = 4.75V
Logical “0” Input Voltage
VCC = 4.75V, IO = −360 µA
2.4
V
Logical “0” Output Voltage
MM74C90, MM74C93
VCC = 4.75V, IO = −360 µA
0.4
V
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE
ISOURCE
ISINK
ISINK
Output Source Current
VCC = 5V, VOUT = 0V
(P-Channel)
TA = 25°C
Output Source Current
VCC = 10V, VOUT = 0V
(P-Channel)
TA = 25°C
Output Sink Current
VCC = 5V, VOUT = VCC
(N-Channel)
TA = 25°C
Output Sink Current
VCC = 10V, VOUT = VCC
(N-Channel)
TA = 25°C
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4
−1.75
−3.3
mA
−8.0
−15
mA
1.75
3.6
mA
8.0
16
mA
(Note 2)
TA = 25°C, CL = 50 pF, unless otherwise specified
Symbol
tpd0, tpd1
tpd0, tpd1
tpd0, tpd1
tpd0, tpd1
tpd0, tpd1
tpd0, tpd1
tpd0, tpd1
tpd0, tpd1
Typ
Max
Propagation Delay Time
Parameter
VCC = 5V
Conditions
Min
200
400
from AIN to QA
VCC = 10
80
150
Propagation Delay Time from
VCC = 5V
450
850
AIN to QB (MM74C93)
VCC = 10V
160
300
Propagation Delay Time from
VCC = 5V
450
800
AIN to QB (MM74C90)
VCC = 10V
160
300
Propagation Delay Time
VCC = 5V
500
1050
from AIN to QC (MM74C93)
VCC = 10
200
400
Propagation Delay Time from
VCC = 5V
500
1000
AIN to QC (MM74C93)
VCC = 10V
200
400
Propagation Delay Time from
VCC = 5V
600
1200
AIN to QD (MM74C93)
VCC = 10V
250
500
Propagation Delay Time from
VCC = 5V
450
800
AIN to QD (MM74C90)
VCC = 10V
160
300
Propagation Delay Time from
VCC = 5V
150
300
R01 or R02 to QA, QB, QC or QD
VCC = 10V
75
150
Propagation Delay Time from
VCC = 5V
200
400
R01 or R02 to QA, QB, QC or QD
VCC = 10V
75
150
Units
ns
ns
ns
ns
ns
ns
ns
ns
(MM74C93)
tpd0, tpd1
ns
(MM74C90)
tpd0, tpd1
Propagation Delay Time from
VCC = 5V
250
500
R91 or R92 to QA or QD
VCC = 10V
100
200
ns
(MM74C90)
tPW
tPW
tPW
tr , tf
Min. R01 or R02 Pulse Width
VCC = 5V
600
250
(MM74C93)
VCC = 10V
30
125
Min. R01 or R02 Pulse Width
VCC = 5V
600
250
(MM74C90)
VCC = 10V
300
125
Min. R91 or R92 Pulse Width
VCC = 5V
500
200
(MM74C90)
VCC = 10V
250
100
Maximum Clock Rise
VCC = 10V
ns
ns
ns
15
µs
and Fall Time
VCC = 10V
tW
Minimum Clock Pulse Width
VCC = 5V
250
100
VCC = 10V
100
50
fMAX
Maximum Clock Frequency
VCC = 5V
2
VCC = 10V
5
CIN
Input Capacitance
Any Input (Note 3)
5
pF
CPD
Power Dissipation Capacitance
Per Package (Note 4)
45
pF
5
ns
MHz
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: CPD determines the no load ac power consumption of any CMOS device. For complete explanation see Family Characteristics application note—
AN-90.
5
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MM74C90 • MM74C93
AC Electrical Characteristics
MM74C90 • MM74C93
AC Test Circuits
MM74C90
MM74C93
Clock rise and fall time tr = tf = 20 ns
Clock rise and fall time tr = tf = 20 ns
Switching Time Waveforms
MM74C90 and MM74C93 are solid line waveforms. Dashed line waveforms are for MM74C90 only.
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MM74C90 • MM74C93 4-Bit Decade Counter • 4-Bit Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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