TI BQ29200DRBT Voltage protection with automatic cell balance for 2-series cell li-ion battery Datasheet

bq29200
bq29209
www.ti.com
SLUSA52 – JUNE 2010
Voltage Protection with Automatic Cell Balance for 2-Series Cell Li-Ion Batteries
Check for Samples: bq29200 , bq29209
FEATURES
•
•
•
•
1
•
•
•
2-Series Cell Secondary Protection
Automatic Cell Imbalance Correction with
External Enable Control
– ±30 mV Enable, 0 mV Disable
Thresholds Typical
External Capacitor-Controlled Delay Timer
External Resistor-Controlled Cell Balance
Current
Low Power Consumption ICC < 3 µA Typical
(VCELL(ALL) < VPROTECT)
•
High-Accuracy Overvoltage Protection:
– ±25 mV with TA = 0°C to 60°C
Fixed Overvoltage Protection Thresholds:
4.30 V, 4.35 V
Small 8L DRB Package
APPLICATIONS
•
2nd Level Protection in Li-Ion Battery Packs
– Netbook Computers
– Power Tools
– Portable Equipment and Instrumentation
– Battery Backup Systems
DESCRIPTION
The bq2920x device is a secondary overvoltage protection IC for two-series cell lithium-ion battery packs that
incorporates a high-accuracy precision overvoltage detection circuit and automatic cell imbalance correction.
The voltage of each cell in a two-series cell battery pack is compared to an internal reference voltage. If either
cell reaches an overvoltage condition, the bq2920x device starts a timer that provides a delay proportional to the
capacitance on the CD pin. Upon expiration of the internal timer, the OUT pin changes from low to high state.
If enabled, the bq2920x will perform automatic cell imbalance correction where the two cells are automatically
corrected for voltage imbalance by loading the cell with the higher charge voltage with a small balancing current.
When the cells are measured to be equal within nominally 0 mV, the load current is removed. It will be re-applied
if the imbalance exceeds nominally 30 mV. The cell mismatch correction circuitry is enabled by pulling the
CB_EN pin low, and disabled when CB_EN is pulled to VDD or greater than 2.2 V.
VC2 1
8
VC1 2
7 VDD
VC1_CB 3
CD 4
OUT
6 CB_EN
_
5 GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
bq29200
bq29209
SLUSA52 – JUNE 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PART NUMBER
–40°C to
+110°C
OUT PIN
LATCH
OPTION
PACKAGE
BQ29200
No
QFN-8
BQ29209
No
PACKAGE
DESIGNATOR
PACKAGE
MARKING
OVP
DRB
200
209
ORDERING INFORMATION
TAPE AND REEL
(LARGE)
TAPE AND REEL
(SMALL)
4.35 V
BQ29200DRBR
BQ29209DRBT
4.30 V
BQ29209DRBR
BQ29209DRBT
THERMAL INFORMATION
bq2920x
THERMAL METRIC
(1)
DRB
UNITS
8 PINS
Junction-to-ambient thermal resistance (2)
qJA
50.5
(3)
qJC(top)
Junction-to-case(top) thermal resistance
qJB
Junction-to-board thermal resistance
yJT
Junction-to-top characterization parameter
yJB
Junction-to-board characterization parameter
(3)
(4)
(5)
(6)
(7)
19.3
(5)
Junction-to-case(bottom) thermal resistance
qJC(bottom)
(1)
(2)
25.1
(4)
0.7
(6)
°C/W
18.9
(7)
5.2
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
PIN FUNCTIONS
2
PIN NAME
NO.
CB_EN
6
Cell balance enable
DESCRIPTION
CD
4
Connection to external capacitor for programmable delay time
GND
5
Ground pin
OUT
8
Output
VC1
2
Sense voltage input for bottom cell
VC1_CB
3
Cell balance input for bottom cell
VC2
1
Sense voltage input for top cell
VDD
7
Power supply
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SLUSA52 – JUNE 2010
FUNCTIONAL BLOCK DIAGRAM
VDD
5V LDO &
POR
VC2
CTRL
CB2_EN
+
CB
Logic
Hys.
ICD(CHG) =
150 nA
-
CB1_EN
VC1
+
VC1_CB
OUT
GND
CB_EN
CD
0.1 µF
ABSOLUTE MAXIMUM RATINGS
Over-operating free-air temperature range (unless otherwise noted) (1)
VALUE / UNIT
Supply voltage range, VMAX
Input voltage range, VIN
Output voltage range, VOUT
VDD–GND
–0.3 to 16 V
VC2–GND, VC1–GND
–0.3 to 16 V
VC2–VC1, CD–GND
–0.3 to 8 V
CB_EN–GND
–0.3 to 16 V
OUT–GND
–0.3 to 16 V
Continuous total power dissipation, PTOT
See package dissipation rating
Storage temperature range, TSTG
–65°C to 150°C
Lead temperature (soldering, 10 s), TSOLDER
(1)
300°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VDD
NOM
MAX
4
10
0
5
UNIT
V
Input voltage range
VC2–VC1, VC1–GND
Delay time capacitance, td(CD)
CCD (See Figure 4)
Voltage monitor filter resistance
RIN (See Figure 4)
100
1K
Ω
Voltage monitor filter capacitance CIN (See Figure 4)
0.01
0.1
µF
Supply voltage filter resistance
RVD (See Figure 4)
Supply voltage filter capacitance
CVD (See Figure 4)
Cell balance resistance
RCB (See Figure 4 and PROTECTION (OUT) TIMING)
Operating ambient temperature range, TA
0.1
100
1K
0.1
Product Folder Link(s): bq29200 bq29209
Ω
µF
100
4.7K
Ω
–40
110
°C
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V
µF
3
bq29200
bq29209
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ELECTRICAL CHARACTERISTICS
Typical values stated where TA = 25°C and VDD = 7.2 V.
Min/Max values stated where TA = –40°C to 110°C and VDD = 4 V to 10 V (unless otherwise noted).
PARAMETER
VPROTECT
Overvoltage bq29209
detection
bq29200
voltage
VHYS
Overvoltage detection
hysteresis
VOA
Overvoltage detection
accuracy
VOA_DRIFT
Overvoltage threshold
temperature drift
xDELAY
Overvoltage delay time
scale factor
TEST CONDITION
MIN NOM MAX
UNIT
4.30
V
4.35
200
300
400
mV
mV
TA = 25°C
–10
10
TA = 0°C to 60°C
–0.4
0.4
TA = –40°C to 110°C
–0.6
0.6
TA = 0°C to 60°C
Note: Does not include external capacitor variation.
5.5
8.0
11.0
TA = –40°C to 110°C
Note: Does not include external capacitor variation.
5.0
8.0
12.5
mV°/C
s/µF
Overvoltage delay time
scale factor in Customer
Test Mode
0.08
s/mF
ICD(CHG)
Overvoltage detection
charging current
150
nA
ICD(DSG)
Overvoltage detection
discharging current
60
µA
VCD
Overvoltage detection
external capacitor
comparator threshold
1.2
V
ICC
Supply current
xDELAY_CTM
(1)
(VC2–VC1) = (VC1–GND) = 3.5 V (See Figure 1)
(VC2–VC1) = (VC1–GND) = VPROTECTMAX,
VDD = VC2, IOH = 0
VC2 = VC1 = VPROTECTMAX, VDD = VC2,
IOH = –100 µA, TA = 0°C to 60°C
3.0
6.0
µA
6
8.25
9.5
V
2
2.5
3
V
200
mV
10
mV
200
mV
(VC2–VC1) and (VC1–GND) < VPROTECT,
IOL = 100 µA, TA = 25°C
VOUT
OUT pin drive voltage
(VC2–VC1) and (VC1–GND) < VPROTECT,
IOL = 0 µA, TA = 25°C
0
VC2 = VC1 = VDD = 4 V, IOL = 100 µA
(VC2–VC1) or (VC1–GND) > VPROTECT,
VDD = 4 V to 10 V, IOH = –100 µA
TA = –40°C to 60°C
(VC2–VC1) or (VC1–GND) > VPROTECT,
VDD = 5 V to 10 V, IOH = –100 µA
TA = 60°C to 110°C
OUT = 2 V, (VC2–VC1) = (VC1–GND) = VPROTECTMAX, VDD =
4 V to 10 V, TA = –40°C to 60°C
IOH
High-level output current
IOL
Low-level output current
OUT = 0.05 V, (VC2–VC1) = (VC1–GND) = 3.5 V,
VDD = VC2
IOH_ZV
High-level short-circuit
output current
OUT = 0V (VC2–VC1) = (VC1–GND) = VPROTECTMAX VDD = 4
to 10 V
IIN
Input current at VCx pins
VMM_DET_ON
(1)
4
Cell mismatch detection
threshold for turning ON
OUT = 2 V, (VC2–VC1) = (VC1–GND) = VPROTECTMAX, VDD =
5 V to 10 V, TA = 60°C to 110°C
2
V
–100
µA
30
Measured at VC1, (VC2–VC1) = (VC1–GND) = 3.5 V,
TA = 0°C to 60°C (See Figure 1)
–0.2
Measured at VC2, (VC2–VC1) = (VC1–GND) = 3.5 V
TA = 0°C to 60°C (See Figure 1)
(VC2–VC1) versus (VC1–GND) and vice-versa when cell
balancing is enabled
17
30
85
mA
–8.0
mA
0.2
µA
2.5
µA
45
mV
Specified by design. Not 100% tested in production.
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SLUSA52 – JUNE 2010
ELECTRICAL CHARACTERISTICS (continued)
Typical values stated where TA = 25°C and VDD = 7.2 V.
Min/Max values stated where TA = –40°C to 110°C and VDD = 4 V to 10 V (unless otherwise noted).
PARAMETER
TEST CONDITION
VMM_DET_OFF
Cell mismatch detection
threshold for turning
OFF
Delta between (VC2–VC1) and (VC1–GND) when cell
balancing is disabled VDD = VC2 = 7.6 V
VCB_EN_ON
Cell balance enable ON
threshold
Active LOW pin at CB_EN
VCB_EN_OFF
Cell balance enable
OFF threshold
Active HIGH at CB_EN
ICB_EN
Cell balance enable ON
input current
CB_EN = GND (See Figure 2)
MIN NOM MAX
–9
0
UNIT
9
mV
1
V
2.2
V
0.2
µA
RECOMMENDED CELL BALANCING CONFIGURATIONS
Typical values stated where TA = 25°C and (VC2–VC1), (VC1–GND) = 3.8 V. Min/Max values stated where TA = –40°C to
110°C, VDD = 4V to 10V, and (VC2–VC1), (VC1–GND) = 3.0 V to 4.2 V. All values assume recommended supply voltage
filter resistance RVDD) of 100 Ω and 5% accurate or better cell balance resistor RCB).
PARAMETER
ICB
Cell balance input current
TEST CONDITION
MIN NOM MAX
RCB = 4700 Ω
0.5
0.75
1
RCB = 2200 Ω
1
1.5
2
RCB = 910 Ω
2
3
4
RCB = 560 Ω
3
4.5
6
RCB = 360 Ω
3.5
6
8.5
RCB = 240 Ω
4
7.5
11
RCB = 120 Ω
5
10
15
UNIT
mA
The cell balancing current may be calculated as follows:
Cell 1 (VC1–GND):
ICB1 =
VC1
RCB
Cell 2 (VC2–VC1):
ICB2 =
(VC2 - VC1)
(RCB + R VB
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TEST CONDITIONS
IIN
IIN
1 VC2
OUT 8
2 VC1
VDD 7
3 VC1_CB
ICC
CB_EN 6
4 CD
GND 5
Figure 1. ICC, IIN Measurement
VCELL
ICB
VCELL±VCB
1 VC2
OUT 8
2 VC1
VDD 7
3 VC1_CB
ICB
CB_EN 6
4 CD
ICB_EN
GND 5
Figure 2. ICB Measurement
PROTECTION (OUT) TIMING
Sizing the external capacitor is based on the desired delay time as follows:
t
d
c CD= xDELAY
Where td is the desired delay time and xDELAY is the overvoltage delay time scale factor, expressed in seconds
per microFarad. xDELAY is nominally 8.0 s/µF. For example, if a nominal delay of 3 seconds is desired, the
customer should use a CCD capacitor that is 3 s / 8.0 s/µF = 0.375 µF.
The delay time is calculated as follows:
é1.2 V ´ C ùû
CD
td = ë
ICD
If the cell overvoltage condition is removed before the external capacitor reaches the reference voltage, the
internal current source is disabled and an internal discharge block is employed to discharge the external
capacitor down to 0 V. In this instance, the OUT pin remains in a low state.
6
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Cell Voltage > VPROTECT
When one or both of the cell voltages rises above VPROTECT, the internal comparator is tripped, and the delay
begins to count to td. If the input remains above VPROTECT for the duration of td, the bq2920x output changes from
a low to a high state, by means of an internal pull-up network, to a regulated voltage of no more than 8.5 V when
IOH = 0 mA.
The external delay capacitor should charge up to no more than the internal LDO voltage (approximately 5 V
typically), and will fully discharge in approximately under 100 ms when the overvoltage condition is removed.
V PROTECT
VPROTECT - VHYS
Cell Voltage
VC2-VC1,
VC1-GND
td
L
OUT
H
Figure 3. Timing for Overvoltage Sensing
CELL CONNECTION SEQUENCE
The recommended cell connection sequence begins from the bottom of the stack, as follows:
1. GND
2. VC1
3. VC2
While not advised, connecting the cells in a sequence other than that described above does not result in errant
activity on the OUT pin. For example:
1. GND
2. VC2 or VC1
3. Remaining VCx pin
It is also recommended that the overvoltage delay timing capacitor, CCD, be propagated before connecting the
cells.
CELL BALANCE ENABLE CONTROL
To avoid prematurely discharging the cells, it is recommended to turn off (pull high) the active-low Cell Balance
Enable Control pin at lower State of Charge (SOC) levels.
BATTERY CONNECTION
Figure 4 shows the configuration for the 2-series cell battery connection.
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RVD
RIN
VCELL2
RIN
CIN
1 VC2
OUT 8
2 VC1
VDD 7
CIN
3 VC1_CB
RCB
VCELL1
CB_EN 6
CVD
GND 5
4 CD
CCD
Figure 4. 2-Series Cell Configuration
CUSTOMER TEST MODE
Customer Test Mode (CTM) helps to greatly reduce the overvoltage detection delay time and enable quicker
customer production testing. This mode is intended for quick-pass board-level verification tests, and, as such,
individual cell overvoltage levels may deviate slightly from the specifications (VPROTECT, VOA). If accurate
overvoltage thresholds are to be tested, use the standard delay settings that are intended for normal use.
To enter CTM, VDD should be set to approximately 9.5 V higher than VC2. When CTM is entered, the device
switches from the normal overvoltage delay time scale factor, xDELAY, to a significantly reduced factor of
approximately 0.08, thereby reducing the delay time during an overvoltage condition.
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part
into Customer Test Mode. Also, avoid exceeding Absolute Maximum Voltages for the
individual cell voltages (VC1–GND) and (VC2–VC1). Stressing the pins beyond the
rated limits may cause permanent damage to the device.
To exit CTM, the device should be powered off before being powered back on.
15 V
VDD
Test Mode entered
VC2
> 10 ms
4.5 V
VPROTECT
(VC2-VC1)
or
(VC1-GND)
VPROTECT VHYST
4V
OUT
8
<<td
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Jul-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
BQ29200DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
BQ29200DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
BQ29209DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
BQ29209DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ29200DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
BQ29200DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
BQ29209DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ29200DRBR
SON
DRB
8
3000
346.0
346.0
29.0
BQ29200DRBT
SON
DRB
8
250
190.5
212.7
31.8
BQ29209DRBT
SON
DRB
8
250
190.5
212.7
31.8
Pack Materials-Page 2
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the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DLP® Products
www.dlp.com
Communications and
Telecom
www.ti.com/communications
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
www.ti.com/clocks
Consumer Electronics
www.ti.com/consumer-apps
Interface
interface.ti.com
Energy
www.ti.com/energy
Logic
logic.ti.com
Industrial
www.ti.com/industrial
Power Mgmt
power.ti.com
Medical
www.ti.com/medical
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
www.ti.com/video
Wireless
www.ti.com/wireless-apps
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2010, Texas Instruments Incorporated
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