Fairchild ML4823CS High frequency power supply controller Datasheet

May 1997
ML4823
High Frequency Power Supply Controller
GENERAL DESCRIPTION
FEATURES
The ML4823 High Frequency PWM Controller is an IC
controller optimized for use in Switch Mode Power
Supply designs running at frequencies to 1MHz.
Propagation delays are minimal through the comparators
and logic for reliable high frequency operation while slew
rate and bandwidth are maximized on the error amplifier.
This controller is designed for single-ended applications
using voltage or current mode and provides for input
voltage feed forward.
■
A 1V threshold current limit comparator provides cycleby-cycle current limit and exceeding a 1.4V threshold
initiates a soft-start cycle. The soft start pin doubles as a
maximum duty cycle clamp. All logic is fully latched to
provide jitter-free operation and prevent multiple pulsing.
An under-voltage lockout circuit with 800mV of hysteresis
assures low startup current and drives the outputs low
during fault conditions.
■
■
■
■
■
■
■
■
■
Practical operation at switching frequencies to 1.0MHz
High current (2A peak) totem pole output
Wide bandwidth error amplifier
Fully latched logic with double pulse suppression
Pulse-by-pulse current limiting
Soft start and max. duty cycle control
Under voltage lockout with hysteresis
5.1V trimmed bandgap reference
Low start-up current (1.1mA)
Pin compatible improved replacement for UC3823
■
Fast shut down path from current limit to output
Soft start latch ensures full soft start cycle
■
Outputs pull low for undervoltage lockout
■
This controller is an improved second source for the
UC3823 controller; however, the ML4823 includes
features not found on the 3823. These features are set in
italics.
BLOCK DIAGRAM
5
6
7
3
2
1
8
11
9
(Pin Configuration Shown for 16-Pin Version)
RT
CLOCK OUT
OSC
CT
1.25V
+
RAMP
R
+
Q
COMP
–
E/A OUT
NI
+
ERROR
AMP
–
INV
S
V+
POWER VC
OUTPUT
SOFT START
POWER GND
–
+
ILIM REF
+
–
UNDER
VOLTAGE
LOCKOUT
5.1V VREF
VREF GEN
Q
S
–
+
9V
13
14
12
4V
ENABLE
VREF
5.1V
R
1.4V
–
+
1V
–
+
ILIM/S.D.
4
INTERNAL
BIAS
VCC
SIGNAL GND
16
15
10
REV. 1.0 10/12/2000
ML4823
PIN CONFIGURATION
4
13
VC
RT
5
12
PWR GND
CT
6
11
ILIM REF
RAMP
7
10
GND
SS
8
9
ILIM/S.D.
VCC
CLOCK
3
2
1
20
19
E/A OUT
4
18
OUTPUT
CLOCK
5
17
VC
NC
6
16
NC
RT
7
15
PWR GND
CT
8
14
ILIM REF
TOP VIEW
9
10
11
12
13
GND
OUTPUT
5.1V REF
14
ILIM/S.D.
3
NC
VCC
E/A OUT
NC
5.1V REF
15
INV
16
2
SS
1
NI
RAMP
INV
ML4823
20-PIN PLCC (Q20)
NI
ML4823
16-PIN DIP (P16)
16-PIN SOIC (S16W)
TOP VIEW
PIN DESCRIPTION
PIN
(Pin Numbers in Parentheses are for PLCC Version)
NAME
FUNCTION
1 (2)
INV
Inverting input to error amp.
2 (3)
NI
Non-inverting input to error amp.
3 (4)
E/A OUT Output of error amplifier and input to
main comparator.
4 (5)
CLOCK
Oscillator output.
5 (7)
RT
Timing resistor for oscillator — sets
charging current for oscillator timing
capacitor (pin 6).
6 (8)
CT
Timing capacitor for oscillator.
7 (9)
RAMP
Non-inverting input to main
comparator. Connected to CT for
Voltage mode operation or to current
sense resistor for current mode.
8 (10)
2
SS
PIN
NAME
FUNCTION
9 (12) ILIM/S.D.
Current limit sense pin. Normally
connected to current sense resistor.
10 (13) GND
Analog signal ground.
11 (14) ILIM REF
Reference input for cycle-by-cycle
current limit comparator.
12 (15) PWR GND Return for the high current totem
pole output.
13 (17) VC
Positive supply for the high current
totem pole output.
14 (18) OUT B
High current totem pole output.
15 (19) VCC
Positive supply for the IC.
16 (20) 5.1V REF
Buffered output for the 5.1V voltage
reference.
Normally connected to soft start
capacitor.
REV. 1.0 10/12/2000
ML4823
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Supply Voltage (VC, VCC) ........................................... 30V
OUTPUT Current, Source or Sink
DC ....................................................................... 0.5A
Pulse (0.5µs) ......................................................... 2.0A
Analog Inputs
(INV, NI, RAMP, SS, ILIM) .................. GND –0.3V to 6V
CLOCK OUTPUT Current ...................................... –5mA
F/A OUT Current ...................................................... 5mA
SOFT START Sink Current ....................................... 20mA
RT Charging Current ............................................... –5mA
Junction Temperature ............................................ 125°C
Storage Temperature Range ..................... –65°C to 150°C
Lead Temperature (Soldering 10 sec.) .................... 260°C
Thermal Resistance (θJA)
Plastic DIP ....................................................... 80°C/W
Plastic SOIC................................................... 105°C/W
Plastic Chip Carrier (PLCC) .............................. 78°C/W
OPERATING CONDITIONS
Temperature Range
ML4823C .................................................. 0°C to 70°C
ML4823I ................................................ –40°C to 85°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, RT = 3.65kΩ, CT = 1000pF, TA = Operating Temperature Range, VCC = 15V. (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
360
400
440
kHz
0.2
2
%
OSCILLATOR
Initial Accuracy
TJ = 25°C,
Voltage Stability
10V ≤ VCC ≤ 30V,
Temperature Stability
Total Variation
5
Line, temp.
Clock Out High
340
3.9
Clock Out Low
%
460
4.5
kHz
V
2.3
2.9
V
Ramp Peak
2.6
2.8
3.0
V
Ramp Valley
0.7
1.0
1.25
V
Ramp Valley to Peak
1.6
1.8
2.0
V
5.025
5.10
5.175
V
REFERENCE
Output Voltage
TJ = 25°C, IO = 1mA
Line Regulation
10V ≤ VCC ≤ 30V
2
20
mV
Load Regulation
1mA ≤ IO ≤ 10mA
5
20
mV
Temperature Stability
–40°C ≤ TJ ≤ 150°C,
0.2
0.4
%
Total Variation
Line, load, temp.
5.225
V
Output Noise Voltage
10Hz to 10kHz
50
Long Term Stability
TJ = 125°C, 1000 hrs,
5
25
mV
Short Circuit Current
VREF = 0V
–50
–100
mA
±30
mV
4.975
–15
µV
ERROR AMPLIFIER
Input Offset Voltage
Input Bias Current
0.6
3
µA
Input Offset Current
0.1
1
µA
Open Loop Gain
REV. 1.0 10/12/2000
1 ≤ VO ≤ 4V
50
95
dB
3
ML4823
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ERROR AMPLIFIER (Continued)
CMRR
1.5 ≤ VCC ≤ 5.5V
50
80
dB
PSRR
10 ≤ VCC ≤ 30V
70
100
dB
Output Sink Current
VE/A OUT = 1V
1
2.5
mA
Output Source Current
VE/A OUT = 4V
–0.5
–1.3
mA
Output High Voltage
IE/A OUT = –0.5mA
4.0
4.7
5.0
V
Output Low Voltage
IE/A OUT = 1mA
0
0.5
1.0
V
Unity Gain Bandwidth
3
5.5
MHz
Slew Rate
6
12
V/µs
PWM COMPARATOR
RAMP Bias Current
VRAMP = 0V
Duty Cycle Range
E/A OUT Zero DC Threshold
–1
0
VRAMP = 0V
1.1
Delay to Output
–5
µA
80
%
1.25
V
50
80
ns
9
20
µA
SOFT START
Charge Current
VSOFT START = 0.5V
3
Discharge Current
VSOFT START = 1V
1
mA
CURRENT LIMIT/SHUTDOWN
ILIM Bias Current
0V ≤ ILIM ≤ 4V
Current Limit Offset
ILIM REF = 1.1V
±10
µA
0
15
mV
ILIM REF Common Mode Range
1.0
1.25
V
Shutdown Threshold
1.25
1.40
1.55
V
50
80
ns
IOUT = 20mA
0.25
0.40
V
IOUT = 200mA
1.2
2.2
V
Delay to Output
OUTPUT
Output Low Level
Output High Level
IOUT = –20mA
12.8
13.5
V
IOUT = –200mA
12.0
13.0
V
Collector Leakage
VC = 30V
100
500
µA
Rise/Fall Time
CL = 1000pF
30
60
ns
UNDER VOLTAGE LOCKOUT
Start Threshold
8.8
9.2
9.7
V
UVLO Hysteresis
0.4
0.8
1.2
V
SUPPLY
Start Up Current
VCC = 8V
1.1
2.5
mA
ICC
INV, RANP, ILIM = 0V
NI = 1V
22
33
mA
Note 1:
4
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
REV. 1.0 10/12/2000
ML4823
FUNCTIONAL DESCRIPTION
OSCILLATOR
The ML4823 oscillator charges the external capacitor (CT)
with a current (ISET) equal to 3/RSET. When the capacitor
voltage reaches the upper threshold (Ramp Peak), the
comparator changes state and the capacitor discharges to
the lower threshold (Ramp Valley) through Q1. While the
capacitor is discharging, Q2 provides a high pulse.
The oscillator period can be described by the following
relationship:
TOSC = TRAMP + TDEADTIME
where: TRAMP = C (Ramp Valley to Peak)/ISET
and:
TDEADTIME = C (Ramp Valley to Peak)/IQ1
ISET
RT
5.1V
3V
ISET
CT
160
+
Q2
CLOCK
OUT
–
IQ1
Q1
400µA
1.0nF
140
TD (ns)
RT
120
100
470pF
80
10k
CLOCK OUT
100k
1M
FREQ (Hz)
TD
Figure 3. Oscillator Deadtime vs Frequency
RAMP PEAK
CT
RAMP VALLEY
Figure 1. Oscillator Block Diagram
100k
30
100nF
25
47nF
20
TD (µs)
RT (OHMS)
22nF
10nF
10k
4.7nF
15
10
2.2nF
1nF
5
470pF
1k
0.1k
1k
10k
100k
1M
10M
FREQ (Hz)
Figure 2. Oscillator Timing Resistance vs Frequency
REV. 1.0 10/12/2000
0
0.47
1.0
2.2
4.7
10.0
22
47
100
CT (nF)
Figure 4. Oscillator Deadtime vs CT (3ký - RT - 100ký)
5
ML4823
ERROR AMPLIFIER
100
The ML4823 error amplifier is a 5.5MHz bandwidth 12V/µs
slew rate op-amp with provision for limiting the positive
output voltage swing (Output Inhibit line) for ease in
implementing the soft start function.
80
60
GAIN
5
40
4
20
(V)
VIN
3
0
0
VOUT
0
φ
2
–90
–20
1
0
0.2
0.4
0.6
0.8
1.0
100
1K
TIME (µs)
10K 100K
1M
–180
10M 100M
FREQ (Hz)
Figure 6. Open Loop Frequency Response
Figure 5. Unity Gain Slew Rate
OUTPUT DRIVER STAGE
The ML4823 Output Driver is a 2A peak output high speed
totem pole circuit designed to quickly switch the gates of
capacitive loads, such as power MOSFET transistors.
0.2
IL (A)
VCC
0
Q2
OUT
TOUT (V)
POWER
VC
–0.2
15
10
5
Q1
POWER
GND
0
0
40
80
120
160
200
TIME (ns)
Figure 7. Simplified Schematic
Figure 9. Rise/Fall Time (CL = 1000pF)
2
IL (A)
3
0
2
TOUT (V)
VSAT (V)
SOURCE
–2
15
10
1
5
SINK
0
0
0
0.5
1.0
IOUT (A)
Figure 8. Saturation Curves
6
1.5
0
100
200
300
400
500
TIME (ns)
Figure 10 Rise/Fall Time (CL = 10,000pF)
REV. 1.0 10/12/2000
ML4823
SOFT START AND CURRENT LIMIT
The ML4823 employs two current limits. When the
voltage at ILIM/SD exceeds the ILIM REF threshold on ILIM
REF, the outputs are immediately shut off and the cycle is
terminated for the remainder of the oscillator period by
resetting the RS flip flop.
If the output current is rising quickly (usually due to
transformer saturation) such that the voltage on pin 9
reaches 1.4V before the outputs have turned off, a soft
start cycle is initiated. The soft start capacitor is discharged
and outputs are held “off” until the voltage at SS reaches
1V, ensuring a complete soft start cycle. The duty cycle on
start up is limited by limiting the output voltage of the
error amplifier voltage to the voltage at the SS pin.
REV. 1.0 10/12/2000
7
ML4823
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P16
16-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)
16
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.26)
PIN 1 ID
1
0.02 MIN
(0.50 MIN)
(4 PLACES)
0.055 - 0.065
(1.40 - 1.65)
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
SEATING PLANE
0.016 - 0.022
(0.40 - 0.56)
0.125 MIN
(3.18 MIN)
0.008 - 0.012
(0.20 - 0.31)
0º - 15º
Package: Q20
20-Pin PLCC
0.385 - 0.395
(9.78 - 10.03)
0.042 - 0.056
(1.07 - 1.42)
0.350 - 0.356
(8.89 - 9.04)
0.025 - 0.045
(0.63 - 1.14)
(RADIUS)
1
0.042 - 0.048
(1.07 - 1.22)
6
PIN 1 ID
16
0.350 - 0.356
(8.89 - 9.04)
0.385 - 0.395
(9.78 - 10.03)
0.200 BSC
(5.08 BSC)
0.290 - 0.330
(7.36 - 8.38)
11
0.009 - 0.011
(0.23 - 0.28)
0.050 BSC
(1.27 BSC)
0.026 - 0.032
(0.66 - 0.81)
0.165 - 0.180
(4.19 - 4.57)
0.146 - 0.156
(3.71 - 3.96)
0.100 - 0.110
(2.54 - 2.79)
0.013 - 0.021
(0.33 - 0.53)
SEATING PLANE
8
REV. 1.0 10/12/2000
ML4823
PHYSICAL DIMENSIONS
inches (millimeters)
Package: S16W
16-Pin Wide SOIC
0.400 - 0.414
(10.16 - 10.52)
16
0.291 - 0.301 0.398 - 0.412
(7.39 - 7.65) (10.11 - 10.47)
PIN 1 ID
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.095 - 0.107
(2.41 - 2.72)
0º - 8º
0.090 - 0.094
(2.28 - 2.39)
0.012 - 0.020
(0.30 - 0.51)
SEATING PLANE
0.005 - 0.013
(0.13 - 0.33)
0.022 - 0.042
(0.56 - 1.07)
0.009 - 0.013
(0.22 - 0.33)
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4823CP
ML4823CQ
ML4823CS
0°C to 70°C
0°C to 70°C
0°C to 70°C
16-Pin PDIP (P16)
20-Pin PLCC (Q20)
20-Pin Wide SOIC (S16W)
ML4823IQ
ML4823IS
ML4823MJ
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
16-Pin PDIP (P16)
20-Pin PLCC (Q20)
16-Pin Wide SOIC (S16W)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
www.fairchildsemi.com
REV. 1.0 10/12/2000
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
© 2000 Fairchild Semiconductor Corporation
9
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