ON MC74HCT595ADTG 8-bit serial-input/serial or parallel-output shift register with latched 3-state outputs and lsttl compatible input Datasheet

MC74HCT595A
8-Bit Serial-Input/Serial or
Parallel-Output Shift
Register with Latched
3-State Outputs and LSTTL
Compatible Inputs
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MARKING
DIAGRAMS
High−Performance Silicon−Gate CMOS
The MC74HCT595A consists of an 8−bit shift register and an 8−bit
D−type latch with three−state parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register also
provides parallel data to the 8−bit latch. The shift register and latch
have independent clock inputs. This device also has an asynchronous
reset for the shift register.
The HCT595A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs. The device inputs are compatible with
standard CMOS or LSTTL outputs.
•
•
•
16
1
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC
Standard No. 7A
Chip Complexity: 328 FETs or 82 Equivalent Gates
Improvements over HC595 / HCT595
− Improved Propagation Delays
− 50% Lower Quiescent Power
− Improved Input Noise and Latchup Immunity
Pb−Free Packages are Available*
HCT595AG
AWLYWW
1
16
16
1
Features
•
•
•
•
•
•
16
SOIC−16
D SUFFIX
CASE 751B
HCT
595A
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
1
A
WL, L
YY, Y
WW, W
G, G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2011
March, 2011 − Rev. 1
1
Publication Order Number:
MC74HCT595A/D
MC74HCT595A
LOGIC DIAGRAM
PIN ASSIGNMENT
SERIAL
DATA
INPUT
A
15
14
1
2
QB
1
16
VCC
3
QC
2
15
QA
4
QD
3
14
A
QE
4
13
OUTPUT ENABLE
QF
5
12
LATCH CLOCK
QG
6
11
SHIFT CLOCK
QH
7
10
RESET
GND
8
9
SQH
SHIFT
REGISTER
LATCH
5
6
7
SHIFT 11
CLOCK
10
RESET
LATCH 12
CLOCK
OUTPUT 13
ENABLE
9
QA
QB
QC
QD
QE
PARALLEL
DATA
OUTPUTS
QF
QG
QH
SQH
SERIAL
DATA
OUTPUT
VCC = PIN 16
GND = PIN 8
ORDERING INFORMATION
Package
Shipping†
MC74HCT595ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HCT595ADR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74HCT595ADTG
TSSOP−16*
96 Units / Rail
MC74HCT595ADTR2G
TSSOP−16*
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HCT595A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
SOIC Package†
TSSOP Package†
_C
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature Range, All Package Types
tr, tf
Input Rise/Fall Time (Figure 1)
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3
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HCT595A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
– 55 to 25_C
v 85_C
v 125_C
Unit
VIH
Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
to
5.5
2.0
2.0
2.0
V
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
to
5.5
0.8
0.8
0.8
V
VOH
Minimum High−Level Output
Voltage, QA − QH
Vin = VIH or VIL
|Iout| v 20 mA
4.5
4.4
4.4
4.4
V
4.5
3.98
3.84
3.7
VOL
Maximum Low−Level Output
Voltage, QA − QH
4.5
0.1
0.1
0.1
4.5
0.26
0.33
0.4
4.5
4.4
4.4
4.4
4.5
3.98
3.84
3.7
4.5
0.1
0.1
0.1
4.5
0.26
0.33
0.4
Symbol
Parameter
Test Conditions
Vin = VIH or VIL
Vin = VIH or VIL
VOH
Minimum High−Level Output
Voltage, SQH
Maximum Low−Level Output
Voltage, SQH
|Iout| v 6.0 mA
Vin = VIH or VIL
IIoutI v 20 mA
Vin = VIH or VIL
VOL
|Iout| v 6.0 mA
Vin = VIH or VIL
|Iout| v 20 mA
IIoutI v 4.0 mA
Vin = VIH or VIL
IIoutI v 20 mA
Vin = VIH or VIL
IIoutI v 4.0 mA
V
V
V
Iin
Maximum Input Leakage
Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
mA
IOZ
Maximum Three−State
Leakage
Current, QA − QH
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
5.5
± 0.5
± 5.0
± 10
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
lout = 0 mA
5.5
4.0
40
160
mA
DICC
Additional Quiescent Supply
Current
Vin = 2.4V, Any One Input
Vin = VCC or GND, Other Inputs
Iout = 0mA
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4
5.5
≥ −55°C
25 to 125°C
2.9
2.4
mA
MC74HCT595A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
VCC
V
Guaranteed Limit
– 55 to 25_C
v 85_C
v 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
4.5 to
5.5
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Shift Clock to SQH
(Figures 1 and 7)
4.5 to
5.5
28
35
42
ns
tPHL
Maximum Propagation Delay, Reset to SQH
(Figures 2 and 7)
4.5 to
5.5
29
36
44
ns
tPLH,
tPHL
Maximum Propagation Delay, Latch Clock to QA − QH
(Figures 3 and 7)
4.5 to
5.5
28
35
42
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to QA − QH
(Figures 4 and 8)
4.5 to
5.5
30
38
45
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to QA − QH
(Figures 4 and 8)
4.5 to
5.5
27
34
41
ns
tTLH,
tTHL
Maximum Output Transition Time, QA − QH
(Figures 3 and 7)
4.5 to
5.5
12
15
18
ns
tTLH,
tTHL
Maximum Output Transition Time, SQH
(Figures 1 and 7)
4.5 to
5.5
15
19
22
ns
Symbol
Parameter
Cin
Maximum Input Capacitance
—
10
10
10
pF
Cout
Maximum Three−State Output Capacitance (Output in
High−Impedance State), QA − QH
—
15
15
15
pF
Typical @ 25°C, VCC = 5.0 V
CPD
300
Power Dissipation Capacitance (Per Package)*
* Used to determine the no−load dynamic power consumption: P D = CPD VCC
2f
pF
+ ICC VCC .
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ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)
Symbol
VCC
V
Parameter
Guaranteed Limit
25_C to –55_C
v 85_C
v 125_C
Unit
tsu
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
4.5 to
5.5
10
13
15
ns
tsu
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
4.5 to
5.5
15
19
22
ns
th
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
4.5 to
5.5
5.0
5.0
5.0
ns
trec
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
4.5 to
5.5
10
13
15
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
4.5 to
5.5
12
15
18
ns
tw
Minimum Pulse Width, Shift Clock
(Figure 1)
4.5 to
5.5
10
13
15
ns
tw
Minimum Pulse Width, Latch Clock
(Figure 6)
4.5 to
5.5
10
13
15
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
4.5 to
5.5
500
500
500
ns
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5
MC74HCT595A
FUNCTION TABLE
Inputs
Operation
Reset
Resulting Function
Serial
Input
A
Shift
Clock
Latch
Clock
Output
Enable
Shift
Register
Contents
Latch
Register
Contents
Serial
Output
SQH
Parallel
Outputs
QA − QH
Reset shift register
L
X
X
L, H, ↓
L
L
U
L
U
Shift data into shift
register
H
D
↑
L, H, ↓
L
D → SRA;
SRN → SRN+1
U
SRG → SRH
U
Shift register remains
unchanged
H
X
L, H, ↓
L, H, ↓
L
U
U
U
U
Transfer shift register
contents to latch
register
H
X
L, H, ↓
↑
L
U
SRN → LRN
U
SRN
Latch register remains
unchanged
X
X
X
L, H, ↓
L
*
U
*
U
Enable parallel outputs
X
X
X
X
L
*
**
*
Enabled
Force outputs into high
impedance state
X
X
X
X
H
*
**
*
Z
SR = shift register contents
LR = latch register contents
D = data (L, H) logic level
U = remains unchanged
↑ = Low−to−High
↓ = High−to−Low
* = depends on Reset and Shift Clock inputs
** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTS
A (Pin 14)
Output Enable (Pin 13)
Active−low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
on this input forces the outputs (QA−QH) into the
high−impedance state. The serial output is not affected by
this control unit.
Serial Data Input. The data on this pin is shifted into the
8−bit serial shift register.
CONTROL INPUTS
Shift Clock (Pin 11)
Shift Register Clock Input. A low− to−high transition on
this input causes the data at the Serial Input pin to be shifted
into the 8−bit shift register.
OUTPUTS
QA − QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Reset (Pin 10)
SQH (Pin 9)
Noninverted, 3−state, latch outputs.
Active−low, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8−bit latch is not affected.
Noninverted, Serial Data Output. This is the output of the
eighth stage of the 8−bit shift register. This output does not
have three−state capability.
Latch Clock (Pin 12)
Storage Latch Clock Input. A low−to−high transition on
this input latches the shift register data.
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6
MC74HCT595A
SWITCHING WAVEFORMS
(VI = 0 to 3 V, VM = 1.3 V)
tr
SHIFT
CLOCK
(VI)
tw
tf
VCC
VCC
90%
VM
10%
tw
RESET
(VI)
GND
1/fmax
OUTPUT
SQH
90%
50%
10%
tTLH
GND
tPHL
50%
OUTPUT
SQH
tPHL
tPLH
VM
trec
VCC
SHIFT
CLOCK
(VI)
tTHL
VM
GND
Figure 1.
LATCH
CLOCK
(VI)
Figure 2.
OUTPUT
ENABLE
VCC
VM
VCC
50%
GND
GND
tPLH
tPHL
OUTPUT Q
OUTPUT Q
tTLH
10%
VOL
90%
VOH
HIGH
IMPEDANCE
tTHL
Figure 4.
VCC
SHIFT
CLOCK
(VI)
VALID
VCC
VM
VM
GND
tsu
GND
LATCH
CLOCK
(VI)
th
VCC
SWITCH
CLOCK
(VI)
tPHZ
50%
Figure 3.
tsu
HIGH
IMPEDANCE
50%
tPZH
90%
QA-QH 50%
OUTPUTS 10%
SERIAL
INPUT A
(VI)
tPLZ
tPZL
VM
VCC
VM
GND
tw
GND
Figure 6.
Figure 5.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 7.
Figure 8.
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7
MC74HCT595A
EXPANDED LOGIC DIAGRAM
OUTPUT
ENABLE
13
LATCH
CLOCK
12
SERIAL
DATA
INPUT A
14
D
Q
D
SRA
Q
15
QA
LRA
R
Q
D
D
SRB
Q
1
QB
LRB
R
Q
D
D
SRC
Q
2
QC
LRC
R
Q
D
D
SRD
Q
3
QD
LRD
PARALLEL
DATA
OUTPUTS
R
Q
D
D
SRE
Q
4
QE
LRE
R
Q
D
D
SRF
Q
5
QF
LRF
R
Q
D
D
SRG
Q
6
QG
LRG
R
SHIFT
CLOCK
Q
D
11
D
SRH
Q
7
QH
LRH
R
RESET
10
9
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8
SERIAL
DATA
OUTPUT SQH
MC74HCT595A
TIMING DIAGRAM
SHIFT
CLOCK
SERIAL DATA
INPUT A
RESET
LATCH
CLOCK
OUTPUT
ENABLE
QA
QB
QC
QD
QE
QF
QG
QH
SERIAL DATA
OUTPUT SQH
NOTE:
implies that the output is in a high−impedance
state.
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9
MC74HCT595A
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
−A
−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
1
−B
−
8
P 8 PL
0.25 (0.010)
M
B
M
G
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
R X 45°
C
−T
SEATING
−
PLANE
J
M
D16PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
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10
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.229 0.244
0.010 0.019
MC74HCT595A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
ÇÇÇ
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
K
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
DETAIL E
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
ON Semiconductor and
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