Intersil ISL84780 Ultra low on-resistance, low voltage, single supply, quad 2:1 analog multiplexer Datasheet

ISL84780
®
Data Sheet
December 27, 2004
Ultra Low ON-Resistance, Low Voltage,
Single Supply, Quad 2:1 Analog
Multiplexer
The Intersil ISL84780 device is a low ON-resistance, low
voltage, bidirectional, Quad SPDT (Dual DPDT) analog
switch designed to operate from a single +1.6V to +3.6V
supply. Targeted applications include battery-powered
equipment that benefit from low on-resistance, and fast
switching speeds (tON = 12ns, tOFF = 8ns). The digital logic
input is 1.8V logic-compatible when using a single +3V supply.
FN6099.1
Features
• Pin Compatible Replacement for the MAX4780
• ON Resistance (RON)
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.36Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.54Ω
• RON Matching between Channels . . . . . . . . . . . . . . . . .0.13Ω
• RON Flatness Across Signal Range . . . . . . . . . . . . . . .0.05Ω
• Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This family of parts may be used to
“mux-in” additional functionality while reducing ASIC design
risk. The ISL84780 is offered in small form factor packages,
alleviating board space limitations.
• Low Power Consumption (PD). . . . . . . . . . . . . . . . . . <0.2µW
The ISL84780 is a committed Quad SPDT that consists of
four normally open (NO) and four normally closed (NC)
switches. This configuration can also be used as a diff dual 2to-1 multiplexer/demultiplexer or a quad 2-to1
multiplexer/demultiplexer. The ISL84780 is pin compatible
with the MAX4780.
• Available in 16 lead 3x3 thin QFN and 16 lead TSSOP
• Fast Switching Action
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns
• Guaranteed Break-Before-Make
• 1.8V Logic Compatible (+3V supply)
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
• Pb-Free Available (RoHS Compliant)
Applications
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
TABLE 1. FEATURES AT A GLANCE
ISL84780
Number of Switches
4
SW
Quad SPDT (Dual DPDT)
3.0V RON
0.36Ω
3.0V tON/tOFF
12ns/8ns
1.8V RON
0.54Ω
1.8V tON/tOFF
19ns/11ns
Packages
16Ld 3x3 TQFN, 16Ld TSSOP
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL84780
Pinouts
Ordering Information
(Note 1)
ISL84780 (TSSOP)
TOP VIEW
IN1-2
1
16 V+
NC1
2
15 IN3-4
NO1
3
14 NC4
COM1
4
13 NO4
NC2
5
12 COM4
NO2
6
11 NC3
COM2
7
10 NO3
GND
8
9 COM3
NC1
IN1-2
V+
IN3-4
ISL84780 (3X3 THIN QFN)
TOP VIEW
16
15
14
13
COM1
2
11
NO4
NC2
3
10
COM4
NO2
4
9
NC3
6
7
8
NO3
NC4
COM3
12
GND
1
COM2
NO1
5
TEMP.
RANGE
(°C)
PART NO.
(BRAND)
PKG.
DWG. #
PACKAGE
ISL84780IR
(780I)
-40 to 85
16 Ld 3x3 Thin QFN
L16.3x3A
ISL84780IR-T
(780I)
-40 to 85
16 Ld 3x3 Thin QFN
Tape and Reel
L16.3x3A
ISL84780IRZ
(780I) (Note)
-40 to 85
16 Ld 3x3 Thin QFN
(Pb-free)
L16.3x3A
ISL84780IRZ-T
(780I) (Note)
-40 to 85
16 Ld 3x3 Thin QFN
L16.3x3A
Tape and Reel (Pb-free)
ISL84780IV
(84780IV)
-40 to 85
16 Ld TSSOP
M16.173
ISL84780IV-T
(84780IV)
-40 to 85
16 Ld TSSOP
Tape and Reel
M16.173
ISL84780IVZ
(84780IV) (Note)
-40 to 85
16 Ld TSSOP
(Pb-free)
M16.173
ISL84780IVZ-T
(84780IV) (Note)
-40 to 85
16 Ld TSSOP
M16.173
Tape and Reel (Pb-free)
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Truth Table
LOGIC
NC SW
NO SW
0
ON
OFF
1
OFF
ON
NOTE:
1. Switches Shown for Logic “0” Input.
NOTE:
Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
Pin Descriptions
PIN
V+
System Power Supply Input (+1.6V to +3.6V)
GND
Ground Connection
IN
Digital Control Input
COM
2
FUNCTION
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
FN6099.1
December 27, 2004
ISL84780
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V
Input Voltages
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA
ESD Rating:
HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
16 Ld 3x3 TQFN Package . . . . . . . . . . . . . . . . . . . .
75
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
150
Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
0
-
V+
V
25
-
0.4
0.6
Ω
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
RON Matching Between Channels,
∆RON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at
max RON, (Note 9)
RON Flatness, RFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(Note 7)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V,
or Floating
Full
-
-
0.7
Ω
25
-
0.13
0.2
Ω
Full
-
-
0.2
Ω
25
-
0.05
0.15
Ω
Full
-
-
0.15
Ω
25
-3
-
3
nA
Full
-20
-
20
nA
25
-4
-
4
nA
Full
-30
-
30
nA
25
-
12
20
ns
Full
-
-
25
ns
25
-
8
14
ns
Full
-
-
17
ns
DYNAMIC CHARACTERISTICS
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 8)
Turn-ON Time, tON
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 8)
Break-Before-Make Time Delay, tD
V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 3, Note 8)
Full
1
3
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
-
-97
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
-
68
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-
-98
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32Ω
25
-
0.002
-
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
62
-
pF
COM ON Capacitance, CCOM(ON)
25
-
125
-
pF
3
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
FN6099.1
December 27, 2004
ISL84780
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6),
Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
1.6
-
3.6
V
25
-
-
0.05
µA
Full
-
-
1.5
µA
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.4
-
-
V
Full
-0.5
-
0.5
µA
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+ (Note 8)
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. Guaranteed not tested.
9. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron
value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4.
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4, 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
0
-
V+
V
25
-
0.54
0.9
Ω
Full
-
-
1
Ω
25
-
19
25
ns
Full
-
-
30
ns
25
-
11
17
ns
Full
-
-
22
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+,
See Figure 5
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.65V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
See Figure 1, Note 8
Turn-OFF Time, tOFF
V+ = 1.65V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
See Figure 1, Note 8
Break-Before-Make Time Delay, tD
V+ = 2.0V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
See Figure 3, Note 8
Full
1
5
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2
25
-
-52
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
See Figure 4
25
-
68
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
See Figure 6
25
-
-98
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
25
-
62
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
25
-
125
-
pF
Input Voltage Low, VINL
Full
-
-
0.4
V
Input Voltage High, VINH
Full
1.0
-
-
V
Full
-0.05
-
0.05
µA
COM ON Capacitance, CCOM(ON)
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+ (Note 8)
4
FN6099.1
December 27, 2004
ISL84780
Test Circuits and Waveforms
V+
V+
LOGIC
INPUT
50%
0V
SWITCH
INPUT
tOFF
VOUT
NO or NC
COM
IN
SWITCH
INPUT VNO
VOUT
90%
SWITCH
OUTPUT
C
tr < 5ns
tf < 5ns
90%
LOGIC
INPUT
CL
35pF
RL
50Ω
GND
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------------R L + R ( ON )
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
RG
∆VOUT
V+
LOGIC
INPUT
ON
ON
C
VG
VOUT
COM
NO or NC
GND
IN
CL
OFF
0V
LOGIC
INPUT
Q = ∆VOUT x CL
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
V+
LOGIC
INPUT
VNX
C
NO
0V
RL
50Ω
IN
SWITCH
OUTPUT
VOUT
VOUT
COM
NC
90%
LOGIC
INPUT
CL
35pF
GND
0V
tD
CL includes fixture and stray capacitance.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
5
FN6099.1
December 27, 2004
ISL84780
Test Circuits and Waveforms (Continued)
V+
V+
C
C
RON = V1/1mA
SIGNAL
GENERATOR
NO or NC
NO or NC
VNX
IN
0V or V+
1mA
COM
COM
ANALYZER
0V or V+
IN
V1
GND
GND
RL
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. RON TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO or NC
COM
50Ω
NO or NC
IN1
IN
0V or V+
NC or NO
COM
ANALYZER
0V or V+
IMPEDANCE
ANALYZER
COM
N.C.
GND
RL
FIGURE 6. CROSSTALK TEST CIRCUIT
GND
FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL84780 is a bidirectional, quad single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.6V to 3.6V supply with low onresistance (0.36Ω) and high speed operation (tON = 12ns,
tOFF = 8ns). The device is especially well suited for portable
battery-powered equipment due to its low operating supply
voltage (1.6V), low power consumption (5.4µW max), low
leakage currents (30nA max), and the tiny TQFN and TSSOP
packages. The ultra low on-resistance and Ron flatness
provide very low insertion loss and distortion to applications
that require signal reproduction.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
6
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ resistor
in series with the input (See Figure 8). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (See Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.
FN6099.1
December 27, 2004
ISL84780
High-Frequency Performance
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNO or NC
VCOM
GND
OPTIONAL PROTECTION
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL84780 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL84780 4.7V
maximum supply voltage provides plenty of room for the
10% tolerance of 3.6V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.6V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
In 50Ω systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 104MHz (See
Figure 15). The frequency response is very consistent over a
wide V+ range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from the switch input to its output. Off Isolation
is the resistance to this feedthrough, while Crosstalk
indicates the amount of feedthrough from one switch to
another. Figure 16 details the high Off Isolation and
Crosstalk rejection provided by this part. At 100kHz, Off
Isolation is about 68dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease Off Isolation and
Crosstalk rejection due to the voltage divider action of the
switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One
of these diodes conducts if any analog signal exceeds V+
or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.0V to 3.6V (See Figure 17). At 3.6V
the VIH level is about 1.27V. This is still below the 1.8V
CMOS guaranteed high output minimum level of 1.4V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
7
FN6099.1
December 27, 2004
ISL84780
Typical Performance Curves TA = 25°C, Unless Otherwise Specified
0.55
0.4
ICOM = 100mA
85°C
0.5
V+ = 1.8V
0.35
RON (Ω)
RON (Ω)
0.45
0.4
25°C
0.3
V+ = 2.7V
0.35
-40°C
V+ = 3V
0.3
V+ = 3.6V
0
1
2
3
0.25
4
V+ = 3V
ICOM = 100mA
0
0.5
1
1.5
2
2.5
3
VCOM (V)
VCOM (V)
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
100
0.6
V+ = 1.8V
ICOM = 100mA
85°C
0.55
50
25°C
V+ = 3V
0.5
0
V+ = 1.8V
Q (pC)
RON (Ω)
-40°C
0.45
-50
0.4
-100
0.35
0.3
-150
0
0.5
1
1.5
0
2
0.5
1
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
2.5
3
20
40
15
30
tOFF (ns)
tON (ns)
2
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
50
85°C 25°C
20
1.5
25°C
-40°C
0
1
85°C
10
5
-40°C
10
0
1.5
VCOM (V)
VCOM (V)
2
2.5
3
V+ (V)
3.5
4
FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE
8
4.5
1
1.5
2
2.5
3
3.5
4
4.5
V+ (V)
FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE
FN6099.1
December 27, 2004
ISL84780
10
-10
0
GAIN
0
PHASE
20
40
60
80
RL = 50Ω
VIN = 0.2VP-P to 2VP-P
1
10
100
100
FREQUENCY (MHz)
CROSSTALK (dB)
-20
-20
20
-30
30
-40
40
-50
50
60
-60
ISOLATION
70
-70
80
-80
CROSSTALK
-90
90
100
-100
-110
1k
600
FIGURE 15. FREQUENCY RESPONSE
OFF ISOLATION (dB)
V+ = 3V
V+ = 3V
PHASE (DEGREES)
NORMALIZED GAIN (dB)
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
10k
100k
1M
10M
FREQUENCY (Hz)
110
100M 500M
FIGURE 16. CROSSTALK AND OFF ISOLATION
1.5
1.4
Die Characteristics
1.3
SUBSTRATE POTENTIAL (POWERED UP):
VINH AND VINL (V)
1.2
GND (QFN Paddle Connection: To Ground or Float)
1.1
TRANSISTOR COUNT:
VINH
1
228
0.9
0.8
PROCESS:
VINL
Si Gate CMOS
0.7
0.6
0.5
0.4
0.3
1
1.5
2
2.5
3
3.5
4
4.5
V+ (V)
FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
9
FN6099.1
December 27, 2004
ISL84780
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
0.25(0.010) M
2
INCHES
E1
GAUGE
PLANE
-B1
B M
MIN
MAX
MIN
MAX
NOTES
A
-
0.043
-
1.10
-
0.05
0.15
-
0.85
0.95
-
A2
L
0.05(0.002)
-A-
SYMBOL
A1
3
A
D
-C-
e
α
c
0.10(0.004)
C A M
B S
0.002
0.0075
0.012
0.19
0.30
9
0.0035
0.008
0.09
0.20
-
D
0.193
0.201
4.90
5.10
3
E1
0.169
0.177
4.30
4.50
4
0.026 BSC
E
0.246
L
0.020
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
0.037
c
N
NOTES:
0.006
0.033
b
e
A2
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
MILLIMETERS
0.65 BSC
0.256
6.25
0.028
0.50
16
0o
-
6.50
0.70
16
8o
0o
6
7
8o
Rev. 1 2/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
10
FN6099.1
December 27, 2004
ISL84780
Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)
)
2X
L16.3x3A
0.15 C A
D
A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
9
D/2
MILLIMETERS
D1
D1/2
2X
N
6
INDEX
AREA
0.15 C B
1
2
3
E1/2
E/2
E1
MIN
NOMINAL
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
A2
-
-
0.80
9
0.30
5, 8
A3
E
b
9
0.20 REF
0.18
D
2X
B
TOP VIEW
0.15 C A
A2
A
D2
/ / 0.10 C
0
C
A3
SIDE VIEW
9
5
NX b
4X P
E
3.00 BSC
-
2.75 BSC
9
1.35
1.50
1.65
7, 8, 10
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
2
8
Nd
4
3
NX k
Ne
4
3
D2
2 N
1
(DATUM A)
2
3
6
INDEX
AREA
E2/2
N e
9
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
SECTION "C-C"
C
L
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
L
L1
10
L
e
TERMINAL TIP
FOR ODD TERMINAL/SIDE
9
12
3. Nd and Ne refer to the number of terminals on each D and E.
A1
e
0.60
-
2. N is the number of terminals.
NX b
10
-
-
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
8
BOTTOM VIEW
C
L
-
θ
NOTES:
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
P
Rev. 0 6/04
(Ne-1)Xe
REF.
E2
7
NX L
C C
7, 8, 10
16
7
L1
9
1.65
N
4X P
8
1.50
0.10 M C A B
D2
(DATUM B)
A1
-
2.75 BSC
1.35
e
SEATING PLANE
9
E1
E2
0.08 C
0.23
3.00 BSC
D1
0.15 C B
2X
4X
SYMBOL
FOR EVEN TERMINAL/SIDE
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2
and D2 MAX dimension.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN6099.1
December 27, 2004
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