AD ADV202BBCZ-115 Jpeg2000 video codec Datasheet

JPEG2000 Video Codec
ADV202
FEATURES
APPLICATIONS
Complete single-chip JPEG2000 compression and
decompression solution for video and still images
Patented SURF™ (spatial ultraefficient recursive filtering)
technology enables low power and low cost wavelet based
compression
Supports both 9/7 and 5/3 wavelet transforms with up to
6 levels of transform
Programmable tile/image size with widths up to 2048 pixels
in 3-component 4:2:2 interleaved mode, and up to
4096 pixels in single-component mode
Maximum tile/image height: 4096 pixels
Video interface directly supporting ITU.R-BT656,
SMPTE125M PAL/ NTSC, SMPTE274M, SMPTE293M (525p),
ITU.R-BT1358 (625p) or any video format with a maximum
input rate of 65 MSPS for irreversible mode or 40 MSPS for
reversible mode
Two or more ADV202s can be combined to support fullframe SMPTE274M HDTV (1080i) or SMPTE296M (720p)
Interlaces temporally coherent frame-based SD video
sources for improved performance
Flexible asynchronous SRAM-style host interface allows
glueless connection to most 16-/32-bit microcontrollers
and ASICs
2.5 V to 3.3 V I/O and 1.5 V core supply
12 mm × 12 mm 121-lead CSPBGA, speed grade 115 MHz, or
13 mm × 13 mm 144-lead CSPBGA, speed grade 150 MHz
Networked video and image distribution systems
Wireless video and image distribution
Image archival/retrieval
Digital CCTV and surveillance systems
Digital cinema systems
Professional video editing and recording
Digital still cameras
Digital camcorders
GENERAL DESCRIPTION
The ADV202 is a single-chip JPEG2000 codec targeted for
video and high bandwidth image compression applications that
can benefit from the enhanced quality and feature set provided
by the JPEG2000 (J2K)—ISO/IEC15444-1 image compression
standard. The part implements the computationally intensive
operations of the JPEG2000 image compression standard as
well as providing fully compliant code-stream generation for
most applications.
The ADV202’s dedicated video port provides glueless
connection to common digital video standards such as ITU.RBT656, SMPTE125M, SMPTE293M [525p], ITU.R-BT1358
[625p], SMPTE274M[1080i], or SMPTE296M[720p]. A variety
of other high speed synchronous pixel and video formats can
also be supported using the programmable framing and
validation signals.
(continued on Page 3)
FUNCTIONAL BLOCK DIAGRAM
ADV202
PIXEL I/F
PIXEL I/F
WAVELET
ENGINE
EC1
EC2
EC3
EXTERNAL
DMA CTRL
PIXEL
FIFO
CODE
FIFO
ATTRIBUTE
FIFO
ANCILLARY
FIFO
INTERNAL BUS AND DMA ENGINE
EMBEDDED RISC
PROCESSOR
SYSTEM
MEMORY
SYSTEM
04723-001
HOST I/F
Figure 1.
Rev. 0
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infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADV202
TABLE OF CONTENTS
General Description ......................................................................... 3
Video Interface (VDATA Bus).................................................. 26
JPEG2000 Feature Support.......................................................... 3
Host Interface (HDATA Bus) ................................................... 26
Specificatons...................................................................................... 4
Direct and Indirect Registers .................................................... 26
Supply Voltages and Current....................................................... 4
Control Access Registers ........................................................... 27
Input/Output Specifications........................................................ 4
Pin Configuration and Bus Sizes/Modes ................................ 27
Clock and RESET Specifications ................................................ 5
Stage Register .............................................................................. 27
Normal Host Mode—Read Operation ...................................... 6
JDATA Mode............................................................................... 27
Normal Host Mode—Write Operation ..................................... 7
External DMA Engine ............................................................... 27
DREQ/DACK DMA Mode—Single FIFO Write Operation .. 8
SPI Port ........................................................................................ 27
DREQ/DACK DMA Mode—Single FIFO Read Operation . 10
Internal Registers............................................................................ 28
External DMA Mode—FIFO Write, Burst Mode................... 12
Direct Registers........................................................................... 28
External DMA Mode—FIFO Read, Burst Mode.................... 13
Indirect Registers........................................................................ 29
Streaming Mode (JDATA)—FIFO Read/Write ...................... 15
PLL ............................................................................................... 30
VDATA Mode Timing ............................................................... 15
Hardware Boot............................................................................ 31
Raw Pixel Mode Timing ............................................................ 17
Video Input Formats ...................................................................... 32
SPI Port Timing .......................................................................... 18
Applications..................................................................................... 34
Pin BGA Assignments and Function Descriptions.................... 19
Encode—Multichip Mode......................................................... 34
Pin BGA Assignments ............................................................... 19
Decode—Multichip Master/Slave ............................................ 35
Pin Function Descriptions ........................................................ 22
Digital Still Camera/Camcorder .............................................. 35
Theory of Operation ...................................................................... 25
Encode/Decode SDTV Video Application.............................. 36
Wavelet Engine ........................................................................... 25
ASIC Application (32-Bit Host/32-Bit ASIC) ......................... 37
Entropy Codecs........................................................................... 25
HIPI (Host Interface—Pixel Interface) ................................... 38
Embedded Processor System .................................................... 25
JDATA Interface ......................................................................... 38
Memory System .......................................................................... 25
Outline Dimensions ....................................................................... 39
Internal DMA Engine ................................................................ 25
Ordering Guide .......................................................................... 40
ADV202 Interface........................................................................... 26
REVISION HISTORY
7/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
ADV202
GENERAL DESCRIPTION
(continued from Page 1)
The ADV202 can process images at a rate of 40MSPS in
reversible mode and at higher rates when used in irreversible
mode. The ADV202 contains a dedicated wavelet transform
engine, three entropy codecs, an on-board memory system, and
an embedded RISC processor that can provide a complete
JPEG2000 compression/decompression solution.
The wavelet processor supports the 9/7 irreversible wavelet
transform and the 5/3 wavelet transform in reversible and
irreversible modes. The entropy codecs support all features in
the JPEG2000 Part 1 specification, except Maxshift ROI.
The ADV202 operates on a rectangular array of pixel samples
called a tile. A tile can contain a complete image, up to the
maximum supported size, or some portion of an image. The
maximum horizontal tile size supported depends on the wavelet
transform selected and the number of samples in the tile.
Images larger than the ADV202’s maximum tile size can be
broken into individual tiles and then sent sequentially to the
chip while still maintaining a single, fully compliant JPEG2000
code stream for the entire image.
JPEG2000 FEATURE SUPPORT
The ADV202 supports a broad set of features that are included
in Part 1 of the JPEG2000 standard (ISO/IEC 15444). See
Getting Started with ADV202 for information on the JPEG2000
features that the ADV202 currently supports.
Depending on the particular application requirements, the
ADV202 can provide varying levels of JPEG2000 compression
support. It can provide raw code-block and attribute data
output, which allows the host software to have complete control
over the generation of the JPEG2000 code stream and other
aspects of the compression process such as bit-rate control.
Otherwise, the ADV202 can create a complete, fully compliant
JPEG2000 code stream (.j2c) and enhanced file formats such as
.jp2, .jpx, and .mj2 (Motion JPEG2000). See Getting Started with
ADV202 for information on the formats that the ADV202
currently supports.
Rev. 0 | Page 3 of 40
ADV202
SPECIFICATONS
SUPPLY VOLTAGES AND CURRENT
Table 1.
Parameter
VDD
IOVDD
PLLVDD
VInput
Temp
IDD
1
2
Description
DC Supply Voltage, Core
DC Supply Voltage, I/O
DC Supply Voltage, PLL
Input Range
Operating Ambient Temperature Range in Free Air
Static Current1
Dynamic Current, Core (JCLK Frequency = 150 MHz)2
Dynamic Current, Core (JCLK Frequency = 108 MHz)
Dynamic Current, Core (JCLK Frequency = 81 MHz)
Dynamic Current, I/O
Dynamic Current, PLL
Min
1.425
2.375
1.425
−0.3
−40
Typ
1.5
3.3
1.5
+25
Max
1.575
3.63
1.575
VDDI/O + 0.3
+85
300
570
420
325
20
2.6
Unit
V
V
V
V
°C
mA
mA
mA
mA
mA
mA
No clock or I/O activity.
ADV202-150 only.
INPUT/OUTPUT SPECIFICATIONS
Table 2.
Parameter
VIH (3.3 V)
VIH (2.5 V)
VIL (3.3 V, 2.5 V)
VOH (3.3 V)
VOH (2.5 V)
VOL (3.3 V, 2.5 V)
IIH
IIL
IOZH
IOZL
IDD
IDD
CI
CO
Description
High Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hi-Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
High Level Three-State Leakage Current
Low Level Three-State Leakage Current
Supply Current (Power Down)
Supply Current (Active)
Input Pin Capacitance
Output Pin Capacitance
Test Conditions
VDD = max
VDD = max
VDD = min
VDD = min, IOH = −0.5 mA
VDD = min, IOH = −0.5 mA
VDD = min, IOL = 2 mA
VDD = max, VIN = VDD
VDD = max, VIN = 0V
VDD = max, VIN = VDD
VDD = max, VIN = 0V
VDD = max
VDD = max
Rev. 0 | Page 4 of 40
Min
2.2
1.9
Typ
Max
0.6
2.4
2.0
0.4
1.0
1
1.0
1.0
100
100
8
8
Unit
V
V
V
V
V
V
µA
µA
µA
µA
µA
mA
pF
pF
ADV202
CLOCK AND RESET SPECIFICATIONS
Table 3.
Parameter
tMCLK
tMCLKL
tMCLKH
tVCLK
tVCLKL
tVCLKH
tRST
Min
13.3
6
6
13.4
5
5
5
Typ
Max
100
Unit
ns
ns
ns
ns
ns
ns
MCLK cycles1
50
For a definition of MCLK, see the PLL section.
tMCLK
tMCLKL
tMCLKH
MCLK
tVCLK
tVCLKL
tVCLKH
04723-010
1
Description
MCLK Period
MCLK Width Low
MCLK Width High
VCLK Period
VCLK Width Low
VCLK Width High
RESET Width Low
VCLK
Figure 2. Input Clock
Rev. 0 | Page 5 of 40
ADV202
NORMAL HOST MODE—READ OPERATION
Table 4.
Parameter
tACK [dir]
Description
RD to ACK, Direct Registers and FIFO Accesses
Min
5 ns
tACK [indir]
RD to ACK, Indirect Registers
10.5 × JCLK
15.5 × JCLK + 7.0 ns
tDRD [dir]
tDRD [indir]
tHZRD
tSC
tSA
tHC
tHA
tRH
tRL
tRCYC
Read Access Time, Direct Registers
Read Access Time, Indirect Registers
Data Hold
CS to RD Setup
Address Setup
CS Hold
Address Hold
Read Inactive Pulse Width
Read Active Pulse Width
Read Cycle Time, Direct Registers
5 ns
10.5 × JCLK
2
0
2
0
2
2.5
2.5
5.0
1.5 × JCLK + 7.0 ns
15.5 × JCLK + 7.0 ns
8.5
Max
1.5 × JCLK + 7.0 ns
For a definition of JCLK, see the PLL section.
tSA
tHA
ADDR
tSC
tHC
CS
tRCYC
tRL
tRH
RD
tACK
ACK
tDRD
HDATA
tHZRD
VALID
Figure 3. Normal Host Mode—Read Operation
Rev. 0 | Page 6 of 40
04723-011
1
Typ
Unit
ns
ns
ns
ns
ns
JCLK 1
JCLK
JCLK
ADV202
NORMAL HOST MODE—WRITE OPERATION
Table 5.
Parameter
tACK (Direct)
Description
WE to ACK, Direct Registers and FIFO Accesses
Min
5
tACK (Indirect)
WE to ACK, Indirect Registers
5
tSD
tHD
tSA
tHA
tSC
tHC
tWH
tWL
tWCYC
Data Setup
Data Hold
Address Setup
Address Hold
CS to WE Setup
CS Hold
Write Inactive Pulse Width (Minimum Time until Next WE Pulse)
Write Active Pulse Width
Write Cycle Time
3.0
1.5
2
2
0
0
2.5
2.5
5
Max
1.5 × JCLK + 7.0 ns
Unit
ns
2.5 × JCLK + 7.0 ns
ns
ns
ns
ns
ns
ns
ns
JCLK1
JCLK
JCLK
For a definition of JCLK, see the PLL section.
tSA
tHA
ADDR
tSC
tHC
CS
tWCYC
tWL
tWH
WE
tACK
ACK
tHD
tSD
HDATA
04723-012
1
Typ
VALID
Figure 4. Normal Host Mode—Write Operation
Rev. 0 | Page 7 of 40
ADV202
DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION
Table 6.
Parameter
DREQPULSE1
tDREQ
Description
DREQ Pulse Width
DACK Assert to Subsequent DREQ Delay
2.5
tWESU
WE to DACK Setup
0
ns
tSU
tHD
DACKLO
DACKHI
tWEHD
Data to DACK Deassert Setup
Data to DACK Deassert Hold
DACK Assert Pulse Width
DACK Deassert Pulse Width
2
2
2
2
ns
ns
JCLK cycles
JCLK cycles
WE Hold after DACK Deassert
0
ns
WFSRQ
tDREQRTN
WE Assert to FSRQ Deassert (FIFO Full)
1.5
2.5 × JCLK + 7.5 ns
JCLK cycles
DACK to DREQ Deassert (DR × PULS = 0)
2.5
3.5 × JCLK + 7.5 ns
JCLK cycles
Max
15
Unit
JCLK cycles2
3.5 × JCLK + 7.5 ns
JCLK cycles
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is not 0. Pulse width depends on the value programmed.
For a definition of JCLK, see the PLL section.
DREQPULSE
tDREQ
DREQ
DACKHI
DACKLO
DACK
tWESU
tWEHD
WE
tHD
tSU
0
HDATA
1
2
3
04723-013
2
Typ
Figure 5. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000)
tDREQRTN
DREQ
DACKHI
DACKLO
DACK
tWESU
tWEHD
WE
tHD
tSU
HDATA
0
1
2
Figure 6. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
Rev. 0 | Page 8 of 40
04723-014
1
Min
1
ADV202
DREQPULSE
tDREQ
DREQ
DACKHI
DACKLO
DACK
tWESU
tWEHD
WEFB
tHD
0
HDATA
1
04723-015
tSU
2
Figure 7. Fly-By DMA Mode —Single Write Cycle (DREQ Pulse Width Is Programmable)
FSC0
WE
WFSRQ
FIFO NOT FULL
HDATA
0
1
2
NOT WRITTEN TO FIFO
Figure 8. DCS DMA Mode—Single Write Access (Rev. 0.1 and Higher)
Rev. 0 | Page 9 of 40
04723-016
FIFO FULL
FSRQ0
ADV202
DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION
Table 7.
Parameter
DREQPULSE
tDREQ
Description
DREQ Pulse Width1
DACK Assert to Subsequent DREQ Delay
Min
1
2.5
tRDSU
RD to DACK Setup
0
tRD
DACK to Data Valid
2.5
tHD
DACKLO
DACKHI
tRDHD
Data Hold
DACK Assert Pulse Width
DACK Deassert Pulse Width
RD Hold after DACK Deassert
1.5
2
2
0
RDFSRQ
tDREQRTN
RD Assert to FSRQ Deassert (FIFO Empty)
DACK to DREQ Deassert (DR × PULS = 0)
1.5
2.5
11
ns
ns
JCLK cycles
JCLK cycles
ns
2.5 × JCLK + 7.5 ns
3.5 × JCLK + 7.5 ns
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.
For a definition of JCLK, see the PLL section.
DREQPULSE
tDREQ
DREQ
DACKHI
DACKLO
DACK
tRDHD
tRDSU
RD
tRD
HDATA
tHD
0
1
2
Figure 9. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000)
tDREQRTN
DREQ
DACKHI
DACKLO
DACK
tRDHD
tRDSU
RD
tRD
HDATA
tHD
0
1
2
Figure 10. Single Read forDREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
Rev. 0 | Page 10 of 40
Unit
JCLK cycles2
JCLK cycles
ns
04723-018
2
Max
15
3.5 × JCLK + 7.5 ns
04723-019
1
Typ
JCLK cycles
JCLK cycles
ADV202
DREQPULSE
tDREQ
DREQ
DACKHI
DACKLO
DACK
tRDSU
tRDHD
tRD
tHD
0
HDATA
1
2
04723-020
RDFB
Figure 11. Fly-By DMA Mode—Single Read Cycle
(DREQ Pulse Width Is Programmable)
FCS0
RD
RDFSRQ
FIFO NOT EMPTY
FIFO EMPTY
HDATA
0
1
Figure 12. DCS DMA Mode—Single Read Access (Rev. 0.1 and Higher)
Rev. 0 | Page 11 of 40
04723-021
FSRQ0
ADV202
EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Table 8.
Parameter
DREQPULSE
tDREQRTN
Desription
DREQ Pulse Width1
DACK to DREQ Deassert (DR × Pulse = 0)
Min
1
2.5
Typ
Max
15
3.5 × JCLK + 7.5 ns
Unit
JCLK cycles2
JCLK cycles
tDACKSU
DACK to WE Setup
0
ns
tSU
tHD
WELO
WEHI
tDREQWAIT
Data Setup
Data Hold
WE Assert Pulse Width
WE Deassert Pulse Width
DACK Deassert to Next DREQ
2.5
2
1.5
1.5
2.5
ns
ns
JCLK cycles
JCLK cycles
JCLK cycles
4.5 × JCLK + 7.5 ns3
1
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is NOT 0. Pulse width depends on the value programmed.
For a definition of JCLK, see the PLL section.
3
If sufficient space is available in FIFO.
2
DREQPULSE
tDREQWAIT
DREQ
DACK
tDACKSU
WELO
WEHI
WE
tHD
HDATA
0
1
13
14
04723-022
tSU
15
Figure 13. Burst Write Cycle forDREQ/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000)
tDREQRTN
tDREQWAIT
DREQ
DACK
tDACKSU
WELO
WEHI
WE
HDATA
0
1
13
14
15
Figure 14. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
Rev. 0 | Page 12 of 40
04723-023
tHD
tSU
ADV202
tDREQRTN
tDREQWAIT
DREQ
DACK
tDACKSU
WELO
WEHI
WEFB
tHD
0
HDATA
1
13
14
04723-024
tSU
15
Figure 15. Burst Write Cycle for Fly-By DMA Mode
(DREQ Pulse Width Is Programmable)
EXTERNAL DMA MODE—FIFO READ, BURST MODE
Table 9.
Parameter
DREQPULSE
tDREQRTN
Description
DREQ Pulse Width1
Min
1
DACK to DREQ Deassert (DR × PULS = 0)
2.5
tDACKSU
DACK to RD Setup
0
tRD
DACK to Data Valid
Data Hold
RD Assert Pulse Width
RD Deassert Pulse Width
DACK Deassert to Next DREQ
2.5
2.5
1.5
1.5
9.7
ns
ns
JCLK cycles
JCLK cycles
2.5
3.5 × JCLK + 7.5 ns3
JCLK cycles
tHD
RDLO
RDHI
tDREQWAIT
Typ
Max
15
Unit
JCLK cycles2
3.5 × JCLK + 7.5 ns
JCLK cycles
ns
1
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is not 0. Pulse width depends on the value programmed.
For a definition of JCLK, see the PLL section.
3
If sufficient data is available in FIFO.
2
DREQPULSE
tDREQWAIT
DREQ
DACK
tDACKSU
RDLO
RDHI
RD
0
HDATA
1
13
14
15
tRD
Figure 16. Burst Read Cycle for DREQ/DACK DMA Mode for Assigned DMA Channel
(EMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0
Rev. 0 | Page 13 of 40
04723-025
tHD
ADV202
tDREQRTN
tDREQWAIT
DREQ
DACK
tDACKSU
RDLO
RDHI
RD
0
HDATA
1
13
14
04723-026
tHD
15
tRD
Figure 17. Burst Read Cycle for DREQ/DACK DMA Mode for Assigned DMA Channel
( EMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
tDREQRTN
tDREQWAIT
DREQ
DACK
tDACKSU
RDFB
0
HDATA
1
13
14
tRD
Figure 18. Burst Read Cycle, Fly-By DMA Mode
(DREQ Pulse Width Is Programmable)
Rev. 0 | Page 14 of 40
15
04723-027
tHD
ADV202
STREAMING MODE (JDATA)—FIFO READ/WRITE
Table 10.
Parameter
JDATATD
VALIDTD
HOLDSU
HOLDHD
JDATASU
JDATAHD
1
Description
MCLK to JDATA Valid
MCLK to VALID Assert/ Deassert
HOLD Setup to Rising MCLK
HOLD Hold from Rising MCLK
JDATA Setup to Rising MCLK
JDATA Hold from Rising MCLK
Min
1.5
1.5
3
3
3
3
Typ
Max
2.5 × JCLK + 7.0 ns
2.5 × JCLK + .7.0 ns
Unit
JCLK cycles1
JCLK cycles
ns
ns
ns
ns
For a definition of JCLK, see the PLL section.
MCLK
JDATATD
JDATAHD
JDATA
VALIDTD
JDATASU
VALID
HOLDSU
04723-028
HOLDHD
HOLD
Figure 19. Streaming Mode Timing—Encode Mode JDATA Output
MCLK
JDATASU
JDATAHD
JDATA
VALIDTD
VALID
HOLDHD
04723-029
HOLDSU
HOLD
Figure 20. Streaming Mode Timing—Decode Mode JDATA Input
VDATA MODE TIMING
Table 11.
Parameter
VDATATD
VDATASU
VDATAHD
HSYNCSU
HSYNCHD
HSYNCTD
VSYNCSU
VSYNCHD
VSYNCTD
FIELDSU
Description
VCLK to VDATA Valid Delay (VDATA Output)
VDATA Setup to Rising VCLK (VDATA Input)
VDATA Hold from Rising VCLK (VDATA Input)
HSYNC Setup to Rising VCLK
HSYNC Hold from Rising VCLK
VCLK to HSYNC Valid Delay
VSYNC Setup to Rising VCLK
VSYNC Hold from Rising VCLK
VCLK to VSYNC Valid Delay
FIELD Setup to Rising VCLK
Rev. 0 | Page 15 of 40
Min
Typ
Max
12
4
4
3
4
12
3
4
12
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADV202
Parameter
FIELDHD
FIELDTD
SYNC DELAY
Description
FIELD Hold from Rising VCLK
VCLK to FIELD Valid
Decode Data Sync Delay for HD Input with EAV/SAV Codes
Decode Data Sync Delay for SD Input with EAV/SAV Codes
Decode Data Sync Delay for DUAL_LANE (Extended) Input
Decode Data Sync Delay for HVF Input (from First Rising VCLK after
HSYNC Low to First Data Sample)
Min
3
Typ
Max
Unit
ns
12
7
9
7
10
VCLK cycles
VCLK cycles
VCLK cycles
VCLK cycles
VCLK
VDATAHD
VDATASU
VDATA(IN)
Cr
Y
Cb
Y
FF
EAV
FF
SAV
Cb
Y
Cr
SAV
Cb
ENCODE CCIR-656 LINE
VCLK
VDATATD
VDATA(OUT)
Cr
Y
Cb
Y
FF
EAV
FF
Y
Cr
DECODE MASTER CCIR-656 LINE
VCLK
VDATATD
VDATA(OUT)
Y
Cr
Y
SYNC DELAY
Cb
Y
FF
EAV
FF
SAV
Cb
Y
DECODE SLAVE CCIR-656 LINE
VCLK
VDATATD
Cb
VDATA(OUT)
Y
Cr
SYNC DELAY
Y
Cb
Y
Cb
Y
Cr
Y
Cb
HSYNCHD*
HSYNC
VSYNCHD*
VSYNC
DECODE SLAVE HVF MODE
VCLK
VDATA(IN)
Y
Cr
Y
Cb
Y
Cr
Y
Cb
Y
Cb
Y
HSYNCSU
HSYNCHD
VSYNCSU
ENCODE HVF MODE
*HSYNC AND VSYNC DO NOT HAVE TO BE APPLIED SIMULTANEOUSLY
VSYNCHD
Cr
Y
Cb
HSYNC
Figure 21. Video Mode Timing
Rev. 0 | Page 16 of 40
04723-030
VSYNC
ADV202
RAW PIXEL MODE TIMING
Table 12.
Description
VCLK to PIXELDATA Valid Delay (PIXELDATA Output)
PIXELDATA Setup to Rising VCLK (PIXELDATA Input)
PIXELDATA Hold from Rising VCLK (PIXELDATA Input)
VCLK to VRDY Valid Delay
VFRM Setup to Rising VCLK (VFRAME Input)
VFRM Hold from Rising VCLK (VFRAME Input)
VCLK to VFRM Valid Delay (VFRAME Output)
VSTRB Setup to Rising VCLK
VSTRB Hold from Rising VCLK
Min
Typ
Max
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
4
12
3
4
12
4
3
VCLK
VDATAHD
VDATASU
PIXEL
DATA(IN)
N–1
N
0
1
2
VFRMHD
VFRMSU
VFRM(IN)
VRDYTD
VRDY
VSTRBHD
VSTRBSU
VSTRB
VCLK
VDATATD
PIXEL
DATA
N
N
0
1
2
VRFMTD
04723-031
Parameter
VDATATD
VDATASU
VDATAHD
VRDYTD
VFRMSU
VFRMHD
VFRMTD
VSTRBSU
VSTRBHD
VFRM(OUT)
Figure 22. Raw Pixel Mode Timing
Rev. 0 | Page 17 of 40
ADV202
SPI PORT TIMING
Table 13.
Description
S_CLK Fall Time
S_CLK Rise Time
SCLK high time
SCLK Low Time
Data Setup Time
Data Hold Time
Active Setup Time
Active Hold Time
SCLK to Output Data Valid
CS to Output Data Valid
SCLK Period
Min
Typ
5
5
75
75
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.5
6.5
135
155
2
36
150
S_CLK
SCLK_LO
SCLKRISE
SCLKFALL
SCLK_HI
MSB
S_MO
LSB
DV_SCLK
S_MI
MSB
LSB
DATASU
S_CSEL
DATAHD
CSELSU
DC_CS
CSELHD
Figure 23. SPI Port—Input Timing
Rev. 0 | Page 18 of 40
04723-032
Parameter
SCLKFALL
SCLKRIS
SCLK_hi
SCLK_lo
Data_su
Data_hd
CSEL_SU
CSEL_HD
DV_SCLK
DV_CS
SCLK
ADV202
PIN BGA ASSIGNMENTS AND FUNCTION DESCRIPTIONS
PIN BGA ASSIGNMENTS
Table 14. Pin BGA Assignments for 121-Lead Package
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Pin Location
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
E1
E2
E3
E4
E5
Pin Description
DGND
HDATA[2]
VDD
DGND
HDATA[0]
HDATA[1]
VDATA[1]
VDD
DGND
VDATA[0]
DGND
HDATA[3]
HDATA[4]
HDATA[5]
HDATA[7]
HDATA[8]
IOVDD
VDATA[6]
VDATA[5]
VDATA[4]
VDATA[2]
VDATA[3]
DGND
HDATA[6]
HDATA[9]
HDATA[10]
HDATA[11]
IOVDD
VDATA[9]
IOVDD
VDATA[8]
VDATA[7]
DGND
HDATA[12]
HDATA[13]
HDATA[14]
HDATA[15]
IOVDD
DGND
VDD
VSYNC
HSYNC
VDATA[10]
VDATA[11]
DGND
HDATA[18]_VDATA[14]
HDATA[17]_VDATA[13]
HDATA[16]_VDATA[12]
DGND
Pin No.
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
Rev. 0 | Page 19 of 40
Pin Location
E6
E7
E8
E9
E10
E11
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
J1
J2
J3
J4
J5
J6
J7
J8
J9
Pin Description
DGND
DGND
IOVDD
VCLK
FIELD
DGND
DGND
HDATA[19]_VDATA[15]
HDATA[20]_VDATA[16]
HDATA[21]_VDATA[17]
DGND
DGND
DGND
DREQ0
DACK0
DREQ1
DGND
DGND
HDATA[22]_VDATA[18]
HDATA[23]_VDATA[19]
HDATA[24]_VDATA[20]_JDATA[0]
DGND
DGND
DGND
IOVDD
DACK1
IRQ
DGND
HDATA[28]_JDATA[4]
HDATA[27]_VDATA[23]_JDATA[3]
HDATA[26]_VDATA[22]_JDATA[2]
HDATA[25]_VDATA[21]_JDATA[1]
IOVDD
DGND
VDD
ACK
RD
ADDR[1]
ADDR[3]
DGND
HDATA[31]_JDATA[7]
HDATA[30]_JDATA[6]
HDATA[29]_JDATA[5]
IOVDD
TEST1
WE
CS
ADDR[0]
ADV202
Pin No.
98
99
100
101
102
103
104
105
106
107
108
109
Pin Location
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
Pin Description
TEST3
DGND
SCOMM[4]
SCOMM[3]
SCOMM[0]
SCOMM[1]
IOVDD
IOVDD
IOVDD
ADDR[2]
TEST2
TEST5
Pin No.
110
111
112
113
114
115
116
117
118
119
120
121
Pin Location
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
Pin Description
DGND
DGND
SCOMM[7]
SCOMM[6]
SCOMM[5]
SCOMM[2]
TEST4
RESET
DGND
MCLK
PLLVDD
DGND
Pin No.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Pin Location
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
G1
Pin Description
HDATA[10]
HDATA[9]
IOVDD
DGND
VDD
VDD
DGND
IOVDD
VDATA[11]
VDATA[10]
VDATA[9]
HDATA[14]
HDATA[13]
HDATA[12]
DGND
DGND
DGND
DGND
DGND
FIELD
VSYNC
HSYNC
VCLK
HDATA[18]_VDATA[14]
HDATA[17]_VDATA[13]
HDATA[16]_VDATA[12]
HDATA[15]
DGND
DGND
DGND
DGND
DACK1
DREQ1
DACK0
DREQ0
HDATA[22]_VDATA[18]
Table 15. Pin BGA Assignments for 144-Lead Package
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Pin Location
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
Pin Description
DGND
HDATA[2]
HDATA[1]
HDATA[0]
DGND
DGND
DGND
DGND
VDATA[2]
VDATA[1]
VDATA[0]
DGND
HDATA[5]
HDATA[4]
HDATA[3]
IOVDD
DGND
VDD
VDD
DGND
IOVDD
VDATA[5]
VDATA[4]
VDATA[3]
HDATA[8]
HDATA[7]
HDATA[6]
IOVDD
DGND
VDD
VDD
DGND
IOVDD
VDATA[8]
VDATA[7]
VDATA[6]
HDATA[11]
Rev. 0 | Page 20 of 40
ADV202
Pin No.
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
Pin Location
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
K1
Pin Description
HDATA[21]_VDATA[17]
HDATA[20]_VDATA[16]
HDATA[19]_VDATA[15]
DGND
DGND
DGND
DGND
DGND
IRQ
ACK
RD
HDATA[26]_VDATA[22]_JDATA[2]
HDATA[25]_VDATA[21]_JDATA[1]
HDATA[24]_VDATA[20]_JDATA[0]
HDATA[23]_VDATA[19]
DGND
DGND
DGND
DGND
DGND
WR
CS
ADDR[0]
HDATA[30]_JDATA[6]
HDATA[29]_JDATA[5]
HDATA[28]_JDATA[4]
HDATA[27]_VDATA[23]_JDATA[3]
DGND
VDD
VDD
DGND
DGND
ADDR[1]
ADDR[2]
ADDR[3]
SCOMM[1]
Pin No.
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Rev. 0 | Page 21 of 40
Pin Location
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
Pin Description
SCOMM[0]
HDATA[31]_JDATA[7]
IOVDD
DGND
VDD
VDD
DGND
IOVDD
TEST3
TEST2
TEST1
SCOMM[4]
SCOMM[3]
SCOMM[2]
IOVDD
DGND
VDD
VDD
DGND
IOVDD
TEST5
RESET
MCLK
DGND
SCOMM[7]
SCOMM[6]
SCOMM[5]
DGND
DGND
DGND
DGND
TEST4
PLLVDD
DGND
DGND
ADV202
PIN FUNCTION DESCRIPTIONS
Table 16.
Mnemonic
MCLK
Pins
Used
1
121-Pin
Package
L9
144-Pin
Package
L12
I/O
I
RESET
1
L7
L11
I
HDATA<15:0>
16
D4–D1, C5–
C3, B5, B4, C2,
B3–B1, A2,
A6–A5
F4, E1–E3,
D1–D3, C1–
C3, B1–B3, A2,
A3, A4
I/O
ADDR<3:0>
4
1
J12, J11, J10,
H12
H11
I
CS
H11, K8, H10,
J9
J8
WE
RDFB
1
J7
H10
I
RD
WEFB
1
H9
G12
I
ACK
1
H8
G11
O
IRQ
1
G10
G10
O
DREQ0
1
F8
F12
O
I
FSRQ0
O
VALID
O
CFG<1>
I
DACK0
1
F9
F11
I
Description
System Input Clock. For details, see the PLL section. Maximum input
frequency on MCLK is 74.25 MHz.
Reset. Causes the ADV202 to immediately reset. CS, RD, WE, DACK0,
DACK1, DREQ0, and DREQ1 must be held high when a RESET is
applied.
Host Data Bus. With HDATA<23:16>, <27:24>, <31:28>, these pins
make up the 32-bit wide host data bus. The async host interface is
interfaced together with ADDR<3:0>, CS, WE, RD, and ACK.
Unused HDATA pins should be pulled down via a 10 kΩ resistor.
Address Bus for the Host Interface.
Chip Select.This signal is used to qualify addressed read and write
access to the ADV202 using the host interface.
Write Enable Used with the Host Interface.
Read Enable when Fly-By DMA Is Enabled.
Note: Simultaneous assertion of WE and DACK low activates the
HDATA bus, even if the DMA channels are disabled.
Read Enable Used with the Host Interface.
Write Enable when Fly-By DMA Is Enabled.
Note: Simultaneous assertion of RD and DACK low activates the
HDATA bus, even if the DMA channels are disabled.
Acknowledge. Used for direct register accesses. This signal indicates
that the last register access was successful.
Note: Due to synchronization issues, control and status register
accesses might incur an additional delay, so the host software should
wait for acknowledgment from the ADV202.
Accesses to the FIFOs (external DMA modes), on the other hand, are
guaranteed to occur immediately, provided that space is available,
and should not wait for ACK, provided that the timing constraints
are observed.
If ACK is shared with more than one device, ACK should be connected
to a pull-up resistor (10 kΩ) and the PLL_HI register, Bit 4, must be set
to 1.
Interrupt. This pin indicates that the ADV202 requires the attention of
the host processor. This pin can be programmed to indicate the status
of the internal interrupt conditions within the ADV202. The interrupt
sources are enabled via bits in register EIRQIE.
Data Request for external DMA Interface. Indicates that the ADV202
is ready to send/receive data to/from the FIFO assigned to DMA
Channel 0.
Used in DCS-DMA Mode. Service request from the FIFO assigned to
Channel 0 (asynchronous mode).
Valid Indication for JDATA Input/Output Stream. Polarity of this pin is
programmable in the EDMOD0 register. VALID is always an output.
Boot Mode Configuration. This pin is read on reset to determine the
boot configuration of the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 kΩ resistor.
Data Acknowledge for External DMA Interface. Signal from the host
CPU, which indicates that the data transfer request (DREQ0) has been
acknowledged and data transfer can proceed. This pin must be held
high at all times, if the DMA interface is not used, even if the DMA
channels are disabled.
Rev. 0 | Page 22 of 40
ADV202
Mnemonic
HOLD
Pins
Used
121-Pin
Package
144-Pin
Package
I
FCS0
DREQ1
I/O
I
1
F10
F10
O
FSRQ1
O
CFG<2>
I
DACK1
1
G9
F9
I
FCS1
HDATA<31:28>
JDATA<7:4>
HDATA<27:24>
JDATA<3:0>
VDATA<23:20>
HDATA<23:16>
4
J2–J4, H1
K3, J1–J3
4
H2–H4, G4
J4, H1–H3
8
G3, G2, F4, F3,
F2 E2, E3, E4
H4, G1–G4,
F1–F3
VDATA<19:12>
SCOMM<7>
SCOMM<6>
SCOMM<5>
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
L2
L3
L4
M2
M3
M4
I/O
I/O
I/O
SCOMM<4>
K1
L1
O
SCOMM<3>
K2
L2
O
SCOMM<2>
L5
L3
O
SCOMM<1>
K4
K1
I
SCOMM<0>
K3
K2
O
VCLK
1
E9
E12
I
VDATA<11:0>
12
D11, D10, C7,
C9, C10, B7,
B8, B9, B11,
B10, A7, A10
D10–D12,
C10–C12,
B10–B12,
A9–A11
I/O
Description
External Hold Indication for JDATA Input/Output Stream. Polarity is
programmable in the EDMOD0 register. This pin is always an input.
Used in DCS-DMA Mode. Chip select for the FIFO assigned to
Channel 0 (asynchronous mode).
Data Request for External DMA Interface. Indicates that the ADV202
is ready to send/receive data to/from the FIFO assigned to DMA
Channel 1.
Used in DCS-DMA Mode. Service request from the FIFO assigned to
Channel 1 (asynchronous mode).
Boot Mode Configuration. This pin is read on reset to determine the
boot configuration of the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 kΩ resistor.
Data Acknowledge for External DMA Interface. Signal from the host
CPU, which indicates that the data transfer request (DREQ1) has been
acknowledged and data transfer can proceed. This pin must be held
high at all times unless a DMA or JDATA access is occurring. This pin
must be held high at all times, if the DMA interface is not used, even if
the DMA channels are disabled.
Used in DCS-DMA Mode. Chip select for the FIFO assigned to
Channel 1 (asynchronous mode).
Host Expansion Bus.
JDATA Bus (JDATA Mode).
Host Expansion Bus.
JDATA Bus (JDATA Mode).
Video Data Expansion Bus.
Host Expansion Bus.
Video Data Expansion Bus. Extended pixel interface mode. Used for
video formats that use Y and CrCb on separate buses.
When not used, this pin should be tied low.
When not used, this pin should be tied low.
This pin must be used in multiple chip mode to align the outputs of
two or more ADV202s. For details, see the Applications section and
the ADV202 Multichip Application application note. When not used,
this pin should be tied low.
LCODE Output in Encode Mode. When LCODE is enabled, the output
on this pin indicates on a high transition that the last data-word for a
field has been read from the FIFO. For an 8-bit interface, such as
JDATA, LCODE is asserted for four consecutive bytes and is enabled
by default.
SPI interface: S_CSEL. When not used, this pin should be tied low.
Used only with boot mode 6.
SPI interface: S_MO. When not used, this pin should be tied low.
Used only with boot mode 6.
SPI interface: S_MI. When not used, this pin should be tied low.
Used only with boot mode 6.
SPI interface: S_CLK. When not used, this pin should be tied low.
Used only with boot mode 6.
Video Data Clock. Must be supplied, if video data is input/output on
the VDATA bus.
Video Data. Unused pins should be pulled down via a 10 kΩ resistor.
Rev. 0 | Page 23 of 40
ADV202
Mnemonic
VSYNC
VFRM
HSYNC
VRDY
FIELD
VSTRB
TEST1
TEST2
TEST3
TEST4
TEST5
VDD
Pins
Used
1
121-Pin
Package
D8
144-Pin
Package
E10
1
D9
E11
1
E10
E9
1
1
1
1
1
J6
K9
J10
L6
K10
A3, A8, D7, H7
K12
K11
K10
M9
L10
B6, B7, C6, C7,
D6, D7, J6, J7,
K6, K7, L6, L7
A1, A5–A8,
A12, B5, B8,
C5, C8, D5, D8,
E4–E8, F5–F8,
G5–G9, H5–
H9, J5, J8–J9,
K5, K8, L5, L8,
M1, M5–M8,
M11, M12
M10
B4, B9, C4, C9,
D4, D9, K4, K9,
L4, L9
DGND
PLLVDD
IOVDD
1
A1, A11, A4,
A9, C1, C11,
D6, E1, E5–E7,
E11, F1, F5–
F7, F11, G1,
G5–G7, G11,
H6, J1, J11,
K11, L1, L8,
L11
L10
B6, C6, C8, D5,
E8, G8, H5, J5,
K5, K6, K7
I/O
I/O
I/O
O
I/O
I
I
I
I
I
O
V
Description
Vertical Sync for Video Mode.
Raw Pixel Mode Framing Signal. Indicates first sample of a tile when
asserted high.
Horizontal Sync for Video Mode.
Raw Pixel Mode Ready Signal.
Field Sync for Video Mode.
Raw Pixel Mode Transfer Strobe.
This pin should be connected to ground via a pull-down resistor.
This pin should be connected to ground via a pull-down resistor.
This pin should be connected to ground via a pull-down resistor.
This pin should be connected to ground via a pull-down resistor.
No connect.
Positive Supply for Core.
GND
Ground.
V
V
Positive Supply for PLL.
Positive Supply for I/O.
Rev. 0 | Page 24 of 40
ADV202
THEORY OF OPERATION
The input video or pixel data is passed on to the ADV202’s pixel
interface, where samples are de-interleaved and passed on to the
wavelet engine, where each tile or frame is decomposed into
subbands using the 5/3 or 9/7 filters. The resultant wavelet
coefficients are then written to internal memory. The entropy
codecs then code the image data so that it conforms to the
JPEG2000 standard. An internal DMA provides high bandwidth
memory-to-memory transfers, as well as high performance
transfers between functional blocks and memory.
ENTROPY CODECS
WAVELET ENGINE
EMBEDDED PROCESSOR SYSTEM
The ADV202 provides a dedicated wavelet transform processor
based on the Analog Devices proven and patented SURF™
technology. This processor can perform up to six wavelet
decomposition levels on a tile. In encode mode, the wavelet
transform processor takes in uncompressed samples, performs
the wavelet transform and quantization, and writes the wavelet
coefficients in all frequency subbands to internal memory. Each
of these subbands is then further broken down into code blocks.
The code-block dimensions can be user-defined, and are used
by the wavelet transform processor to organize the wavelet
coefficients into code blocks when writing to internal memory.
Each completed code block is then entropy coded by one of the
entropy codecs.
The ADV202 incorporates an embedded 32-bit RISC processor.
This processor is used for configuration, control, and management of the dedicated hardware functions, as well as for parsing
and generation of the JPEG2000 code stream. The processor
system includes ROM and RAM for both program and data
memory, an interrupt controller, standard bus interfaces, and
other hardware functions such as timers and counters.
In decode mode, wavelet coefficients are read from internal
memory and recomposed into uncompressed samples.
The entropy codec block performs context modeling and
arithmetic coding on a code block of the wavelet coefficients.
Additionally, this block also performs the distortion metric
calculations during compression that are required for optimal
rate and distortion performance. Because the entropy coding
process is the most computationally intensive operation in the
JPEG2000 compression process, three dedicated hardware
entropy codecs are provided on the ADV202.
MEMORY SYSTEM
The memory system’s main function is to manage wavelet
coefficient data, interim code-block attribute data, and
temporary work space for creating, parsing, and storing the
JPEG2000 code stream. The memory system can also be used
for program and data memory for the embedded processor.
INTERNAL DMA ENGINE
The internal DMA engine provides high bandwidth memoryto-memory transfers, as well as high performance transfers
between memory and functional blocks. This function is critical
for high speed generation and parsing of the code stream.
Rev. 0 | Page 25 of 40
ADV202
ADV202 INTERFACE
There are several possible modes to interface to the ADV202
using the VDATA bus and the HDATA bus or the HDATA bus
alone.
VIDEO INTERFACE (VDATA BUS)
The video interface can be used in applications in which
uncompressed pixel data is on a separate bus from compressed
data. For example, it is possible to use the VDATA bus to input
uncompressed video while using the HDATA bus to output the
compressed data. This interface is ideal for applications
requiring very high throughput such as live video capture.
The control and data channel bus widths can be specified
independently, which allows the ADV202 to support
applications that require control and data buses of different
widths.
The host interface is used for configuration, control, and status
functions, as well as for transferring compressed data streams. It
can be used for uncompressed data transfers in certain modes.
The host interface can be shared by as many as four concurrent
data streams in addition to control and status communications.
The data streams are
• Uncompressed tile data (for example, still image data)
• Fully encoded JPEG2000 code stream (or unpackaged code
blocks)
• Code-block attributes
• Ancillary data
Optionally, the ADV202 interlaces ITU.R-BT656 resolution
video on the fly prior to wavelet processing, which yields
significantly better compression performance for temporally
coherent frame-based video sources. Additionally, high
definition digital video such as SMPTE274M (1080i) is
supported using two or more ADV202 devices.
The video interface can support video data or still image data
input/output, 8-, 10-, and 12-bit single or multiplexed
components, and dual-lane 8-, 10-, and 12-bit components. The
VDATA interface supports digital video in YCbCr format in
single input mode or Y and CbCr in dual-lane input mode.
YCbCr data must be in 4:2:2 format.
The ADV202 uses big endian byte alignment for 16- and 32-bit
transfers. All data is left-justified (MSB).
Pixel Input on the Host Interface
Video data can be input/output in several different modes on
the VDATA bus, as described in Table 17. In all these modes, the
pixel clock must be input on the VCLK pin.
Pixel input on the host interface supports 8-, 10-, 12-, 14-, and
16-bit raw pixel data formats. It can be used for pixel (still
image) input/output or compressed video output. Because there
are no timing codes or sync signals associated with the input
data on the host interface, dimension registers and internal
counters are used and must be programmed to indicate the start
and end of the frame. See the ADV202 in HIPI Mode technical
note for details on how to use the ADV202 in this mode.
Table 17. Video Input/Output Modes
Host Bus Configuration
Mode
EAV/SAV
HVF
Extended
Raw video
HDTV
Description
Accepts video with embedded EAV/SAV codes,
where the YCbCr data is interleaved onto a single
bus.
Accepts video data accompanied with separate H,
V, and F signals where YCbCr data is interleaved
onto a single bus.
Y and CrCb are on separate buses accompanied by
EAV/SAV codes.
Used for still picture data and nonstandard video.
VFRM, VSTRB, and VRDY are used to program the
dimensions of the image.
For applications in which video data is clocked into
the part at higher rates than 27 MHz.
HOST INTERFACE (HDATA BUS)
The ADV202 can connect directly to a wide variety of host
processors and ASICs using an asynchronous SRAM-style
interface, DMA accesses or streaming mode (JDATA) interface.
The ADV202 supports 16- and 32-bit buses for control and 8-,
16-, and 32-bit buses for data transfer.
For maximum flexibility, the host interface provides several
configurations to meet particular system requirements. The
default bus mode uses the same pins to transfer control, status,
and data to and from the ADV202. In this mode, the ADV202
can support 16- and 32-bit control transfers and 8-, 16-, and
32-bit data transfers. The size of these busses can be selected
independently, allowing, for example, a 16-bit microcontroller
to configure and control the ADV202 while still providing
32-bit data transfers to an ASIC or external memory system.
DIRECT AND INDIRECT REGISTERS
To minimize pin count and cost, the number of address pins has
been limited to four, which yields a total direct address space of
16 locations. These locations are most commonly used by the
external controller and are, therefore, accessible directly. All
other registers in the ADV202 can be accessed indirectly
through the IADDR and IDATA registers.
Rev. 0 | Page 26 of 40
ADV202
CONTROL ACCESS REGISTERS
With the exception of the indirect address and data registers
(IADDR and IDATA), all control/status registers in the ADV202
are 16 bits wide and are half-word (16-bit) addressable only.
When 32-bit host mode is enabled, the upper 16 bits of the
HDATA bus are ignored on writes and return all zeros on reads
of 16-bit registers.
PIN CONFIGURATION AND BUS SIZES/MODES
The ADV202 provides a wide variety of control and data
configurations, which allows it to be used in many applications
with little or no glue logic. The following modes are configured
using the BUSMODE register. In the following descriptions, host
refers to normal addressed accesses (CS/RD/WR/ADDR) and
data refers to external DMA accesses (DREQ/DACK).
32-Bit Host/32-Bit Data
In this mode, the HDATA<31:0> pins provide full 32-bit wide
data access to PIXEL, CODE, ATTR, and ANCL FIFOs. The
expanded video interface (VDATA) is not available in this
mode.
16-Bit Host/32-Bit Data
This mode allows a 16-bit host to configure and communicate
with the ADV202 while still allowing 32-bit accesses to the
PIXEL, CODE, ATTR, and ANCL FIFOs using the external
DMA capability.
All addressed host accesses are 16 bits and, therefore, use only
the HDATA<15:0> pins. The HDATA<31:16> pins provide the
additional 16 bits necessary to support the 32-bit external DMA
transfers to and from the FIFOs only. The expanded video
interface (VDATA) is not available in this mode.
16-Bit Host/16-Bit Data
This mode uses 16-bit transfers, if used for host or external
DMA data transfers. This mode allows for the use of the
extended pixel interface modes.
has been provided to allow 16-bit hosts to access these registers
and memory locations using the stage register (STAGE). STAGE
is accessed as a 16-bit register using HDATA[15:0]. Prior to
writing to the desired register, the stage register must be written
with the upper (most significant) half-word.
When the host subsequently writes the lower half-word to the
desired control register, HDATA is combined with the
previously staged value to create the required 32-bit value that is
written. When a register is read, the upper (most significant)
half-word is returned immediately on HDATA and the lower
half-word can be retrieved by reading the stage register on a
subsequent access. For details on using the stage register, see the
ADV202 User’s Guide.
Note: The stage register does not apply to the four data channels
(PIXEL, CODE, ATTR, or ANCL). These channels are always
accessed at the specified data width and do not require the use
of the stage register.
JDATA MODE
JDATA mode is typically used only when the dedicated video
interface (VDATA) is also enabled. This mode allows code
stream data (compressed data compliant with JPEG2000) to be
input or output on a single dedicated 8-bit bus (JDATA<7:0>).
The bus is always an output during compression operations, and
is an input during decompression.
A 2-pin handshake is used to transfer data over this
synchronous interface. VALID is used to indicate that the
ADV202 is ready to provide or accept data and is always an
output. HOLD is always an input and is asserted by the host if it
cannot accept/provide data. For example, JDATA mode allows
real-time applications, in which pixel data is input over the
VDATA bus while the compressed data stream is output over
the JDATA bus.
EXTERNAL DMA ENGINE
16-Bit Host/8-Bit Data (JDATA Bus Mode)
This mode provides separate data input/output and host control
interface pins. Host control accesses are 16 bits and use
HDATA<15:0>, while the dedicated data bus uses JDATA<7:0>.
The external DMA interface is provided to enable high
bandwidth data I/O between an external DMA controller and
the ADV202 data FIFOs. Two independent DMA channels can
each be assigned to any one of the four data stream FIFOs
(PIXEL, CODE, ATTR, or ANCL).
JDATA uses a valid/hold synchronous transfer protocol. The
direction of the JDATA bus is determined by the mode of the
ADV202. If the ADV202 is encoding (compression), then
JDATA<7:0> is an output. If the ADV202 is decoding
(decompression), then JDATA<7:0> is an input. Host control
accesses remain asynchronous. See also JDATA section below.
The controller supports asynchronous DMA using a
Data-Request/Data-Acknowledge (DREQ/DACK) protocol in
either single or burst access modes. Additional functionality is
provided for single address compatibility (fly-by) and dedicated
chip select (DCS) modes.
STAGE REGISTER
The SPI port provides serial communication to and from the
ADV202. The ADV202 is always the SPI master.
Because the ADV202 contains both 16-bit and 32-bit registers
and its internal memory is mapped as 32-bit data, a mechanism
SPI PORT
Rev. 0 | Page 27 of 40
ADV202
INTERNAL REGISTERS
This section describes the internal registers of the ADV202.
The host must first initialize the direct registers before any
application-specific operation can be implemented.
DIRECT REGISTERS
The ADV202 has 16 direct registers, as listed in Table 18. The
direct registers are accessed over the ADDR [3–0],
HDATA[31…0], CS, RD, WR, and ACK pins.
For additional information on accessing and configuring these
registers, see the ADV202 User’s Guide.
Table 18. Direct Registers
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Name
PIXEL
CODE
ATTR
ANCL
CMDSTA
EIRQIE
EIRQFLG
SWFLAG
BUSMODE
MMODE
STAGE
IADDR
IDATA
BOOT
PLL_HI
PLL_LO
Description
Pixel FIFO Access Register
Compressed Code Stream Access Register
Attribute FIFO Access Register
Ancillary FIFO Access Register
Command Stack
External Interrupt Enabled
External Interrupt Flags
Software Flag Register
Bus Mode Configuration Register
Miscellaneous Mode Register
Staging Register
Indirect Address Register
Indirect Data Register
Boot Mode Register
PLL Control Register—High Byte
PLL Control Register—Low Byte
Rev. 0 | Page 28 of 40
ADV202
INDIRECT REGISTERS
The indirect registers, listed in Table 19, are accessed by both
the host system and the internal 32-bit embedded processor, via
the ESF or the firmware.
Both 32-bit and 16-bit hosts can access the indirect registers.
32-bit hosts use the IADDR and IDATA registers, while the
16 bit hosts use IADDR, IDATA, and the stage register.
In certain modes such as custom-specific input format or HIPI
mode, indirect registers must be accessed by the user through
the use of the IADDR and IDATA registers. The indirect
register address space starts at Internal Address 0xFFFF0000.
For additional information on accessing and configuring these
registers, see the ADV202 User’s Guide.
Table 19. Indirect Registers
Address
0xFFFF0400
0xFFFF0404
0xFFFF0408
0xFFFF040C
0xFFFF0410
0xFFFF0414
0xFFFF0418
0xFFFF041C
0xFFFF0420
0xFFFF0424
0xFFFF0428
0xFFFF042C
0xFFFF0430
0xFFFF0440
0xFFFF0444
0xFFFF0448
0xFFFF044C
0xFFFF1408
0xFFFF140C
0xFFFF1410
0xFFFF1414
0xFFFF1418
0xFFFF141C
0xFFFF1420
0xFFFF1424
0xFFFF1428
0xFFFF142C
0xFFFF1430
0xFFFF1434 to 0xFFFF14FC
Name
PMODE1
COMP_CNT_STATUS
LINE_CNT_STATUS
XTOT
YTOT
F0_START
F1_START
V0_START
V1_START
V0_END
V1_END
PIXEL_START
PIXEL_END
MS_CNT_DEL
LINE_CNT_INTERRUPT
PMODE2
VMODE
EDMOD0
EDMOD1
FFTHRP
FFCNTP
FFMODE
FFTHRC
FFTHRA
FFTHRN
FFCNTC
FFCNTA
FFCNTN
Reserved
Description
Pixel/Video Format
Horizontal Count
Vertical Count
Total Samples per Line
Total Lines per Frame
Start Line of Field 0 [F0]
Start Line of Field 1 [F1]
Start of Active Video Field 0 [F0]
Start of Active Video Field 1 [F1]
End of Active Video Field 0 [F0]
End of Active Video Field 1 [F1]
Horizontal Start of Active Video
Horizontal End of Active Video
Master/Slave Delay
Line Count Interrupt
Pixel Mode 2
Video Mode
External DMA Mode Register 0
External DMA Mode Register 1
FIFO Threshold for Pixel FIFO
FIFO Full/Empty Count for Pixel FIFO
FIFO Mode Register
FIFO Threshold for Code FIFO
FIFO Threshold for ATTR FIFO
FIFO Threshold for ANCL FIFO
FIFO Full/ Empty Count for CODE FIFO
FIFO Full/Empty Count for ATTR FIFO
FIFO Full/Empty Count for ANCL FIFO
Reserved
Rev. 0 | Page 29 of 40
ADV202
PLL
The ADV202 uses the PLL_HI and PLL_LO direct registers to
configure the PLL. Any time the PLL_LO register is modified,
the host must wait at least 20 µs before reading or writing any
other register. If this delay is not implemented, erratic behavior
might result.
The PLL can be programmed to have any possible final
multiplier value as long as
• JCLK > 50 MHz and < 150 MHz (144-pin version).
• For MCLK frequencies greater than 50 MHz, the input clock
divider must be enabled, that is, IPD set to 1.
• IPD cannot be enabled for MCLK frequencies below 20 MHz.
To achieve the lowest power consumption, an MCLK frequency
of 27 MHz is recommended for a standard definition CCIR656
input. The PLL circuit is recommended to have a multiplier of 3.
This sets JCLK and HCLK to 81 MHz.
BYPASS
• JCLK > 50 MHz and < 115 MHz (121-pin version).
IPD
• JCLK ≥ 2 × VCLK for single-component input.
÷2
PHASE
DETECT
LPF
JCLK
VCO
÷2
÷2
• JCLK ≥ 2 × VCLK for YCrCb [4:2:2] input.
HCLKD
LFB
• In JDATA mode (JDATA), JCLK must be 4 × MCLK or
higher.
Figure 24. PLL Architecture and Control Functions
• The maximum burst frequency for external DMA modes is
≤ 0.36 JCLK.
Table 20. Recommended PLL Register Settings
IPD
0
0
0
0
1
1
1
1
LFB
0
0
1
1
0
0
1
1
PLLMULT
N
N
N
N
N
N
N
N
HCLKD
0
1
0
1
0
1
0
1
HCLK
N × MCLK
N × MCLK/2
2 × N × MCLK
N × MCLK
N × MCLK/2
N × MCLK/4
N × MCLK
N × MCLK/2
JCLK
N × MCLK
N × MCLK
2 × N × MCLK
2 × N × MCLK
N × MCLK/2
N × MCLK/2
N × MCLK
N × MCLK
PLL_HI
0x0008
0x0008
0x0008
0x0008
PLL_LO
0x0004
0x0004
0x0004
0x0084
Table 21. Recommended Values for PLL_HI and PLL_LO Registers
Video Standard
SMPTE125M or ITU-R.BT656 (NTSC or PAL)
SMPTE293M (525p)
ITU-R.BT1358 (625p)
SMPTE274M (1080i)
CLKIN Frequency on MCLK
27 MHz
27 MHz
27 MHz
74.25 MHz
Rev. 0 | Page 30 of 40
HCLK
÷PLLMULT
04723-009
MCLK
• HCLK < 115 MHz.
ADV202
HARDWARE BOOT
The boot mode can be configured via hardware using the CFG
pins or via software (see the ADV202 User’s Guide). The first
boot mode after power-up is set by the CFG pins.
Only boot modes 2, 4, and 6, described in Table 22, are available
via hardware.
Table 22. Hardware Boot Modes
Boot Mode
Hardware Boot
Mode 2
Settings
CFG<1> tied high,
CFG<2> tied low
Hardware Boot
Mode 4
Hardware Boot
Mode 6
CFG<1> tied low,
CFG<2> tied high
CFG<1> and <2>
tied high
Description
No-Boot Host Mode. ADV202 does not boot, but all internal registers and memory are accessible
through normal host I/O operations.
For details, see the ADV202 User’s Guide and the Getting Started with the ADV202 application note.
SoC boot mode. The embedded software framework (ESF) takes control and establishes
communications with the host.
SPI boot mode. Boot firmware over SPI from external flash memory.
Rev. 0 | Page 31 of 40
ADV202
VIDEO INPUT FORMATS
The ADV202 supports a wide variety of formats for
uncompressed video and still image data. The actual interface
and bus modes selected for transferring uncompressed data
dictates the allowed size of the input data and the number of
samples transferred with each access.
The host interface can support 8-, 10-, 12-, 14-, and 16-bit data
formats. The video interface can support video data or still
image data input/output. Supported formats are 8-, 10-, 12-, or
16-bit single or 2 × 8-bit, 2 × 10-bit, 2 × 12-bit multiplexed
formats. See the ADV202 User’s Guide for details. All formats
can support less precision than provided by specifying the
actual data width/precision in the PMODE register.
The maximum allowable data input rate is limited by using
irreversible or reversible compression modes and the data width
(or precision) of the input samples. Use Table 23 and Table 24 to
determine the maximum data input rate.
Table 23. Maximum Pixel Data Input Rates
Compression
Interface Mode
144-PIN PACKAGE
HDATA
Irreversible
Irreversible
Irreversible
Irreversible
Reversible
Reversible
Reversible
Reversible
VDATA
Irreversible
Irreversible
Irreversible
Reversible
Reversible
Reversible
121-PIN PACKAGE
HDATA
Irreversible
Irreversible
Irreversible
Irreversible
Reversible
Reversible
Reversible
Reversible
VDATA
Irreversible
Irreversible
Irreversible
Reversible
Reversible
Reversible
Input Format
Input Rate Limit
Active Resolution
(MSPS)1
Approx Min Peak Output
Rate, Compressed Data2
(Mbps)
Approx Max Output Rate,
Compressed Data3
(Mbps)
8-bit data
10-bit data
12-bit data
16-bit data
8-bit data
10-bit data
12-bit data
14-bit data
8-bit data
10-bit data
12-bit data
8-bit data
10-bit data
12-bit data
45
45
45
45
40
32
27
23
65
65
65
40
32
27
130
130
130
130
130
130
130
130
130
130
130
130
130
130
200
200
200
200
200
200
200
200
200
200
200
200
200
200
8-bit data
10-bit data
12-bit data
16-bit data
8-bit data
10-bit data
12-bit data
14-bit data
8-bit data
10-bit data
12-bit data
8-bit data
10-bit data
12-bit data
34
34
34
34
30
24
20
17
48
48
48
30
24
20
98
98
98
98
98
98
98
98
98
98
98
98
98
98
150
150
150
150
150
150
150
150
150
150
150
150
150
150
1
Input rate limits for HDATA might be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings.
Minimum peak output rate or guaranteed sustained output rate.
3
Maximum output rate, or output rate above this value is not possible.
2
Rev. 0 | Page 32 of 40
ADV202
Table 24. Maximum Supported Tile Width for Data Input on HDATA and VDATA Buses
Compression Mode
9/7i
9/7i
9/7i
5/3i
5/3i
5/3i
5/3r
5/3r
5/3r
Input Format
Single-component
Two-component
Three-component
Single-component
Two-component
Three-component
Single-component
Two-component
Three-component
Tile/Precinct Maximum Width
2048
1024 each
1024 (Y)
4096
2048 (each)
2048 (Y)
4096
2048
1024
Rev. 0 | Page 33 of 40
ADV202
APPLICATIONS
This section describes typical video applications for the
ADV202 JPEG2000 video processor.
In decode mode, a master/slave configuration (as shown in
Figure 26) or a slave/slave configuration can be used to
synchronize the outputs of the two ADV202s. See the ADV202
Multichip Application application note for details on how to
configure the ADV202s in a multichip application.
ENCODE—MULTICHIP MODE
Due to the data input rate limitation (see Table 23), an 1080i
application requires at least two ADV202s to encode or decode
full-resolution 1080i video. In encode mode, the ADV202
accepts Y and CbCr data on separate buses. The input data must
be in EAV/SAV format. An encode example is shown in
Figure 25.
ADV202
_1_SLAVE
32-BIT HOST CPU
DATA[31:0]
ADDR[3:0]
ADV7402
10-BIT SD/HD
VIDEO
DECODER
HDATA[31:0]
ADDR[3:0]
CS
CS
RD
RD
WR
WE
ACK
ACK
IRQ
IRQ
VCLK
LLC
1080i
VIDEO OUT
MCLK
VDATA[11:2]
DREQ
DREQ
DACK
DACK
G I/O
Applications that have two separate VDATA outputs sent to an
FPGA or buffer before they are sent to an encoder do not
require synchronization at the ADV202 outputs.
Y
FIELD
VSYNC
HSYNC
SCOMM[5]
Y[9:0]
CbCr
C[9:0]
ADV202
_2_SLAVE
HDATA[31:0]
ADDR[3:0]
CS
RD
RD
WR
WE
ACK
ACK
IRQ
IRQ
DREQ
DREQ
DACK
DACK
MCLK
HSYNC
VSYNC
FIELD
VDATA[11:2]
CbCr
SCOMM[5]
Figure 25. Encode—Multichip Application
Rev. 0 | Page 34 of 40
04723-002
CS
VCLK
ADV202
In a slave/slave configuration, the common HVF for both
ADV202s is generated by an external house sync and each
SCOMM[5] is connected to the same GPIO output on the host.
DECODE—MULTICHIP MASTER/SLAVE
In a master/slave configuration, it is expected that the master
HVF outputs are connected to the slave HVF inputs and that
each SCOMM[5] pin is connected to the same GPIO on the
host.
SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be
unmasked on both devices to enable multichip mode.
ADV202
_1_MASTER
32-BIT HOST CPU
DATA[31:0]
HDATA[31:0]
ADDR[3:0]
ADDR[3:0]
CS
CS
RD
RD
WR
WE
ACK
ACK
IRQ
IRQ
ADV730xA
10-BIT SD/HD
VIDEO
DECODER
VCLK
CLKIN
1080i
VIDEO OUT
MCLK
VDATA[11:2]
DREQ
DREQ
DACK
DACK
G I/O
74.25MHz
OSC
Y
Y
FIELD
VSYNC
HSYNC
SCOMM[5]
Y[9:0]
CbCr
C[9:0]
ADV202
_2_SLAVE
HDATA[31:0]
ADDR[3:0]
CS
RD
WR
WE
ACK
ACK
IRQ
IRQ
DREQ
DREQ
DACK
DACK
HSYNC
VSYNC
FIELD
VDATA[11:2]
CbCr
04723-003
CS
RD
VCLK
MCLK
SCOMM[5]
Figure 26. Decode —Multichip Master/Slave Application
DIGITAL STILL CAMERA/CAMCORDER
Figure 27 is a typical configuration for a digital camera or camcorder.
FPGA
D[9:0]
SDATA
SCK
SL
10
DATA INPUTS[9:0]
SERIAL DATA
SERIAL CLK
SERIAL EN
ADV202
MCLK
VCLK
VFRM
VRDY
VSTRB
VDATA[11:2]
HDATA[15:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
Figure 27. Digital Still Camera/Camcorder Application
Rev. 0 | Page 35 of 40
16-BIT
HOST CPU
DATA[15:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
04723-004
AD9843A
ADV202
ENCODE/DECODE SDTV VIDEO APPLICATION
Figure 28 shows two ADV202 chips using 10-bit CCIR656 in normal host mode.
ADV202
ADV7189
10-BIT
VIDEO
DECODER
VDATA[11:2]
32-BIT
HOST CPU
DATA[31:0]
INTR
ADDR[3:0]
CS
RD
WE
ACK
DECODE MODE
VCLK
MCLK
LLC1
HDATA[31:0]
IRQ
ADDR[3:0]
CS
RD
WE
ACK
ADV202
ADV7301A
10-BIT
VIDEO
ENCODER
VDATA[11:2]
P[9:0]
VCLK
CLKIN
32-BIT
HOST CPU
DATA[31:0]
INTR
ADDR[3:0]
CS
RD
WE
ACK
VIDEO IN
P[19:10]
VIDEO OUT
MCLK
HDATA[31:0]
IRQ
ADDR[3:0]
CS
RD
WE
ACK
27MHz
OSC
Figure 28. Encode/Decode—SDTV Video Application
Rev. 0 | Page 36 of 40
04723-005
ENCODE MODE
ADV202
ASIC APPLICATION (32-BIT HOST/32-BIT ASIC)
Figure 29 shows two ADV202 chips using 10-bit CCIR656 in normal host mode.
ASIC
ADV7189
ADV202
10-BIT
VIDEO
DECODER
DREQ0
DREQ0
DACK0
DACK0 VDATA[11:2]
DATA[31:0]
HDATA[31:0]
VIDEO IN
P[19:10]
VCLK
LLC1
MCLK
32-BIT
HOST CPU
DATA[31:0]
ASIC
IRQ
ADDR[3:0]
CS
RD
WE
ACK
ENCODE MODE
ADV730xA
ADV202
10-BIT
VIDEO
ENCODER
DREQ0
DREQ0
DACK0
DACK0 VDATA[11:2]
P[9:0]
VCLK
CLKIN
DATA[31:0]
HDATA[31:0]
31 -BIT
HOST CPU
DATA[31:0]
IRQ
ADDR[3:0]
CS
RD
WE
ACK
VIDEO OUT
MCLK
27MHz
OSC
IRQ
ADDR[3:0]
CS
RD
WE
ACK
Figure 29. Encode/Decode ASIC Application
Rev. 0 | Page 37 of 40
DECODE MODE
04723-006
IRQ
ADDR[3:0]
CS
RD
WE
ACK
ADV202
HIPI (HOST INTERFACE—PIXEL INTERFACE)
Figure 30 is a typical configuration using HIPI mode.
ADV202
Y0/G0<MSB>
Y0/G0<6>
Y0/G0<5>
Y0/G0<4>
Y0/G0<3>
Y0/G0<2>
Y0/G0<1>
Y0/G0<0>
Cb0/G1<MSB>
Cb0/G1<6>
Cb0/G1<5>
Cb0/G1<4>
Cb0/G1<3>
Cb0/G1<2>
Cb0/G1<1>
Cb0/G1<0>
Y1/G2<MSB>
Y1/G2<6>
Y1/G2<5>
Y1/G2<4>
Y1/G2<3>
Y1/G2<2>
Y1/G2<1>
Y1/G2<0>
Cr0/G3<MSB>
Cr0/G3<6>
Cr0/G3<5>
Cr0/G3<4>
Cr0/G3<3>
Cr0/G3<2>
Cr0/G3<1>
Cr0/G3<0>
32-BIT HOST
HDATA<31>
HDATA<30>
HDATA<29>
HDATA<28>
HDATA<27>
HDATA<26>
HDATA<25>
HDATA<24>
HDATA<23>
HDATA<22>
HDATA<21>
HDATA<20>
HDATA<19>
HDATA<18>
HDATA<17>
HDATA<16>
HDATA<15>
HDATA<14>
HDATA<13>
HDATA<12>
HDATA<11>
HDATA<10>
HDATA<9>
HDATA<8>
HDATA<7>
HDATA<6>
HDATA<5>
HDATA<4>
HDATA<3>
HDATA<2>
HDATA<1>
HDATA<0>
DATA<31:0>
CS
CS
RD
RD
WR
WE
ACK
ACK
IRQ
IRQ
DREQ0
DACK0
RAW PIXEL
DATAPATH
DREQ
DACK
DREQ1
DACK1
COMPRESSED
DATAPATH
74.25MHz
04723-007
DREQ
DACK
MCLK
Figure 30. Host Interface—Pixel Interface mode
JDATA INTERFACE
Figure 31 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR656.
ADV202
JDATA[7:0]
HOLD
VALID
16-BIT
HOST CPU
ADV7189
VDATA[11:2]
YCrCb
FIELD
VSYNC
HSYNC
FIELD
VS
HS
VIDEO IN
VCLK
MCLK
DATA[15:0]
IRQ
ADDR[3:0]
CS
RD
WE
ACK
P[19:10]
HDATA[15:0]
IRQ
ADDR[3:0]
CS
RD
WE
ACK
Figure 31. JDATA Application
Rev. 0 | Page 38 of 40
LLC1
04723-008
ASIC
ADV202
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
12.20
12.00 SQ
11.80
11 10 9 8 7 6 5 4 3 2 1
A
BALL A1
INDICATOR
TOP VIEW
B
C
D
E
F
G
J
10.00
BSC SQ
H
K
L
1.00 BSC
BOTTOM VIEW
1.85*
1.71
1.40
DETAIL A
1.31*
1.21
1.11
DETAILA
0.50 NOM
0.30 MIN
0.70
0.60
0.50
0.20 NOM
COPLANARITY
SEATING
PLANE
BALL DIAMETER
COMPLIANT WITH JEDEC STANDARDS MO-192-ABD-1
EXCEPT FOR DIMENSIONS INDICATED BY A "*" SYMBOL
Figure 32. 121-Lead Chip Scale Ball Grid Array [CSPBGA]
(BC-121)
Dimensions shown in millimeters
A1 CORNER
INDEX AREA
13 .00
BSC SQ
12
11
10
9
8
7
6
5
4
3
2
A
B
C
D
E
F
G
H
J
K
L
M
BALL A1
INDICATOR
TOP VIEW
DETAIL A
1
11.00
BSC
BOTTOM VIEW
1.00 BSC
*1.85
MAX
DETAILA
*1.32
1.21
1.11
0.53
0.43
0.70
SEATING
0.60
PLANE
0.50
BALL DIAMETER
COMPLIANT WITH JEDEC STANDARDS MO-192-AAD-1
EXCEPT FOR DIMENSIONS INDICATED BY A "*" SYMBOL
Figure 33. 144-Lead Chip Scale Ball Grid Array [CSPBGA]
(BC-144-3)
Dimensions shown in millimeters
Rev. 0 | Page 39 of 40
COPLANARITY
0.20 MAX
ADV202
ORDERING GUIDE
Model
ADV202BBC-115
ADV202BBCZ-1151
ADV202BBC-150
ADV202BBCZ-1501
ADV202-HD-EB
ADV202-SD-EB
1
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Speed
Grade
115 MHz
115 MHz
150 MHz
150 MHz
Operating Voltage
1.5 V internal, 2.5 V or 3.3 V I/O
1.5 V internal, 2.5 V or 3.3 V I/O
1.5 V internal, 2.5 V or 3.3 V I/O
1.5 V internal, 2.5 V or 3.3 V I/O
Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04723–0–7/04(0)
Rev. 0 | Page 40 of 40
Package Description
121-Lead CSPBGA
121-Lead CSPBGA
144-Lead CSPBGA
144-Lead CSPBGA
High Definition Evaluation Board
Standard Definition Evaluation
Board
Package
Option
BC-121
BC-121
BC-144-3
BC-144-3
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