Intersil CD4015 Cmos dual 4-stage static shift register with serial input/parallel output Datasheet

CD4015BT
Data Sheet
July 1999
CMOS Dual 4-Stage Static Shift Register
With Serial Input/Parallel Output
Intersil’s Satellite Applications FlowTM (SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
CD4015BT consists of two identical, independent, 4-stage
serial-input/parallel output registers. Each register has
independent CLOCK and RESET inputs as well as a single
serial DATA input. “Q” outputs are available from each of the
four stages on both registers. All register stages are D type,
master-slave flip-flops. The logic level present at the DATA
input is transferred into the first register stage and shifted
over one stage at each positive-going clock transition.
Resetting of all stages is accomplished by a high level on the
reset line. Register expansion to 8 stages using one
CD4015BT, or to more than 8 stages using additional
CD4015BT’s is possible.
• QML Class T, Per MIL-PRF-38535
• Radiation Performance
- Gamma Dose (γ) 1 x 105 RAD(Si)
- SEP Effective LET > 75 MEV/gm/cm2
• Medium Speed Operation 12MHz (typ.) Clock Rate at VDD
- VSS = 10V
• Fully Static Operation
• 8 Master-Slave Flip-Flops Plus Input and Output Buffering
• 100% Tested For Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
Pinouts
CD4015BT (SBDIP), CDIP2-T16
TOP VIEW
Detailed Electrical Specifications for the CD4015BT are
contained in SMD 5962-96624. A “hot-link” is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
5962R9662401TEC
5962R9662401TXC
PART
NUMBER
CD4015BDTR
CD4015BKTR
-55 to 125
-55 to 125
Q4B 2
15 DATA B
Q3A 3
14 RESET B
Q2A 4
13 Q1B
Q1A 5
12 Q2B
RESET A 6
11 Q3B
DATA A 7
10 Q4A
9 CLOCK A
VSS 8
Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
ORDERING
NUMBER
16 VDD
CLOCK B 1
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
TEMP.
RANGE
(oC)
4621.1
Features
Specifications
Ordering Information
File Number
CD4015BT (FLATPACK), CDFP4-F16
TOP VIEW
CLOCK B
1
16
VDD
Q4B
2
15
DATA B
Q3A
3
14
RESET B
Q2A
4
13
Q1B
Q1A
5
12
Q2B
RESET A
6
11
Q3B
DATA A
7
10
Q4A
VSS
8
9
CLOCK A
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.
CD4015BT
Functional Diagram
VDD
16
DATA A
CLOCK A
RESET A
7
5
9
4
4
STAGE
6
Q1A
Q2A
3
Q3A
10
DATA B
CLOCK B
15
13
1
12
RESET B
Q1B
Q2B
4
STAGE
14
Q4A
11
Q3B
2
Q4B
8
VSS
Logic Diagram
Q1 13 (5)
Q2 12 (4)
Q3 11 (3)
Q4
2
(10)
DATA
†
D
15
(7)
Q
D
Q
CL
Q
D
Q
CL
Q
D
Q
Q
CL
CLOCK
†
CL
1
(9)
R
R
R
Q
R
CL
RESET
†
14
(6)
CL
CL
p
p
n
n
Q
CL
CL
D Q
VDD
CL Q
≡
D
R
CL
Q
CL
CL
CL
VSS
p
p
n
n
†ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
R
CL
CL
TRUTH TABLE
CL
X
D
R
Q1
Qn
0
0
0
Qn-1
1
0
1
Qn-1
X
0
Q1
Qn
X
1
0
0
X = Don’t care Case
2
(No Change)
CD4015BT
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
(2032µm x 2489µm x 533µm ±25.4µm)
Type: Phosphorus Doped Silox (SiO2)
80 x 98 x 21mils ±1mil
Thickness: 13kÅ ±2.6kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm2
Type: Al
Thickness: 12.5kÅ ±1.5kÅ
TRANSISTOR COUNT:
SUBSTRATE POTENTIAL:
60
Leave Floating or Tie to VDD; Bond Pad #16 (VDD) First
PROCESS:
BACKSIDE FINISH:
Bulk CMOS
Silicon
Metallization Mask Layout
CD4015BT
80mils
1
3
2
16
15
14
4
5
98mils
13
12
6
7
8
9
10
11
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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