IDT IDT71L016L100PH Low power 3v cmos sram 1 meg (64k x 16-bit) Datasheet

ADVANCE
INFORMATION
IDT71L016
LOW POWER 3V CMOS SRAM
1 MEG (64K x 16-BIT)
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
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The IDT71L016 is a 1,048,576-bit very low-power Static
RAM organized as 64K x 16. It is fabricated using IDT’s highreliability CMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides
a cost-effective solution for low-power memory needs. It uses
a 6-transistor memory cell.
All input and output signals of the IDT71L016 are LVTTLcompatible and operation is from a single extended-range
3.3V supply. This extended supply range makes the device
ideally suited for unregulated battery-powered applications.
Fully static asynchronous circuitry is used, requiring no clocks
or refresh for operation.
The IDT71L016 is packaged in a JEDEC standard 44-pin
TSOP Type II.
64K x 16 Organization
Wide Operating Voltage Range: 2.7V to 3.6V
Speed Grades: 70ns, 100ns
Low Operating Power: 45mA (max)
Low Standby Power: 5µA (max)
Low-Voltage Data Retention: 1.5V (min)
Available in a 44-pin TSOP package
FUNCTIONAL BLOCK DIAGRAM
OE
A0 - A15
Output
Enable
Buffer
Address
Buffers
Row / Column
Decoders
I/O 15
CS
8
Chip
Enable
Buffer
High
Byte
I/O
Buffer
8
I/O 8
WE
Write
Enable
Buffer
64K x 16
Memory
Array
16
Sense
Amps
and
Write
Drivers
I/O 7
8
Low
Byte
I/O
Buffer
8
I/O 0
BHE
Byte
Enable
Buffers
BLE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
1997 Integrated Device Technology, Inc.
3771 drw 01
MAY 1997
DSC-3771/2
1
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A4
1
44
A5
A3
2
43
A6
A2
3
42
A7
A1
4
41
OE
A0
5
40
BHE
CS
6
39
BLE
I/O 0
7
38
I/O 15
I/O 1
8
37
I/O 14
I/O 2
9
36
I/O 13
I/O 3
10
35
I/O 12
VDD
11
VSS
SO44-2
34
VSS
12
33
VDD
I/O 4
13
32
I/O 11
CAPACITANCE
I/O 5
14
31
I/O 10
(TA = +25°C, f = 1.0MHz)
I/O 6
15
30
I/O 9
I/O 7
16
29
I/O 8
WE
17
28
NC
A15
18
27
A8
A14
19
26
A9
A13
20
25
A10
A12
21
24
A11
NC
22
23
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 3dV
6
pF
CI/O
I/O Capacitance
VOUT = 3dV
7
pF
NOTE:
3771 tbl 06
1. This parameter is guaranteed by device characterization, but not production tested.
NC
3771 drw 02
TSOP
TOP VIEW
PIN DESCRIPTIONS
A0 – A15
Address Inputs
Input
CS
Chip Select
Input
WE
Write Enable
Input
OE
Output Enable
Input
BHE
High Byte Enable
Input
BLE
Low Byte Enable
Input
I/O0 - I/O15
Data Input/Output
I/O
VDD
Power
Pwr
VSS
Ground
Gnd
3771 tbl 01
TRUTH TABLE(1)
CS
OE
WE
BLE
BHE
I/O0-I/O7
I/O8-I/O15
Function
H
X
X
X
X
High-Z
High-Z
Deselected - Standby
L
L
H
L
H
DATAOUT
High-Z
Low Byte Read
L
L
H
H
L
High-Z
DATAOUT
High Byte Read
L
L
H
L
L
DATAOUT
DATAOUT
Word Read
L
X
L
L
L
DATAIN
DATAIN
Word Write
L
X
L
L
H
DATAIN
High-Z
Low Byte Write
L
X
L
H
L
High-Z
DATAIN
High Byte Write
L
H
H
X
X
High-Z
High-Z
Outputs Disabled
L
X
X
H
H
High-Z
High-Z
Outputs Disabled
NOTE:
1.H = VIH, L = VIL, X = Don't care.
3771 tbl 02
2
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Com’l. and Ind'l.
Unit
VTERM(2)
Terminal Voltage with
Respect to VSS
–0.5 to +4.6
V
VTERM(3)
Terminal Voltage with
Respect to VSS
–0.5 to VDD+0.5V
V
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–55 to +125
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
NOTES:
3771 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VDD terminals only.
3. Input, Output,and I/O terminals; 4.6V maximum.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Temperature
VSS
VDD
Commercial
0°C to +70°C
0V
2.7V to 3.6V
-40°C to +85°C
0V
2.7V to 3.6V
Industrial
3771 tbl 04
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
VDD
Supply Voltage
VSS
Ground
VIH
Input High Voltage
VIL
Min.
Typ.
Max.
Unit
2.7
3.0
3.6
V
0
0
0
V
2.0
—
VDD+0.3(1)
V
—
0.8
V
(2)
Input Low Voltage
–0.3
NOTE:
3771 tbl 05
1. VIH (max.) = VDD + 1.5V for pulse width less than 5ns, once per cycle.
2. VIL (min.) = –1.5V for pulse width less than 5ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
VDD = 2.7V to 3.6V, Commercial and Industrial Temperature Ranges
Symbol
Min.
Max.
Unit
|ILI|
Input Leakage Current
Parameter
VDD = Max., VIN = VSS to VDD
Test Conditions
—
1
µA
|ILO|
Output Leakage Current
VDD = Max., CS = VIH, VOUT = VSS to VDD
—
1
µA
VOH
Output High Voltage
IOH = –1mA, VDD = Min.
2.4
—
V
VOL
Output Low Voltage
IOL = 2mA, VDD = Min.
—
0.4
V
3771 tbl 07
DC ELECTRICAL CHARACTERISTICS(1, 2)
VDD = 2.7 to 3.6V, VLC = 0.2V, VHC = VDD–0.2V, Commercial and Industrial Temperature Ranges
Symbol
ICC2
Parameter
Dynamic Operating Current
CS
= VLC, Outputs Open,
VDD = 3.6V, f = fMAX(3)
ICC
ISB1
Static Operating Current
Standby Supply Current
Typ.(5)
Max.
Unit
-70 ns
—
45
mA
-100 ns
—
35
—
10
mA
µA
Test Conditions
WE
= VLC, Outputs Open,
= VHC, VDD = 3.6V, f = 0(4)
CS
= VHC, Outputs Open,
CS
VDD = 3.6V
NOTES:
1. All values are maximum guaranteed values.
2. Input low and high voltage levels are 0.2V and VDD-0.2V respectively for all tests.
3. fMAX = 1/tRC (all address inputs are cycling at fMAX).
4. f = 0 means no address input lines are changing .
5. Typical conditions are VDD = 3.0V and specified temperature.
-40 to 85°C
—
10
0 to 70°C
—
5
40°C
—
2
25°C
—
1
3771 tbl 08
3
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(VLC = 0.2V, VHC = VDD - 0.2V)
Symbol
Parameter
Test Condition
VDR
VCC for Data Retention
—
ICCDR
Data Retention Current
tCDR(3)
Chip Deselect to Data
Retention Time
tR(3)
Operation Recovery Time
CS
Min.
Typ. (1)
Max.
Unit
1.5
—
—
V
—
<1
5
µA
0
—
—
ns
tRC(2)
—
—
≥ VHC
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
ns
3771 tbl 09
LOW VDD DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
V DD
2.7V
2.7V
V DR ≥ 1.5V
tCDR
CS
V IH
tR
V IH
V DR
3771 drw 05
AC TEST LOAD
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
VDD
GND to 2.5V
3070Ω
DATA OUT
See Figure 1
3771 tbl 09
50pF*
3150Ω
3771 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
4
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VDD = 2.7 to 3.6V, All Temperature Ranges)
Symbol
Parameter
71L016L70
71L016L100
Min.
Max.
Min.
Max.
Units
Read Cycle
tRC
Read Cycle Time
70
—
100
—
ns
tAA
Address Access Time
—
70
—
100
ns
tACS
Chip Select Access Time
—
70
—
100
ns
tCLZ(1)
Chip Select Low to Output in Low-Z
10
—
10
—
ns
Chip Select High to Output in High-Z
—
25
—
30
ns
tOE
Output Enable Low to Output Valid
—
35
—
50
ns
tOLZ(1)
Output Enable Low to Output in Low-Z
5
—
5
—
ns
Output Enable High to Output in High-Z
—
25
—
30
ns
tOH
Output Hold from Address Change
10
—
15
—
ns
tBE
Byte Enable Low to Output Valid
—
35
—
50
ns
tCHZ
(1)
tOHZ
tBLZ
(1)
(1)
tBHZ(1)
Byte Enable Low to Output in Low-Z
5
—
5
—
ns
Byte Enable High to Output in High-Z
—
25
—
30
ns
Write Cycle
tWC
Write Cycle Time
70
—
100
—
ns
tAW
Address Valid to End of Write
65
—
80
—
ns
tCW
Chip Select Low to End of Write
65
—
80
—
ns
tBW
Byte Enable Low to End of Write
65
—
80
—
ns
tAS
Address Set-up Time
0
—
0
—
ns
tWR
Address Hold from End of Write
0
—
0
—
ns
tWP
Write Pulse Width
55
—
70
—
ns
tDW
Data Valid to End of Write
30
—
40
—
ns
tDH
Data Hold Time
0
—
0
—
ns
tOW(1)
Write Enable High to Output in Low-Z
5
—
5
—
ns
tWHZ(1)
Write Enable Low to Output in High-Z
—
25
—
30
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
ns
3771 tbl 10
TIMING WAVEFORM OF READ CYCLE NO. 1(1,2,3)
tRC
ADDRESS
tAA
tOH
DATAOUT
PREVIOUS DATAOUT VALID
tOH
DATAOUT VALID
3771 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
5
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2(1)
tRC
ADDRESS
tAA
tOH
OE
tOHZ
tOE
tOLZ
(3)
(3)
CS
tCLZ (3)
tACS (2)
tCHZ
(3)
,
BHE BLE
tBE (2)
tBLZ
tBHZ
(3)
DATAOUT
(3)
DATA OUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
3771 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1,2,3,5)
tWC
ADDRESS
tAW
CS
tCW
(3)
tCHZ
(6)
tBW
BHE
,
BLE
tWR
tWP
tBHZ
(6)
WE
tAS
tWHZ
(6)
tOW
DATAOUT
PREVIOUS DATA VALID
(4)
DATA VALID
tDW
DATAIN
(6)
tDH
DATAIN VALID
3771 drw 08
NOTES:
1. WE or (BHE and BLE) or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
6
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1,2,5)
tWC
ADDRESS
tAW
CS
tCW (3)
tAS
tBW
BHE
,
BLE
tWP
tWR
WE
DATAOUT
tDW
DATAIN
tDH
DATAIN VALID
3771 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 3 (BHE, BLE CONTROLLED TIMING)(1,2,5)
tWC
ADDRESS
tAW
CS
tCW
(3)
tAS
tBW
BHE , BLE
tWP
tWR
WE
DATAOUT
tDW
DATAIN
tDH
DATAIN VALID
3771 drw 10
NOTES:
1. WE or (BHE and BLE) or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
7
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT 71L016
Device
Type
L
XXX
XX
X
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PH
400-mil TSOP Type II (SO44-2)
70
100
Speed in nanoseconds
3771 drw 11
8
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