AD AD5551BR-REEL7 2.7 v to 5.5 v, serial-input, voltage-output, 14-bit dac Datasheet

2.7 V to 5.5 V, Serial-Input,
Voltage-Output, 14-Bit DACs
AD5551/AD5552
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
VDD
Full 14-bit performance
3 V and 5 V single supply operation
Low 0.625 mW power dissipation
1 μs settling time
Unbuffered voltage output capable of driving 60 kΩ
loads directly
SPI/QSPI/MICROWIRE-compatible interface standards
Power-on reset clears DAC output to 0 V (unipolar mode)
5 kV HBM ESD classification
8
AD5551
14-BIT DAC
VREF 3
1 VOUT
2 AGND
14-BIT DATA LATCH
CS 4
CONTROL
LOGIC
SERIAL INPUT REGISITER
SCLK 5
01943-001
DIN 6
7
APPLICATIONS
DGND
Figure 1.
Digital gain and offset adjustment
Automatic test equipment
Data acquisition systems
Industrial process control
VDD
14
AD5552
RFB
RINV
1 RFB
13 INV
VREFF 6
GENERAL DESCRIPTION
14-BIT DAC
VREFS 5
These DACs provide 14-bit performance without any adjustments. The DAC output is unbuffered, which reduces power
consumption and offset errors contributed by an output buffer.
With an external op amp, the AD5552 can be operated in
bipolar mode generating a ±VREF output swing. The AD5552
also includes Kelvin sense connections for the reference and
analog ground pins to reduce layout sensitivity. For higher
precision applications, refer to 16-bit DACs AD5541, AD5542,
and AD5544.
The AD5551/AD5552 utilize a versatile 3-wire interface that is
compatible with SPI, QSPI™, MICROWIRE™, and DSP interface
standards. The AD5551 and AD5552 are available in 8-lead and
14-lead SOIC packages.
3 AGNDF
14-BIT DATA LATCH
CS 7
LDAC 11
SCLK 8
DIN 10
2 VOUT
CONTROL
LOGIC
4 AGNDS
SERIAL INPUT REGISITER
12
DGND
01943-002
The AD5551/AD5552 are single, 14-bit, serial-input, voltageoutput DACs that operate from a single 2.7 V to 5.5 V supply.
The DAC output range extends from 0 V to VREF.
Figure 2.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Single Supply Operation.
The AD5551 and AD5552 are fully specified and
guaranteed for a single 2.7 V to 5.5 V supply.
Low Power Consumption.
Typically 0.625 mW with a 5 V supply.
3-Wire Serial Interface.
Unbuffered output capable of driving 60 kΩ loads, which
reduces power consumption as there is no internal buffer
to drive.
Power-On Reset Circuitry.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2010 Analog Devices, Inc. All rights reserved.
AD5551/AD5552
TABLE OF CONTENTS
Features .............................................................................................. 1
Bipolar Output Operation ......................................................... 12
Applications ....................................................................................... 1
Output Amplifier Selection....................................................... 12
General Description ......................................................................... 1
Force Sense Buffer Amplifier Selection ................................... 12
Functional Block Diagrams ............................................................. 1
Reference and Ground ............................................................... 13
Product Highlights ........................................................................... 1
Power-On Reset .......................................................................... 13
Revision History ............................................................................... 2
Power Supply and Reference Bypassing .................................. 13
Specifications..................................................................................... 3
Microprocessor Interfacing ........................................................... 14
Timing Characteristics ................................................................ 4
ADSP-21xx to AD5551/AD5552 Interface ............................. 14
Absolute Maximum Ratings............................................................ 5
68HC11 to AD5551/AD5552 Interface ................................... 14
ESD Caution .................................................................................. 5
MICROWIRE to AD5551/AD5552 Interface ........................ 14
Pin Configurations and Function Descriptions ........................... 6
80C51/80L51 to AD5551/AD5552 Interface .......................... 14
Typical Performance Characteristics ............................................. 7
Applications Information .............................................................. 15
Terminology .................................................................................... 10
Optocoupler Interface................................................................ 15
Theory of Operation ...................................................................... 11
Decoding Multiple AD5551/AD5552s .................................... 15
Digital-to-Analog Section ......................................................... 11
Outline Dimensions ....................................................................... 16
Serial Interface ............................................................................ 11
Ordering Guide .......................................................................... 16
Unipolar Output Operation ...................................................... 11
REVISION HISTORY
5/10—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Data Sheet Title, Features Section, General
Description Section, and Product Highlights Section ................. 1
Changes to Specifications Section .................................................. 3
Changes to Table 3 ............................................................................ 5
Changes to Pin VDD Description in Table 4 and Table 5 ............. 6
Changes to Typical Performance Characteristics Section ........... 7
Changes to First Paragraph in Theory of Operation Section ... 11
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
7/00—Revision 0: Initial Version
Rev. A | Page 2 of 16
AD5551/AD5552
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter 1
STATIC PERFORMANCE
Resolution
Relative Accuracy, INL
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
Zero-Code Error
Zero-Code Temperature Coefficient
AD5552
Bipolar Resistor Matching
Bipolar Zero Offset Error
Bipolar Zero Temperature Coefficient
Bipolar Zero-Code Error
Bipolar Gain Error
OUTPUT CHARACTERISTICS 2
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DAC Output Impedance
Power Supply Rejection Ratio
DAC REFERENCE INPUT
Reference Input Range
Reference Input Resistance 3
LOGIC INPUTS
Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
Input Capacitance2
Hysteresis Voltage2
REFERENCE2
Reference −3 dB Bandwidth
Reference Feedthrough
Signal-to-Noise Ratio
Reference Input Capacitance
POWER REQUIREMENTS
VDD
IDD
Power Dissipation
Min
Typ
Max
±0.15
±0.15
−0.3
±0.1
0.1
±0.05
±1.0
±0.8
+0.5
14
−1.5
1.000
±0.0015
±0.25
±0.2
−0.3
−0.3
0
−VREF
±1
±0.0152
±1
±1.2
±1.2
VREF − 1 LSB
VREF − 1 LSB
1
17
1.1
0.2
6.25
±1.0
2.0
9
7.5
VDD
±1
0.8
Unit
Bits
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
RFB/RINV, typically RFB = RINV = 28 kΩ
Ratio error
V
V
μs
V/μs
nV-sec
nV-sec
kΩ
LSB
Unipolar operation
AD5552 bipolar operation
To ½ LSB of FS, CL = 10 pF
CL = 10 pF, measured from 0% to 63%
1 LSB change around the major carry
All 1s loaded to DAC, VREF = 2.5 V
Tolerance typically 20%
ΔVDD ± 10%
V
kΩ
kΩ
Unipolar operation
AD5552, bipolar operation
0.15
2.2
1
92
26
26
MHz
mV p-p
dB
pF
pF
10
2.7
125
0.625
5.5
150
0.825
1
Temperature range is as follows: B version: −40°C to +85°C;
Guaranteed by design, not subject to production test.
3
Reference input resistance is code-dependent, minimum at 2555H.
2
Rev. A | Page 3 of 16
B grade
Guaranteed monotonic
Ω/Ω
%
LSB
ppm/°C
LSB
LSB
μA
V
V
pF
V
2.4
Test Condition
V
μA
mW
All 1s loaded
All 0s loaded, VREF = 1 V p-p at 100 kHz
Code 0000H
Code 3FFFH
Digital inputs at rails
AD5551/AD5552
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ 5.5 V, AGND = DGND = 0 V. All specifications −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 2.
Limit at TMIN, TMAX
All Versions
25
40
20
20
15
15
35
20
15
0
30
30
30
Parameter 1, 2
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
2
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time
LDAC pulse width
CS high to LDAC low setup
CS high time between active periods
Guaranteed by design, not production tested.
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to
90% of +3 V and timed from a voltage level of +1.6 V).
t1
SCLK
t2
t6
t3
t5
t7
t4
CS
t12
t8
t9
DIN
DB13
DB0
t11
LDAC*
*AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
Figure 3. Timing Diagram
Rev. A | Page 4 of 16
t10
01943-003
1
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
AD5551/AD5552
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted
Table 3.
Parameter
VDD to AGND
Digital Input Voltage to DGND
VOUT to AGND
AGND, AGNDF, AGNDS to DGND
Input Current to Any Pin Except Supplies
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature, (TJ max)
Package Power Dissipation
Thermal Impedance
SOIC (R-8)
SOIC (R-14)
Lead Temperature, Soldering
Peak Temperature1
ESD2
1
2
Rating
–0.3 V to +6 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to +0.3 V
±10 mA
−40°C to +85°C
−65°C to +150°C
150°C
(TJ max – TA)/θJA
θJA
149.5°C/W
104.5°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
260°C
5 kV
As per JEDEC Standard 20.
HBM classification.
Rev. A | Page 5 of 16
AD5551/AD5552
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RFB 1
14
VDD
VOUT 2
13
INV
12
DGND
AGNDF 3
AD5552
VREF 3
CS 4
8
AD5551
VDD
7
DGND
TOP VIEW
(Not to Scale)
6
DIN
5
SCLK
CS 7
01943-004
VOUT 1
AGND 2
11 LDAC
TOP VIEW
(Not to Scale)
10 DIN
VREFS 5
9 NC
VREFF 6
8
SCLK
NC = NO CONNECNT
01943-005
AGNDS 4
Figure 5. AD5552 Pin Configuration
Figure 4. AD5551 Pin Configuration
Table 4. AD5551 Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
VOUT
AGND
VREF
CS
SCLK
6
7
8
DIN
DGND
VDD
Description
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry.
This is the voltage reference input for the DAC. Connect to external reference ranges from 2 V to VDD.
This is an active low-logic input signal. The chip select signal is used to frame the serial data input.
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40%
and 60%.
Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK.
Digital Ground. Ground reference for digital circuitry.
Analog Supply Voltage, 2.7 V to 5.5 V ± 10%.
Table 5. AD5552 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
RFB
VOUT
AGNDF
AGNDS
VREFS
VREFF
CS
SCLK
9
10
11
NC
DIN
LDAC
12
13
DGND
INV
14
VDD
Description
Feedback Resistor. In bipolar mode, connect this pin to external op amp output.
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
This is the voltage reference input (sense) for the DAC. Connect to external reference ranges from 2 V to VDD.
This is the voltage reference input (force) for the DAC. Connect to external reference ranges from 2 V to VDD.
This is an active low-logic input signal. The chip select signal is used to frame the serial data input.
Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40%
and 60%.
No Connect.
Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK.
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
input register.
Digital Ground. Ground reference for digital circuitry.
Connected to the internal scaling resistors of the DAC. Connect the INV pin to external op amps inverting input in
bipolar mode.
Analog Supply Voltage, 2.7 V to 5.5 V ± 10%.
Rev. A | Page 6 of 16
AD5551/AD5552
TYPICAL PERFORMANCE CHARACTERISTICS
0.125
0.125
0
–0.062
–0.125
0
8192
16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE
0.062
0
–0.062
–0.125
0
8192
Figure 6. Integral Nonlinearity vs. Code
Figure 9. Differential Nonlinearity vs. Code
0.062
0.187
DIFFERENTIAL NONLINEARITY (LSB)
0
–0.062
–0.125
–0.187
–0.250
–60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
VDD = 5V
VREF = 2.5V
0.125
0.062
0
–0.062
–0.125
–60
01943-007
Figure 7. Integral Nonlinearity vs. Temperature
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
Figure 10. Differential Nonlinearity vs. Temperature
0.187
0.125
VDD = 5V
TA = 25°C
VREF = 2.5V
TA = 25°C
0.062
0.125
LINEARITY ERROR (LSB)
DNL
0
–0.062
DNL
0.062
0
INL
–0.062
–0.125
–0.187
2
3
4
5
SUPPLY VOLTAGE (V)
6
7
01943-008
INL
Figure 8. Linearity Error vs. Supply Voltage
–0.125
0
1
2
3
4
REFERENCE VOLTAGE (V)
5
Figure 11. Linearity Error vs. Reference Voltage
Rev. A | Page 7 of 16
6
01943-011
INTEGRAL NONLINEARITY (LSB)
VDD = 5V
VREF = 2.5V
LINEARITY ERROR (LSB)
16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE
01943-010
–0.187
VDD = 5V
VREF = 2.5V
01943-009
DIFFERENTIAL NONLINEARITY (LSB)
0.062
01943-006
INTEGRAL NONLINEARITY (LSB)
VDD = 5V
VREF = 2.5V
AD5551/AD5552
0
0.037
VDD = 5V
VREF = 2.5V
TA = 25°C
–0.025
0.025
ZERO-CODE ERROR (LSB)
GAIN ERROR (LSB)
–0.050
–0.075
–0.100
–0.125
–0.150
–0.175
VDD = 5V
VREF = 2.5V
TA = 25°C
0.012
0
–0.012
–0.025
–40
25
TEMPERATURE (°C)
–0.037
01943-012
–0.225
85
Figure 12. Gain Error vs. Temperature
25
TEMPERATURE (°C)
85
Figure 15. Zero-Code Offset Error vs. Temperature
132
2.0
VDD = 5V
VREF = 2.5V
130 TA = 25°C
TA = 25°C
128
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
–40
01943-015
–0.200
126
124
122
120
1.5
REFERENCE VOLTAGE
VDD = 5V
1.0
SUPPLY VOLTAGE
VREF = 2.5V
0.5
–40
25
TEMPERATURE (°C)
85
0
01943-013
116
0
1
2
3
4
6
Figure 16. Supply Current vs. Reference Voltage or Supply Voltage
Figure 13. Supply Current vs. Temperature
200
200
VDD = 5V
VREF = 2.5V
TA = 25°C
180
REFERENCE CURRENT (µA)
160
140
120
100
80
60
40
150
100
50
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
DIGITAL INPUT VOLTAGE (V)
0
0
10,000
20,000
30,000 40,000
CODE (Decimal)
50,000
60,000
Figure 17. Reference Current vs. Code
Figure 14. Supply Current vs. Digital Input Voltage
Rev. A | Page 8 of 16
70,000
01943-017
20
01943-014
SUPPLY CURRENT (µV)
5
VOLTAGE (V)
01943-016
118
AD5551/AD5552
VREF = 2.5V
VDD = 5V
TA = 25°C
VREF = 2.5V
VDD = 5V
TA = 25°C
2µs/DIV
CS (5V/DIV)
DIN (5V/DIV)
10pF
50pF
100pF
200pF
VOUT (0.5V/DIV)
01943-018
2µs/DIV
Figure 18. Digital Feedthrough
Figure 20. Large Signal Settling Time
5
1.236
CS
–10
1.230
–15
1.228
VOUT
–20
1.226
VOUT (50mV/DIV)
GAIN = –216
–25
0
0.5
1.0
1.5
TIME (ns)
01943-019
0.5µs/DIV
–30
2.0
Figure 19. Digital-to-Analog Glitch Impulse
Figure 21. Small Signal Settling Time
Rev. A | Page 9 of 16
01943-021
1.232
DIGITAL VOLTAGE (V)
VOUT (1V/DIV)
–5
VOLTAGE (V)
VREF = 2.5V
VDD = 5V
TA = 25°C
0
1.234
1.224
–0.5
01943-020
VOUT (50mV/DIV)
AD5551/AD5552
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL vs. code plot can be seen in Figure 6.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. A typical DNL vs. code plot can be seen
in Figure 9.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It
is the deviation in slope of the DAC transfer characteristic
from ideal.
Gain Error Temperature Coefficient
This is a measure of the change in gain error with changes in
temperature. It is expressed in ppm/°C.
Zero-Code Error
Zero code error is a measure of the output error when zero code
is loaded to the DAC register.
Zero-Code Temperature Coefficient
This is a measure of the change in zero code error with a change
in temperature. It is expressed in mV/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by
1 LSB at the major carry transition. A plot of the glitch impulse
is shown in Figure 19.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. CS is
held high, while the CLK and DIN signals are toggled. It is
specified in nV-sec and is measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa. A
typical plot of digital feedthrough is shown in Figure 18.
Power Supply Rejection Ratio
This specification indicates how the output of the DAC is
affected by changes in the power supply voltage. Power-supply
rejection ratio is quoted in terms of % change in output per %
change in VDD for full-scale output of the DAC. VDD is varied
by ±10%.
Reference Feedthrough
This is a measure of the feedthrough from the VREF input to the
DAC output when the DAC is loaded with all 0s. A 100 kHz,
1 V p-p is applied to VREF. Reference feedthrough is expressed
in mV p-p.
Rev. A | Page 10 of 16
AD5551/AD5552
THEORY OF OPERATION
The AD5551/AD5552 are single, 14-bit, serial input, voltage
output DACs. They operate from a single supply ranging from
2.7 V to 5.5 V and consume typically 125 μA with a supply of
5 V. Data is written to these devices in a 14-bit word format, via
a 3-or 4-wire serial interface. To ensure a known power-up
state, these parts were designed with a power-on reset function.
In unipolar mode, the output is reset to 0 V, while in bipolar
mode, the AD5552 output is set to −VREF. Kelvin sense
connections for the reference and analog ground are included
on the AD5552.
DIGITAL-TO-ANALOG SECTION
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 22. The DAC
architecture of the AD5551/AD5552 is segmented. The four
MSBs of the 14-bit data word are decoded to drive 15 switches,
E1 to E15. Each of these switches connects one of 15 matched
resistors to either AGND or VREF. The remaining 10 bits of the
data word drive switches S0 to S9 of a 10-bit voltage mode R-2R
ladder network.
VOUT
2R
2R . . . . .
2R
2R
2R . . . . .
2R
S0
S1 . . . . .
S9
E1
E2 . . . . .
E15
UNIPOLAR OUTPUT OPERATION
01943-022
VREF
10-BIT R-2R LADDER
FOUR MSBs DECODED
INTO 15 EQUAL SEGMENTS
Figure 22. DAC Architecture
With this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by
the reference is heavily code dependent. The output voltage is
dependent on the reference voltage as shown in the following
equation:
VOUT =
The AD5552 has an LDAC function that allows the DAC latch
to be updated asynchronously by bringing LDAC low after CS
goes high. LDAC should be maintained high while data is
written to the shift register. Alternatively, LDAC may be tied
permanently low to update the DAC synchronously. With
LDAC tied permanently low, the rising edge of CS loads
the data to the DAC.
These DACs are capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low-supply current, typically
300 μA, and a low-offset error. The AD5551 provides a unipolar
output swing ranging from 0 V to VREF. The AD5552 can be configured to output both unipolar and bipolar voltages. Figure 23
shows a typical unipolar output voltage circuit. The code table
for this mode of operation is shown in Table 6.
2.5V
5V
10µF
0.1µF
SERIAL
INTERFACE
CS
VREF × D
0.1µF
VDD VREFF *
DIN
2N
AD5551/
AD5552
SCLK
LDAC*
where:
D is the decimal data word loaded to the DAC register.
N is the resolution of the DAC.
DGND
AGND
VOUT
AD820/
OP196
UNIPOLAR
OUTPUT
EXTERNAL
OP AMP
*AD5552 ONLY.
Figure 23. Unipolar Output
For a reference of 2.5 V, the equation simplifies to the following,
VOUT =
VREFS *
01943-023
2R
R
The AD5551/AD5552 are controlled by a versatile 3-wire serial
interface, which operates at clock rates up to 25 MHz and is
compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. The timing diagram can be seen in Figure 3. Input
data is framed by the chip select input, CS. After a high-to-low
transition on CS, data is shifted synchronously and latched into
the input register on the rising edge of the serial clock, SCLK.
Data is loaded MSB first in 14-bit words. After 14 data bits
have been loaded into the serial input register, a low-to-high
transition on CS transfers the contents of the shift register to
the DAC. Data can only be loaded to the part while CS is low.
+
R
SERIAL INTERFACE
Table 6. Unipolar Code Table
2.5 × D
16,384
This gives a VOUT of 1.25 V with midscale loaded, and a VOUT
of 2.5 V with full-scale loaded to the DAC. The LSB size is
VREF/16,384.
DAC Latch Contents
MSB
LSB
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
Rev. A | Page 11 of 16
Analog Output
VREF × (16,383/16,384)
VREF × (8192/16,384) = ½ VREF
VREF × (1/16,384)
0V
AD5551/AD5552
Assuming a perfect reference, the worst-case output voltage
may be calculated from the following equation:
VOUT −UNI =
Assuming a perfect reference, the worst-case bipolar output
voltage may be calculated from the following equation.
D
× (VREF + VGE ) + VZSE + INL
214
VOUT − BIP =
where:
VOUT–UNI is the unipolar mode worst-case output.
D is the decimal code loaded to the DAC.
VREF is the reference voltage applied to part.
VGE is the gain error in volts.
VZSE is the zero-scale error in volts.
INL is the integral nonlinearity in volts.
OUTPUT AMPLIFIER SELECTION
With the aid of an external op amp, the AD5552 may be configured to provide a bipolar voltage output. A typical circuit of
such operation is shown in Figure 24. The matched bipolar
offset resistors RFB and RINV are connected to an external op amp
to achieve this bipolar output swing where RFB = RINV = 28 kΩ.
Table 7 shows the transfer function for this output operating
mode. Also provided on the AD5552 are a set of Kelvin
connections to the analog ground inputs.
5V 2.5V
+
10µF
0.1µF
+5V
RFB
VDD
VREFF
CS
VREFS
RFB
INV
RINV
DIN
SCLK
AD5552
LDAC
DGND
AGNDF AGNDS
EXTERNAL
OP AMP
VOUT
UNIPOLAR
OUTPUT
–5V
Figure 24. Bipolar Output (AD5552 Only)
01943-024
SERIAL
INTERFACE
1 + (2 + RD) / A
where:
VOS is the external op amp input offset voltage.
RD is the RFB and RIN resistor matching error, unitless.
A is the op amp open-loop gain.
BIPOLAR OUTPUT OPERATION
0.1µF
[(VOUT −UNI + VOS )(2 + RD) − VREF (1 + RD)
For bipolar mode, use a precision amplifier, supplied from a
dual power supply. This provides the ±VREF output. In a singlesupply application, selection of a suitable op amp may be more
difficult as the output swing of the amplifier does not usually
include the negative rail, in this case AGND. This can result in
some degradation of the specified performance unless the
application does not use codes near zero.
The selected op amp needs to have a very low-offset voltage,
(the DAC LSB is 152 μV with a 2.5 V reference), to eliminate
the need for output offset trims. Input bias current should also
be very low as the bias current multiplied by the DAC output
impedance (approximately 6K) adds to the zero-code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code-independent, but to minimize gain errors,
the input impedance of the output amplifier should be as high
as possible. The amplifier should also have a 3 dB bandwidth of
1 MHz or greater. The amplifier adds another time constant to
the system, therefore increasing the settling time of the output.
A higher 3 dB amplifier bandwidth results in a faster effective
settling time of the combined DAC and amplifier.
Table 7. Bipolar Code Table
FORCE SENSE BUFFER AMPLIFIER SELECTION
DAC Latch Contents
MSB
LSB
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
These amplifiers can be single-supply or dual supplies, low
noise amplifiers. A low-output impedance at high frequencies
is preferred as they need to be able to handle dynamic currents
of up to ±20 mA.
Analog Output
+VREF × (8191/8192)
+VREF × (1/8192)
0V
−VREF × (1/8192)
−VREF × (8191/8192) = –VREF
Rev. A | Page 12 of 16
AD5551/AD5552
REFERENCE AND GROUND
POWER-ON RESET
As the input impedance is code-dependent, the reference pin
should be driven from a low-impedance source. The AD5551/
AD5552 operate with a voltage reference ranging from 2 V to
VDD. Although DAC’s full-scale output voltage is determined by
the reference, references below 2 V results in reduced accuracy.
Table 6 and Table 7 outline the analog output voltage for
particular digital codes. For optimum performance, Kelvin
sense connections are provided on the AD5552.
These parts have a power-on reset function to ensure the output
is at a known state upon power-up. After power-up, the DAC
register contains all zeros, until data is loaded from the serial
register. However, the serial register is not cleared on power-up,
so its contents are undefined. When loading data initially to the
DAC, 14 bits or more should be loaded to prevent erroneous
data appearing on the output. If more than 14 bits are loaded,
only the last 14 are kept, and if fewer than 14 are loaded, bits
remain from the previous word. If the AD5551/AD5552 needs
to be interfaced with data shorter than 14 bits, the data should
be padded with zeros at the LSBs.
If the application does not require separate force and sense
lines, they should be tied together close to the package to
minimize voltage drops between the package leads and the
internal die. ADR291 and ADR293 are suitable references
for this product.
POWER SUPPLY AND REFERENCE BYPASSING
For accurate high-resolution performance, it is recommended
that the reference and supply pins be bypassed with a 10 μF
tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.
Rev. A | Page 13 of 16
AD5551/AD5552
MICROPROCESSOR INTERFACING
MICROWIRE TO AD5551/AD5552 INTERFACE
Figure 27 shows an interface between the AD5551/AD5552 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and into the AD5551/
AD5552 on the rising edge of the serial clock. No glue logic is
required as the DAC clocks data into the input shift register on
the rising edge.
CS
SO
DIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 27. MICROWIRE to AD5551/AD5552 Interface
80C51/80L51 TO AD5551/AD5552 INTERFACE
A serial interface between the AD5551/AD5552 and the 80C51/
80L51 microcontroller is shown in Figure 28. TxD of the microcontroller drives the SCLK of the AD5551/AD5552, while RxD
drives the serial data line of the DAC. P3.3 is a bit programmable
pin on the serial port which is used to drive CS.
AD5551/
AD5552*
ADSP-21xx*
CS
AD5551/
AD5552*
80C51/
80L51*
P3.4
LDAC**
CS
P3.3
CS
DT
DIN
RxD
DIN
SCLK
TxD
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5552 ONLY.
01943-025
LDAC**
TFS
FO
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5552 ONLY.
Figure 25. ADSP-21xx to AD5551/AD5552 Interface
Figure 28. 80C51/80L51 to AD5551/AD5552 Interface
68HC11 TO AD5551/AD5552 INTERFACE
Figure 26 shows a serial interface between the AD5551/AD5552
and the 68HC11 microcontroller. SCK of the 68HC11 drives the
SCLK of the DAC, while the MOSI output drives the serial data
line DIN. CS signal is driven from one of the port lines. The
68HC11 is configured for master mode; MSTR = 1, CPOL = 0,
and CPHA = 0. Data appearing on the MOSI output is valid on
the rising edge of SCK.
AD5551/
AD5552*
68HC11/
68L11*
PC6
LDAC**
PC7
CS
MOSI
DIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5552 ONLY.
01943-026
SCK
01943-027
ADSP-21xx TO AD5551/AD5552 INTERFACE
Figure 25 shows a serial interface between the AD5551/AD5552
and the ADSP-21xx. The ADSP-21xx should be set to operate in
the SPORT (serial port) transmit alternate framing mode. The
ADSP-21xx is programmed through the SPORT control register
and should be configured as follows: internal clock operation,
active low framing, 16-bit word length. The first 2 bits are don’t
care as AD5551/AD5552 keeps the last 14 bits. Transmission is
initiated by writing a word to the Tx register after the SPORT
has been enabled. Because of the edges-triggered difference, an
inverter is required at the SCLKs between the DSP and the DAC.
AD5551/
AD5552*
MICROWIRE*
01943-028
Microprocessor interfacing to the AD5551/AD5552 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data
signal and a synchronization signal. The AD5551/AD5552
require a 14-bit data word with data valid on the rising edge of
SCLK. The DAC update may be done automatically when all
the data is clocked in or it may be done under control of LDAC
(AD5552 only).
Figure 26. 68HC11/68L11 to AD5551/AD5552 Interface
The 80C51/80L51 provides the LSB first, while the AD5551/
AD5552 expect the MSB of the 14-bit word first. Take care to
ensure that the transmit routine takes this into account. Usually
it can be done through software by shifting out and accumulating the bits in the correct order before inputting to the DAC.
Also, 80C51 outputs 2 byte words/16 bits data, thus the first
two bits, after rearrangement, should be don’t care as they are
dropped from the 14-bit word of the DAC.
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock must
be inverted as the DAC clocks data into the input shift register
on the rising edge of the serial clock. The 80C51/80L51 transmits
its data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. As the DAC requires a 14-bit word,
P3.3 (or any one of the other programmable bits) is the CS
input signal to the DAC, so P3.3 should be brought low at the
beginning of the 16-bit write cycle 2 × 8 bit words and held low
until the 16-bit 2 × 8 cycle is completed. After that, P3.3 is
brought high again and the new data loads to the DAC. Again,
the first two bits, after rearranging, should be don’t care. LDAC
on the AD5552 may also be controlled by the 80C51/80L51
serial port output by using another bit programmable pin, P3.4.
Rev. A | Page 14 of 16
AD5551/AD5552
APPLICATIONS INFORMATION
OPTOCOUPLER INTERFACE
DECODING MULTIPLE AD5551/AD5552S
The digital inputs of the AD5551/AD5552 are Schmitttriggered, so they can accept slow transitions on the digital
input lines. This makes these parts ideal for industrial applications where it may be necessary that the DAC is isolated from
the controller via optocouplers. Figure 29 illustrates such an
interface.
The CS pin of the AD5551/AD5552 can be used to select one of
a number of DACs. All devices receive the same serial clock and
serial data, but only one device receives the CS signal at any one
time. The DAC addressed is determined by the decoder. There
is some digital feedthrough from the digital input lines. Using a
burst clock minimizes the effects of digital feedthrough on the
analog signal channels. Figure 30 shows a typical circuit.
POWER
10µF
0.1µF
SCLK
CS
VDD
DIN
10kΩ
SCLK
SCLK
VDD
ENABLE
10kΩ
CS
CODED
ADDRESS
SCLK
EN
CS
DECODER
DGND
CS
10kΩ
AD5551/
AD5552
VOUT
DIN
GND
SCLK
01943-029
DIN
VOUT
DIN
VDD
DIN
AD5551/
AD5552
SCLK
VOUT
CS
VOUT
DIN
VDD
AD5551/
AD5552
VDD
AD5551/
AD5552
Figure 29. AD5551/AD5552 in an Optocoupler Interface
CS
AD5551/
AD5552
DIN
VOUT
SCLK
Figure 30. Addressing Multiple AD5551/AD5552s
Rev. A | Page 15 of 16
01943-030
5V
REGULATOR
AD5551/AD5552
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 31. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
8
14
1
7
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
060606-A
4.00 (0.1575)
3.80 (0.1496)
Figure 32. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1
AD5551BRZ
AD5551BRZ-REEL7
AD5551BR
AD5551BR-REEL7
AD5552BRZ
1
INL
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
DNL
±0.8 LSB
±0.8 LSB
±0.8 LSB
±0.8 LSB
±0.8 LSB
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Z = RoHS Compliant Part.
©2000–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01943-0-5/10(A)
Rev. A | Page 16 of 16
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
14-Lead SOIC_N
Package Option
R-8
R-8
R-8
R-8
R-14
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