PCM66P ® FPO FPO 16-Bit CMOS Monolithic Audio DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● LOW COST 16-BIT 2-CHANNEL CMOS MONOLITHIC D/A CONVERTER The PCM66P is a low cost, dual output 16-bit CMOS digital-to-analog converter. The PCM66P features true glitch-free voltage outputs, internal reference and requires only a single +5V supply. Total power dissipation is less than 50mW max. Low maximum Total Harmonic Distortion + Noise (–86dB max; PCM66PJ) is 100% tested. Either one or two channel output modes are fully user selectable. ● ● ● ● ● ● SINGLE SUPPLY +5V OPERATION 50mW POWER DISSIPATION GLITCH-FREE VOLTAGE OUTPUTS LOW DISTORTION: –86dB max THD + N COMPLETE WITH REFERENCE SERIAL INPUT FORMAT The PCM66P comes in a space-saving 20-pin plastic SOIC package. PCM66P accepts a serial data input format and is compatible with other Burr-Brown PCM products such as the industry standard PCM56P. ● SINGLE OR DUAL DAC MODE OPERATION ● PLASTIC 20-PIN SOIC PACKAGE VCC (+5V) V REF Reference A COM SDM SEL LRDAC LRCLK Control Logic 16-Bit VOUT DAC Integrate & Hold Amp V OUT WDCLK CLK DATA Serial-to-Parallel Shift Register International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (602) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1990 Burr-Brown Corporation L CH Out Integrate & Hold Amp R CH Out D COM • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-1051D Printed in U.S.A. October, 1993 SPECIFICATIONS ELECTRICAL All specifications at 25°C, and +VCC = +5V unless otherwise noted. PCM66P AND PCM66P, J PARAMETER CONDITIONS MIN TYP RESOLUTION DYNAMIC RANGE MAX UNITS 16 Bits 96 DIGITAL INPUT Logic Family Logic Level: VIH VIL Data Format Input Clock Frequency DYNAMIC CHARACTERISTICS TOTAL HARMONIC DISTORTION + N(2) PCM60P/66P: f = 991Hz (0dB)(3) f = 991Hz (–20dB) f = 991Hz (–60dB) PCM60P-J/66P-J: f = 991Hz (0dB) f = 991Hz (–20dB) f = 99lHz (–60db) IIH = +40µA max IIL = –40µA max +2.4 0 IDLE CHANNEL SNR(6) ANALOG OUTPUT Output Range Output Impedance Short Circuit Duration Settling Time Glitch Energy POWER SUPPLY REQUIREMENTS +VCC Supply Voltage Supply Current Power Dissipation +5.25 0.8 V V Serial BTC(1) 8.5 fS fS fS fS fS fS = 176.4kHz(4) = 176.4kHz = 176.4kHz = 176.4kHz = 176.4kHz = 176.4kHz MHz –88 –68 –28 –92 –68 –28 CHANNEL SEPARATION TRANSFER CHARACTERISTICS ACCURACY Gain Error Gain Mismatch Bipolar Zero Error(5) Gain Drift Warm-up Time dB TTL Compatible CMOS +80 0°C to 70°C –86 +85 ±2 ±1 ±30 100 VOUT = 2.6 Channel to Channel –82 dB ±10 1 20-20kHz with A-weighted filter dB dB dB dB dB dB % % mV ppm/°C minute ±90 dB 2.6 2 Vp-p Ω To Be Determined Suffieicnt to Meet 176.4kHz THD + N Specs Meets All THD + N Specs Without External Output Deglitching +4.75 VCC = +5V TEMPERATURE RANGE Specification Operating Storage 0 –30 –60 +5 +9.5 +5.25 50 V mA mW +70 +70 +100 °C °C °C NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (DistortionRMS + NoiseRMS) / SignalRMS. (3) D/A converter output frequency/signal level (on both left and right channels). (4) D/A converter sample frequency (4 x 44.1kHz; 4 times oversampling per channel). (5) Offset error at bipolar zero. (6) Ratio of output at BPZ (Bipolar Zero) to the full scale range using 20kHz low pass filter in addition to an A-weighted filter. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent right or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM66P 2 PACKAGE INFORMATION(1) PCM66P PIN ASSIGNMENTS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION MNEMONIC Left/Right Clock Word Clock Clock Input Data Input No Connection Digital Common Analog Common Left Channel VOUT Output Common Right Channel VOUT Analog Supply Analog Supply Reference Decouple Reference Sense Reference Output Analog Supply Analog Supply Digital Supply Single DAC Mode Left/Right DAC Select MODEL LRCLK WDCLK CLK DATA NC DCOM ACOM L CH Out VCOM R CH Out +VCC +VCC CREF VREF SENSE VREF +VCC +VCC +VCC SDM SEL LRDAC PCM66P PCM66P, J PACKAGE PACKAGE DRAWING NUMBER 20-Pin SOIC 20-Pin SOIC 248 248 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. USA OEM PRICES ORDERING INFORMATION MODEL 1–24 Basic Model Number PCM66P $11.80 P: Plastic PCM66P-J 13.30 Performance Grade Code 25-99 PCM66P100+ -X $10.40 11.70 $9.15 10.30 ABSOLUTE MAXIMUM RATINGS DC Supply Voltage ............................................................................ ±10V Input Voltage Range ........................................................... –3V to +5.25V Power Dissipation ............................................................................ 50mW Operating Temperature .................................................... –30°C to +70°C Storage Temperature ...................................................... –60°C to +100°C Lead Temperature (soldering, 10s) ............................................... +300°C THEORY OF OPERATION ships. Data for left and right channel output is loaded alternately into the PCM66P while the control logic switches the left and right output amplifiers between the appropriate integrate and hold modes. Data word latching is controlled by WDCLK (word clock) and channel selection is made by LRCLK (left/right clock). Figure 1 shows the timing for the single DAC two-channel mode of operation. The block diagram in Figure 2 shows how a single DAC output provides switched output to both integrate and hold amplifiers. Output between left and right channels in this mode is not in phase. See Figure 3 for proper connection of the PCM66P in the two-channel DAC mode. The PCM66P is a dual output, 16-bit CMOS digital-to-analog audio converter. The PCM66P, complete with internal reference, has two glitch-free voltage outputs and requires only a single +5V power supply. Output modes using either one or two channels per DAC are user selectable. The PCM66P accepts a serial data input format that is compatible with other BurrBrown PCM products such as the industry standard PCM56P. ONE DAC TWO-CHANNEL OPERATION Normally, the PCM66P is operated with a continuous clock input in a two-channel output mode. This mode is selected when SDM SEL is held low (single DAC mode select). Refer to the truth table shown by Table I for exact control logic relation- PIN FUNCTIONS SDM SEL LRDAC LRCLCK WDCLK SERIAL DATA WORD INPUT LEFT CHANNEL OUTPUT RIGHT CHANNEL OUTPUT 0 0 0 0 X X X X 0 0 1 1 0 1 0 1 Right Right Left Left Hold Integrate Hold Hold Hold Hold Hold Integrate 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 Inhibited Inhibited Left Left VCOM VCOM VCOM VCOM Hold Hold Integrate Integrate 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 Right Right Inhibited Inhibited VCOM VCOM VCOM VCOM Hold Hold Integrate Integrate NOTE: Positive edge of CLK (P3) latches LRCLK (P1), WDCLK (P2), and DATA (P4). TABLE I. PCM66P Logic Truth Table. ® 3 PCM66P TWO CHANNEL PER DAC OUTPUT MODE P3 (CLK) P2 (WDCLK) Load Right Channel Data P1 (LRCLK) P4 (DATA) 1 2 9 8 10 11 Hold P10 (LCH OUT) 12 13 Load Left Channel Data 14 15 16 1 2 8 9 10 11 12 13 Integrate Hold Hold Integrate 14 15 16 P10 (LCH VOUT ) P12 (RCH OUT) P12 (RCH VOUT ) NOTES: Single DAC Mode Select = 0; L/R DAC Select = X; WDCLK = 50% duty cycle; Serial Data is read in MSB first with BTC coding (MSB = Bit 1). SINGLE CHANNEL PER DAC OUTPUT MODE P3 (CLK) Both DACs P2 (WDCLK) Both DACs P1 (LRCLK) Both DACs P4 (DATA) Both DACs Load Right DAC Data 1 2 8 P12 (RCH OUT) Right DAC 9 10 11 12 13 Load Left DAC Data 14 15 16 1 2 8 9 10 11 12 13 Hold Integrate Hold Integrate P12 (RCH VOUT ) Right DAC P12 (RCH OUT) Left DAC P12 (RCH VOUT ) Left DAC NOTES: Single DAC Mode Select = 1; L/R DAC Select = 0 (Left DAC) or 1 (Right DAC). FIGURE 1. PCM66P Timing Diagram. ® PCM66P 4 14 15 16 DATA Serial/Parallel Shift Register CLK Mode Control Logic WDCLK LRCLK LRDAC 16-Bit Input Data Latch 4kΩ 10kΩ 16-Bit D/A Converter SDM SEL 30kΩ 20kΩ – + 0–3.5V 4kΩ 30kΩ LCH V OUT VCOM Reference – + – + 20kΩ – + V REF SEN +V CC V REF R CH V OUT C REF +V CC FIGURE 2. PCM66P Block Diagram. PCM66P Digital Input L CH Out Mode Select 1 LRCLK Mode 2 20 2 WDCLK Mode 1 19 3 CLK +VCC 18 4 DATA +VCC 17 5 NC +VCC 16 6 D COM 7 A COM 8 L CH Out 9 V COM +VCC 12 10 R CH Out +VCC 11 VREF 15 V REF SEN 330pF 330pF input with no additional input signals being required to latch the appropriate data from an alternating L/R data word input stream. In the single DAC mode, the PCM66P’s left channel output is disabled and held at +VCOM. In this mode both DACs share common inputs for DATA, CLK, WDCLK, and LRCLK. Otherwise circuit connection is the same as the two-channel DAC mode, with the exception of LRDAC whose level selects whether the single DAC will output dedicated left or right channel data. 10µF INTEGRATE AND HOLD OUTPUT AMPLIFIERS The PCM66P incorporates integrate and hold amplifiers on each output channel. This allows a single, very fast DAC to feed both amplifiers and reduce circuit complexity. It also serves to block the output glitch from the DAC to the individual channel outputs and effectively makes the PCM66P outputs “glitch-free.” The PCM66P is a single +5V supply device with a voltage output swing of 2.8Vp-p. The outputs swing asymmetrically around VCOM (+VCC – 2.33V). See Table II for exact input/output relationships. Since true CMOS amplifiers are used on the PCM66P, the load resistance on the outputs should not be less than 100kΩ and the capacitive loads should not exceed 100pF. For maximum low-distortion performance, output buffer amplifiers should be considered. 14 CREF 13 R CH Out CREF 0.1µF + 100µF CCOM 3.3µF +VCC +5V FIGURE 3. PCM66P Connection Diagram. TWO DAC TWO-CHANNEL OPERATION In phase, two-channel output can be obtained by using two PCM66Ps and choosing the single DAC mode (setting SDM SEL high). With the use of a high or low input level on LRDAC (P left/right DAC select), each DAC can have its right channel output dedicated to either left or right data ® 5 PCM66P DIGITAL INPUT performance is typically indicative of 14-bit to 15-bit integral linearity in the DAC depending on the grade specified. The relationship between THD + N and linearity, however, is not such that an absolute linearity specification for every individual output code can be guaranteed. ANALOG OUTPUT Binary Two’s Complement (Hex) DAC Output (V) Voltage (V) VOUT Mode 7FFF 0000 8000 2E5B +FS BPZ –FS VCOM +3.5629443 +2.1629871 +0.7630299 +2.6700000 IDLE CHANNEL SNR TABLE II. PCM66P Input/Output Relationships. Another appropriate spec for a digital audio converter is idle channel signal-to-noise ratio (idle channel SNR). This is the ratio of the noise on either DAC output at bipolar zero in relation to the full scale range of the DAC. The output of the DAC is band limited from 20Hz to 20kHz and an Aweighted filter is applied to make this measurement. DISCUSSION OF SPECIFICATIONS TOTAL HARMONIC DISTORTION + NOISE The key specification for the PCM66P is total harmonic distortion plus noise. Digital data words are read into the PCM66P at four times the standard audio sampling frequency of 44.1kHz or 176.4kHz for each channel, such that a sine wave output of 991Hz is realized. For production testing, the output of the DAC goes to a programmable gain amplifier to provide gain at lower signal output test levels and then through a 20kHz low pass filter before being fed into an analog type distortion analyzer. Figure 4 shows a block diagram of the production THD + N test setup. OFFSET, GAIN, AND TEMPERATURE DRIFT The PCM66P is specified for other important parameters such as channel separation and gain mismatch between output channels. And although the PCM66P is primarily meant for use in dynamic applications, typical specs are also given for more traditional DC parameters such as gain error, bipolar zero offset error, and temperature gain drift. TIMING CONSIDERATIONS In terms of signal measurement, THD + N is the ratio of DistortionRMS + NoiseRMS/SignalRMS expressed in dB. For the PCM66P, THD + N is 100% tested at three different output levels using the test setup shown in Figure 4. It is significant to note that this circuit does not include any output deglitching circuitry. This means the PCM66P meets even its –60dB THD + N specification without use of external deglitchers. The data format of the PCM66P is binary two’s complement (BTC) with the most significant bit (MSB) being first in the serial input bit stream. Table II describes the exact input data to voltage output coding relationship. Any number of bits can precede the 16 bits to be loaded, as only the last 16 will be transferred to the parallel DAC register on the first positive edge of CLK (clock input) after WDCLK (word clock) has gone low. All inputs to the PCM66P are TTL level compatible. ABSOLUTE LINEARITY Even though absolute integral and differential linearity specs are not given for the PCM66P, the extremely low THD + N Use 400Hz High-Pass Filter and 30kHz Low-Pass Filter Meter Settings Distortion Meter (Shiba Soku Model 725 or Equivalent) Low-Pass Filter (Toko APQ-25 or Equivalent) Programmable Gain Amp 0dB to 60dB LOW-PASS FILTER CHARACTERISTIC Binary Counter Digital Code (EPROM) Parallel-to-Serial Conversion DUT (PCM60P/66P) (PCM66P) Gain (dB) 0 –20 –40 –60 –80 –100 –120 Clock Latch Enable Timing Logic Sampling Rate = 44.1kHz x 4 (176.4kHz) Output Frequency = 991Hz FIGURE 4. THD + N Test Setup Diagram. ® PCM66P 6 1 1 2 3 4 5 10 10 10 10 10 Frequency (Hz) WDCLK DUTY CYCLE WDCLK is the input signal that controls when data is loaded and how long each output is in the integrate mode. It is therefore recommended that a 50% (high) duty cycle be maintained on WDCLK. This will ensure that each output will have enough time to reach its final output value, and that the output level of each channel will be within the gain mismatch specification. Refer to Figure 1 for exact timing relationships of WDCLK to CLK and LRCLK and the outputs of the PCM66P. The WDCLK can be high longer than 50%, as long as setup and hold times shown in Figure 5 are observed and the time high is roughly equivalent for both left and right channels. 60ns min P3 (CLK) P4 (DATA) 15ns min P2 (WDCLK) P1 (LRCLK) 15ns min FIGURE 5. PCM66P Setup and Hold Timing Diagram. SETUP AND HOLD TIME The individual serial data bit shifts, the serial to parallel data transfer, and left/right control are triggered on positive CLK edges. The setup time required for DATA, WDCLK, and LRCLK to be latched by the next positive going CLK is 15ns minimum. A minimum hold time of 15ns is also required after the positive going CLK edge for each data bit to be shifted into the serial input register. Refer to Figure 5 for the timing relationship of these signals. 100µF decoupling capacitor as shown in Figure 3 should be used regardless of how good the +5V supply is to maximize power supply rejection. All grounds should be connected to the analog ground plane as close to the PCM66P as possible. FILTER CAPACITOR REQUIREMENTS As shown in Figure 3, CREF and VREF SENSE should have decoupling capacitors of 0.1µF (C4) and 10µF (C5) to +VCC respectively with no special tolerance being required. To maximize channel separation between left and right channels, 5% 300pF capacitors (C2 and C3) between VCOM and left and right channel outputs are required in addition to a 5% 3µF capacitor (C1) between VCOM and +5V. The ratio of 10k to 1 is the important factor here for proper circuit operation. Placement of all capacitors should be as close to the appropriate pins of the PCM66P as possible to reduce noise pickup from surrounding circuitry. MAXIMUM CLOCK RATE The 100% tested maximum clock rate of 8.47MHz for the PCM66P is derived by multiplying the standard audio sample rate of 44.1kHz times eight (4X oversampling times two channels) times the standard audio word bit length of 24 (44.1kHz x 4 x 2 x 24 = 8.47MHz). Note that this clock rate accommodates a 24-bit word length, even though only 16 bits are actually being used. APPLICATIONS “STOPPED-CLOCK” OPERATION The PCM66P is normally operated with a continuous clock input signal. If the clock is to be stopped between input data words, the last 16 bits shifted in are not actually shifted from the serial register to the latched parallel DAC register until the first clock after the one used to input bit 16 (LSB). This means the data is not shifted into the DHC latch until the start of the next 16-bit data word input, unless at least one additional clock accompanies the 16 used to serially shift in data in the first place. In either case, the setup and hold times for DATA, WDCLK, and LRCLK must still be observed. INSTALLATION Probably the most popular use of the PCM66P is in applications requiring single power supply operation. For example, the PCM66P is ideal for automotive compact disk (CD) and digital audio tape (DAT) playback units. To use a more complex bipolar DAC requiring ±5V supplies in the +12V application, for example, would require driving a stable “floating” ground and regulating the +12V to +10V. The single supply CMOS PCM66P would only require a +5V zener diode to regulate its 50mW max supply. The outputs could be AC coupled to the rest of the circuit for perfectly acceptable high dynamic performance. The PCM66P is ideal in any application requiring a minimum of additional circuitry as well as ultra-low-power CMOS performance. The PCM66P only requires a single +5V supply. The +5V supply, however, is used in deriving the internal reference. It is therefore very important that this supply be as “clean” as possible to reduce coupling of supply noise to the outputs. If a good analog supply is available at greater than +5V, a zener diode can be used to obtain a stable +5V supply. A Of course, the PCM66P is the D/A converter of choice in any application requiring very low power dissipation. Portable battery powered test and measurement equipment requiring very low distortion digital to analog converters would be an ideal application for the CMOS PCM66P with its 50mW max power dissipation. ® 7 PCM66P