VCA810 SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 High Gain Adjust Range, Wideband, Voltage-Controlled Amplifier FEATURES DESCRIPTION D D D D D D D D D The VCA810 is a DC-coupled, wideband, continuously variable, voltage-controlled gain amplifier. It provides a differential input to single-ended output conversion with a high-impedance gain control input used to vary the gain over a –40dB to +40dB range linear in dB/V. HIGH GAIN ADJUST RANGE: 40dB DIFFERENTIAL IN/SINGLE-ENDED OUT LOW INPUT NOISE VOLTAGE: 2.4nV/Hz CONSTANT BANDWIDTH vs GAIN: 35MHz Operating from ±5V supplies, the gain control voltage for the VCA810 will adjust the gain from –40dB at 0V input to +40dB at –2V input. Increasing the control voltage above ground will attenuate the signal path to > 80dB. Signal bandwidth and slew rate remain constant over the entire gain adjust range. This 40dB/V gain control is accurate within ±1.5dB (±0.9dB for High Grade), allowing the gain control voltage in an AGC application to be used as a Received Signal Strength Indicator (RSSI) with ±1.5dB accuracy. HIGH dB/V GAIN LINEARITY: 0.3dB GAIN CONTROL BANDWIDTH: 25MHz LOW OUTPUT DC ERROR: < 40mV HIGH OUTPUT CURRENT: 60mA LOW SUPPLY CURRENT: 24.8mA (max for −40C to +85C temperature range) Excellent common-mode rejection and common-mode input range at the two high-impedance inputs allow the VCA810 to provide a differential receiver operation with gain adjust. The output signal is referenced to ground. Zero differential input voltage gives a 0V output with a small DC offset error. Low input noise voltage ensures good output SNR at the highest gain settings. APPLICATIONS D D D D D D D OPTICAL RECEIVER TIME GAIN CONTROL SONAR SYSTEMS VOLTAGE-TUNABLE ACTIVE FILTERS LOG AMPLIFIER In applications where pulse edge information is critical, and the VCA810 is being used to equalize varying channel loss, minimal change in group delay over gain setting will retain excellent pulse edge information. PULSE AMPLITUDE COMPENSATION AGC RECEIVER WITH RSSI IMPROVED REPLACEMENT FOR THE VCA610 An improved output stage provides adequate output current to drive the most demanding loads. While principally intended to drive analog-to-digital converters (ADCs) or 2nd-stage amplifiers, the ±60mA output current will easily drive doubly-terminated 50Ω lines or a passive post filter stage over the ±1.7V output voltage range. +5V 6 V+ V− VCA810 1 VCA810 RELATED PRODUCTS 8 Gain Adjust + X1 2 VC 5 VOUT SIGNAL BANDWIDTH (MHz) DUALS VCA811 — 80 2.4 80 — VCA2612 45 1.25 80 — VCA2613 45 1 80 — VCA2614 45 3.6 40 — VCA2616 45 3.3 40 — VCA2618 45 5.5 30 SINGLES 3 0 → −2V − 40dB → +40dB Gain INPUT NOISE (nV/Hz) GAIN ADJUST RANGE (dB) 7 −5V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2003−2004, Texas Instruments Incorporated ! ! www.ti.com " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6.5VDC Internal Power Dissipation . . . . . . . See Thermal Analysis Section Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS Input Common-Mode Voltage Range . . . . . . . . . . . . . . . . . . . . ±VS Storage Temperature Range: D . . . . . . . . . . . . . . −40°C to +125°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . +300°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . . . . 2000V (Charge Device Model) . . . . . . . . . . . . . . . . . . . 1500V (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING VCA810ID SO−8 D −40°C to +85°C VCA810 VCA810AID SO−8 D −40°C to +85°C VCA810A(2) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY VCA810ID Rails, 100 VCA810IDR Tape and Reel, 2500 VCA810AID Rails, 100 VCA810AIDR Tape and Reel, 2500 (1) For the most current specification and package information, see the Package Option Addendum located at the end of this data sheet. (2) The A indicating high grade will appear opposite the pin 1 marking indicator. PIN CONFIGURATION Top View SO−8 −In −VS 8 7 +VS VOUT 6 5 A(1) VCA810 1 +In 2 3 4 GND Gain NC(2) Control, VC NOTES: (1) High Grade Indicator. (2) NC = Not Connected. 2 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS: VS = 5V Boldface limits are tested at +25C. RL = 500Ω, and VIN = single-ended input on V+ with V− at ground, unless otherwise noted. VCA810ID TYP PARAMETER AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth Large-Signal Bandwidth Frequency Response Peaking Slew Rate Settling Time to 0.1% Rise-and-Fall Time Group Delay Group Delay Variation Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise Fully Attenuated Feedthrough Overdrive Recovery DC PERFORMANCE Output Offset Voltage(4) (both inputs grounded) Output Offset Voltage Drift Input Offset Voltage(4) Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT Common-Mode Input Range Common-Mode Rejection Ratio Input Impedance Differential Input Range(5) OUTPUT Voltage Output Swing Output Current Output Short-Circuit Current Output Impedance GAIN CONTROL (VC, Pin 3) Specified Gain Range Maximum Control Voltage Minimum Control Voltage Gain Accuracy Gain Drift Gain Control Slope Gain Control Linearity(6) Gain Control Bandwidth MIN/MAX OVER TEMPERATURE CONDITIONS +25°C +25°C(1) +0°C to +70°C(2) −40°C to +85°C(2) −2V ≤ VC ≤ 0 VO = 2VPP, −2 ≤ VC ≤ −1 VO < 500mVPP, −2 ≤ VC ≤ 0 VO = 3.5V Step, −2 ≤ VC ≤ −1, 10%−90% VO = 1V Step, −2 ≤ VC ≤ −1 VO = 1V Step, −2 ≤ VC ≤ −1 G=0dB, VC=−1V, f = 5MHz, VO = 500mVPP VO < 500mVPP, −2 ≤ VC ≤ 0, f = 5MHz 35 35 0.1 350 30 10 6.2 3.5 30 30 0.5 300 40 12 29 29 0.5 300 41 12.1 VO = 1VPP, f = 1MHz, VC = −1V, G = 0dB VO = 1VPP, f = 1MHz,VC = −1V, G = 0dB VC = −2V −2V ≤ VC ≤ 0V f ≤ 1MHz, VC > +200mV VIN = 2V to 0V, VC = −2V, G = 40dB Single-Ended or Differential Input −71 −35 2.4 1.4 −80 100 −51 −34 2.8 1.8 −70 150 −2V ≤ VC ≤ 0V ±4 22 Both Inputs Grounded ±0.1 0.25 −2V ≤ VC ≤ 0V −6 −10 −2V ≤ VC ≤ 0V ±100 600 VCM = 0.5V, VC = −2V, Input Referred VCM = 0V, Single-Ended VCM = 0V, Differential VC = 0V, VCM = 0V ±2.4 95 1 || 1 >10||<2 3 VC = −2V, RL ≥ 500Ω VC = −2V, RL = 100Ω VO = 0V VO = 0V VO = 0V, f < 100kHz ±1.8 ±1.7 ±60 ±120 0.2 Single-Ended or Differential Input ∆VC/∆dB = 25mV/dB G = −40dB G = +40dB −1.8V ≤ VC ≤ −0.2V VC < −1.8V, VC > −0.2V −1.8V ≤ VC ≤ −0.2V VC < −1.8V, VC > −0.2V −1.8V ≤ VC ≤ 0V VC < −1.8V UNITS MIN/ MAX TEST LEVELS(3) 29 29 0.5 295 41 12.1 MHz MHz dB V/µs ns ns ns ns min min min min min min typ typ B B B B B B C C −50 −32 3.4 2.0 −49 −29 3.5 2.1 dBc dBc nV/√Hz pA/√Hz dB ns min min max max max min B B B B B B ±30 ±125 ±0.30 ±1 −12 ±25 ±700 ±1.4 ±32 ±125 ±0.35 ±1.2 −14 ±30 ±800 ±2.2 mV V/°C mV µV/°C µA nA/°C nA nA/°C max max max max max max max max A B A B A B A B 2.3 85 ±2.3 83 ±2.2 80 V dB MΩ||pF kΩ||pF VPP min min typ typ typ A A C C C 1.7 1.6 40 ±1.4 ±1.3 ±35 ±1.3 ±1.2 ±32 V V mA mA Ω min min min typ typ A A A C C dB V V dB dB dB/°C dB/°C dB/V dB dB MHz typ typ typ max max max max typ max max min C C C A A B B C A A B ±40 0 −2 ±0.4 ±0.5 1.5 2.2 ±2.5 ±3.7 ±0.02 ±0.03 ±3.5 ±4.7 ±0.03 ±0.04 −40 ±0.3 ±0.7 25 1 1.6 20 ±1.1 ±2.5 19 ±1.2 ±3.2 19 (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +30°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Total output offset is: Output Offset Voltage ± Input Offset Voltage x Gain. (5) Maximum input at minimum gain for < 1dB gain compression. (6) Maximum deviation from best line fit. (7) Magnitude. 3 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS: VS = 5V (continued) Boldface limits are tested at +25C. RL = 500Ω, and VIN = single-ended input on V+ with V− at ground, unless otherwise noted. VCA810ID TYP PARAMETER CONDITIONS +25°C Gain Control Slew Rate Gain Settling Time Input Bias Current Gain + Power-Supply Rejection Ratio Gain − Power-Supply Rejection Ratio POWER SUPPLY Specified Operating Voltage Minimum Operating Voltage Maximum Operating Voltage Positive Supply Quiescent Current Maximum Quiescent Current Minimum Quiescent Current Maximum Quiescent Current Minimum Quiescent Current Negative Supply Quiescent Current(7) Maximum Quiescent Current Minimum Quiescent Current Maximum Quiescent Current Minimum Quiescent Current Positive Power-Supply Rejection Ratio Negative Power-Supply Rejection Ratio THERMAL CHARACTERISTICS Specification Operating Range: ID Package Thermal Resistance D SO−8 80dB Gain Step 1%, 80dB Step VC = −1V VC = −2V, G = +40dB, +VS = 5V ±0.5V VC = −2V, G = +40dB, −VS = 5V ±0.5V 900 0.8 −1.5 0.5 0.7 MIN/MAX OVER TEMPERATURE +25°C(1) +0°C to +70°C(2) −40°C to +85°C(2) UNITS MIN/ MAX TEST LEVELS(3) typ typ max max max C C A A A −3.5 1.5 1.5 −4.5 1.8 1.8 −8 2 2 dB/ns µs µA dB/V dB/V 4 6 ±4 ±6 ±4 ±6 V V V typ min max C A A 10 10 18 18 12.5 7.5 20.5 15.5 12.6 7.2 22 14.5 12.7 7.1 22.3 13.5 mA mA mA mA min max min max A A A A 12 12 20 20 90 85 14.5 9.5 22.5 17.5 75 70 14.6 9.4 24.5 16.5 75 70 14.7 9.3 24.8 16 73 68 mA mA mA mA dB dB max min max min min min A A A A A A °C typ C °C/W typ C ±5 +VS = +VS = +VS = +VS = +5V, G = −40dB +5V, G = −40dB +5V, G = +40dB +5V, G = +40dB −VS = −5V, G = −40dB −VS = −5V, G = −40dB −VS = −5V, G = +40dB −VS = −5V, G = +40dB Input Referred, VC = −2V Input Referred, VC = −2V −40 to +85 Junction-to-Ambient 125 (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +30°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Total output offset is: Output Offset Voltage ± Input Offset Voltage x Gain. (5) Maximum input at minimum gain for < 1dB gain compression. (6) Maximum deviation from best line fit. (7) Magnitude. HIGH GRADE DC SPECIFICATIONS: VS = 5V (VCA810AID) Boldface limits are tested at +25C. RL = 500Ω, and VIN = single-ended input on V+ with V− at ground, unless otherwise noted. VCA810AID TYP PARAMETER CONDITIONS DC PERFORMANCE Single-Ended or Differential Input Output Offset Voltage −2V < VC < 0 +25°C MIN/MAX OVER TEMPERATURE +25°C(1) +0°C to +70°C(2) −40°C to +85°C(2) UNITS MIN/ MAX TEST LEVELS(3) ±4 14 ±24 ±26 mV max A Input Offset Voltage ±0.1 0.2 ±0.25 ±0.3 mV max A Input Offset Current ±100 500 ±600 ±700 mA max A −1.8V ≤ VC ≤ −0.2V VC < −1.8V, VC > −0.2V −1.8V ≤ VC ≤ 0V ±0.4 0.9 ±1.9 ±2.9 dB max A ±0.5 1.5 ±3.0 ±4.0 dB max A ±0.3 0.6 ±0.7 ±0.8 dB max A VC < −1.8V ±0.7 1.1 ±1.9 ±2.7 dB max A GAIN CONTROL (VC, Pin 3) Gain Accuracy Gain Control Linearity(4) Single-Ended or Differential Input (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +30°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Maximum deviation from best line fit. (5) Magnitude. 4 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 HIGH GRADE DC SPECIFICATIONS: VS = 5V (VCA810AID) (continued) Boldface limits are tested at +25C. RL = 500Ω, and VIN = single-ended input on V+ with V− at ground, unless otherwise noted. VCA810AID TYP PARAMETER MIN/MAX OVER TEMPERATURE CONDITIONS +25°C +25°C(1) +0°C to +70°C(2) −40°C to +85°C(2) UNITS MIN/ MAX TEST LEVELS(3) +VS = +5V, G = −40dB +VS = +5V, G = −40dB 10 11.5 11.6 11.7 10 8.5 8.2 8.1 mA min A mA max +VS = +5V, G = +40dB +VS = +5V, G = +40dB 18 19.5 21 A 21.3 mA min 18 16.5 A 15.5 14.5 mA max A −VS = −5V, G = −40dB −VS = −5V, G = −40dB 12 12 14 14.1 14.2 mA min A 10 9.9 9.8 mA max −VS = −5V, G = +40dB −VS = −5V, G = +40dB A 20 22 24 24.3 mA min A 20 18 17 16.5 mA max A POWER SUPPLY Positive Supply Quiescent Current Maximum Quiescent Current Minimum Quiescent Current Maximum Quiescent Current Minimum Quiescent Current Negative Supply Quiescent Current(5) Maximum Quiescent Current Minimum Quiescent Current Maximum Quiescent Current Minimum Quiescent Current (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +30°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Maximum deviation from best line fit. (5) Magnitude. 5 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS: VS = 5V RL = 500Ω and VIN = single-ended input on V+ with V− at ground, unless otherwise noted. SMALL−SIGNAL FREQUENCY RESPONSE GAIN CONTROL FREQUENCY RESPONSE 60 3 R L = 500Ω VIN = 10mVPP, VOUT = 1VPP 0 40 VIN = 100mVPP, VOUT = 1VPP −3 Gain (dB) Gain (dB) 20 VIN = 1VPP, VOUT = 1VPP 0 VOUT = 2VPP, VIN = 200mVPP −20 −9 −12 VOUT = 2VPP, VIN = 20mVPP −40 −6 −15 VC = −1VDC + 10mVPP −18 −60 1 10 100 1 1000 10 HIGH GAIN PULSE RESPONSE ATTENUATED PULSE RESPONSE 0.6 150 VIN = 10mVPP G = +40dB VIN = 2VPP G = −20dB 0.4 Output Voltage (V) Output Voltage (mV) 100 50 G = −40dB 0 −50 0.2 G = +20dB 0 −0.2 −0.4 −100 −0.6 −150 Time (20ns/div) Time (20ns/div) GAIN CONTROL PULSE RESPONSE 1.2 GAIN vs CONTROL VOLTAGE 60 G = 0dB to −40dB, VIN = 1VDC Specified Operating Range 40 1.0 20 0.8 Gain (dB) Output Voltage (V) 100 Frequency (MHz) Frequency (MHz) 0.6 0.4 0.2 0 −20 −40 −60 0 G = 0dB to +40dB, VIN = 10mVDC −0.2 Output Disabled for +0.15V ≤ VC ≤ +2V −80 −100 Time (20ns/div) 0.5 0 −0.5 −1.0 −1.5 Control Voltage, VC (V) 6 −2.0 −2.5 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS: VS = 5V continued RL = 500Ω and VIN = single-ended input on V+ with V− at ground, unless otherwise noted. HARMONIC DISTORTION vs R LOAD HARMONIC DISTORTION vs FREQUENCY −20 −30 Harmonic Distortion (dBc) G = 0dB, 3rd−Harmonic G = 0dB, 3rd−Harmonic Harmonic Distortion (dBc) VO = 1VPP RL = 500Ω −35 −40 −45 −50 G = +40dB, 3rd−Harmonic −55 G = +40dB, 2nd−Harmonic −60 −65 −70 G = 0dB, 2nd−Harmonic 1 −40 G = +40dB, 3rd−Harmonic −50 −60 G = +40dB, 2nd−Harmonic f = 1MHz VO = 1VPP RL = 500Ω −70 G = 0dB, 2nd−Harmonic −80 100 −75 0.1 −30 10 1000 Load (Ω) Frequency (MHz) HARMONIC DISTORTION vs OUTPUT VOLTAGE f = 1MHz RL = 500Ω Harmonic Distortion (dBc) −30 HARMONIC DISTORTION vs GAIN −20 G = 0dB, 3rd−Harmonic Harmonic Distortion (dBc) −20 −40 −50 G = +40dB, 2nd−Harmonic −60 −70 −80 G = +40dB, 3rd−Harmonic −90 −30 3rd−Harmonic −40 −50 −60 2nd−Harmonic −70 G = 0dB, 2nd−Harmonic −100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 −80 1 0 5 10 15 Output Voltage (VPP) Max Useful Output Voltage Range 0.1 Resulting Output Voltage Resulting Input Voltage Input and Output Measured at 1dB Compression 0.01 −40 −30 −20 −10 0 Gain (dB) 10 30 35 40 HARMONIC DISTORTION vs ATTENUATION Output Limited Max Useful Input Voltage Range 25 −20 Harmonic Distortion (dBc) Input/Output Voltage (VPP) Input Limited 20 Gain (dB) INPUT/OUTPUT RANGE vs GAIN 10 1 f = 1MHz VO = 1VPP RL = 500Ω 20 30 40 −30 f = 1MHz VIN = 1VPP RL = 500Ω 3rd−Harmonic −40 −50 −60 2nd−Harmonic −70 −80 −40 −35 −30 −25 −20 −15 −10 −5 0 Attenuation (dB) 7 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS: VS = 5V continued RL = 500Ω and VIN = single-ended input on V+ with V− at ground, unless otherwise noted. NOISE DENSITY vs CONTROL VOLTAGE INPUT VOLTAGE AND CURRENT NOISE 10000 10 RS = 20Ω on Each Input Input−Referred Voltage Noise Density en (nv√Hz) in (pA√Hz) en (nv√Hz) eO (nv√Hz) 1000 100 Differential Input Voltage Noise (2.4nV/√Hz) Output−Referred Voltage Noise Density 10 Current Noise (1.8pA/√Hz) Each Input 1 0 1 −0.2 −0.4 −0.6 −0.8 −1.0 −1.2 −1.4 −1.6 −1.8 −2.0 100 1k 10k Control Voltage (V) 100k 1M 10M Frequency (Hz) OUTPUT OFFSET VOLTAGE TOTAL ERROR BAND vs GAIN FULLY ATTENUATED ISOLATION vs FREQUENCY 50 0 40 Output Offset Error (mV) −20 Isolation (dB) VC = +0.1V −40 −60 VC = +0.2V −80 −100 30 Maximum Error Band 20 10 Typical Devices 0 −10 −20 −30 −40 −50 −40 −120 1M 10M 100M −30 −20 −10 0 10 20 30 40 Gain (dB) Frequency (Hz) OUTPUT OFFSET VOLTAGE DISTRIBUTION 250 TYPICAL GAIN ERROR PLOT 0.4 Total Tested = 1462 Deviation from −40dB/V Gain Slope 0.3 G = +40dB 200 0.1 Count 0 100 −0.1 −0.2 50 −0.3 −0.4 0 −0.5 0 −0.5 −1 Control Voltage (V) 8 150 −1.5 −2 <−50 <−45 <−40 <−35 <−30 <−25 <−20 <−15 <−10 <−5 <0 <5 <10 <15 <20 <25 <30 <35 <40 <45 <50 >50 Gain Error (dB) 0.2 Output Offset Voltage (mV) " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS: VS = 5V continued RL = 500Ω and VIN = single-ended input on V+ with V− at ground, unless otherwise noted. GROUP DELAY vs GAIN GROUP DELAY vs FREQUENCY 10 10 8 8 Group Delay (ns) Group Delay (ns) VO = 1VPP RL = 500Ω VO = 1VPP R L = 500Ω 9 1MHz 7 6 5MHz 5 G = 0dB 6 G = +40dB 4 2 10MHz 4 −40 −30 −20 0 −10 0 10 20 30 40 1 10 Gain (dB) OVERDRIVE RECOVERY AT MAXIMUM GAIN OVERDRIVE RECOVERY AT MAXIMUM ATTENUATION 2.5 15 VOUT 1.5 1.0 10x VIN 0.5 VOUT 10 Input/Output Voltage (mV) Input/Output Voltage (V) 2.0 0 −0.5 −1.0 −1.5 5 VIN 0 200 −5 −10 −15 −20 −2.0 −25 −2.5 Time (100ns/div) Time (100ns/div) COMMON−MODE REJECTION RATIO AND POWER−SUPPLY REJECTION RATIO vs FREQUENCY COMMON−MODE REJECTION RATIO AND POWER−SUPPLY REJECTION RATIO vs GAIN 100 110 Input−Referred 100 CMRR, PSRR (dB) 90 80 70 60 50 PSRR 40 30 80 70 60 50 30 20 10 10 0 −30 −20 −10 CMRR, G = 0dB 40 20 −40 CMRR, G = ±40dB 90 CMRR CMRR, PSRR (dB) 110 100 Frequency (MHz) PSRR, G = 0dB PSRR, G = +40dB 0 0 Gain (dB) 10 20 30 40 0.1 1 10 100 Frequency (MHz) 9 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS: VS = 5V continued RL = 500Ω and VIN = single-ended input on V+ with V− at ground, unless otherwise noted. GAIN CONTROL −PSRR AT MAX GAIN 6 5 5 4 4 Gain (dB) Gain (dB) GAIN CONTROL +PSRR AT MAX GAIN 6 3 3 2 2 1 1 0 0 1k 10k 100k 1M 10M 1k 100M 10k Frequency (Hz) 14 20 19 12 15 5 6 0 10 x Input Offset Current (I OS) −5 17 16 14 13 −10 0 −15 11 −20 10 −25 0 25 50 75 100 125 Quiescent Current for −VS 15 2 Temperature (_C) 10 10 8 −2 −50 100M 18 Supply Current (mA) Input Bias Current (I B) Output Offset Voltage (mV) Input Bias and Offset Current (µA) 20 4 10M TYPICAL SUPPLY CURRENT vs CONTROL VOLTAGE 25 Output Offset Voltage (VOS) 10 1M Frequency (Hz) TYPICAL DC DRIFT vs TEMPERATURE 16 100k 12 Quiescent Current for +VS 0 −0.5 −1.0 Control Voltage (V) −1.5 −2.0 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 APPLICATIONS INFORMATION CIRCUIT DESCRIPTION The VCA810 is a high gain adjust range, wideband, voltage amplifier with a voltage-controlled gain, as shown in Figure 1. The circuit’s basic voltage amplifier responds to the control of an internal gain-control amplifier. At its input, the voltage amplifier presents the high impedance of a differential stage, permitting flexible input impedance matching. To preserve termination options, no internal circuitry connects to the input bases of this differential stage. For this reason, the user must provide DC paths for the input base currents from a signal source, either through a grounded termination resistor or by a direct connection to ground. The differential input stage also permits rejection of common-mode signals. At its output, the voltage amplifier presents a low impedance, simplifying impedance matching. An open-loop design produces wide bandwidth at all gain settings. A ground-referenced differential to single-ended conversion at the output retains the low output offset voltage. +5V V+ V− VCA810 1 8 0V to −2V. Optionally, making VC slightly positive (≥ +0.15V) effectively disables the amplifier, giving > 80dB of signal path attenuation at low frequencies. Internally, the gain-control circuit varies the amplifier gain by varying the transconductance, gm, of a bipolar transistor using the transistor bias current. Varying the bias currents of differential stages varies gm to control the voltage gain of the VCA810. A gm-based gain adjust normally suffers poor thermal stability. The VCA810 includes circuitry to minimize this effect. VCA810 OPERATION Figure 2 shows the circuit configuration used as the basis of the Electrical Characteristics and Typical Characteristics. Voltage swings reported in the specifications are taken directly at the input and output pins. For test purposes, the input impedance is set to 50Ω with a resistance to ground. A 25Ω resistance (RT) is included on the V− input to get bias current cancellation. Proper supply bypassing is shown in Figure 2, and consists of two capacitors on each supply pin: one large electrolytic capacitor (2.2µF to 6.8µF), effective at lower frequencies, and one small ceramic capacitor (0.1µF) for high frequency decoupling. For more information on decoupling, refer to the Board Layout section. Gain Adjust + V OUT X1 +5V −5V 2 VC 3 0 → −2V 0.1µF 0.1µF 6.8µF + 6.8µF + −40dB → +40dB Gain −5V 8 VI Figure 1. Block Diagram of the VCA810 A gain control voltage, VC, controls the amplifier gain magnitude through a high-speed control circuit. Gain polarity can be either inverting or non-inverting, depending upon the amplifier input driven by the input signal. The gain control circuit presents the high-input impedance of a non-inverting op amp connection. The control voltage pin is referred to ground as shown in Figure 1. The control voltage VC varies the amplifier gain according to the exponential relationship G ǒVńVǓ + 10 This translates to *2(V )1) C 50Ω Source RS 50Ω 1 RT 25Ω 6 7 2 VCA810 5 3 VO RL 500Ω RC VC Figure 2. Variable Gain, Specification and Test Circuit . the log gain relationship ǒ Ǔ G (dB) + *40 @ V C)1 dB. Thus, G(dB) varies linearly over the specified −40dB to +40dB range as VC varies from Notice that both inverting and non-inverting inputs are connected to ground with a resistor (RS and RT). Matching the DC source impedance looking out of each input will minimize input offset voltage error. 11 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 RANGE FINDING TGC AMPLIFIER The block diagram in Figure 3 illustrates the fundamental configuration common to pulse-echo range finding systems. A photodiode preamp provides an initial gain stage to the photodiode. Between gain corrections, resistor R1 charges the capacitor in a negative direction, increasing the amplifier gain. R1, R2, and CH determine the release time of this action. Resistor R2 forms a voltage divider with R1, limiting the maximum negative voltage developed on CH. This limit prevents input overload of the VCA810 gain control circuit. Figure 5 shows the AGC response for the values shown in Figure 4. 20Ω OPA657 VCA810 ADC and DSP 20kΩ CF 20Ω VC VC 0 VIN t −VB RSSI Port 2mV to 2V 100kHz VO VCA810 VC −2V R3 1kΩ HP5082 OPA820 Time−Gain Compensated Control Voltage R1 50kΩ Figure 3. Typical Range Finding Application VOUT PEAK = VR R2 50kΩ R4 100Ω VR CH 0.1µF CC 47pF 0.1 VDC V− The control voltage VC varies the amplifier gain for a basic signal-processing requirement: compensation for distance attenuation effects, sometimes called Time-Gain Compensation (TGC). Time-gain compensation increases the amplifier gain as the signal moves through the air to compensate for signal attenuation. For this purpose, a ramp signal applied to the VCA810 gain control input linearly increases the dB gain of the VCA810 with time. Figure 4. 60dB Input Range AGC WIDE-RANGE AGC AMPLIFIER The voltage-controlled gain feature of the VCA810 makes this amplifier ideal for precision AGC applications with control ranges as large as 60dB. The AGC circuit of Figure 4 adds an op amp and diode for amplitude detection, a hold capacitor to store the control voltage and resistors R1 through R3 that determine attack and release times. Resistor R4 and capacitor CC phase compensate the AGC feedback loop. The op amp compares the positive peaks of output VO with a DC reference voltage, VR. Whenever a VO peak exceeds VR, the OPA820 output swings positive, forward-biasing the diode and charging the holding capacitor. This charge drives the capacitor voltage in a positive direction, reducing the amplifier gain. R3 and the CH largely determine the attack time of this AGC correction. 12 Output Voltage (50mV/div) 0.15 0.10 0.05 VIN = 1VPP VIN = 100mVPP 0 −0.05 −0.10 VIN = 10mVPP −0.15 −0.20 Time (5µs/div) Figure 5. AGC Output Voltage for 100kHz Sinewave at 10mVPP, 100mVPP and 1VPP " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 STABILIZED WEIN-BRIDGE OSCILLATOR Adding Wein-bridge feedback to the above AGC amplifier produces an amplitude-stabilized oscillator. As Figure 6 shows, this alternative requires the addition of just two resistors (RW1, RW2) and two capacitors (CW1, CW2). Connecting the feedback network to the amplifier non-inverting input introduces positive feedback to induce oscillation. The feedback factor displays a frequency dependence due to the changing impedances of the CW capacitors. As frequency increases, the decreasing impedance of the CW2 capacitor increases the feedback factor. Simultaneously, the decreasing impedance of the CW1 decreases this factor. Analysis shows that the maximum factor occurs at f W + 1 Hz, making 2p @ R W @ C W CW2 4700pF RW2 300Ω CW1 4700pF this the frequency most conducive to oscillation. At this frequency, the impedance magnitude of CW equals RW, and inspection of the circuit shows that this condition produces a feedback factor of 1/3. Thus, self-sustaining oscillation requires a gain of three through the amplifier. The AGC circuitry establishes this gain level. Following initial circuit turn-on, R1 begins charging CH negative, increasing the amplifier gain from its minimum. When this gain reaches three, oscillation begins at fW; the continued charging effect of R1 makes the oscillation amplitude grow. This growth continues until that amplitude reaches a peak value equal to VR. Then, the AGC circuit counteracts the R1 effect, controlling the peak amplitude at VR by holding the amplifier gain at a level of three. Making VR an AC signal, rather than a DC reference, produces amplitude modulation of the oscillator output. f = 1/2πRW1CW1 RW1 = RW2 CW1 = CW2 RW1 300Ω VO VCA810 VC VOPEAK = VR R3 1kΩ HP5082 OPA820 R1 50kΩ R2 50kΩ CH 1µF R4 100Ω VR 0.1 VDC CC 10pF V− Figure 6. Amplitude-Stabilized Oscillator 13 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 LOW DRIFT WIDEBAND LOG AMP Combining the last two expressions and solving for VOL yields the circuit’s logarithmic response: The VCA810 can be used to provide a 2.5MHz (–3dB) log amp with low offset voltage and low gain drift. The exponential gain-control characteristic of the VCA810 permits simple generation of a temperature-compensated logarithmic response. Enclosing the exponential function in an op-amp feedback path inverts this function, producing the log response. Figure 7 shows the practical implementation of this technique. A DC reference voltage, VR, sets the VCA810 inverting input voltage. This configuration makes the amplifier output voltage VOA = −GVR, where G + 10 VR −10mV *2(V )1) C . VOA = −GVR VCA810 VC ( VOL = − 1 + R1 470Ω R2 330Ω VOL OPA820 R1 R2 ) 1 + 0.5 Log(−V IN /VR) R3 100Ω VIN CC 50pF Figure 7. Temperature Compensated Log Response A second input voltage also influences VOA through control of gain G. The feedback op amp forces VOA to equal the input voltage VIN connected at the op amp inverting input. Any difference between these two signals drops across R3, producing a feedback current that charges CC. The resulting change in VOL adjusts the gain of the VCA810 to change VOA. At equilibrium: V OA + VIN + *V R @ 10 *2(V )1) C (1) The op amp forces this equality by supplying the gain control voltage, V C + 14 R1 @ VOL . R 1)R 2 ǒ V OL + * 1) Ǔ ƪ ǒ Ǔƫ R2 V @ 1)0.5 @ log * IN R1 VR (2) An examination of this result illustrates several circuit characteristics. First, the argument of the log term, −VIN/VR, reveals an option and a constraint. In Figure 7, VR represents a DC reference voltage. Optionally, making this voltage a second signal produces log-ratio operation. Either way, the log term’s argument constrains the polarities of VR and VIN. These two voltages must be of opposite polarities to ensure a positive argument. This polarity combination results when VR connects to the inverting input of the VCA810. Alternately, switching VR to the amplifier non-inverting input removes the minus sign of the log term argument. Then, both voltages must be of the same polarity in order to produce a positive argument. In either case, the positive polarity requirement of the argument restricts VIN to a unipolar range. Figure 8 illustrates these constraints. The above VOL expression reflects a circuit gain introduced by the presence of R1 and R2. This feature adds a convenient scaling control to the circuit. However, a practical matter sets a minimum level for this gain. The voltage divider formed by R1 and R2 attenuates the voltage supplied to the VC terminal by the op amp. This attenuation must be great enough to prevent any possibility of an overload voltage at the VC terminal. Such an overload saturates the VCA810 gain-control circuitry, reducing the amplifier’s gain. For the feedback connection of Figure 7, this overload condition permits a circuit latch. To prevent this, choose R1 and R2 to ensure that the op amp cannot possibly deliver a more negative input than −2.5V to the VC terminal. Figure 8 exhibits three zones of operation described below: Zone I: VC > 0V. The VCA810 is operating in full attenuation (−80dB). The non-inverting input of the OPA820 will see ∼0V. VOL is going to be the integration of the input signal. Zone II: −2V < VC < 0V. The VCA810 is in its normal operating mode, creating the log relationship in Equation (2). Zone III: VC < −2V. The VCA810 control pin is out of range, and some measure should be taken so that it does not exceed –2.5V. A limiting action could be achieved by using a voltage limiting amplifier. " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 1 5 Output Voltage (V) 4 Output Voltage (V) 3 2 1 II 0 I −1 −2 0.1 0.01 III −3 0.001 +3.0 −4 −5 0.001 0.01 0.1 1 10 +2.5 +2.0 +1.5 +1.0 +0.5 0 Input Voltage (V) 100 VIN/VR Voltage Ratio Figure 10. Exponential Amplifier Response Figure 8. Test Result for LOG Amp for VR = −100mV LOW DRIFT, WIDEBAND EXPONENTIAL AMP A common use of the log amp above involves signal companding. The inverse function, signal expanding, requires an exponential transfer function. The VCA810 produces this latter response directly, as shown in Figure 9. DC reference VR again sets the amplifier input voltage, and the input signal VIN now drives the gain control point. Resistors R1 and R2 attenuate this drive to prevent overloading the gain control input. Setting these resistors at the same values as in the preceding log amp produces an exponential amplifier with the inverse function of the log amp. Testing the circuit given in Figure 9 gives the exponential response shown in Figure 10. VOLTAGE-CONTROLLED LOW-PASS FILTER In the circuit of Figure 11, the VCA810 serves as the variable-gain element of a voltage-controlled low-pass filter. This section discusses how this implementation expands the circuit voltage swing capability over that normally achieved with the equivalent multiplier implementation. The circuit response pole responds to control voltage VC according to the relationship in Equation (3): fP + G 2p @ R 2C where G + 10 (3) *2(V )1) C . With the components shown, the circuit provides a linear variation of the low-pass cutoff from 300Hz to 1MHz. VR −10mV VCA810 +0.5V VI R2 330Ω VOL = −VR x 10 VC OPA698 VL R1 470Ω −3.4V 500Ω −2 ( R1 VIN ) +1 R1 + R2 The response control results from amplification of the feedback voltage applied to R2. First consider the case where the VCA810 produces G = 1. Then, the circuit performs as if this amplifier were replaced by a short circuit. Visually doing so leaves a simple voltage amplifier with a feedback resistor bypassed by a capacitor. This basic circuit produces a response pole at f P + G . 2p @ R 2C 500Ω VIN Figure 9. Exponential Amplifier 15 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 For G > 1, the circuit applies a greater voltage to R2, increasing the feedback current this resistor supplies to the summing junction of the OPA820. The increased feedback current produces the same result as if R2 had been decreased in value in the basic circuit described above. Decreasing the effective R2 resistance moves the circuit pole to a higher frequency, producing the 3 G response control. 2p @ R 2C 0 Finite loop gain and a signal-swing limitation set performance boundaries for the circuit. Both limitations occur when the VCA810 attenuates, rather than amplifies, the feedback signal. These two limitations reduce the circuit’s utility at the lower extreme of the VCA810 gain range. For −1 ≤ VC ≤ 0, this amplifier produces attenuating gains in the range from 0dB to −40dB. This range directly reduces the net gain in the circuit’s feedback loop, increasing gain error effects. Additionally, this attenuation transfers an output swing limitation from the OPA820 output to the overall circuit’s output. Note that OPA820 output voltage, VOA, relates to VO through the expression, V O + G @ V OA . Thus, a G < 1 limits the maximum VO swing to a value less than the maximum VOA swing. VC = −2V −3 Gain (dB) fP + Figure 12 shows the low-pass frequency for different control voltages. VC = −1.4V −6 VC = −1.6V VC = −1.8V −9 −12 −15 10k 100k 1M 10M Frequency (Hz) Figure 12. Voltage-Controlled Low-Pass Filter Frequency Response TUNABLE EQUALIZER A circuit analogous to the above low-pass filter produces a voltage-controlled equalizer response. The gain control provided by the VCA810 of Figure 13 varies this circuit response zero from 1Hz to 10kHz, according to the relationship of Equation (4): R2 330Ω R1 330Ω C 0.047µF VI fZ [ OPA820 VOA VCA810 VC VO R + * 2@ VI R1 fP + 1 1)s R 2C 2 G G 2pR2C G + 10 *2(V )1) C Figure 11. Tunable Low-Pass Filter 16 G 2p @ GR 1C VO where G + 10 *2(V )1) C (4) . To visualize the circuit’s operation, consider a circuit condition and an approximation that permit replacing the VCA810 and R3 with short circuits. First, consider the case where the VCA810 produces G = 1. Replacing this amplifier with a short circuit leaves the operation unchanged. In this shorted state, the circuit is simply a voltage amplifier with an R-C bypass around R1. The resistance of this bypass, R3, serves only to phasecompensate the circuit, and practical factors make R3 << R1. Neglecting R3 for the moment, the circuit becomes just a voltage amplifier with a capacitive bypass of R1. This circuit produces a response zero at f Z + 1 . 2p @ R 1C " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 Adding the VCA810 as shown in Figure 13 permits amplification of the signal applied to capacitor C, and produces voltage control of the frequency fZ. Amplified signal voltage on C increases the signal current conducted by the capacitor to the op amp feedback network. The result is the same as if C had been increased in value to GC. Replacing C with this effective capacitance value With the components shown, BW = 50kHz. This bandwidth provides an integrator response duration of four decades of frequency for fZ = 1Hz, dropping to one decade for fZ = 10kHz. 1 . 2p @ R 1GC Another factor limits the high-frequency performance of the resulting high-pass filter: the finite bandwidth of the op amp. This limits the frequency duration of the equalizer response. Limitations such as bandwidth and stability are clearly shown in Figure 14. 100 AOL 90 G = +40dB 80 70 Gain (dB) produces the circuit control expression f Z + G = +15dB 60 50 40 G = −15dB 30 20 G = −40dB 10 0 1 100 1k 10k 100k 1M 10M 100M Frequency (Hz) R2 750Ω R1 750Ω VI 10 OPA820 50Ω VCA810 VOA C 2µF R3 3Ω VO Figure 14. Amplifier Noise Gain and AOL for Different Gain OPA846 50Ω VC 1 −2(V + 1) with G = 10 C FZ ≈ 2π x GR + R C) ( 1 3 VOLTAGE-CONTROLLED BAND-PASS FILTER The variable gain of the VCA810 also provides voltage control over the center frequency of a band-pass filter. As shown in Figure 15, this filter follows from the state-variable configuration with the VCA810 replacing the inverter common to that configuration. Variation of the VCA810 gain moves the filter’s center frequency through a 100:1 range following the relationship of Equation (5): Figure 13. Tunable Equalizer fO + Other limitations of this circuit are stability versus VCA810 gain and input signal level for the circuit. Figure 14 also illustrates these two factors. As the VCA810 gain increases, the crossover slope between the AOL curve of the OPA846 and noise gain will be greater than 20dB/decade, rendering the circuit unstable. The signal level for high gain of the VCA810 will meet two limitations: the output voltage swings of both the VCA810 and the OPA846. The expression VOA = GVI relates these two voltages. Thus, an output voltage limit VOAL constrains the input voltage to VI ≤ VOAL/G. *ǒV )1Ǔ 10 C 2p @ RC (5) As before, variable gain controls a circuit time constant to vary the filter response. The gain of the VCA810 amplifies or attenuates the signal driving the lower integrator of the circuit. This amplification alters the effective resistance of the integrator time constant, producing the response of Equation (6): * nRC VO + VI s2 ) s ) G s nRC R 2C 2 (6) 17 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 Evaluation of this response equation reveals a passband gain of AO = –1, a bandwidth of BW = 1/2nRC, and a ǒ * V )1 Ǔ selectivity of Q + n @ 10 C . Note that variation of control voltage VC alters Q but not bandwidth. The gain provided by the VCA810 restricts the output swing of the filter. Output signal VO must be constrained to a level that does not drive the VCA810 output, VOA, into its saturation limit. Note that these two outputs have voltage swings related by VOA = GVO. Thus, a swing limit VOAL imposes a circuit output limit of VOL ≤ VOAL/G. Figure 16 shows the frequency response for two different gain conditions of the schematic shown in Figure 15. In particular, notice the center frequency shift and the selectivity of Q changing as the gain is increased. C 0.047µF * nRC VO + VI s2 ) s ) G s nR 5kΩ nR 5kΩ nRC VI R 330Ω fO + 1/2 OPA2822 VO C 0.047µF BW + 50Ω R 330Ω VOA *(V )1) 10 C 2pRC 1 2pRC Q + n @ 10 VCA810 1/2 OPA2822 50Ω A O + −1 VC Figure 15. Tunable Band-Pass Filter 0 −5 −10 Gain (dB) −15 −20 −25 −30 −35 −40 −45 −50 100 1k 10k 100k Frequency (Hz) Figure 16. Tunable Band-Pass Filter Response 18 *(V )1) C R 2C 2 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 DESIGN-IN TOOLS DEMONSTRATION BOARDS A PC board is available to assist in the initial evaluation of circuit performance using the VCA810. This evaluation board (EVM) is available free, as an unpopulated PC board delivered with descriptive documentation. The summary information for this board is shown in Table 1 below: PRODUCT PACKAGE BOARD PART NUMBER VCA810ID SO−8 DEM-VCA81xD LITERATURE REQUEST NUMBER SBOU025 Table 1. EVM Ordering Information Go to the TI web site (www.ti.com ) to request evaluation boards through the VCA810 product folder. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can play a major role in circuit performance. A SPICE model for the VCA810 is available through the TI web page. The applications group is also available for design assistance. The models available from TI predict typical small signal AC performance, transient steps, DC performance, and noise under a wide variety of operating conditions. The models include the noise terms found in the electrical specifications of the relevant product data sheet. OPERATING SUGGESTIONS INPUT/OUTPUT RANGE The VCA810’s 80dB gain range allows the user to handle an exceptionally wide range of input signal levels. If the input and output voltage range specifications are exceeded, however, signal distortion and amplifier overdrive will occur. The VCA810 maximum input and output voltage range is best illustrated in the Typical Characteristics plot, Input/Output Range vs Gain. This chart plots input and output voltages versus gain in dB. The maximum input voltage range is the largest at full attenuation (−40dB) and decrease as the gain increases. Similarly, the maximum useful output voltage range increases as the input decreases. We can distinguish three overloading issues as a result of the operating mode: high attenuation, mid-range gain-attenuation, and high gain. From –40dB to –10dB, gain overdriving the input stage is the only method to overdrive the VCA810. Preventing this type of overdrive is achieved by limiting the input voltage range. From –10dB to +40dB, overdriving can be prevented by limiting the output voltage range. There are two limiting mechanisms operating in this situation. From –10dB to +10dB, an internal stage is the limiting factor; from +10dB to +40dB, the output stage is the limiting factor. Output overdriving occurs when either the maximum output voltage swing or output current is exceeded. The VCA810 high output current of ±60mA insures that virtually all output overdrives will be limited by voltage swing rather than by current limiting. Table 2 summarizes these overdrive conditions. GAIN RANGE LIMITING MECHANISM TO PREVENT, OPERATE DEVICE WITHIN: −40dB < G < −10dB Input Stage Overdrive Input Voltage Range −10dB < G < +10dB Internal Stage Overdrive Output Voltage Range +5dB < G < +40dB Output Stage Overdrive Output Voltage Range Table 2. Output Signal Compression OVERDRIVE RECOVERY As shown in the Typical Characteristics plot, Input/Output Range vs Gain, the onset of overdrive occurs whenever the actual output begins to deviate from the ideal expected output. If possible, the user should operate the VCA810 within the linear regions shown in order to minimize signal distortion and overdrive delay time. However, instances of amplifier overdrive are quite common in Automatic Gain Control (AGC) circuits, which involve the application of variable gain to input signals of varying levels. The VCA810 design incorporates circuitry that allows it to recover from most overdrive conditions in 200ns or less. Overdrive recovery time is defined as the time required for the output to return from overdrive to linear operation, following the removal of either an input or gain-control overdrive signal. The overdrive plots for maximum gain and maximum attenuation are shown in the Typical Characteristics plots. 19 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 OUTPUT OFFSET ERROR Several elements contribute to the output offset voltage error; among them are the input offset voltage, the output offset voltage, the input bias current and the input offset current. To simplify the following analysis, the output offset voltage error is dependent only on the output-offset voltage of the VCA810 and the input offset voltage. The output offset error can then be expressed as Equation (7): ǒ Ǔ@V G V OS + VOSO)10 dB 20 (7) IOS amplification of the offset effects produces the greatest output offset. Two features minimize the offset control circuit noise contribution to the amplifier input circuit. First, making the resistance of R2 a low value minimizes the noise directly introduced by the control circuit. This approach reduces both the thermal noise of the resistor and the noise produced by the resistor with the amplifier input noise current. A second noise reduction results from capacitive bypass of the potentiometer output. This reduction filters out power-supply noise that would otherwise couple to the amplifier input. This filtering action diminishes as the wiper position approaches either end of the potentiometer, but practical conditions prevent such settings. Over its full adjustment range, the offset control circuit produces a ±5mV input offset correction for the values shown. However, the VCA810 only requires one tenth of this range for offset correction, assuring that the potentiometer wiper will always be near the potentiometer center. With this setting, the resistance seen at the wiper remains high, which stabilizes the filtering function. with: D VOS: Output Offset Error D VOSO: Output Offset Voltage D GdB: VCA810 Gain in dB D VIOS: Input Offset Voltage This is shown in Figure 17. 50 Output Offset Error (mV) 40 30 Maximum Error Band V+ 20 10 Typical Devices R1 VIN 10kΩ RV 100kΩ 0 −10 −20 V− −30 1µF VCA810 R2 10Ω VO VC −40 −50 −40 −30 −20 −10 0 10 20 30 40 Gain (dB) Figure 17. Output Offset Error vs. Gain The histogram Output Offset Voltage at Maximum Gain in the Typical Characteristics curves shows the distribution for the output offset voltage at maximum gain. OFFSET ADJUSTMENT Where desired, the offset of the VCA810 can be removed as shown in Figure 18. This circuit simply presents a DC voltage to one of the amplifier inputs to counteract the offset error voltage. For best offset performance, the trim adjustment should be made with the amplifier set at the maximum gain of the intended application. The offset voltage of the VCA810 varies with gain as shown in Figure 17, limiting the complete offset cancellation to one selected gain. Selecting the maximum gain optimizes offset performance for higher gains where high 20 Figure 18. Optional Offset Adjustment GAIN CONTROL The VCA810 gain is controlled by means of a unipolar negative voltage applied between ground and the gain control input, pin 3. If use of the output disable feature is required, a ground-referenced bipolar voltage is needed. Output disable occurs for +0.15V ≤ VC ≤ +2V, and produces > 80dB of attenuation. The control voltage should be limited to +2V in disable mode, and –2.5V in gain mode in order to prevent saturation of internal circuitry. The VCA810 gain-control input has a –3dB bandwidth of 25MHz and varies with frequency, as shown in the Typical Characteristic curves. This wide bandwidth, although useful for many applications, can allow high-frequency noise to modulate the gain control input. In practice, this can be easily avoided by filtering the control input, as " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 shown in Figure 19. RP should be no greater than 100Ω so as not to introduce gain errors by interacting with the gain control input bias current of 6µA. E O + G ǒVńVǓ @ VO VCA610 The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation (8) shows the general form for the output noise voltage using the terms shown in Figure 20. ǸE 2 ǒ NI) IBI @ R TǓ )ǒIBN @ R SǓ )4kTǒR S)R TǓ 2 2 (8) CP f *3dB + RP Dividing this expression by the gain will give the equivalent input-referred spot-noise voltage at the non-inverting input as shown by Equation (9). 1 2pRPC P EN + VC Figure 19. Control Line Filtering GAIN CONTROL AND TEEPLE POINT When the VCA810 controlled voltage reaches −1.5V, also referred to as the Teeple point, the signal path undergoes major changes. From 0V to the Teeple point, the gain is controlled by one bank of amplifiers: a low-gain VCA. As the Teeple point is passed, the signal path is switched to a higher gain VCA. This gain-stage switching can be seen most clearly in the Noise Density vs Control Voltage Typical Characteristics curve. The output-referred voltage noise density increases proportionally to the control voltage and reaches a maximum value at the Teeple point. As the gain increases and the internal stages switch, the output-referred voltage noise density drops suddenly and restarts its proportional increase with the gain. NOISE PERFORMANCE The VCA810 offers 2.4nV/√Hz input-referred voltage noise and 1.8 pA/√Hz input-referred current noise at a gain of +40dB. The input-referred voltage noise, and the input-referred current noise terms, combine to give low output noise under a wide variety of operating conditions. Figure 20 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. +5V IBN * RS ERS 4kTRS * IBI − ENI VCA810 EO VC RT * −5V 4kTRT ǸE 2 ǒ NI) I BI @ RTǓ )ǒI BN @ RSǓ )4kTǒRS)R TǓ 2 2 (9) Evaluating these two equations for the VCA810 circuit and component values shown in Figure 2 (maximizing gain) will give a total output spot-noise voltage of 272.3nV√Hz and a total equivalent input-referred spot-noise voltage of 2.72nV√Hz. This total input-referred spot-noise voltage is higher than the 2.4nV√Hz specification for the VCA810 alone. This reflects the noise added to the output by the input current noise times the input resistance RS and RT. Keeping input impedance low is required to maintain low total equivalent input-referred spot-noise voltage. THERMAL ANALYSIS The VCA810 will not require heatsinking or airflow in most applications. Maximum desired junction temperature would set the maximum allowed internal power dissipation as described in this section. In no case should the maximum junction temperature be allowed to exceed +150_C. Operating junction temperature (TJ ) is given by T J + T A)P D @ q JA . The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load; for a grounded resistive load, however, it is at a maximum when the output is fixed at a voltage equal to one-half of either supply voltage (for equal bipolar supplies). Under this worst-case condition, PDL = VS2/(4 • RL), where RL is the resistive load. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an VCA810ID (SO-8 package) in the circuit of Figure 2 operating at maximum gain and at the maximum specified ambient temperature of +85°C. PD = 10V(24.8mA) + 52/(4 • 500Ω) = 260.5mW Figure 20. VCA810 Noise Analysis Model Maximum TJ = +85°C + (0.260W • 125_C/W) = 117.6°C 21 " #$% www.ti.com SBOS275C − JUNE 2003 − REVISED OCTOBER 2004 This maximum operating junction temperature is well below most system level targets. Most applications will be lower since an absolute worst-case output stage power was assumed in this calculation of VCC/2 which is beyond the output voltage range for the VCA810. BOARD LAYOUT Achieving optimum performance with a high-frequency amplifier such as the VCA810 requires careful attention to board layout parasitic and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. This includes the ground pin (pin 2). Parasitic capacitance on the output can cause instability: on both the inverting input and the non-inverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. Place a small series resistance (> 25Ω) with the input pin connected to ground to help decouple package parasitic. b) Minimize the distance (< 0.25”) from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These capacitors may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high-frequency performance of the VCA810. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep the leads and PC board trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Since the output pin is the most sensitive to parasitic capacitance, always position the series output resistor, if any, as close as possible to the output pin. Other network 22 components, such as inverting or non-inverting input termination resistors, should also be placed close to the package. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. e) Socketing a high-speed part like the VCA810 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the VCA810 onto the board. INPUT AND ESD PROTECTION The VCA810 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All pins on the VCA810 are internally protected from ESD by means of a pair of back-to-back reverse-biased diodes to either power supply, as shown in Figure 21. These diodes will begin to conduct when the pin voltage exceeds either power supply by about 0.7V. This situation can occur with loss of the amplifier power supplies while a signal source is still present. The diodes can typically withstand a continuous current of 30mA without destruction. To insure long-term reliability, however, diode current should be externally limited to 10mA whenever possible. +VS External Pin ESD Protection diodes internally connected to all pins. Internal Circuitry −VS Figure 21. Internal ESD Protection PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY VCA810AID ACTIVE SOIC D 8 100 VCA810AIDR ACTIVE SOIC D 8 2500 VCA810ID ACTIVE SOIC D 8 100 VCA810IDR ACTIVE SOIC D 8 2500 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. 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