Sony CXP84332 Cmos 8-bit single chip microcomputer Datasheet

CXP84332/84340
CMOS 8-bit Single Chip Microcomputer
Description
CXP84332/84340 is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer/counter, remote control reception
circuit, and the like besides the basic configurations of
8-bit CPU, ROM, RAM, and I/O port.
The CXP84332/84340 also provides a power-on
reset function and a sleep/stop function that enables
lower power consumption.
80 pin QFP (Plastic)
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
400ns at 10MHz operation
122µs at 32kHz operation
• Incorporated ROM capacity
32K bytes (CXP84332)
40K bytes (CXP84340)
• Incorporated RAM capacity
1120 bytes
• Peripheral functions
— A/D converter
8 bits, 8 channels, successive approximation method
(Conversion time of 32µs/10MHz)
— Serial interface
Incorporated 8-bit, 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock synchronization, 1 channel
— Timers
8-bit timer
8-bit timer/counter
19-bit time base timer
16-bit capture timer/counter
32kHz timer/counter
— Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO
— PWM output
14 bits, 1 channel
• Interruption
15 factors, 15 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
80-pin plastic QFP
• Piggyback/evaluation chip
CXP84300 80-pin ceramic QFP
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93841A7X-PS
–2–
PE5/TO
PB0/CINT
PE1/EC1
16 BIT CAPTURE
TIMER/COUNTER2
8 BIT TIMER 1
8 BIT TIMER/COUNTER 0
FIFO
FIFO
PE0/EC0
SERIAL
INTERFACE
UNIT 0
REMOCON
14 BIT PWM GENERATOR
A/D CONVERTER
AVss
SERIAL INTERFACE UNIT 1
8
AVREF
PB6/SI1
PB7/SO1
PB5/SCK1
PB1/CS0
PB3/SI0
PB4/SO0
PB2/SCK0
PE2/RMC
PE4/PWM
AN0 to AN7
2
2
PI0/INT0
PI1/INT1
PI2/INT2
PI3/INT3
2 2
INTERRUPT CONTROLLER
Block Diagram
PRESCALER/
TIME BASE TIMER
ROM
32K/40K BYTES
SPC700
CPU CORE
VDD
Vss
TEX
TX
EXTAL
XTAL
RST
32kHz
TIMER/COUNTER
RAM
1120 BYTES
CLOCK GEN./
SYSTEM CONTROL
8
8
8
PI0 to PI7
PH0 to PH7
PG0 to PG7
PF0 to PF7
PE4 to PE5
2
8
PE0 to PE3
PD0 to PD7
PC0 to PC7
PB7
PB0 to PB6
PA0 to PA7
4
8
8
7
8
CXP84332/84340
PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A
PE3/NMI
CXP84332/84340
PI5
PI6
PI7
PG0
PG1
PG2
PG3
VDD
NC
PG4
PG5
PG6
PG7
PF0
PF1
PF2
Pin Assignment (Top View)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
64
PI4
PF4
2
63
PI3/INT3
PF5
3
62
PI2/INT2
PF6
4
61
PI1/INT1
PF7
5
60
PI0/INT0
PD0
6
59
PE5TO
PD1
7
58
PE4/PWM
PD2
8
57
PE3/NMI
PD3
9
56
PE2/RMC
PD4
10
55
PE1/EC1
PD5
11
54
PE0/EC0
PD6
12
53
PB7/SO1
PD7
13
52
PB6/SI1
PC0
14
51
PB5/SCK1
PC1
15
50
PB4/SO0
PC2
16
49
PB3/SI0
PC3
17
48
PB2/SCK0
PC4
18
47
PB1/CS0
PC5
19
46
PB0/CINT
PC6
20
45
PA7/AN7
PC7
21
44
PA6/AN6
PH0
22
43
PA5/AN5
PH1
23
42
PA4/AN4
PH2
24
41
PA3/AN3
Note) NC (Pin 73) must be connected to VDD.
–3–
PA2/AN2
PA1/AN1
PA0/AN0
AVSS
AVREF
TEX
TX
VSS
XTAL
EXTAL
RST
PH7
PH6
PH5
PH4
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PH3
PF3
CXP84332/84340
Pin Description
Symbol
I/O
PA0/AN0
to
PA7/AN7
I/O/Analog input
PB0/CINT
I/O/Input
PB1/CS0
I/O/Input
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
PB7/SO1
Output/Output
Description
(Port A)
8-bit I/O port. I/O can be
set in a unit of single bits.
Incorporation of the
pull-up resistance can be
set through the software
in a unit of 4 bits.
(8 pins)
(Port B)
Lower 7-bit I/O port in
which I/O can be set in a
unit of single bits. Also,
an uppermost bit (PB7)
exclusively for output.
Incorporation of pull-up
resistor can be set
through the software in a
unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
External capture input to 16-bit timer/counter.
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
I/O
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving
12mA sink current. Incorporation of pull-up resistor can be set through
the software in a unit of 4 bits.
(8 pins)
PD0 to PD7
I/O
(Port D)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(8 pins)
PE0/EC0
Input/Input
PC0 to PC7
PE1/EC1
Input/Input
PE2/RMC
Input/Input
PE3/NMI
Input/Input
PE4/PWM
Output/Output
PE5/TO/ADJ
Output/Output/
Output
PF0 to PF7
I/O
(Port E)
6-bit port. Lower 4 bits
are for inputs; upper
2 bits are for outputs.
Incorporation of pull-up
resistor can be set
through the software.
(8 pins)
External event inputs for timer/counter.
(2 pins)
Remote control reception circuit input.
Non-maskable interruption request input.
14-bit PWM output.
Rectangular wave output for 16-bit
timer/counter . Output for 32kHz oscillation
frequency demultiplication.
(Port F)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of
pull-up resistor can be set through the software in a unit of 4 bits.
(8 pins)
–4–
CXP84332/84340
Symbol
I/O
Description
I/O
(Port G)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(8 pins)
PH0 to PH7
I/O
(Port H)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(8 pins)
PI0/INT0
to
PI3/INT3
I/O/Input
PI4 to PI7
I/O
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Crystal connectors for 32kHz timer/counter clock oscillation circuit.
Connect a 32kHz crystal oscillator between TEX and TX.
For usage as event input, connect clock oscillation source to TEX, and
open TX.
RST
Input
Low-level active, system reset.
PG0 to PG7
NC
AVREF
(Port I)
8-bit I/O ports. I/O can be set in a unit of single
bits. Incorporation of pull-up resistor can be set
through the software in a unit of 4 bits.
(8 pins)
External interruption
request inputs.
Crystal connectors for system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to XTAL.
NC. Under normal operating conditions, connect to VDD.
Input
Reference voltage input for A/D converter.
AVss
A/D converter GND.
VDD
Positive power supply.
Vss
GND
–5–
CXP84332/84340
Input/Output Circuit Formats for Pins
Pin
Port A
AAA
AAA
AAA
AAA
AAA
AAA
AAA
When reset
Circuit format
∗
Pull-up resistance
"0" when reset
AA
AA
AA
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
IP
"0" when reset
Data bus
Input protection
circuit
Hi-Z
RD (Port A)
Port A input
selection
"0" when reset
8 pins
Port B
Input multiplexer
A/D converter
AAAA
AAAA
AAAA
AAAA
AAAA
∗ Pull-up transistors
approx. 10kΩ
∗
Pull-up resistance
"0" when reset
AA
AA
AA
Port B data
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
IP
"0" when reset
Hi-Z
Schmitt input
Data bus
RD (Port B)
4 pins
Port B
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
CINT
CS0
SI0
SI1
∗ Pull-up transistors
approx. 10kΩ
∗
Pull-up resistance
"0" when reset
SCK OUT
Output enable
Port B output
selection
PB2/SCK0
PB5/SCK1
AA
AA
AA
"0" when reset
IP
Port B data
Port B direction
"0" when reset
Schmitt input
Data bus
RD (Port B)
2 pins
SCK in
–6–
∗ Pull-up transistors
approx. 10kΩ
Hi-Z
CXP84332/84340
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Pin
When reset
Circuit format
Port B
∗
Pull-up resistance
SO
Output enable
Port B output
selection
AA
AA
AA
"0" when reset
PB4/SO0
IP
Port B data
Port B direction
Hi-Z
"0" when reset
Data bus
RD (Port B)
∗ Pull-up transistors
approx. 10kΩ
1 pin
Port B
Internal reset signal
SO
AAAA
AAAA
AAAA
AA
Output enable
PB7/SO1
∗
Port B output
selection
"1" when reset
High level
Port B data
∗ Pull-up transistors
approx. 200kΩ
Data bus
1 pin
RD (Port B)
AAAA
AAAA
AAAA
AAAA
AAAA
Port C
∗2
Pull-up resistance
"0" when reset
Port C data
PC0 to PC7
∗1
Port C direction
"0" when reset
RD (Port C)
8 pins
4 pins
Port E
Hi-Z
IP
∗1 High current drive
of 12mA possible
∗2 Pull-up transistors
approx. 10kΩ
Data bus
PE0/EC0
PE1/EC1
PE2/RMC
PE3/NMI
AA
A
AA
A
AAAA
AAAA
Schmitt input
EC0
EC1
RMC/NMI
IP
Data bus
RD (Port E)
–7–
Hi-Z
CXP84332/84340
Pin
When reset
Circuit format
Port E
AAAA
AAAA
AAAA
AA
AA
PWM
Port E output
selection
PE4/PWM
"0" when reset
Port E data
"1" when reset
Data bus
High level
RD (Port E)
1 pin
Port E
AA
AAA
AA
AAA
AAA
AAA
AAA
Ouput enable
TO
ADJ16K
ADJ2K
PE5/TO/ADJ
MPX
Port E output
selection
Port E output
selection
"00" when reset
AA
Port E output
selection
"0" when reset
Port E data
High level
∗ ADJ signals are frequency division
outputs for 32kHz oscillation frequency
adjustment. ADJ2K provides usage as
buzzer output.
"1" when reset
Data bus
RD (Port E)
1 pin
Port D
Port F
Port G
Port H
PD0 to PD7
PF0 to PF7
PG0 to PG7
PH0 to PH7
PI4 to PI7
Port I
AAAA
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistance
"0" when reset
Port data
Port direction
"0" when reset
Data bus
A
AA
A
AA
IP
RD
∗ Pull-up transistors
approx. 10kΩ
36 pins
–8–
Hi-Z
CXP84332/84340
Pin
When reset
Circuit format
Port I
AAAA
AAAA
AAAA
AAAA
AAAA
A
AA
A
AA
INT0
INT1
INT2
INT3
∗ Pull-up transistors
approx. 10kΩ
∗
Pull-up resistance
"0" when reset
Port data
PI0/INT0
to
PI3/INT3
Port direction
IP
"0" when reset
Data bus
RD
4 pins
EXTAL
XTAL
2 pins
TEX
TX
2 pins
AA
A
AA
AA
A
AA
AA
AA
AA
A
AA
AA
A
AA
AA
AA
EXTAL
IP
IP
Hi-Z
• Diagram shows circuit
composition during oscillation.
• Feedback resistor is removed
during stop.
Oscillation
XTAL
TEX
IP
• Diagram shows circuit
composition during oscillation.
IP
• When the operation of the oscillation
circuit is stopped by the software, the
feedback resistor is removed, and
TEX and TX become "Low" level and
"High" level respectively.
TX
Oscillation
Pull-up resistor
RST
1 pin
AA
AA
OP Mask option
Low level
IP
–9–
Schmitt input
CXP84332/84340
Absolute Maximum Ratings
Item
(Vss = 0V reference)
Symbol
Supply voltage
Ratings
Unit
VDD
–0.3 to +7.0
V
AVSS
V
Remarks
Input voltage
VIN
–0.3 to +0.3
–0.3 to +7.0∗1
Output voltage
VOUT
–0.3 to +7.0∗1
V
High level output current
IOH
–5
mA
Output per pin
–50
mA
Total for all output pins
IOL
15
mA
IOLC
20
mA
Value per pin, excluding large current outputs
Value per pin∗2 for large current outputs
Low level total output current
∑IOL
100
mA
Total for all output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
600
mW
High level total output current ∑IOH
Low level output current
V
∗1 VIN and VOUT must not exceed VDD + 0.3V.
∗2 The high current drive transistor is the N-ch transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
Recommended Operating Conditions
Item
Supply voltage
High level input
voltage
Symbol
Min.
Max.
4.5
5.5
3.5
5.5
2.7
5.5
Guaranteed operation range with TEX clock
2.5
5.5
VIH
0.7VDD
VDD
V
Guaranteed data hold range during stop
∗2
VIHS
0.8VDD
VDD
V
VDD
VIHEX
Low level input
voltage
Operating temperature
(Vss = 0V reference)
VDD – 0.4 VDD + 0.3
Unit
Remarks
High-speed mode guaranteed operation
range∗1
V
Low-speed mode guaranteed operation
range∗1
V
Hysteresis input∗3
EXTAL∗4
∗2
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
Topr
–20
+75
°C
Hysteresis input∗3
EXTAL∗4
∗1 High-speed mode is 1/2 frequency demultiplication clock selection; low-speed mode is 1/16 frequency
demultiplication clock selection.
∗2 Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF to PH, PI4 to PI7).
∗3 Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2,
INT3.
∗4 Specifies only during external clock input.
– 10 –
CXP84332/84340
Electrical Characteristics
DC Characteristics
Item
High level
output voltage
Low level
output voltage
(Ta = –20 to +75°C, Vss = 0V reference)
Symbol
Pins
VOH
PA to PD,
PE4, PE5,
PF to PI
VOL
PC
IIHE
IILE
EXTAL
IIHT
Input current
I/O leakage
current
IILT
TEX
IILR
RST∗1
IIL
PA to PD∗2,
PF to PI∗2
IIZ
Typ.
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIH = 5.5V
0.1
10
µA
–0.1
–10
µA
–1.5
–400
µA
–2.0
mA
VDD = 5.5V,
VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
µA
–10
±10
µA
20
42
mA
35
100
µA
1.1
8
mA
9
30
µA
10
µA
20
pF
Sleep mode
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
IDDS2
Unit
4.0
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD
Max.
VDD = 4.5V, IOH = –0.5mA
High-speed mode operation
(1/2 frequency demultiplier clock)
IDD2
IDDS1
Min.
PE0 to PE3, VDD = 5.5V,
VI = 0, 5.5V
RST∗1
IDD1
Power supply
current∗3
Conditions
Stop mode
IDDS3
Input capacity
CIN
VDD = 5.5V, termination of 10MHz and
32kHz crystal oscillation
Pins other
than PB7,
PE4, PE5,
AVREF, VDD,
VSS
Clock 1MHz
0V for all pins excluding measured
pins
10
∗1 RST specifies the input current when pull-up resistance has been selected; leakage current when no
resistance has been selected.
∗2 Pins PA to PD, and PF to PI specify the input current when pull-up resistance has been selected; leakage
current when no resistance has been selected. (Excludes output PB7)
∗3 When all pins are open.
– 11 –
CXP84332/84340
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
System clock frequency
fC
System clock input pulse
width
Event count input clock
rise time, fall time
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
System clock frequency
fC
Event count input clock
input pulse width
tTL,
tTH
tTR,
tTF
System clock input
rise time, fall time
Event count input clock
pulse width
Event count input clock
rise time, fall time
Pin
Conditions
Min.
XTAL
Fig. 1, Fig. 2
EXTAL
Typ.
1
EXTAL
Fig. 1, Fig. 2
External clock drive
EXTAL
Fig. 1, Fig. 2
External clock drive
EC0
EC1
Fig. 3
EC0
EC1
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
Fig. 3
TEX
Fig. 3
Max.
Unit
10
MHz
ns
37.5
200
tsys + 50∗1
ns
ns
20
ms
kHz
32.768
µs
10
20
ms
∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
1/fc
VDD – 0.4V
EXTAL
0.4V
tCF
tXH
tXL
tCR
Fig. 1. Clock timing
AAAAA
AAAA
AAAA
AAAAAAAAA AAAA
AAAAAAAAA AAAA
Crystal oscillation
Ceramic oscillation
EXTAL
C1
External clock
EXTAL
XTAL
C2
32kHz clock applied condition
Crystal oscillation
TEX
XTAL
74HC04
Fig. 2. Clock applied condition
– 12 –
C1
TX
C2
CXP84332/84340
TEX
EC0
EC1
0.8VDD
0.2VDD
tEH
tTH
tEF
tTF
tEL
tTL
tER
tTR
Fig. 3. Event count clock timing
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Condition
Pin
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↑ → SCK0
float delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↓ → SO0
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS0 ↑ → SO0
float delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS0 High level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK0 cycle time
tKCY
Input mode
2tsys + 200
ns
16000/fc
ns
tsys + 100
ns
8000/fc – 50
ns
SCK0 input mode
100
ns
SCK0 output mode
200
ns
tsys + 200
ns
100
ns
SCK0
SCK0
High and Low level widths
tKH
tKL
SCK0
SI0 input setup time
(for SCK0 ↑)
tSIK
SI0
SI0 input hold time
(for SCK0 ↑)
tKSI
SCK0 ↓ → SO0
delay time
tKSO
SI0
SO0
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
– 13 –
CXP84332/84340
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
Input
data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
Fig. 4. Serial transfer CH0 timing
– 14 –
CXP84332/84340
Serial transfer (CH1)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
SCK1 cycle time
tKCY
SCK1
SCK1 High and Low level
widths
tKH
tKL
SCK1
SI1 input setup time
(for SCK1 ↑)
tSIK
SI1
SI1 input hold time
(for SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Condition
Min.
Input mode
ns
16000/fc
ns
400
ns
8000/fc – 50
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
SCK1 input mode
200
ns
SCK1 output mode
100
ns
Output mode
Input mode
Output mode
SCK1 input mode
200
ns
SCK1 output mode
100
ns
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
Input data
0.2VDD
tKSO
0.8VDD
Output data
SO1
Unit
1000
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
SI1
Max.
0.2VDD
Fig. 5. Serial transfer CH1 timing
– 15 –
CXP84332/84340
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)
Item
Symbol
Max.
Unit
Resolution
8
Bits
Linearity error
±5
LSB
Zero transition voltage
VZT∗1
Full-scale transition
voltage
VFT∗2
Conversion time
tCONV
tSAMP
Sampling time
Pin
Min.
Ta = 25°C
VDD = 5.0V
VSS = AVSS = 0V
AVREF
Analog input voltage
AN0 to AN7
–10
70
150
mV
4930
5050
5120
mV
AVREF
IREFS
µs
µs
VDD – 0.5
VDD
V
0
AVREF
V
1.0
mA
10
µA
Operation mode
IREF
AVREF current
Typ.
160/fADC∗3
12/fADC∗3
Reference input voltage VREF
VIAN
Condition
Sleep mode
Stop mode
32kHz operation mode
0.6
Digital conversion value
FFH
FEH
∗1 VZT : Value at which the digital conversion value changes
from 00H to 01H and vice versa.
∗2 VFT : Value at which the digital conversion value changes
from FEH to FFH and vice versa.
∗3 fADC indicates the below values due to ADC operation
clock selection.
During PS2 selection, fADC = fc/2
During PS1 selection, fADC = fc
Linearity error
01H
00H
VFT
VZT
Analog input
Fig. 6. Definition of A/D converter terms
– 16 –
CXP84332/84340
(4) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
Condition
External interruption
High and Low level widths
tIH
tIL
INT0
INT1
INT2
INT3
NMI
PJ0 to PJ7
Reset input Low level width
tRSL
RST
Min.
Max.
Unit
1
µs
8/fc
µs
tIH
tIL
0.8VDD
INT0
INT1
INT2
INT3
NMI
(NMI specifies only for
the falling edge.)
0.2VDD
tIL
tIH
Fig 7. Interruption input timing
tRSL
RST
0.2VDD
Fig. 8. RST input timing
– 17 –
CXP84332/84340
Appendix
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
(i) Main clock
EXTAL
EXTAL
XTAL
C2
C1
AAAA
AAAA
AAAA
(ii) Main clock
(iii) Sub clock
EXTAL
TEX
XTAL
XTAL
TX
Rd
C2
C1
C1 C2
Fig. 9. Recommended oscillation circuit
Manufacturer
MURATA
MFG
CO., LTD.
Model
fc (MHz)
CSA4.19MG
4.19
CSA8.00MTZ
8.00
CSA10.0MTZ
10.00
CST4.19MGW∗
CST8.00MTW∗
CST10.0MTW∗
RIVER
HC-49/U03
ELETEC
CORPORATION
C1 (pF)
KINSEKI
LTD.
P3
Rd (Ω)
Circuit
example
(i)
30
30
0
4.19
(ii)
8.00
10.00
4.19
12
8.00
12
0
10.00
(i)
4.19
HC-49/U (-S)
C2 (pF)
27
27
10.00
20
20
32.768kHz
50
22
8.00
0
1M
Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).
Mask option table
Item
Reset pin pull-up resistance
Content
Non-existent
Existent
– 18 –
(iii)
CXP84332/84340
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
17.9 ± 0.4
+ 0.4
14.0 – 0.1
40
A
+ 0.2
0.1 – 0.05
25
1
24
0.8
0.2
M
+ 0.15
0.35 – 0.1
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP080-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.6g
JEDEC CODE
– 19 –
0.8 ± 0.2
80
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