ATMEL AT29C432-15TI 4 megabit 5-volt flash with 256k e2prom memory Datasheet

Features
•
•
•
•
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ConcurrentFlash Memory
Unique Architecture Allows the Flash Array
To Be Read During the E2PROM Write Cycle
4 Megabit 5-volt Flash
Configured as a 512K x 8 Memory Array
120 ns Read Access Time
Sector Program Operation
Single Cycle Reprogram (No Erase Necessary)
2048 Sectors, 256-Bytes Wide
10 ms Sector Rewrite
JEDEC Standard Software Data Protection
256K bit Full Feature E2PROM
Configured as a 32K x 8 Memory Array
Byte or Page (16 bytes) Write Capability
Write Cycle Time: 10 ms
JEDEC Standard Software Data Protection
Pinout Similar to 32-Pin 4 Mb Flash
Data Memory Endurance: 10,000 cycles
4 Megabit
5-volt Flash with
256K E2PROM
Memory
Description
The AT29C432 is a CMOS memory specifically designed for applications requiring
both a high density nonvolatile program memory and a smaller nonvolatile data memory. The AT29C432 provides this in the form of a 4 megabit Flash array integrated
with a 256K bit full featured E2PROM array on the same device. A unique feature of
this device is its concurrent read while writing capability. This provides the host system read access to the Flash program memory during the write cycle time of the
E2PROM.
The two memory arrays share all I/O lines, Address lines and OE and WE inputs.
Each memory array has its own Chip Enable input: CEF for the Flash array and CEE
for the E2PROM array.
Additionally, Software Data Protection has been independently implemented for both
arrays and is always enabled. The AT29C432 has a pinout similar to the AT29C040A
Flash memory. A system designer using a Flash memory for program storage and
another smaller, non volatile memory for data storage can easily replace both memories with the AT29C432.
Pin Configurations
Pin Name
Function
A0 - A18
Addresses
OE
Output Enable
WE
Write Enable
I/O0 - I/O7 Data Inputs/Outputs
CEE
Chip Enable E2PROM
CEF
Chip Enable Flash
NC
No Connect
TSOP
Type 1
AT29C432
ConcurrentFlash
Preliminary
Device Operation
Flash Memory Array
READ: The Flash memory array is read like a Static
RAM. When CEF and OE are low, and WE and CEE are
high, the data stored at the memory location determined
by the address inputs is asserted on the I/O’s.
PROGRAM: The Flash memory array is divided into 2048
sectors, each comprised of 256 bytes. For read operations these sectors appear seamless; however, for reprogramming the sector boundaries must be taken into account. The state of adresses A0 - A3 and A15 - A18 specify the individual byte address within a sector and the state
of addresses A4 - A14 define the sector to be written.
The AT29C432 employs the JEDEC standard software
data protection feature; therefore, each programming sequence must be preceded by the three byte program command sequence. Using the software data protection feature, byte loads are used to enter the 256 bytes of a sector
to be programmed. The Flash memory array can only be
programmed using the software data protection feature.
The Flash memory array is programmed on a sector basis.
If a byte of data within the sector is to be changed, data for
the entire 256-byte sector must be loaded into the device.
The Flash memory array automatically does a sector
erase prior to loading the data into the sector. An erase
command is not required.
Software data protection protects the device from inadvertent programming. A series of three program commands
to specific addresses with specific data must be presented
to the device before programming may occur. The same
three program commands must begin each program operation. All software program commands must obey the
sector program timing specifications. Power transitions
will not reset the software data protection feature, however
the software feature will guard against inadvertent program cycles during power transitions.
Any attempt to write to the device without the three-byte
command sequence will start the internal write timers. No
data will be written to the device; however, for the duration
of tWCF, a read operation will effectively be a polling operation.
After the software data protection’s three-byte command
code is given, a byte load is performed by applying a low
pulse on the WE or CEF input with CEF or WE low (respectively) and OE and CEE high. The address is latched
on the falling edge of CEF or WE, whichever occurs last.
The data is latched by the first rising edge of CEF or WE.
The 256 bytes of data must be loaded into each sector.
Any byte that is not loaded during the programming of its
sector will be indeterminate. Once the bytes of a sector
are loaded into the device, they are simultaneously programmed during the internal programming period. After
the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition
on WE (or CEF) within 150 µs of the low to high transition
of WE (or CEF) of the preceding byte. If a high to low
transition is not detected within 150 µs of the last low to
(continued)
2
AT29C432
AT29C432
Device Operation (Continued)
high transition, the load period will end and the internal
programming period will start. The sector address must
be valid during each high to low transition of WE (or CEF).
The bytes may be loaded in any order; sequential loading
is not required. Once a programming operation has been
initiated, and for the duration of tWCF, a read operation will
effectively be a data polling operation.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the Flash memory
array in the following ways: (a) VCC sense—if VCC is below 3.8V (typical), the program function is inhibited. (b)
VCC power on delay—once VCC has reached the VCC
sense level, the device will automatically time out 10 ms
(typical) before programming. (c) Program inhibit—holding any one of OE low, CEF high or WE high inhibits program cycles. (d) Noise filter—pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
DATA POLLING: A maximum amount of time for program and write operations is specified; the actual time is
frequently faster than the specification. In order to take advantage of the faster typical times, the Flash memory array features DATA polling to indicate the end of a program
cycle. During a program cycle an attempted read of the
last byte loaded will result in the complement of the loaded
data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle
may begin. DATA polling may begin at any time during the
program cycle.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product. In addition, users may wish to use the
software product identification mode to identify the part
(i.e. using the device code), and have the system software
use the appropriate sector size for program operations.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
E2PROM Memory Array
READ: The E2PROM memory array is read like a Static
RAM. When CEE and OE are low and WE and CEF are
high, the data stored at the memory location determined
by the address inputs is asserted on the I/O’s.
command sequence. This sequence should then immediately be followed by one to sixteen bytes of data. After the
last byte has been written, the AT29C432 will automatically time itself to completion of the internal write cycle.
The write cycle is initiated by both WE and CEE going low;
the address is latched by the falling edge of WE or CEE
(whichever occurs last) and the data is latched by the rising edge of WE or CEE (whichever occurs first). All write
operations (byte or page) must conform to the page write
limits as shown in the timing diagram for E2PROM write
operations. All bytes during a page write operation must
reside on the same page as defined by the state of the A4
- A14 inputs. For each WE high to low transition during
the page write operation, A4 - A14 must be the same.
The A0 - A3 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in
any order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
During the internal write operation (tWCE) attempts to read
the E2PROM will be equivalent to DATA polling operations; however, attempts to read the Flash array will return
valid data.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the E2PROM
memory array in the following ways: (a) VCC sense—if
VCC is below 3.8V (typical), the program function is inhibited. (b) VCC power on delay—once VCC has reached the
VCC sense level, the device will automatically time out 10
ms (typical) before programming. (c) Program inhibit—
holding any one of OE low, CEE high or WE high inhibits
program cycles. (d) Noise filter—pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
DATA POLLING: A maximum amount of time for program and write operations is specified; the actual time is
frequently faster than the specification. In order to take
advantage of the faster typical times, the E2PROM memory array features DATA polling to indicate the end of a
program cycle. During a program cycle an attempted read
of the last byte loaded will result in the complement of the
loaded data on I/O7. Once the program cycle has been
completed, true data is valid on all outputs and the next
cycle may begin. DATA polling may begin at any time during the program cycle.
(continued)
WRITE: The E2PROM memory array may be written in
either a single byte write or page write operation. Because software data protection is always enabled both
write operations must be preceded by the three byte write
3
Device Operation (Continued)
Memory Arrays
Concurrent Read While Write
Valid Concurrent Read
The architecture of the AT29C432 provides concurrent
read while write capability. With other programmable nonvolatile memories internal high voltage operations prevent
the reading of data while a write operation is in process.
However, the AT29C432 is partitioned in a manner to allow read operations from the Flash memory array during a
write operation within the E2PROM memory array.
Reads from the Flash are allowed throughout the
E2PROM write cycle time (tWCE). The E2PROM memory
array must be deselected (CEE HIGH).
Conceptually the device was designed assuming the
Flash memory array would be utilized for infrequently updated program storage and the E2PROM memory array
would be used for frequently updated data storage. This
simple concept eliminates complicated software and hardware schemes using multiple blocks of memory just to
hold duplicate down-load routines.
Reads from the Flash are allowed during tWPH o f a
E2PROM write so long as tBLC for the E2PROM write is not
violated. The E2PROM memory array must be deselected
(CEE HIGH).
Invalid Concurrent Reads
Attempts to read the Flash memory array during tWCF will
effectively be polling operations.
Attempts to access the Flash memory array while CEE is
low will be ignored. That is, CEE low and CEF low at the
same time is not allowed. Attempts to read the E2PROM
memory array while a write to the Flash memory array is
in progress is not allowed.
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
All Output Voltages
with Respect to Ground .............-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
Pin Capacitance (f = 1 MHz, T = 25°C)
Parameter
Typ
Max
Units
Conditions
CIN
Input Capacitance
4
10
pF
VIN = 0V
COUT
Output Capacitance
8
12
pF
VOUT = 0V
Note:
4
(1)
1. This parameter is characterized and is not 100% tested.
AT29C432
AT29C432
DC and AC Operating Range
Operating
Temperature (Case)
Com.
Ind.
VCC Power Supply
AT29C432-12
AT29C432-15
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
4.5V - 5.5V
4.5V - 5.5V
Operating Modes
Mode
CEE
CEF
OE
WE
Ai
I/O
Flash Read
VIH
VIL
VIL
VIH
Ai
DOUT
E2PROM
Read
VIL
VIH
VIL
VIH
Ai
DOUT
Flash Program
VIH
VIL
VIH
VIL
Ai
DIN
E2PROM
VIL
VIH
VIH
VIL
Ai
DIN
Standby/Write Inhibit
Program
VIH
VIH
X
X
X
High Z
Program Inhibit
X (2)
X
X
VIH
Program Inhibit
X
X
VIL
X
Output Disable
X
X
VIH
X
High Z
Illegal
VIL
VIL
VIL
X
DOUT
Undefined
Illegal
VIL
VIL
VIH
X
High Z
Product Identification
A1 - A18 = VIL, A9 = VH, (3)
Hardware
VIH
VIL
VIL
VIH
A0 = VIL
A1 - A18 = VIL, A9 = VH, (3)
A0 = VIH
Software (5)
Notes: 1. For detailed operational timing refer to the appropriate timing diagrams and AC characteristics tables.
2. X indicates input state can be either VIH or VIL.
3. VH = 12.0V ± 0.5V
Manufacturer Code (4)
Device Code (4)
A0 = VIL, A1 - A18 = VIL
Manufacturer Code (4)
A0 = VIH, A1 - A18 = VIL
Device Code (4)
4. Manufacturer Code: 1F, Device Code: B4
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
ILI
Input Load Current
VIN = 0V to VCC
10
µA
ILO
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB
VCC Standby Current
CEE = CEF = VCC - 0.3V
to VCC + 1.0V
300
µA
f = 5 MHz; IOUT = 0 mA
40
mA
0.8
V
ICC
VCC Active Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
2.0
IOL = 2.1 mA
V
0.45
V
IOH = -400 µA; VCC = 4.5V
2.4
V
IOH = -100 µA; VCC = 4.5V
4.2
V
5
AC Read Characteristics
AT29C432-12
Symbol
Parameter
Min
tCED
CEE to CEF Active Delay (or CEF to
CEE Active Delay)
100
tACC
Max
Min
Max
100
Address to Output Delay
120
tCE
(1)
CEE (or CEF) to Output Delay
120
tOE
(2)
OE to Output Delay
0
tDF
(3, 4)
CE or OE to Output Float
0
Output Hold from OE, CEE or CEF or
Address change
0
tOH
AT29C432-15
Units
ns
150
ns
0
150
ns
50
0
70
ns
30
0
40
ns
0
ns
AC Read Waveforms (1, 2, 3, 4)
Notes: 1. CEF (CEE) may be delayed up to tACC - tCE after the
address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling
edge of CEF (CEE) without impact on tCE or by
tACC - tOE after an address change without impact on
tACC.
3. tDF is specified from OE or CEF (CEE) whichever occurs first
(CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
tR, tF < 5 ns
6
AT29C432
Output Test Load
AT29C432
Flash Array
AC Write Timing Characteristics
Symbol
Parameter
Min
Max
Units
tWCF
Write Cycle Time
10
ms
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tWP
Write Pulse Width (WE or CEF)
100
ns
tOES
OE Disable to WE or CEF Active
0
ns
tDS
Data Set-up Time
50
ns
tDH
Data Hold Time
10
ns
tCS
CEF to WE or WE to CEF Setup Time
0
ns
tCH
CEF to WE or WE to CEF Hold Time
0
ns
tOEH
WE or CEF Disable to OE Active
10
ns
tWPH
WE or CEF Pulse Width High
100
ns
tBLC
Byte Load Cycle Time
150
µs
AC Flash Array Write Waveforms
Note:
1. BYTE ADDRESS is the first destination address for the sector write operation. All write operations must begin with the
three byte write enable sequence.
7
E2PROM Array
AC Write Timing Characteristics
Symbol
Parameter
Min
Max
Units
tWCE
Write Cycle Time
10
ms
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tWP
Write Pulse Width (WE or CEE)
100
ns
tOES
OE Disable to WE or CEE Active
0
ns
tDS
Data Set-up Time
50
ns
tDH
Data Hold Time
10
ns
tCS
CEE to WE or WE to CEE Setup Time
0
ns
tCH
CEE to WE or WE to CEE Hold Time
0
ns
tOEH
WE or CEE Disable to OE Active
10
ns
tWPH
WE or CEE Pulse Width High
100
ns
tBLC
Byte Load Cycle Time
150
µs
AC E2PROM Array Write Waveforms
Note:
8
1. Only A0 - A14 are valid address inputs for the E2PROM write operations, A15 - A18 are don’t care. BYTE ADDRESS is
the first destination address for either a byte write or page write operation. All write operations, byte only or page write,
must begin with the three byte write enable sequence.
AT29C432
AT29C432
Concurrent Read While Write
Notes: 1. The Flash array may be read in between individual
byte loads to the E2PROM array as shown above.
This diagram only illustrates one read access between byte loads, but the host processor may continue reading the Flash array so long as tBLC is not
violated. This effectively allows the host the opportunity to respond to system interrupts while operating
out of the Flash program memory, even in the middle of performing an E2PROM data update.
2. Flash read operations are also valid throughout the
E2PROM’s internal write cycle defined by tWCE.
3. Having both CEF and CEE active simultaneously is an
illegal state.
Chip Enable Delays
9
AC Data Polling Characteristics
Symbol
Parameter
tWCE
(1)
Min
Max
Units
Write Cycle Time, E2PROM
10
ms
tWCF
Write cycle Time, Flash
10
ms
tOEH
WE or CEE (CEF) Disable to OE Active
10
ns
AC Data Polling Waveform
Note:
1. The above timing diagram illustrates DATA Polling where Dn is equal to the state of I/07 for the last byte written and Dn
is its complement.
Software Product (1)
Identification Exit
Software Product (1)
Identification Entry
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 10 mS
ENTER PRODUCT
IDENTIFICATION
(2, 3, 5)
MODE
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A18 = VIL. Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH. CEF = Low, CEE = High
3. The device does not remain in identification mode if powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1F
Device Code: B4
10
AT29C432
PAUSE 10 mS
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
AT29C432
Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
120
40
150
Ordering Code
Package
Operation Range
0.3
AT29C432-12TC
40T
Commercial
(0° to 70°C)
40
0.3
AT29C432-12TI
40T
Industrial
(-40° to 85°C)
40
0.3
AT29C432-15TC
40T
Commercial
(0° to 70°C)
40
0.3
AT29C432-15TI
40T
Industrial
(-40° to 85°C)
Package Type
40T
40 Lead, Thin Small Outline Package (TSOP)
Packaging Information
40T, 40 Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches) *
*Controlling dimension: millimeters
11
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