Cypress CY7C1062DV33-10BGXI 16-mbit (512 k x 32) static ram Datasheet

CY7C1062DV33
16-Mbit (512 K × 32) Static RAM
16-Mbit (512 K × 32) Static RAM
Features
Functional Description
■
High speed
❐ tAA = 10 ns
The CY7C1062DV33 is a high performance CMOS Static RAM
organized as 524,288 words by 32 bits.
■
Low active power
❐ ICC = 175 mA at 100 MHz
■
Low complementary metal oxide semiconductor (CMOS)
standby power
❐ ISB2 = 25 mA
■
Operating voltages of 3.3 ± 0.3 V
To write to the device, take Chip Enables (CE1, CE2, and CE3
LOW) and Write Enable (WE) input LOW. If Byte Enable A (BA)
is LOW, then data from I/O pins (I/O0 through I/O7) is written into
the location specified on the address pins (A0 through A18). If
Byte Enable B (BB) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A18). Likewise, BC and BD correspond with the I/O
pins I/O16 to I/O23 and I/O24 to I/O31, respectively.
■
2.0 V data retention
■
Automatic power down when deselected
■
Transistor-transistor logic (TTL) compatible inputs and outputs
■
Easy memory expansion with CE1, CE2, and CE3 features
■
Available in Pb-free 119-ball plastic ball grid array (PBGA)
package
To read from the device, take Chip Enables (CE1, CE2, and CE3
LOW) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If the first BA is LOW, then data from the
memory location specified by the address pins appear on I/O0 to
I/O7. If BB is LOW, then data from memory appears on I/O8 to
I/O15. Likewise, Bc and BD correspond to the third and fourth
bytes. See Truth Table on page 10 for a complete description of
read and write modes.
The input and output pins (I/O0 through I/O31) are placed in a
high impedance state when the device is deselected (CE1, CE2,
or CE3 HIGH), the outputs are disabled (OE HIGH), the byte
selects are disabled (BA-D HIGH), or during a write operation
(CE1, CE2 and CE3 LOW and WE LOW).
OUTPUT BUFFERS
512 K x 32
ARRAY
SENSE AMPS
A(9:0)
ROW DECODER
INPUT BUFFERS
CONTROL LOGIC
Logic Block Diagram
I/O0–I/O31
WE
CE1
CE2
CE3
OE
BA
BB
BC
BD
COLUMN
DECODER
A(18:10)
Cypress Semiconductor Corporation
Document Number: 38-05477 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 20, 2011
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CY7C1062DV33
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
AC Switching Characteristics ......................................... 6
Data Retention Characteristics ....................................... 7
Over the Operating Range ............................................... 7
Data Retention Waveform ................................................ 7
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 10
Document Number: 38-05477 Rev. *H
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagram ............................................................ 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History ........................................................... 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
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CY7C1062DV33
Selection Guide
-10
Unit
Maximum access time
Description
10
ns
Maximum operating current
175
mA
Maximum CMOS standby current
25
mA
Pin Configuration
Figure 1. 119-ball PBGA (Top View) [1]
1
2
3
4
5
6
7
A
I/O16
A
A
A
A
A
I/O0
B
C
D
E
F
G
H
J
K
L
M
N
P
I/O17
I/O18
I/O19
A
Bc
VDD
A
CE2
VSS
CE1
NC
VSS
A
CE3
VSS
A
Ba
VDD
I/O1
I/O2
I/O3
I/O20
VSS
VDD
VSS
VDD
VSS
I/O4
I/O21
VDD
VSS
VSS
VSS
VDD
I/O5
I/O22
VSS
VDD
VSS
VDD
VSS
I/O6
I/O23
NC
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
I/O7
NC
I/O24
I/O25
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
I/O8
I/O9
I/O10
R
T
U
I/O26
VDD
VSS
VSS
VSS
VDD
I/O27
VSS
VDD
VSS
VDD
VSS
I/O11
I/O28
VDD
VSS
VSS
VSS
VDD
I/O12
I/O29
A
Bd
NC
Bb
A
I/O13
I/O30
A
A
WE
A
A
I/O14
I/O31
A
A
OE
A
A
I/O15
Note
1. NC pins are not connected on the die.
Document Number: 38-05477 Rev. *H
Page 3 of 15
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CY7C1062DV33
DC input voltage [2] ............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied .......................................... –55 C to +125 C
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, method 3015) .................................. >2001 V
Latch-up current ..................................................... >200 mA
Operating Range
Supply voltage on
VCC relative to GND [2] ................................–0.5 V to +4.6 V
DC voltage applied to outputs
in High Z state [2] ................................ –0.5 V to VCC + 0.5 V
Range
Ambient Temperature
VCC
Industrial
–40 C to +85 C
3.3 V  0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions [3]
VOH
Output HIGH voltage
Min VCC, IOH = –4.0 mA
VOL
Output LOW voltage
Min VCC, IOL = 8.0 mA
VIH
Input HIGH voltage
[2]
-10
Min
Max
Unit
2.4
–
V
–
0.4
V
2.0
VCC + 0.3
V
VIL
Input LOW voltage
–0.3
0.8
V
IIX
Input leakage current
GND < VIN < VCC
–1
+1
A
IOZ
Output leakage current
GND < VOUT < VCC, output disabled
–1
+1
A
ICC
VCC operating supply current
VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA,
CMOS levels
–
175
mA
ISB1
Automatic CE power-down
current – TTL Inputs
Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX
–
30
mA
ISB2
Automatic CE power-down
current – CMOS Inputs
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
–
25
mA
Notes
2. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
3. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3 HIGH.
Document Number: 38-05477 Rev. *H
Page 4 of 15
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CY7C1062DV33
Capacitance
Parameter [4]
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
Max
TA = 25 C, f = 1 MHz, VCC = 3.3 V
Unit
8
pF
10
pF
Thermal Resistance
Parameter [4]
Description
JA
Thermal resistance
(Junction to ambient)
JC
Thermal resistance
(Junction to case)
Test Conditions
119-ball PBGA Unit
Still air, soldered on a 3 × 4.5 inch, four layer printed circuit
board.
20.31
C/W
8.35
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [5]
50 
OUTPUT
Z0 = 50
R1 317 
3.3V
VTH = 1.5 V
OUTPUT
30 pF*
R2
351
5 pF*
*Including jig
and scope
(a)
*Capacitive Load consists of all
components of the test environment
3.0V
GND
(b)
All input pulses
90%
10%
90%
10%
Fall Time:> 1 V/ns
Rise Time > 1 V/ns
(c)
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating
VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage.
Document Number: 38-05477 Rev. *H
Page 5 of 15
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CY7C1062DV33
AC Switching Characteristics
Over the Operating Range
Parameter [6]
Description
-10
Min
Max
Unit
Read Cycle
tpower
VCC(typical) to the first access [7]
100
–
s
tRC
Read cycle time
10
–
ns
tAA
Address to data valid
–
10
ns
tOHA
Data hold from address change
3
–
ns
tACE
CE Active LOW to data valid
[8]
–
10
ns
tDOE
OE LOW to data valid
–
5
ns
1
–
ns
–
5
ns
[9]
tLZOE
OE LOW to low Z
tHZOE
OE HIGH to high Z [9]
tLZCE
3
–
ns
CE Deselect HIGH to high Z
[8, 9]
–
5
ns
tPU
CE Active LOW to power-up
[8, 10]
0
–
ns
tPD
CE Deselect HIGH to power-down [8, 10]
–
10
ns
tDBE
Byte enable to data valid
5
ns
1
–
ns
–
5
ns
10
–
ns
7
–
ns
tHZCE
tLZBE
tHZBE
CE Active LOW to low Z
[8, 9]
Byte enable to low Z
[9]
Byte disable to high Z
[9]
Write Cycle [11, 12]
tWC
Write cycle time
[8]
tSCE
CE Active LOW to write end
tAW
Address setup to write end
7
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
7
–
ns
tSD
Data setup to write end
5.5
–
ns
tHD
Data hold from write end
0
–
ns
WE HIGH to low Z
[9]
3
–
ns
tHZWE
WE LOW to high Z
[9]
–
5
ns
tBW
Byte enable to end of write
7
–
ns
tLZWE
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in (a) of Figure 2 on page 5, unless specified otherwise.
7. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
8. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3
HIGH.
9. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 2 on page 5. Transition is measured ±200 mV
from steady state voltage.
10. These parameters are guaranteed by design and are not tested.
11. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 LOW, CE3 LOW and WE LOW. Chip enables must be active and WE must be LOW
to initiate a write, and the transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal
that terminates the write.
12. The minimum write cycle time for Write Cycle No.2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05477 Rev. *H
Page 6 of 15
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CY7C1062DV33
Data Retention Characteristics
Over the Operating Range
Parameter
Conditions [13]
Description
VDR
VCC for data retention
ICCDR
Data retention current
tCDR [15]
Chip deselect to data retention
time
tR [16]
Operation recovery time
VCC = 2 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V, or VIN < 0.2 V
Min
Typ [14]
Max
Unit
2
–
–
V
–
–
25
mA
0
–
–
ns
tRC
–
–
ns
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
3.0 V
VDR > 2V
tCDR
3.0 V
tR
CE
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [17, 18]
tRC
RC
ADDRESS
tOHA
DATA I/O
PREVIOUS DATA VALID
tAA
DATA OUT VALID
Notes
13. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3 HIGH
14. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
15. Tested initially and after any design or process changes that affects these parameters.
16. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
17. Device is continuously selected. OE, CE, BA, BB, BC, BD = VIL.
18. WE is HIGH for read cycle.
Document Number: 38-05477 Rev. *H
Page 7 of 15
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CY7C1062DV33
Switching Waveforms (continued)
Figure 5. Read Cycle No. 2 (OE Controlled) [19, 20, 21]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BA, BB, BC , BD
tLZOE
tHZCE
tDBE
tLZBE
DATA I/O
tHZBE
HIGH IMPEDANCE
DATA OUT VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Figure 6. Write Cycle No. 1 (CE Controlled) [19, 21, 22, 23]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BA, BB, BC, BD
tSD
DATA I/O
tHD
DATA IN VALID
Notes
19. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3
HIGH.
20. WE is HIGH for read cycle.
21. Address valid before or similar to CE transition LOW.
22. Data I/O is high impedance if OE or BA, BB, BC, BD = VIH.
23. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05477 Rev. *H
Page 8 of 15
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CY7C1062DV33
Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [24, 25, 26, 27]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BA, BB, BC, BD
tHZWE
tSD
tHD
DATA IN VALID
DATA I/O
tLZWE
Figure 8. Write Cycle No. 3 (BA, BB, BC, BD Controlled)
[24]
tWC
ADDRESS
tSA
tBW
BA, BB, BC, BD
tAW
tHA
tPWE
WE
tSCE
CE
tSD
DATA I/O
tHD
DATA IN VALID
Notes
24. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3
HIGH.
25. Address valid before or similar to CE transition LOW.
26. Data I/O is high impedance if OE or BA, BB, BC, BD = VIH.
27. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05477 Rev. *H
Page 9 of 15
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CY7C1062DV33
Truth Table
CE1 CE2 CE3
OE
WE
BA
BB
Bc
BD
I/O0–I/O7
I/O8–I/O15 I/O16–I/O23 I/O24–I/O31
Mode
Power
H
X
X
X
X
X
X
X
X
High Z
High Z
High Z
High Z
power-down
(ISB)
X
H
X
X
X
X
X
X
X
High Z
High Z
High Z
High Z
power-down
(ISB)
X
X
H
X
X
X
X
X
X
High Z
High Z
High Z
High Z
power-down
(ISB)
L
L
L
L
H
L
L
L
L
Data out
Data out
Data out
Data out
Read all bits
(ICC)
L
L
L
L
H
L
H
H
H
Data out
High Z
High Z
High Z
Read byte A
bits only
(ICC)
L
L
L
L
H
H
L
H
H
High Z
Data out
High Z
High Z
Read byte B
bits only
(ICC)
L
L
L
L
H
H
H
L
H
High Z
High Z
Data out
High Z
Read byte C
bits only
(ICC)
L
L
L
L
H
H
H
H
L
High Z
High Z
High Z
Data out
Read Byte D
bits only
(ICC)
L
L
L
X
L
L
L
L
L
Data in
Data in
Data in
Data in
Write all bits
(ICC)
L
L
L
X
L
L
H
H
H
Data in
High Z
High Z
High Z
Write byte A
bits only
(ICC)
L
L
L
X
L
H
L
H
H
High Z
Data in
High Z
High Z
Write byte B
bits only
(ICC)
L
L
L
X
L
H
H
L
H
High Z
High Z
Data in
High Z
Write byte C
bits only
(ICC)
L
L
L
X
L
H
H
H
L
High Z
High Z
High Z
Data in
Write byte D
bits only
(ICC)
L
L
L
H
H
X
X
X
X
High Z
High Z
High Z
High Z
Selected,
outputs
disabled
(ICC)
L
L
L
X
X
H
H
H
H
High Z
High Z
High Z
High Z
Selected,
outputs
disabled
(ICC)
Document Number: 38-05477 Rev. *H
Page 10 of 15
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CY7C1062DV33
Ordering Information
Speed
(ns)
10
Ordering Code
CY7C1062DV33-10BGI
Package
Diagram
Package Type
51-85115 119-ball Plastic Ball Grid Array (14 × 22 × 2.4 mm)
CY7C1062DV33-10BGXI
Operating
Range
Industrial
119-ball Plastic Ball Grid Array (14 × 22 × 2.4 mm) (Pb-free)
Ordering Code Definitions
CY 7 C 1 06 2
D V33 - 10 BG X
I
Temperature Range:
I = Industrial
Pb-free
Package Type:
BG = 119-ball PBGA
Speed: 10 ns
Voltage range: V33 = 3 V to 3.6 V
Process Technology: D = C9, 90 nm
Data width: 2 = × 32-bits
06 = 16-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05477 Rev. *H
Page 11 of 15
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CY7C1062DV33
Package Diagram
Figure 9. 119-ball PBGA (14 × 22 × 2.4 mm) BG119 Package Outline, 51-85115
51-85115 *C
Document Number: 38-05477 Rev. *H
Page 12 of 15
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CY7C1062DV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
chip enable
CMOS
complementary metal oxide semiconductor
°C
degree Celsius
I/O
input/output
MHz
megahertz
OE
output enable
A
microampere
PBGA
plastic ball grid array
s
microsecond
SRAM
static random access memory
mA
milliampere
TTL
transistor-transistor logic
ns
nanosecond
WE
write enable

ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 38-05477 Rev. *H
Symbol
Unit of Measure
Page 13 of 15
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CY7C1062DV33
Document History
Document Title: CY7C1062DV33, 16-Mbit (512 K × 32) Static RAM
Document Number: 38-05477
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
201560
SWI
See ECN
Advance data sheet for C9 IPP
*A
233748
RKF
See ECN
AC, DC parameters are modified as per EROS (Spec # 01-2165)
Pb-free offering in the Ordering Information
*B
469420
NXR
See ECN
Converted from Advance Information to Preliminary
Removed –8 and –12 speed bins from product offering
Removed Commercial operating Range
Changed J7 Ball of PBGA from DNU to NC in the pinout diagram
Included the Maximum ratings for Static Discharge Voltage and Latch Up
Current on page 2
Changed ICC(Max) from 220 mA to 150 mA
Changed ISB1(Max) from 70 mA to 30 mA
Changed ISB2(Max) from 40 mA to 25 mA
Specified the Overshoot specification in footnote 1
Changed tSD from 5.5 ns to 5 ns
Added Data Retention Characteristics table and waveform on page 5.
Updated the 48-pin FBGA package
Updated the Ordering Information Table
*C
499604
NXR
See ECN
Added note 1 for NC pins
Updated Test Condition for ICC in DC Electrical Characteristics table
Added note for tACE, tLZCE, tHZCE, tPU, tPD, and tSCE in AC Switching
Characteristics Table on page 4
*D
1462583
VKN /
AESA
See ECN
Converted from preliminary to final
Updated block diagram
Changed ICC spec from 150 mA to 175 mA
Updated thermal specs
*E
2541850
VKN /
PYRS
07/22/08
Added -10BGI part in the Ordering Information table
*F
3109102
AJU
12/13/2010
Added Ordering Code Definitions.
Updated Package Diagram.
*G
3137613
PRAS
01/13/2011
Added Acronyms and Units of Measure.
Updated datasheet as per template
Updated all footnotes sequentially
*H
3416006
TAVA
10/20/2011
Updated Features.
Updated DC Electrical Characteristics.
Updated Switching Waveforms.
Updated in new template.
Document Number: 38-05477 Rev. *H
Description of Change
Page 14 of 15
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CY7C1062DV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
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© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05477 Rev. *H
Revised October 20, 2011
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All products and company names mentioned in this document may be the trademarks of their respective holders.
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