SPANSION MBM29LV400TC-55PW Flash memory cmos 4m (512k x 8/256k x 16) bit Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20862-8E
FLASH MEMORY
CMOS
4M (512K × 8/256K × 16) BIT
MBM29LV400TC/BC-55/70/90
■ FEATURES
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(1) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
44-pin SOP (Package suffix: PF)
48-pin CSOP (Package suffix: PCV)
48-ball FBGA (Package suffix: PBT)
48-ball SCSP (Package suffix: PW)
• Minimum 100,000 program/erase cycles
• High performance
55 ns maximum access time
• Sector erase architecture
One 8K word, two 4K words, one 16K word, and seven 32K words sectors in word mode
One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
(Continued)
■ PRODUCT LINE UP
Part No.
Power Supply Voltage (V)
MBM29LV400 TC/BC
-55
V
VCC = 3.3 V +0.3
–0.3 V
-70
VCC = 3.0 V
-90
+0.6 V
–0.3 V
Max Address Access Time (ns)
55
70
90
Max CE Access Time (ns)
55
70
90
Max OE Access Time (ns)
30
30
35
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
(Continued)
• Embedded EraseTM* Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection set function by Extended sector Protect command
• Fast Programming Function by Extended Command
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
■ PACKAGES
48-pin plastic TSOP (1)
48-pin plastic TSOP (1)
Marking Side
44-pin plastic SOP
Marking Side
Marking Side
2
(FPT-48P-M19)
(FPT-48P-M20)
(FPT-44P-M16)
48-pin plastic CSOP
48-pin plastic FBGA
48-pin plastic SCSP
(LCC-48P-M03)
(BGA-48P-M11)
(WLP-48P-M02)
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ GENERAL DESCRIPTION
The MBM29LV400TC/BC are a 4M-bit, 3.0 V-only Flash memory organized as 512K bytes of 8 bits each or 256K
words of 16 bits each. The MBM29LV400TC/BC are offered in a 48-pin TSOP(1), 44-pin SOP, 48-pin CSOP,
and 48-ball FBGA packages. These devices are designed to be programmed in-system with the standard system
3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also
be reprogrammed in standard EPROM programmers.
The standard MBM29LV400TC/BC offer access times 70 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The MBM29LV400TC/BC are pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV400TC/BC are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV400TC/BC are erased when shipped from the
factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29LV400TC/BC memories electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
3
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ PIN ASSIGNMENTS
SOP
(Top View)
TSOP(1)
A15
A14
A13
A12
A11
A10
A9
A8
N.C.
N.C.
WE
RESET
N.C.
N.C.
RY/BY
N.C.
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
MBM29LV400TC/MBM29LV400BC
Normal Bend
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
DQ 15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
FPT-48P-M19
A1
A2
A3
A4
A5
A6
A7
A17
N.C.
RY/BY
N.C.
N.C.
RESET
WE
N.C.
N.C.
A8
A9
A10
A11
A12
A13
A14
A15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
MBM29LV400TC/MBM29LV400BC
Reverse Bend
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE
A16
N.C.
1
44
RESET
RY/BY
2
43
WE
A17
3
42
A8
A7
4
41
A9
A6
5
40
A10
A5
6
39
A11
A4
7
38
A12
A3
8
37
A13
A2
9
36
A14
A1
10
35
A15
A0
11
34
A16
CE
12
33
BYTE
VSS
13
32
V SS
OE
14
31
DQ 15/A-1
DQ0
15
30
DQ 7
DQ8
16
29
DQ 14
DQ1
17
28
DQ 6
DQ9
18
27
DQ 13
DQ2
19
26
DQ5
DQ10
20
25
DQ 12
DQ3
21
24
DQ4
DQ11
22
23
VCC
FPT-44P-M16
FPT-48P-M20
(Continued)
4
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
(TOP VIEW)
A1
A2
A3
A4
A5
A6
A7
A17
N.C.
RY/BY
N.C.
N.C.
RESET
WE
N.C.
N.C.
A8
A9
A10
A11
A12
A13
A14
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CSOP-48
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE
A16
G6
H6
LCC-48P-M03
FBGA
(Top View)
Marking side
A6
B6
C6
D6
E6
A13
A12
A14
A15
A16
A5
B5
C5
D5
E5
A9
A8
A10
A11
DQ7 DQ14 DQ13 DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE RESET N.C
N.C
DQ5
DQ12
VCC
DQ4
E4
F3
G3
H3
A3
B3
RY/BY N.C
C3
D3
N.C
N.C
F6
BYTE DQ15/A-1 VSS
F5
DQ2 DQ10
G5
H5
DQ11 DQ3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A1
B1
C1
D1
E1
F1
G1
H1
A3
A4
A2
A1
A0
CE
OE
VSS
BGA-48P-M11
(Continued)
5
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
(Continued)
SCSP
(Top View)
Marking side
A6
B6
C6
D6
E6
A3
A4
A2
A1
A0
CE
G6
OE
H6
VSS
A5
B5
C5
D5
E5
F5
G5
A7
A17
A6
A5
DQ0
DQ8
DQ9 DQ1
A4
B4
G4
RY/BY N.C
A3
B3
H5
C4
D4
E4
F4
N.C
N.C
DQ2
DQ10 DQ11 DQ3
D3
E3
F3
N.C
DQ5 DQ12 VCC
DQ4
H2
C3
WE RESET N.C
B2
C2
D2
E2
A8
A10
A11
DQ7 DQ14 DQ13 DQ6
A1
B1
C1
D1
E1
A12
A14
A15
A16
F1
G2
H3
A2
A13
F2
G3
H4
A9
WLP-48P-M02
6
F6
G1
H1
BYTE DQ15/A-1 VSS
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ PIN DESCRIPTIONS
Pin
Function
A17 to A0, A-1
Address Inputs
DQ15 to DQ0
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RY/BY
Ready/Busy Output
RESET
Hardware Reset Pin/Temporary Sector Unprotection
BYTE
Selects 8-bit or 16-bit mode
N.C.
No Internal Connection
VSS
Device Ground
VCC
Device Power Supply
■ LOGIC SYMBOL
A-1
18
A17 to A0
16 or 8
DQ 15 to DQ 0
CE
OE
WE
RESET
RY/BY
BYTE
7
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ BLOCK DIAGRAM
RY/BY
Buffer
DQ15 to DQ0
RY/BY
VCC
VSS
Erase Voltage
Generator
Input/Output
Buffers
WE
BYTE
RESET
State
Control
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE
STB
Data Latch
OE
STB
Low VCC Detector
A17 to A0
A-1
8
Timer for
Program/Erase
Address
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ DEVICE BUS OPERATIONS
MBM29LV400TC/400BC User Bus Operations Table (BYTE = VIH)
A0
A1
A6
A9
DQ0 to DQ15
Operation
CE OE WE
RESET
L
L
H
L
L
L
VID
Code
H
L
L
H
H
L
L
VID
Code
H
L
L
H
A0
A1
A6
A9
DOUT
H
Standby
H
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
High-Z
H
L
H
L
A0
A1
A6
A9
DIN
H
L
VID
L
H
L
VID
X
H
Verify Sector Protection * *
L
L
H
L
H
L
VID
Code
H
Temporary Sector Unprotection*5
X
X
X
X
X
X
X
X
VID
Reset (Hardware)/Standby
X
X
X
X
X
X
X
High-Z
L
Auto-Select Manufacturer Code *
Auto-Select Device Code *
Read *
1
1
3
Write (Program/Erase)
2,
4
Enable Sector Protection * *
2,
4
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See “■DC CHARACTERISTICS” for voltage levels.
*1: Manufacturer and device codes are accessed via a command register write sequence. See “MBM29LV400TC/
400BC Standard Command Definitions Table” in ■DEVICE BUS OPERATIONS.
*2: Refer to “7. Sector Protection” in ■FUNCTIONAL DESCRIPTION.
*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4: VCC = 3.3 V ± 10%
*5: Also used for the extended sector protection.
Operation
MBM29LV400TC/400BC User Bus Operations (BYTE = VIL)
15/
OE WE DQ
A0
A1
A6
A9
CE
A-1
DQ0 to DQ7 RESET
Auto-Select Manufacturer Code *1
L
L
H
L
L
L
L
VID
Code
H
Auto-Select Device Code *1
L
L
H
L
H
L
L
VID
Code
H
Read *3
L
L
H
A-1
A0
A1
A6
A9
DOUT
H
Standby
H
X
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
X
High-Z
H
Write (Program/Erase)
L
H
L
A-1
A0
A1
A6
A9
DIN
H
Enable Sector Protection *2, *4
L
VID
L
L
H
L
VID
X
H
L
L
H
L
L
H
L
VID
Code
H
X
X
X
X
X
X
X
X
X
VID
X
X
X
X
X
X
X
X
High-Z
L
Verify Sector Protection *2, *4
Temporary Sector Unprotection *
5
Reset (Hardware)/Standby
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See “■DC CHARACTERISTICS” for voltage levels.
*1: Manufacturer and device codes are accessed via a command register write sequence. See “MBM29LV400TC/
400BC Standard Command Definitions Table” in ■DEVICE BUS OPERATIONS.
*2: Refer to “7. Sector Protection” in ■FUNCTIONAL DESCRIPTION.
*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4: VCC = 3.3 V ± 10%
*5: Also used for the extended sector protection.
9
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
Command
Sequence
Word
Read/Reset
Byte
Word
Read/Reset
Byte
Word
Autoselect
Byte
Word
Program
Byte
Word
Chip Erase
Byte
Word
Sector Erase
Byte
Bus
Write
Cycles
Req’d
1
3
3
4
6
6
MBM29LV400TC/400BC Standard Command Definitions
First Bus Second Bus Third Bus Fourth Bus
Fifth Bus
Sixth Bus
Write Cycle Write Cycle Write Cycle Read/Write
Write Cycle Write Cycle
Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
XXXh
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
F0h
AAh
AAh
AAh
AAh
AAh
—
2AAh
555h
2AAh
555h
2AAh
555h
2AAh
555h
2AAh
555h
—
55h
55h
55h
55h
55h
—
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
—
—
—
—
—
—
—
F0h
RA
RD
—
—
—
—
90h
—
—
—
—
—
—
A0h
PA
PD
—
—
—
—
80h
80h
555h
AAAh
555h
AAAh
AAh
AAh
2AAh
555h
2AAh
555h
55h
55h
555h
AAAh
SA
Sector Erase Suspend
Erase can be suspended during sector erase with Addr. (“H” or “L”). Data (B0h)
Sector Erase Resume
Erase can be resumed after suspend with Addr. (“H” or “L”). Data (30h)
10h
30h
Notes: • Address bits A11 to A17 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA)
• Bus operations are defined in “MBM29LV400TC/400BC User Bus Operations Tables (BYTE = VIH and
BYTE = VIH)” in ■DEVICE BUS OPERATIONS.
• RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
• RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
• The system should generate the following address patterns:
Word Mode: 555h or 2AAh to addresses A0 to A10
Byte Mode: AAAh or 555h to addresses A–1 and A0 to A10
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• The command combinations not described in “MBM29LV400TC/400BC Standard Command Definitions
Table” and “MBM29LV400TC/BC Extended Command Definitions Table” in ■DEVICE BUS
OPERATIONS are illegal.
10
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
MBM29LV400TC/BC Extended Command Definitions
Bus
First Bus
Second Bus
Third Bus
Write
Write Cycle
Write Cycle
Write Cycle
Cycles
Addr
Data
Addr
Data
Addr
Data
Req'd
Command
Sequence
Word
Set to
Fast Mode
Byte
Fast Program *1
Reset from Fast
Mode *1
Extended Sector
Protect *2
Word
Byte
555h
3
AAAh
XXXh
2
PA
XXXh
AAAh
Addr
Data
20h
—
—
PD
—
—
—
—
F0h *3
—
—
—
—
XXXh
2
90h
Byte
555h
55h
555h
A0h
XXXh
Word
2AAh
AAh
Fourth Bus
Read Cycle
XXXh
XXXh
Word
4
XXXh
60h
SPA
60h
SPA
40h
SPA
SD
Byte
SPA : Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).
SD : Sector protection verify data. Output 01h at protected sector addresses and output 00h at unprotected
sector addresses.
*1: This command is valid while Fast Mode.
*2: This command is valid while RESET= VID.
*3: This data “00h” is also acceptable.
MBM29LV400TC/400BC Sector Protection Verify Autoselect Codes
A6
A1
A0
Type
A12 to A17
A-1*1
Manufacture’s Code
MBM29LV400TC
Device Code
MBM29LV400BC
X
VIL
VIL
VIL
X
VIL
VIL
VIH
X
VIL
VIL
VIH
Sector
Addresses
VIL
VIH
VIL
Byte
Word
Byte
Word
Sector Protection
Code (HEX)
VIL
04h
VIL
B9h
X
22B9h
VIL
BAh
X
22BAh
VIL
01h*2
*1: A-1 is for Byte mode. In byte mode, DQ8 to DQ14 become “High-Z” and DQ15 becomes the lower address A-1.
*2: Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.
Extended Autoselect Code Table
Type
Manufacturer’s Code
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
04h
A-1/0
MBM29 (B)* B9h A-1
LV400TC (W) 22B9h 0
Device
Code
MBM29 (B)* BAh A-1
LV400BC (W) 22BAh 0
Sector Protection
(B): Byte mode
(W): Word mode
HI-Z : High-Z
01h
A-1/0
0
0
0
0
0
0
0
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
1
0
0
0
1
0
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
0
0
0
0
1
0
0
1
0
1
1
1
0
0
1
1
0
1
1
1
0
0
1
1
0
1
1
1
0
1
0
0
1
0
0
0
1
0
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
* : At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address.
11
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes.
• Individual-sector, multiple-sector, or bulk-erase capability.
• Individual or multiple-sector protection is user definable.
(×8)
(×16)
7FFFFh
3FFFFh
16K byte
(×16)
7FFFFh
3FFFFh
6FFFFh
37FFFh
5FFFFh
2FFFFh
4FFFFh
27FFFh
3FFFFh
1FFFFh
2FFFFh
17FFFh
1FFFFh
0FFFFh
0FFFFh
07FFFh
07FFFh
03FFFh
05FFFh
02FFFh
03FFFh
01FFFh
00000h
00000h
64K byte
7BFFFh
3DFFFh
8K byte
64K byte
79FFFh
3CFFFh
8K byte
64K byte
77FFFh
3BFFFh
32K byte
64K byte
6FFFFh
37FFFh
64K byte
64K byte
5FFFFh
2FFFFh
64K byte
64K byte
4FFFFh
27FFFh
64K byte
64K byte
3FFFFh
1FFFFh
64K byte
32K byte
2FFFFh
17FFFh
64K byte
8K byte
1FFFFh
0FFFFh
64K byte
8K byte
0FFFFh
07FFFh
64K byte
16K byte
00000h
00000h
MBM29LV400TC Sector Architecture
12
(×8)
MBM29LV400BC Sector Architecture
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
Sector Address Tables (MBM29LV400TC)
Sector
Address
A17
A16
A15
A14
A13
A12
Address Range (×8)
Address Range (×16)
SA0
0
0
0
X
X
X
00000h to 0FFFFh
00000h to 07FFFh
SA1
0
0
1
X
X
X
10000h to 1FFFFh
08000h to 0FFFFh
SA2
0
1
0
X
X
X
20000h to 2FFFFh
10000h to 17FFFh
SA3
0
1
1
X
X
X
30000h to 3FFFFh
18000h to 1FFFFh
SA4
1
0
0
X
X
X
40000h to 4FFFFh
20000h to 27FFFh
SA5
1
0
1
X
X
X
50000h to 5FFFFh
28000h to 2FFFFh
SA6
1
1
0
X
X
X
60000h to 6FFFFh
30000h to 37FFFh
SA7
1
1
1
0
X
X
70000h to 77FFFh
38000h to 3BFFFh
SA8
1
1
1
1
0
0
78000h to 79FFFh
3C000h to 3CFFFh
SA9
1
1
1
1
0
1
7A000h to 7BFFFh
3D000h to 3DFFFh
SA10
1
1
1
1
1
X
7C000h to 7FFFFh
3E000h to 3FFFFh
Sector Address Tables (MBM29LV400BC)
Sector
Address
A17
A16
A15
A14
A13
A12
Address Range (×8)
Address Range (×16)
SA0
0
0
0
0
0
X
00000h to 03FFFh
00000h to 01FFFh
SA1
0
0
0
0
1
0
04000h to 05FFFh
02000h to 02FFFh
SA2
0
0
0
0
1
1
06000h to 07FFFh
03000h to 03FFFh
SA3
0
0
0
1
X
X
08000h to 0FFFFh
04000h to 07FFFh
SA4
0
0
1
X
X
X
10000h to 1FFFFh
08000h to 0FFFFh
SA5
0
1
0
X
X
X
20000h to 2FFFFh
10000h to 17FFFh
SA6
0
1
1
X
X
X
30000h to 3FFFFh
18000h to 1FFFFh
SA7
1
0
0
X
X
X
40000h to 4FFFFh
20000h to 27FFFh
SA8
1
0
1
X
X
X
50000h to 5FFFFh
28000h to 2FFFFh
SA9
1
1
0
X
X
X
60000h to 6FFFFh
30000h to 37FFFh
SA10
1
1
1
X
X
X
70000h to 7FFFFh
38000h to 3FFFFh
13
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ FUNCTIONAL DESCRIPTION
1. Read Mode
The MBM29LV400TC/BC have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or change CE pin from “H” or “L”
2. Standby Mode
There are two ways to implement the standby mode on the MBM29LV400TC/BC devices, one using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA. The device can be read with standard access time
(tCE) from either of these standby modes. During Embedded Algorithm operation, VCC active current (ICC2) is
required even CE = “H”.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V
(CE = “H” or “L”). Under this condition the current is consumed is less than 5 µA. Once the RESET pin is taken
high, the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
3. Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29LV400TC/400BC data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To activate this mode, MBM29LV400TC/400BC automatically switch themselves to low power mode when
MBM29LV400TC/400BC addresses remain stably during access fine of 150 ns. It is not necessary to control
CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level).
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29LV400TC/400BC read-out the data for changed addresses.
4. Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins
to be in a high impedance state.
5. Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, A6, and A-1. (See “MBM29LV400TC/400BC Sector Protection Verify
Autoselect Codes Table” in ■DEVICE BUS OPERATIONS.)
14
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29LV400TC/BC are erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in “MBM29LV400TC/400BC Standard Command Definitions Table” (■DEVICE
BUS OPERATIONS). (Refer to “2. Autoselect Command” in ■COMMAND DEFINITIONS.)
Byte 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and (A0 = VIH) represents the device identifier
code (MBM29LV400TC = B9h and MBM29LV400BC = BAh for ×8 mode; MBM29LV400TC = 22B9h and
MBM29LV400BC = 22BAh for ×16 mode). These two bytes/words are given in “MBM29LV400TC/400BC Sector
Protection Verify Autoselect Codes Table” and “Extended Autoselect Code Table” (■DEVICE BUS
OPERATIONS). All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity
bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See
“MBM29LV400TC/400BC Sector Protection Verify Autoselect Codes Table” and “Extended Autoselect Code
Table” in ■DEVICE BUS OPERATIONS.)
6. Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
7. Sector Protection
The MBM29LV400TC/BC feature hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 10). The sector protection feature is enabled using programming
equipment at the user’s site. The devices are shipped with all sectors unprotected. Alternatively, Fujitsu may
program and protect sectors in the factory prior to shiping the device.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V), CE = VIL, and A6 = VIL. The sector addresses ( A17, A16, A15, A14, A13, and A12) should be set to the
sector to be protected. “Sector Address Tables (MBM29LV400TC/BC)” in ■FLEXIBLE SECTOR-ERASE
ARCHITECTURE define the sector address for each of the eleven (11) individual sectors. Programming of the
protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same.
Sector addresses must be held constant during the WE pulse. See “13. AC Waveforms for Sector Protection
Timing Diagram” in ■TIMING DIAGRAM and “5. Sector Protection Algorithm” in ■FLOW CHART for sector
protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses ( A17, A16, A15, A14, A13, and A12) while (A6,
A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the
devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6
are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
A-1 requires to apply to VIL on byte mode.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02h, where the higher order addresses (A17, A16, A15, A14, A13, and
A12) are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See “MBM29LV400TC/
400BC Sector Protection Verify Autoselect Codes Table” and “Extended Autoselect Code Table” in ■DEVICE
BUS OPERATIONS for Autoselect codes.
15
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
8. Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29LV400TC/BC devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected
again. See “14. Temporary Sector Unprotection Timing Diagram” in ■TIMING DIAGRAM and “6. Temporary
Sector Unprotection Algorithm” in ■FLOW CHART.
9. RESET
Hardware Reset
The MBM29LV400TC/BC devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See “9. RESET/RY/BY Timing
Diagram” in ■TIMING DIAGRAM for the timing diagram. Refer to “8. Temporary Sector Unprotection” for
additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
16
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the
read mode. “MBM29LV400TC/400BC Standard Command Definitions Table” in ■DEVICE BUS OPERATIONS
defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h)
commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands
are functionally equivalent, resetting the device to the read mode. Please note that commands are always written
at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.
1. Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset
operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The devices remain enabled for reads until the command
register contents are altered.
The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
2. Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read
cycle from address XX01h for ×16(XX02h for ×8) returns the device code (MBM29LV400TC = B9h and
MBM29LV400BC = BAh for ×8 mode; MBM29LV400TC = 22B9h and MBM29LV400BC = 22BAh for ×16 mode).
(See “MBM29LV400TC/400BC Sector Protection Verify Autoselect Codes Table” and “Extended Autoselect Code
Table” in ■DEVICE BUS OPERATIONS.) All manufacturer and device codes will exhibit odd parity with DQ7
defined as the parity
bit. Sector state (protection or unprotection) will be informed by address XX02h for ×16 (XX04h for ×8).
Scanning the sector addresses (A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical
“1” at device output DQ0 for a protected sector. The programming verification should be perform margin mode
on the protected sector. (See “MBM29LV400TC/400BC User Bus Operations Tables (BYTE = VIH and BYTE =
VIH)” in ■DEVICE BUS OPERATIONS.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
3. Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
17
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware
Sequence Flags Table” in ■COMMAND DEFINITIONS.) Therefore, the devices require that a valid address to
the devices be supplied by the system at this particular instance of time. Hence, Data Polling must be performed
at the memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“1. Embedded ProgramTM Algorithm” in ■FLOW CHART illustrates the Embedded ProgramTM Algorithm using
typical command strings and bus operations.
4. Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (See “8. Write Operation Status”.) at which time the device returns to read the mode.
Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
“2. Embedded EraseTM Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
5. Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data=30h) is latched on the rising edge of WE. After time-out of 50 µs from the rising edge of the last sector
erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29LV400TC/400BC
Standard Command Definitions Table” (■DEVICE BUS OPERATIONS). This sequence is followed with writes
of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between
writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is
recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts
can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of
the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs
within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window
is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend
during this time-out period will reset the devices to the read mode, ignoring the previous command string.
Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase
on those sectors and allow them to complete. (Refer to “8. Write Operation Status” for Sector Erase Timer
operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 10).
18
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (See “8. Write Operation Status”.) at
which time the devices return to the read mode. Data polling must be performed at an address within any of
the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time
(Preprogramming)] × Number of Sector Erase
“2. Embedded EraseTM Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
6. Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.
Writing the Erase Resume command resumes the erase operation. The addresses are DON’T CARES when
writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/
BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of
the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further
writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or by the Toggle Bit I
(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address
while DQ6 can be read from any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
7. Extended Command
(1) Fast Mode
MBM29LV400TC/BC has Fast Mode function. This mode dispenses with the initial two unclock cycles
required in the standard program command sequence by writing Fast Mode command into the command
19
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in
standard program command. (Do not write erase command in this mode.) The read operation is also executed
after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command
register. (Refer to “8. Embedded ProgramTM Algorithm for Fast Mode” in ■FLOW CHART Extended
algorithm.) The VCC active current is required even CE = VIH during Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to
“8. Embedded ProgramTM Algorithm for Fast Mode” in ■FLOW CHART Extended algorithm.)
(3) Extended Sector Protection
In addition to normal sector protection, the MBM29LV400TC/BC has Extended Sector Protection as extended
function. This function enable to protect sector by forcing VID on RESET pin and write a commnad sequence.
Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only
RESET pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET
pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command
register. Then, the sector addresses pins (A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should
be set to the sector to be protected (recommend to set VIL for the other addresses pins), and write extended
sector protect command (60h). A sector is typically protected in 150 µs. To verify programming of the
protection circuitry, the sector addresses pins (A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should
be set and write a command (40h). Following the command write, a logical “1” at device output DQ0 will
produce for protected sector in the read operation. If the output data is logical “0”, please repeat to write
extended sector protect command (60h) again. To terminate the operation, it is necessary to set RESET pin
to VIH.
8. Write Operation Status
Hardware Sequence Flags
DQ7
DQ6
DQ5
DQ3
DQ2
DQ7
Toggle
0
0
1
0
Toggle
0
1
Toggle*1
1
1
0
0
Toggle
Data
Data
Data
Data
Data
DQ7
Toggle
0
0
1 *2
Embedded Program Algorithm
DQ7
Toggle
1
0
1
Exceeded Embedded Erase Algorithm
Time
Erase
Limits
Erase Suspend Program
Suspende
(Non-Erase Suspended Sector)
d Mode
0
Toggle
1
1
N/A
DQ7
Toggle
1
0
N/A
Status
Embedded Program Algorithm
Embedded Erase Algorithm
In
Progress
Erase Suspend Read
(Erase Suspended Sector)
Erase
Erase Suspend Read
Suspende
(Non-Erase Suspended Sector)
d Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
*1:Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle.
*2: Reading from non-erase suspend sector address indicates logic “1” at the DQ2 bit.
20
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
9. DQ7
Data Polling
The MBM29LV400TC/BC devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in “3. Data Polling Algorithm” (■FLOW CHART).
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29LV400TC/BC data pins (DQ7) may change asynchronously while the output
enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant
of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the
DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm
operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0
to DQ7 will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See “Hardware Sequence Flags Table” in ■COMMAND DEFINITIONS.)
See “6. AC Waveforms for Data Polling during Embedded Algorithm Operations” in ■TIMING DIAGRAM for the
Data Polling timing specifications and diagrams.
10. DQ6
Toggle Bit I
The MBM29LV400TC/BC also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
See “7. AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” in ■TIMING DIAGRAM for the
Toggle Bit I timing specifications and diagrams.
21
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
11. DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in “MBM29LV400TC/400BC User
Bus Operations Tables (BYTE = VIH and BYTE = VIH)” (■DEVICE BUS OPERATIONS).
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the
DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
12. DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on
the second status check, the command may not have been accepted.
See “Hardware Sequence Flags Table” in ■COMMAND DEFINITIONS.
13. DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also “Hardware Sequence Flags Table” in ■COMMAND DEFINITIONS
and “15. DQ2 vs. DQ6” in ■TIMING DIAGRAM.
22
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
14. Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle
bit after the first read. After the second read, the system would compare the new value of toggle bit with the first.
If the toggle bit is not toggling, this indicates that the device has completed the program or erase operation. The
system can read array data on DQ7 to DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see “11. DQ5”) . If it is the system should then determine
again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high.
If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If
it is still toggling, the device did not complete the operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 though successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the
status of operation. (See “4. Toggle Bit Algorithm” in ■ FLOW CHART.)
Toggle Bit Status Table
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Toggle*1
Erase-Suspend Read
(Erase-Suspend Sector)
1
1
Toggle
Erase-Suspend Program
DQ7
Toggle
1*2
Mode
Program
*1 : Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle.
*2 : Reading from non-erase suspend sector address indicates logic “1” at the DQ2 bit.
15. RY/BY
Ready/Busy
The MBM29LV400TC/BC provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29LV400TC/BC are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. Refer to “8. RY/BY Timing Diagram during Program/Erase Operations”
and “9. RESET/RY/BY Timing Diagram” in ■TIMING DIAGRAM for a detailed timing diagram. The RY/BY pin
is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to VCC; multiples of devices may
be connected to the host system via more than one RY/BY pin in parallel.
23
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
16. Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV400TC/BC devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0
to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer
to “10. Timing Diagram for Word Mode Configuration” and “11. Timing Diagram for Byte Mode Configuration”
and “12. BYTE Timing Diagram for Write Operations” in ■TIMING DIAGRAM for the timing diagram.
17. Data Protection
The MBM29LV400TC/BC are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
18. Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
19. Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
20. Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
21. Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
22. Sector Protection
Device user is able to protect each sector individually to store and protect data. Protection circuit voids both
program and erase commands that are addressed to protected sectors.
Any commands to program or erase addressed to protected sector are ignored (see “Sector Protection” in
■ FUNCTIONAL DESCRIPTION) .
24
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Storage Temperature
Ambient Temperature with Power Applied
Voltage with Respect to Ground All pins
except A9, OE, RESET *1,*2
A9, OE and RESET *1,*3
1
Power Supply Voltage *
Rating
Unit
Min
Max
Tstg
–55
+125
°C
TA
–40
+85
°C
VIN, VOUT
–0.5
VCC+0.5
V
VIN
–2.0
+13.0
V
VCC
–0.5
+5.5
V
*1: Voltage is defined on the basis of VSS = GND = 0 V.
*2: Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns.
*3: Minimum DC input voltage on A9, OE and RESET pins is –0.5 V. During voltage transitions, A9, OE and RESET
pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage
(VIN – VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which
may overshoot to +14.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Ambient Temperature
TA
Power Supply Voltage*
VCC
Part Number
Value
Unit
Min
Max
MBM29LV400TC/BC-55
–20
+70
°C
MBM29LV400TC/BC-70/-90
–40
+85
°C
MBM29LV400TC/BC-55
+3.0
MBM29LV400TC/BC-70/-90
+2.7
+3.6
V
* : Voltage is defined on the basis of VSS = GND = 0 V.
Note: Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
25
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ MAXIMUM OVERSHOOT/ MAXIMUM UNDERSHOOT
20 ns
20 ns
+0.6 V
−0.5 V
−2.0 V
20 ns
Figure 1
Maximum Undershoot Waveform
20 ns
VCC +2.0 V
VCC +0.5 V
+2.0 V
20 ns
Figure 2
20 ns
Maximum Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
VCC +0.5 V
20 ns
20 ns
Note: This waveform is applied for A9, OE, and RESET.
Figure 3
26
Maximum Overshoot Waveform 2
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Leakage Current
ILI
VIN = VSS to VCC, VCC = VCC Max
–1.0

+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCC, VCC = VCC Max
–1.0

+1.0
µA
A9, OE, RESET Inputs Leakage
Current
ILIT
VCC = VCC Max
A9, OE, RESET = 12.5 V
—

35
µA

22

25

12

15
CE = VIL, OE = VIH,
f=10 MHz
1
VCC Active Current *
ICC1
CE = VIL, OE = VIH,
f=5 MHz
Byte
Word
Byte
Word
—
—
mA
mA
VCC Active Current *2
ICC2
CE = VIL, OE = VIH
—

35
mA
VCC Current (Standby)
ICC3
VCC = VCC Max, CE = VCC ± 0.3 V,
RESET = VCC ± 0.3 V
—
1
5
µA
VCC Current (Standby, Reset)
ICC4
VCC = VCC Max,
RESET = VSS ± 0.3 V
—
1
5
µA
VCC Current
(Automatic Sleep Mode) *3
ICC5
VCC = VCC Max, CE = VSS ± 0.3 V,
RESET = VCC ± 0.3 V
VIN = VCC ± 0.3 V or VSS ± 0.3 V
—
1
5
µA
Input Low Voltage
VIL
—
–0.5

0.6
V
Input High Voltage
VIH
—
2.0

VCC+0.3
V
Voltage for Autoselect and Sector
Protection (A9, OE, RESET) *4, *5
VID
—
11.5
12
12.5
V
Output Low Voltage
VOL
IOL = 4.0 mA, VCC = VCC Min
—

0.45
V
VOH1
IOH = –2.0 mA, VCC = VCC Min
2.4

—
V
VOH2
IOH = –100 µA
VCC–0.4

—
V
2.3
2.4
2.5
V
Output High Voltage
Low VCC Lock-Out Voltage
VLKO
—
*1: The ICC current listed includes both the DC operating current and the frequency dependent component (at 10
MHz).
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*4: This timing is only for Sector Protection operation and Autoselect mode.
*5: (VID – VCC) do not exceed 9 V.
27
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Symbol
Parameter
Value *
Test
Setup
-55
-70
-90
Unit
Min Max Min Max Min Max
JEDEC Standard
Read Cycle Time
tAVAV
tRC
—
55

70

90

ns
Address to Output Delay
tAVQV
tACC
CE = VIL
OE = VIL

55

70

90
ns
Chip Enable to Output Delay
tELQV
tCE
OE = VIL

55

70

90
ns
Output Enable to Output Delay
tGLQV
tOE
—

30

30

35
ns
Chip Enable to Output High-Z
tEHQZ
tDF
—

25

25

30
ns
Output Enable to Output High-Z
tGHQZ
tDF
—

25

25

30
ns
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
tAXQX
tOH
—
0

0

0

ns
RESET Pin Low to Read Mode
—
tREADY
—

20

20

20
µs
CE to BYTE Switching Low or High
—
tELFL,
tELFH
—

5

5

5
ns
*: Test Conditions:
Output Load: 1 TTL gate and 30 pF (MBM29LV400TC/BC-55/70)
1 TTL gate and 100 pF (MBM29LV400TC/BC-90)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or 3.0 V
Timing measurement reference level
Input: 1.5 V
Output:1.5 V
3.3 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Notes: CL = 30 pF including jig capacitance (MBM29LV400TC/BC-55/70)
CL = 100 pF including jig capacitance (MBM29LV400TC/BC-90)
Figure 4
28
Test Conditions
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
• Write/Erase/Program Operations
Parameter
Symbol
-55
-70
-90
JEDEC Standard Min Typ Max Min Typ Max Min Typ Max
Unit
Write Cycle Time
tAVAV
tWC
55


70


90


ns
Address Setup Time
tAVWL
tAS
0


0


0


ns
Address Hold Time
tWLAX
tAH
45


45


45


ns
Data Setup Time
tDVWH
tDS
30


35


45


ns
Data Hold Time
tWHDX
tDH
0


0


0


ns
—
tOES
0


0


0


ns
—
tOEH
0


0


0


ns
10


10


10


ns
Read Recover Time Before Write
tGHWL
tGHWL
0


0


0


ns
Read Recover Time Before Write
tGHEL
tGHEL
0


0


0


ns
CE Setup Time
tELWL
tCS
0


0


0


ns
WE Setup Time
tWLEL
tWS
0


0


0


ns
CE Hold Time
tWHEH
tCH
0


0


0


ns
WE Hold Time
tEHWH
tWH
0


0


0


ns
Write Pulse Width
tWLWH
tWP
30


35


45


ns
CE Pulse Width
tELEH
tCP
30


35


45


ns
Write Pulse Width High
tWHWL
tWPH
25


25


25


ns
CE Pulse Width High
tEHEL
tCPH
25


25


25


ns
tWHWH1
tWHWH1

8


8


8

µs

16


16


16

µs
tWHWH2
tWHWH2

1


1


1

s
—
tVCS
50


50


50


µs
—
tVIDR
500 
 500 
 500 

ns
—
tVLHT




µs
—
tWPP
 100 
 100 

µs
OE Setup Time to WE Active *2
—
tOESP
4


4


4


µs
CE Setup Time to WE Active *2
—
tCSP
4


4


4


µs
Recover Time From RY/BY
—
tRB
0


0


0


ns
RESET Pulse Width
—
tRP
500 
 500 
 500 

ns
RESET Hold Time Before Read
—
tRH
200 
 200 
 200 

ns
BYTE Switching Low to Output High-Z
—
tFLQZ


25


25


30
ns
BYTE Switching High to Output Active
—
tFHQV


55


70


90
ns
Program/Erase Valid to RY/BY Delay
—
tBUSY


90


90


90
ns
Delay Time from Embedded Output Enable
—
tEOE


55


70


90
ns
Output Enable Setup Time
Output Enable
Hold Time
Programming
Operation
Read
Toggle and Data Polling
Byte
Word
Sector Erase Operation *1
VCC Setup Time
Rise Time to VID *2
Voltage Transition Time *
Write Pulse Width *
2
2
4

100 
4

4
*1: This does not include the preprogramming time.
*2: This timing is for Sector Protection operation.
29
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Min
Typ
Max
Sector Erase Time
—
1
10
s
Word Programming Time
—
16
360
µs
Byte Programming Time
—
8
300
µs
Chip Programming Time
—
4.2
12.5
s
100,000
—
—
cycle
Program/Erase Cycle
Comments
Excludes programming time
prior to erasure
Excludes system-level
overhead
Excludes system-level
overhead
—
■ TSOP(1) PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
Typ
Max
Unit
7.5
9
pF
8
10
pF
9.5
12.5
pF
Typ
Max
Unit
7.5
9
pF
8
10
pF
9.5
12.5
pF
Typ
Max
Unit
7.5
9
pF
8
10
pF
9.5
12.5
pF
Notes: • Test conditions TA = + 25°C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
■ SOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
Notes: • Test conditions TA = + 25°C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
■ CSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
Notes: • Test conditions TA = + 25°C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
30
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ FBGA PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
Typ
Max
Unit
7.5
9
pF
8
10
pF
9.5
12.5
pF
Typ
Max
Unit
7.5
9
pF
8
10
pF
9.5
12.5
pF
Notes: • Test conditions TA = + 25°C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
■ SCSP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
Notes: • Test conditions TA = + 25°C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
31
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ TIMING DIAGRAM
• Key to Timing Diagram
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
“H” or “L”
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
“Off” State
1. AC Waveforms for Read Operations
tRC
Address
Address Stable
tACC
CE
tOE
tDF
OE
tOEH
WE
tOH
tCE
Outputs
32
High-Z
Output Valid
High-Z
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
2. AC Waveforms for Hardware Reset/Read Operations
tRC
Address
Address Stable
tACC
tRH
RESET
tOH
High-Z
Outputs
Output Valid
3. AC Waveforms for Alternate WE Controlled Program Operations
Data Polling
3rd Bus Cycle
Address
555h
tWC
PA
tAS
PA
tRC
tAH
CE
tCH
tCS
tCE
OE
tGHWL
tWP
tWPH
tOE
tWHWH1
WE
tOH
tDF
tDS
tDH
Data
Notes: •
•
•
•
•
•
A0h
PD
DQ7
DOUT
DOUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the ×16 mode. The addresses differ from ×8 mode.
33
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
4. AC Waveforms for Alternate CE Controlled Program Operations
3rd Bus Cycle
Address
Data Polling
PA
555h
tWC
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CE
tDS
tDH
Data
Notes: •
•
•
•
•
•
34
A0h
PD
DQ7
DOUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the ×16 mode. The addresses differ from ×8 mode.
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
5. AC Waveforms Chip/Sector Erase Operations
Address
2AAh
555h
tWC
tAS
555h
555h
2AAh
SA*
tAH
CE
tCS
tCH
OE
tGHWL
tWP
tWPH
WE
tDS
AAh
Data
10h for Chip Erase
tDH
55h
80h
AAh
55h
10h/
30h
tVCS
VCC
* : SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAh (Byte)
for Chip Erase.
Note : These waveforms are for the ×16 mode. The addresses differ from ×8 mode.
35
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
6. AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tCH
tOE
tDF
OE
tOEH
WE
tCE
*
DQ7
Data
High-Z
DQ7 =
Valid Data
DQ7
tWHWH1 or 2
DQ0 to DQ6
Data
DQ0 to DQ6 = Output Flag
High-Z
DQ0 to DQ6
Valid Data
tEOE
tBUSY
RY/BY
*: DQ7 = Valid Data (The device has completed the Embedded operation).
7. AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
tDH
DQ6
Data
tBUSY
*
DQ6 = Toggle
DQ6 =
Stop Toggling
DQ6 = Toggle
tOE
RY/BY
*: DQ6 stops toggling (The device has completed the Embedded operation).
36
Valid
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
8. RY/BY Timing Diagram during Program/Erase Operations
CE
Rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
9. RESET/RY/BY Timing Diagram
WE
RESET
tRP
tRB
RY/BY
tREADY
10. Timing Diagram for Word Mode Configuration
CE
tCE
BYTE
Data Output
(DQ7 to DQ0)
DQ14 to DQ0
Data Output
(DQ14 to DQ0)
tELFH
tFHQV
DQ15 /A-1
A-1
DQ15
37
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
11. Timing Diagram for Byte Mode Configuration
CE
BYTE
tELFL
DQ14 to DQ0
Data Output
(DQ14 to DQ0)
Data Output
(DQ7 to DQ0)
tACC
DQ15 /A-1
DQ15
A-1
tFLQZ
12. BYTE Timing Diagram for Write Operations
Falling edge of the last write signal
CE or WE
Input
Valid
BYTE
tAS
38
tAH
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
13. AC Waveforms for Sector Protection Timing Diagram
A17, A16, A15
A14, A13, A12
SPAX
SPAY
A0
A1
A6
VID
VIH
A9
tVLHT
VID
VIH
OE
tVLHT
tVLHT
tVLHT
tWPP
WE
tOESP
tCSP
CE
Data
01h
tVCS
tOE
VCC
SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected
Note: A-1 is VIL on byte mode.
39
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
14. Temporary Sector Unprotection Timing Diagram
VCC
tVIDR
tVLHT
tVCS
VID
VIH
RESET
CE
WE
tVLHT
tVLHT
Program or Erase Command Sequence
RY/BY
Unprotection Period
15. DQ2 vs. DQ6
Enter
Embedded
Erasing
WE
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
DQ6
DQ2*
Toggle
DQ2 and DQ6
with OE or CE
* : DQ2 is read from the erase-suspended sector.
40
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
16. Extended Sector Protection Timing Diagram
VCC
tVCS
RESET
tVLHT
tVIDR
tWC
Address
tWC
SPAX
SPAX
SPAY
A0
A1
A6
CE
OE
TIME-OUT
tWP
WE
Data
60h
60h
40h
01h
60h
tOE
SPAX: Sector Address to be protected
SPAY : Next Sector Address to be protected
TIME-OUT : Time-Out window = 150 µs (Min)
41
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ FLOW CHART
1. Embedded ProgramTM Algorithm
EMBEDDED ALGORITHM
Start
Write Program Command
Sequence
(See below)
Data Polling
No
Verify Data
?
Embedded
Program
Algorithm
in progress
Yes
Increment Address
No
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
Notes : • The sequence is applied for × 16 mode.
• The addresses differ from × 8 mode.
42
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
2. Embedded EraseTM Algorithm
EMBEDDED ALGORITHM
Start
Write Erase Command
Sequence
(See below)
Data Polling
No
Data = FFh
?
Embedded
Erase
Algorithm
in Progress
Yes
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/10h
Sector Address/30h
Sector Address/30h
Additional sector
erase commands
are optional.
Sector Address/30h
Notes : • The sequence is applied for × 16 mode.
• The addresses differ from × 8 mode.
43
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
3. Data Polling Algorithm
Start
Read Byte
(DQ7 to DQ0)
Addr. = VA
DQ7 = Data?
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during
sector erase or multiple sector
erases operation
= Any of the sector addresses within
the sector not being protected
during chip erase operation
Yes
No
No
DQ5 = 1?
Yes
Read Byte
(DQ7 to DQ0)
Addr. = VA
DQ7 = Data?
*
Yes
No
Fail
Pass
* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
44
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
4. Toggle Bit Algorithm
Start
Read (DQ7 to DQ0)
Addr. = "H" or "L"
*1
Read (DQ7 to DQ0)
Addr. = "H" or "L"
DQ6 = Toggle
?
No
Yes
No
DQ5 = 1?
Yes
Read DQ7 to DQ0
Twice
Addr. = "H" or "L"
DQ6 = Toggle
?
*1, *2
No
Yes
Program/Erase
Operation Not
Complete. Write
Reset Command
Program/Erase
Operation
Complete
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1” .
45
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
5. Sector Protection Algorithm
Start
Setup Sector Addr.
(A17, A16, A15, A14, A13, A12)
PLSCNT = 1
OE = VID, A9 = VID,
CE = VIL, RESET = VIH
A6 = A0 = VIL, A1 = VIH
Activate WE Pulse
Time out 100 µs
Increment PLSCNT
WE = VIH, CE = OE = VIL
(A9 should remain VID)
(
Read from Sector
Addr. = SPA, A1 = VIH, *
A6 = A0 = VIL
)
No
No
PLSCNT = 25?
Yes
Remove VID from A9
Write Reset Command
Data = 01h?
Yes
Yes
Protect Another Sector?
No
Device Failed
Remove VID from A9
Write Reset Command
Sector Protection
Completed
*: A-1 is V IL on byte mode.
46
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
6. Temporary Sector Unprotection Algorithm
Start
RESET = VID *1
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed *2
*1: All protected sectors are unprotected.
*2: All previously protected sectors are protected once again.
47
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
7. Extended Sector Protection Algorithm
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector
Unprotection Mode
No
Extended Sector
Protection Entry?
Yes
To Setup Sector Protection
Write XXXh/60h
PLSCNT = 1
To Protect Sector
Write SPA/60h to Sector Address
(A6 = A0 = VIL, A1 = VIH)
Time Out 150 µs
Increment PLSCNT
To Verify Sector Protection
Setup Next Sector Address
Write SPA/40h to Sector Address
(A6 = A0 = VIL, A1 = VIH)
Read from Sector Address
(Addr. = SPA, A1 = VIH,
A6 = A0 = VIL)
No
No
PLSCNT = 25?
Yes
Remove VID from RESET
Write Reset Command
Device Failed
Data = 01h?
Yes
Protection Other Sector
?
No
Remove VID from RESET
Write Reset Command
Sector Protection
Completed
48
Yes
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
8. Embedded ProgramTM Algorithm for Fast Mode
FAST MODE ALGORITHM
Start
555h/AAh
Set Fast Mode
2AAh/55h
555h/20h
XXXh/A0h
Program Address/Program Data
Data Polling
Verify Data?
No
In Fast Program
Yes
Increment Address
No
Last Address
?
Yes
Programming Completed
XXXh/90h
Reset Fast Mode
XXXh/F0h
Notes : • The sequence is applied for × 16 mode.
• The addresses differ from × 8 mode.
49
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ ORDERING INFORMATION
Part No.
Package
Access Time
44-pin plastic SOP
(FPT-44P-M16)
55
70
90
MBM29LV400TC-55PFTN
MBM29LV400TC-70PFTN
MBM29LV400TC-90PFTN
48-pin plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
55
70
90
MBM29LV400TC-55PFTR
MBM29LV400TC-70PFTR
MBM29LV400TC-90PFTR
48-pin plastic TSOP (1)
(FPT-48P-M20)
(Reverse Bend)
55
70
90
MBM29LV400TC-55PCV
MBM29LV400TC-70PCV
MBM29LV400TC-90PCV
48-pin plastic CSOP
(LCC-48P-M03)
55
70
90
MBM29LV400TC-55PBT
MBM29LV400TC-70PBT
MBM29LV400TC-90PBT
48-pin plastic FBGA
(BGA-48P-M11)
55
70
90
MBM29LV400TC-55PW
MBM29LV400TC-70PW
MBM29LV400TC-90PW
48-pin plastic SCSP
(WLP-48P-M02)
55
70
90
MBM29LV400BC-55PF
MBM29LV400BC-70PF
MBM29LV400BC-90PF
44-pin plastic SOP
(FPT-44P-M16)
55
70
90
MBM29LV400BC-55PFTN
MBM29LV400BC-70PFTN
MBM29LV400BC-90PFTN
48-pin plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
55
70
90
MBM29LV400BC-55PFTR
MBM29LV400BC-70PFTR
MBM29LV400BC-90PFTR
48-pin plastic TSOP (1)
(FPT-48P-M20)
(Reverse Bend)
55
70
90
MBM29LV400BC-55PCV
MBM29LV400BC-70PCV
MBM29LV400BC-90PCV
48-pin plastic CSOP
(LCC-48P-M03)
55
70
90
MBM29LV400BC-55PBT
MBM29LV400BC-70PBT
MBM29LV400BC-90PBT
48-pin plastic FBGA
(BGA-48P-M11)
55
70
90
MBM29LV400BC-55PW
MBM29LV400BC-70PW
MBM29LV400BC-90PW
48-pin plastic SCSP
(WLP-48P-M02)
55
70
90
MBM29LV400TC-55PF
MBM29LV400TC-70PF
MBM29LV400TC-90PF
50
Sector
Architecture
Top Sector
Bottom Sector
Remarks
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
MBM29LV400
T
C
-55
PFTN
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP) Normal Bend
PFTR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Bend
PF =
44-Pin Small Outline Package
PCV = 48-Pin C- leaded Small Outline
Package (CSOP)
PBT = 48-Ball Fine Pitch Ball Grid Array
Package (FBGA)
PW =
48-Ball Super Chip Size Package
(SCSP)
SPEED OPTION
See Product Selector Guide
Device Revision
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29LV400
4Mega-bit (512K × 8-Bit or 256K × 16-Bit) CMOS Flash Memory
3.0 V-only Read, Program, and Erase
51
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
■ PACKAGE DIMENSIONS
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
44-pin plastic SOP
(FPT-44P-M16)
+0.25
+.010
+0.03
*1 28.45 –0.20 1.120 –.008
0.17 –0.04
+.001
.007 –.002
44
23
16.00±0.20
(.630±.008)
Details of "A" part
*2 13.00±0.10
(.512±.004)
2.35±0.15
(Mounting height)
(.093±.006)
INDEX
0.25(.010)
1
1.27(.050)
22
"A"
0~8˚
+0.08
0.42 –0.07
+.0031
.017 –.0028
0.13(.005)
M
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
+0.10
0.20 –0.15
+.004
.008 –.006
(Stand off)
0.10(.004)
C
2002 FUJITSU LIMITED F44023S-c-6-6
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
52
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are + 0.15 (.006) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
48-pin plastic TSOP(1)
(FPT-48P-M19)
LEAD No.
1
48
INDEX
Details of "A" part
0.25(.010)
0~8˚
0.60±0.15
(.024±.006)
24
25
* 12.00±0.20
20.00±0.20
(.787±.008)
* 18.40±0.20
(.724±.008)
"A"
0.10(.004)
(.472±.008)
+0.10
1.10 –0.05
+.004
.043 –.002
(Mounting
height)
+0.03
0.17 –0.08
+.001
.007 –.003
C
0.10±0.05
(.004±.002)
(Stand off height)
0.50(.020)
0.22±0.05
(.009±.002)
0.10(.004)
M
2003 FUJITSU LIMITED F48029S-c-6-7
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
53
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are + 0.15 (.006) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
48-pin plastic TSOP(1)
(FPT-48P-M20)
LEAD No.
1
48
Details of "A" part
INDEX
0.60±0.15
(.024±.006)
0~8˚
0.25(.010)
24
25
+0.03
0.17 –0.08
+.001
0.10(.004)
.007 –.003
0.50(.020)
0.22±0.05
(.009±.002)
M
0.10±0.05
(.004±.002)
(Stand off height)
+0.10
"A"
1.10 –0.05
+.004
* 18.40±0.20
(.724±.008)
20.00±0.20
(.787±.008)
C
0.10(.004)
.043 –.002
(Mounting height)
* 12.00±0.20(.472±.008)
2003 FUJITSU LIMITED F48030S-c-6-7
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
54
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) .
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
48-pin plastic CSOP
(LCC-48P-M03)
48
"A"
25
10.00±0.20
(.394±.008)
*2 9.50±0.10
(.374±.004)
INDEX
INDEX
+0.05
0.05 –0
+.002
.002 –.0
(Stand off)
LEAD No.
1
24
*1
10.00±0.10(.394±.004)
0.95±0.05(.037±.002)
(Mounting height)
0.22±0.035
(.009±.001)
Details of "A" part
0˚~10˚
0.40(.016)
0.08(.003)
0.65(.026)
1.15(.045)
9.20(.362)REF
C
2003 FUJITSU LIMITED C48056S-c-2-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
55
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
48-ball plastic FBGA
(BGA-48P-M11)
+0.15
8.00±0.20(.315±.008)
+.006
1.05 –0.10 .041 –.004
(Mounting height)
0.38±0.10(.015±.004)
(Stand off)
(5.60(.220))
0.80(.031)TYP
6
5
INDEX
6.00±0.20
(.236±.008)
4
(4.00(.157))
3
2
1
H
C0.25(.010)
G
F
E
D
48-ø0.45±0.10
(48-ø.018±.004)
C
B
A
ø0.08(.003)
M
0.10(.004)
C
2001 FUJITSU LIMITED B48011S-c-5-3
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
56
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
(Continued)
48-pin plastic SCSP
(WLP-48P-M02)
(3.50=0.50x7)
((.138=.020x7))
4.67±0.10(.184±.004)
0.50(.020)
TYP
Y
3.52±0.10
(.139±.004)
INDEX AREA
(LASER MARKING)
(2.50=0.50x5)
((.098=.020x5))
0.50(.020)
TYP
X
4-Ø0.13(4-Ø.005)
1.00(.039)
Max.
Z
C
0.10(.004) Z
0.25(.010)
Min.
48-Ø0.35±0.10
(48-Ø.014±.004)
0.08(.003)
M
XYZ
(Stand off)
2001 FUJITSU LIMITED W48002S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
57
MBM29LV400TC-70/90/12/MBM29LV400BC-70/90/12
FUJITSU LIMITED
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