Fairchild MM74HC4049MTCX Hex inverting logic level down converter . hex logic level down converter Datasheet

Revised October 1999
MM74HC4049 • MM74HC4050
Hex Inverting Logic Level Down Converter •
Hex Logic Level Down Converter
General Description
The MM74HC4049 and the MM74HC4050 utilize
advanced silicon-gate CMOS technology, and have a modified input protection structure that enables these parts to
be used as logic level translators which will convert high
level logic to a low level logic while operating from the low
logic supply. For example, 0–15V CMOS logic can be converted to 0–5V logic when using a 5V supply. The modified
input protection has no diode connected to VCC, thus allowing the input voltage to exceed the supply. The lower zener
diode protects the input from both positive and negative
static voltages. In addition each part can be used as a sim-
ple buffer or inverter without level translation. The
MM74HC4049 is pin and functionally compatible to the
CD4049BC and the MM74HC4050 is compatible to the
CD4050BC
Features
■ Typical propagation delay: 8 ns
■ Wide power supply range: 2V–6V
■ Low quiescent supply current: 20 µA maximum (74HC)
■ Fanout of 10 LS-TTL loads
Ordering Code:
Order Number
Package Number Package Description
MM74HC4049M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC4049SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4049MTC
MTC16
MM74HC4049N
N16E
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC4050M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC4050SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4050MTC
MTC16
MM74HC4050N
N16E
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
MM74HC4049
© 1999 Fairchild Semiconductor Corporation
MM74HC4050
DS005214
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MM74HC4049 • MM74HC4050 Hex Inverting Logic Level Down Converter • Hex Logic Level Down Converter
February 1984
MM74HC4049 • MM74HC4050
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
(Note 2)
Supply Voltage (VCC )
−0.5 to +7.0V
DC Input Voltage (VIN)
−1.5 to +18V
−0.5 to VCC +0.5V
DC Output Voltage (VOUT)
−20 mA
Clamp Diode Current (IZK, IOK)
DC Output Current, per pin (IOUT)
±25 mA
DC VCC or GND Current, per pin (ICC)
±50 mA
Max
Units
2
6
V
DC Input Voltage
0
15
V
0
VCC
V
−40
+85
°C
(VIN)
DC Output Voltage
(VOUT)
−65°C to +150°C
Storage Temperature Range (TSTG)
Min
Supply Voltage (VCC)
Operating Temperature Range (TA)
Power Dissipation (PD)
Input Rise or Fall Times
(Note 3)
600 mW
(tr, tf) VCC = 2.0V
1000
ns
S.O. Package only
500 mW
VCC = 4.5V
500
ns
VCC = 6.0V
400
ns
Lead Temperature (TL)
(Soldering 10 seconds)
260°C
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
VIH
VIL
Parameter
Conditions
TA = 25°C
VCC
Typ
TA = −40°C to 85°C TA = −55°C to 125°C
Units
Guaranteed Limits
Minimum HIGH Level Input
2.0V
1.5
1.5
1.5
V
Voltage
4.5V
3.15
3.15
3.15
V
6.0V
4.2
4.2
4.2
V
Maximum LOW Level Input
2.0V
0.5
0.5
0.5
V
4.5V
1.35
1.35
1.35
V
6.0V
1.8
1.8
1.8
V
Voltage
VOH
(Note 4)
Minimum HIGH Level
VIN = VIH or VIL
Output Voltage
|IOUT | ≤ 20 µA
2.0V
2.0
1.9
1.9
1.9
V
4.5V
4.5
4.4
4.4
4.4
V
6.0V
6.0
5.9
5.9
5.9
V
|IOUT | ≤ 4.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|IOUT | ≤ 5.2 mA
6.0V
5.7
5.48
5.34
5.2
V
VIN = VIH or VIL
VOL
Maximum LOW Level
VIN = VIH or VIL
Output Voltage
|IOUT | ≤ 20 µA
2.0V
0
0.1
0.1
0.1
V
4.5V
0
0.1
0.1
0.1
V
6.0V
0
0.1
0.1
0.1
V
V
VIN = VIH or VIL
|IOUT | ≤ 4 mA
4.5V
0.2
0.26
0.33
0.4
|IOUT | ≤ 5.2 mA
6.0V
0.2
0.26
0.33
0.4
V
VIN = VCC or GND
6.0V
±0.1
±1.0
±1.0
µA
2.0V
±0.5
±5
±5
µA
6.0V
2.0
20
40
µA
IIN
Maximum Input Current
ICC
Maximum Quiescent Supply VIN = VCC or GND
VIN = 15V
Current
IOUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Symbol
Parameter
tPHL, tPLH
Conditions
Typ
Maximum Propagation Delay
8
Guaranteed
Limit
15
Units
ns
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
tPHL, tPLH
tTHL, tTLH
Parameter
Conditions
Typ
TA = −40° to 85°C TA = −55° to 125°C
Units
Guaranteed Limits
Maximum Propagation
2.0V
30
85
100
130
ns
Delay
4.5V
10
17
20
26
ns
ns
6.0V
9
15
18
22
Maximum Output
2.0V
25
75
95
110
ns
Rise and Fall
4.5V
7
15
19
22
ns
6
13
16
19
Time
CPD
TA = 25°C
VCC
Power Dissipation
6.0V
(per gate)
25
ns
pF
Capacitance (Note 5)
CIN
Maximum Input
5
10
10
10
pF
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
3
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MM74HC4049 • MM74HC4050
AC Electrical Characteristics
MM74HC4049 • MM74HC4050
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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MM74HC4049 • MM74HC4050
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
5
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MM74HC4049 • MM74HC4050 Hex Inverting Logic Level Down Converter • Hex Logic Level Down Converter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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