MOTOROLA MC74HC4514N 1-of-16 decoder/demultiplexer with address latch high-performance silicon-gate cmo Datasheet

SEMICONDUCTOR TECHNICAL DATA
"
! High–Performance Silicon–Gate CMOS
The MC74HC4514 is identical in pinout to the MC14514B metal–gate
CMOS device. The device inputs are compatible with standard CMOS
outputs, with pullup resistors; they are compatible with LSTTL outputs.
This device consists of a 4–bit storage latch with a Latch Enable and Chip
Select input. When a low signal is applied to the Latch Enable input, the
Address is stored, and decoded. When the Chip Select input is high, all
sixteen outputs are forced to a low level.
The Chip Select input is provided to facilitate the chip–select, demultiplexing, and cascading functions.
The demultiplexing function is accomplished by using the Address inputs
to select the desired device output, and then by using the Chip Select as a
data input.
1
1
ORDERING INFORMATION
MC74HCXXXXN
MC74HCXXXXDW
A0
BINARY
ADDRESS
INPUTS
A1
A2
3
21
4–BIT
STORAGE
LATCH
4–TO–16
LINE
DECODER
A3
LATCH
ENABLE
1
ACTIVE–HIGH
OUTPUTS
CHIP
SELECT
PIN 24 = VCC
PIN 12 = GND
10/95
 Motorola, Inc. 1995
1
Plastic
SOIC
PIN ASSIGNMENT
LOGIC DIAGRAM
2
DW SUFFIX
SOIC PACKAGE
CASE 751E–04
24
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 268 FETs or 67 Equivalent Gates
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
N SUFFIX
PLASTIC PACKAGE
CASE 724–03
24
•
•
•
•
•
•
11
9
10
8
7
6
5
4
18
17
20
19
14
13
16
15
REV 6
LATCH
ENABLE
1
24
A0
2
23
A1
3
22
VCC
CHIP
SELECT
A3
Y7
4
21
A2
Y6
5
20
Y10
Y5
6
19
Y11
Y4
7
18
Y8
Y3
8
17
Y9
Y1
9
16
Y14
Y2
10
15
Y15
Y0
11
14
Y12
GND
12
13
Y13
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MC74HC4514
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
DC Supply Voltage (Referenced to GND)
2
6.0
V
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
VOH
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
Iin
ICC
4.0 mA
5.2 mA
4.0 mA
5.2 mA
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC74HC4514
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
tPLH,
tPHL
Maximum Propagation Delay, Chip Select to Output Y
(Figures 1 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 5)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
ns
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Symbol
Parameter
tPHL
tPLH
Maximum Propagation Delay, Latch Enable to Output Y
(Figures 3 and 5)
tPHL
tTLH,
tTHL
Cin
Unit
ns
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
pF
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70
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
tsu
Minimum Setup Time, Input A to Latch Enable
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th
Minimum Hold Time, Latch Enable to Input A
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
tw
Minimum Pulse Width, Latch Enable
(Figure 3)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
Symbol
Parameter
Unit
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
MC74HC4514
SWITCHING WAVEFORMS
tf
CHIP
SELECT
tr
VCC
90%
50%
10%
VALID
GND
tPLH
INPUT A
tPHL
VCC
50%
GND
90%
50%
10%
OUTPUT Y
tPLH
tTLH
OUTPUT Y
tTHL
Figure 1.
tPHL
50%
Figure 2.
VALID
tw
VCC
VCC
LATCH
ENABLE
INPUT A
50%
50%
50%
GND
tsu
GND
tPLH
OUTPUT Y
VALID
tPHL
th
VCC
LATCH
ENABLE
50%
Figure 3.
50%
GND
Figure 4.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
Figure 5. Test Circuit
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC4514
FUNCTION TABLE
PIN DESCRIPTIONS
Latch
Enable
Chip
Select
A3
A2
A1
A0
Selected
Output
(High)
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
Y0
Y1
Y2
Y3
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
Y4
Y5
Y6
Y7
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
Y8
Y9
Y10
Y11
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
Y12
Y13
Y14
Y15
X
H
X
X
X
X
All
Outputs = L
L
L
X
X
X
X
Latched
Data
Address Inputs
ADDRESS INPUTS
A0, A1, A2, A3 (Pins 2, 3, 21, 22)
Address Inputs. These inputs are decoded to produce a
high level on one of 16 outputs. The inputs are arranged
such that A3 is the most–significant bit and A0 is the least–
significant bit. The decimal equivalent of the binary input
address indicates which of the 16 data outputs, Y0 – Y15, is
selected.
OUTPUTS
Y0 – Y15 (Pins 11, 9, 10, 8, 7, 6, 5, 4, 18, 17, 20, 19, 14,
13, 16, 15)
Active–High Outputs. These outputs produce a high level
when selected (Latch Enable = H, Chip Select = L) and are at
a low level when not selected.
CONTROL INPUTS
Latch Enable (Pin 1)
Latch Enable Input. A low level on this input stores the
data on the Address data inputs in the 4–bit latch. A high
level on the Latch Enable input makes the latch transparent
and allows the outputs to follow the inputs. Note that the data
is latched only while the Latch Enable input is at a low level.
Chip Select (Pin 23)
Chip Select Input. A high on this input produces a low level
on all outputs, regardless of what appears at the address or
Latch Enable inputs. A low level on the Chip Select input
allows the selected output to produce a high level.
TIMING DIAGRAM
INPUT A
LATCH ENABLE
CHIP SELECT
OUTPUT Y
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
MC74HC4514
EXPANDED LOGIC DIAGRAM
Y0
ABCD
11
Y1
ABCD
9
Y2
ABCD
10
A0
A1
A2
2
3
21
DATA
Q
LE
Q
Y3
ABCD
8
Y4
ABCD
7
Y5
ABCD
6
DATA
Q
LE
Q
Y6
ABCD
5
Y7
ABCD
4
Y8
ABCD
18
DATA
Q
Y9
ABCD
17
LE
A3
22
DATA
Y10
ABCD
20
Q
Y11
ABCD
19
Q
Y12
ABCD
14
LATCH 1
ENABLE
LE
Y13
ABCD
13
Q
Y14
ABCD
16
Y15
ABCD
15
CHIP 23
SELECT
MOTOROLA
6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC4514
A12
CHIP
SELECT
A11
A3
A10
A2
A9
A1
A8
A0
+V
MC4514
MC146805
MICROPROCESSOR MEMORY DECODING
LATCH
ENABLE
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
0000–00FF
0100–01FF
0200–02FF
0300–03FF
0400–04FF
0500–05FF
0600–06FF
0700–07FF
0800–08FF
0900–09FF
0A00–0AFF
0B00–0BFF
0C00–0CFF
0D00–0DFF
0E00–0EFF
0F00–0FFF
TO DEVICE SELECTS
HC04
CHIP
SELECT
A2
MC4514
A3
A1
A0
+V
High–Speed CMOS Logic Data
DL129 — Rev 6
LATCH
ENABLE
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
1000–10FF
1100–11FF
1200–12FF
1300–13FF
1400–14FF
1500–15FF
1600–16FF
1700–17FF
1800–18FF
1900–19FF
1A00–1AFF
1B00–1BFF
1C00–1CFF
1D00–1DFF
1E00–1EFF
1F00–1FFF
MOTOROLA
MC74HC4514
CODE TO CODE CONVERSION — HEXADECIMAL TO BCD
+V
A3
A2
A1
MC146805
A0
LATCH
ENABLE
CHIP
SELECT
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
COMMON CATHODE LEDs
R=2k
GND
A2
A1
R = 10 k
A0
HC4050
MOTOROLA
MC4511
A3
ALL DIODES GENERAL
PURPOSE GERMANIUM
8
R = 2 kΩ
HC4050
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC4514
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 724–03
ISSUE D
–A–
24
13
1
12
NOTES:
1. CHAMFERED CONTOUR OPTIONAL.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
4. CONTROLLING DIMENSION: INCH.
–B–
L
C
–T–
NOTE 1
K
SEATING
PLANE
N
E
G
M
J
F
D
24 PL
0.25 (0.010)
24 PL
0.25 (0.010)
T A
M
M
T B
M
M
24
12X
P
0.010 (0.25)
1
M
B
M
12
D
J
0.010 (0.25)
T A
M
S
B
S
F
R
C
–T–
M
22X
MILLIMETERS
MIN
MAX
31.25
32.13
6.35
6.85
3.69
4.44
0.38
0.51
1.27 BSC
1.02
1.52
2.54 BSC
0.18
0.30
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
13
–B–
SEATING
PLANE
INCHES
MIN
MAX
1.230
1.265
0.250
0.270
0.145
0.175
0.015
0.020
0.050 BSC
0.040
0.060
0.100 BSC
0.007
0.012
0.110
0.140
0.300 BSC
0_
15_
0.020
0.040
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
–A–
24X
DIM
A
B
C
D
E
F
G
J
K
L
M
N
K
G
X 45 _
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0_
8_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0_
8_
0.395
0.415
0.010
0.029
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
9
*MC74HC4514/D*
MC74HC4514/D
MOTOROLA
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