Cypress CY7C1049CV33-10VXA 4 mbit (512k x 8) static ram Datasheet

CY7C1049CV33
4 Mbit (512K x 8) Static RAM
Features
Functional Description
■
Temperature ranges
❐ Commercial: 0°C to 70°C
❐ Industrial/Automotive -A: –40°C to 85°C
❐ Automotive-E: –40°C to 125°C
The CY7C1049CV33 is a high performance CMOS Static RAM
organized as 524,288 words by eight bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. Writing
to the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A18).
■
High Speed
❐ tAA = 10 ns
■
Low Active Power
❐ 324 mW (max)
■
2.0V Data Retention
■
Automatic Power Down when Deselected
■
TTL-compatible Inputs and Outputs
■
Easy Memory Expansion with CE and OE features
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049CV33 is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
IO0
INPUT BUFFER
IO1
512K x 8
ARRAY
IO3
IO4
IO5
IO6
CE
•
IO7
POWER
DOWN
A17
A18
A15
A13
A14
OE
A16
COLUMN DECODER
WE
Cypress Semiconductor Corporation
Document #: 38-05006 Rev. *G
IO2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
198 Champion Court
•
San Jose, CA 95134-1709
•408-943-2600
Revised January 07, 2010
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CY7C1049CV33
Contents
Features ............................................................................
Functional Description.....................................................
Logic Block Diagram........................................................
Contents ............................................................................
Pin Configuration .............................................................
Selection Guide ................................................................
Pin Definitions ..................................................................
Maximum Ratings.............................................................
Operating Range...............................................................
Electrical Characteristics.................................................
Capacitance ......................................................................
Thermal Resistance..........................................................
Document #: 38-05006 Rev. *G
1
1
1
2
3
3
4
5
5
5
5
5
AC Switching Characteristics ......................................... 7
Switching Waveforms ...................................................... 8
Truth Table........................................................................ 9
Ordering Information ....................................................... 9
Package Diagrams ......................................................... 10
Document History Page................................................. 11
Sales, Solutions, and Legal Information ...................... 12
Worldwide Sales and Design Support....................... 12
Products .................................................................... 12
PSoC Solutions ......................................................... 12
Page 2 of 12
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CY7C1049CV33
Pin Configuration
Figure 1. 36-Pin SOJ (Top View)
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
Figure 2. 44-Pin TSOP II (Top View)
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
VSS
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Selection Guide
Description
-10
-12
-15
10
12
15
ns
Commercial
90
85
-
mA
Industrial/Automotive-A
100
95
-
mA
-
-
95
mA
10
10
-
mA
-
-
15
mA
Maximum Access Time
Maximum Operating Current
Automotive-E
Maximum CMOS Standby Current
Commercial/Industrial/ Automotive-A
Automotive-E
Document #: 38-05006 Rev. *G
Unit
Page 3 of 12
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CY7C1049CV33
Pin Definitions
Pin Name
A0–A18
36-SOJ
Pin Number
44 TSOP-II
Pin Number
1–5,14–18,
3–7,16–20,
20–24,32–35 26–30,38–41
I/O Type
Input
Description
Address inputs used to select one of the address locations.
I/O0–I/O7
7,8,11,12,25,
26,29,30
9,10,13,14,
31,32,35,36
Input/Output Bidirectional data I/O lines. Used as input or output lines depending
on operation
NC[1]
19,36
1,2,21,22,23,2
4,25,42,43, 44
WE
13
15
Input/Control Write Enable input, active LOW. When selected LOW, a WRITE is
conducted. When selected HIGH, a READ is conducted.
CE
6
8
Input/Control Chip Enable input, active LOW. When LOW, selects the chip. When
HIGH, deselects the chip.
OE
31
37
Input/Control Output Enable, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data pins.
VSS, GND
10,28
12,34
VCC
9,27
11,33
No Connect
Ground
No connects. This pin is not connected to the die
Ground for the device. Should be connected to ground of the system.
Power Supply Power supply inputs to the device.
Note
1. NC pins are not connected on the die.
Document #: 38-05006 Rev. *G
Page 4 of 12
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CY7C1049CV33
Input Voltage[2] ...................................... –0.5V to VCC + 0.5V
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Operating Range
Range
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Ambient Temperature
VCC
0°C to +70°C
3.3V ± 0.3V
Commercial
Supply Voltage on VCC to Relative GND[2] –0.5V to +4.6VDC
Voltage Applied to Outputs
in High-Z State[2].................................... –0.5V to VCC + 0.5V
Industrial/
Automotive-A
–40°C to +85°C
Automotive-E
–40°C to +125°C
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min.; IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min.,; IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[2]
IIX
Input Load Current
GND < VI < VCC
-10
Min
-12
Max
2.4
Min
2.4
0.4
Com’l/Ind’l/
Auto-A
-15
Max
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Automatic CE
Power Down Current
—TTL Inputs
Max. VCC, CE > VIH;
VIN > VIH or
VIN < VIL, f = fMAX
Com’l/Ind’l/
Auto-A
Automatic CE
Power Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Com’l/Ind’l/
Auto-A
Max
2.4
ISB2
V
V
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
–0.3
0.8
–0.3
0.8
–0.3
0.8
–1
+1
–1
+1
–20
90
85
Ind’l/Auto-A
100
95
40
40
V
μA
+20
mA
Auto-E
ISB1
0.4
2.0
Com’l
Unit
V
0.4
Auto-E
ICC
Min
95
mA
Auto-E
45
10
10
mA
mA
Auto-E
15
mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max
Unit
8
pF
8
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
ΘJA
ΘJC
Description
Test Conditions
Thermal Resistance (Junction Test conditions follow standard
to Ambient)
test methods and procedures for
measuring thermal impedance,
Thermal Resistance
per EIA / JESD51.
(Junction to Case)
36-Pin SOJ
44-TSOP-II
Unit
46.51
41.66
°C/W
18.8
10.56
°C/W
Notes
2. VIL (min) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05006 Rev. *G
Page 5 of 12
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CY7C1049CV33
Figure 3. AC Test Loads and Waveforms [3]
10-ns devices:
12-, 15-ns devices:
Z = 50Ω
50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
3.0V
GND
Rise Time: 1 V/ns
R 317Ω
3.3V
OUTPUT
30 pF*
OUTPUT
(a)
(b)
High-Z characteristics:
ALL INPUT PULSES
90%
10%
(c)
R 317Ω
3.3V
90%
10%
R2
351Ω
30 pF
1.5V
Fall Time: 1 V/ns
OUTPUT
R2
351Ω
5 pF
(d)
Note
4. AC characteristics (except High-Z) for 10 ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown
in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document #: 38-05006 Rev. *G
Page 6 of 12
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CY7C1049CV33
AC Switching Characteristics
Over the Operating Range [5]
-10
Parameter
Description
Min
-12
Max
Min
-15
Max
Min
Max
Unit
Read Cycle
tpower[6]
VCC(typical) to the first access
100
tRC
Read Cycle Time
10
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z[7, 8]
CE LOW to
Low-Z[8]
tHZCE
CE HIGH to
High-Z[7, 8]
tPU
CE LOW to Power Up
tLZCE
tPD
Write Cycle
100
12
10
3
3
12
5
0
6
0
5
3
3
ns
15
ns
7
6
ns
ns
7
0
12
ns
ns
3
0
10
ns
7
6
5
ns
15
0
3
0
CE HIGH to Power Down
15
12
10
μs
100
ns
ns
15
ns
[9, 10]
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
7
8
10
ns
tAW
Address Setup to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Setup to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
ns
tSD
Data Setup to Write End
5
6
7
ns
tHD
Data Hold from Write End
0
0
0
ns
Low-Z[8]
tLZWE
WE HIGH to
tHZWE
WE LOW to High-Z[7, 8]
3
3
5
3
6
ns
7
ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of
these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05006 Rev. *G
Page 7 of 12
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CY7C1049CV33
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [11, 12]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [12, 13]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
HIGH IMPEDANCE
DATA OUT
DATA VALID
tLZCE
tPD
tPU
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
50%
50%
ICC
ISB
Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [14, 15]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
NOTE 16
tHD
DATA VALID
tHZOE
Notes
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycles.
13. Address valid before or similar to CE transition LOW.
14. Data I/O is high impedance if OE = VIH.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
16. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 38-05006 Rev. *G
Page 8 of 12
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CY7C1049CV33
Switching Waveforms
(continued)
Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [15]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
NOTE 16
DATA I/O
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
CE
OE
WE
I/O0–I/O7
Mode
Power
H
X
X
High-Z
Power Down
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High-Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
10
Ordering Code
Package
Diagram
Package Type
Operating
Range
CY7C1049CV33-10VXC
51-85090
36-Pin (400-Mil) Molded SOJ (Pb-Free)
CY7C1049CV33-10ZXI
51-85087
44-Pin TSOP II (Pb-Free)
CY7C1049CV33-10VXA
51-85090
36-Pin (400-Mil) Molded SOJ (Pb-Free)
Automotive-A
12
CY7C1049CV33-12VXC
51-85090
36-Pin (400-Mil) Molded SOJ (Pb-Free)
Commercial
CY7C1049CV33-12ZSXA
51-85087
44-Pin TSOP II (Pb-Free)
Automotive-A
15
CY7C1049CV33-15VXE
51-85090
36-Pin (400-Mil) Molded SOJ (Pb-Free)
Automotive-E
CY7C1049CV33-15ZSXE
51-85087
44-Pin TSOP II (Pb-Free)
Document #: 38-05006 Rev. *G
Commercial
Industrial
Page 9 of 12
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CY7C1049CV33
Package Diagrams
Figure 8. 36-Pin (400-Mil) Molded SOJ V36, 51-85090
PIN 1 I.D
.007
.013
.435
.445
.395
.405
.360
.380
.920
.930
DIMENSIONS IN INCHES MIN.
MAX.
.128
.148
.050
TYP.
.026
.032
.025 MIN.
.015
.020
SEATING PLANE
51-85090 *D
Figure 9. 44-Pin TSOP II, 51-85087
PIN 1 I.D.
10.262 (0.404)
10.058 (0.396)
1
11.938 (0.470)
11.735 (0.462)
22
OR E
K X A
SG
EJECTOR PIN
44
23
BOTTOM VIEW
TOP VIEW
0.800 BSC
(0.0315)
0.400(0.016)
0.300 (0.012)
BASE PLANE
18.517 (0.729)
18.313 (0.721)
DIMENSION IN MM (INCH)
MAX
MIN.
Document #: 38-05006 Rev. *G
0.10 (.004)
0.150 (0.0059)
0.050 (0.0020)
1.194 (0.047)
0.991 (0.039)
10.262 (0.404)
10.058 (0.396)
SEATING
PLANE
0.210 (0.0083)
0.120 (0.0047)
0°-5°
0.597 (0.0235)
0.406 (0.0160)
51-85087 *B
Page 10 of 12
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CY7C1049CV33
Document History Page
Document Title: CY7C1049CV33, 4 Mbit (512K x 8) Static RAM
Document Number: 38-05006
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
**
112569
HGK
03/06/02
New data sheet
*A
114091
DFP
04/25/02
Changed Tpower unit from ns to μs
*B
116479
CEA
09/16/02
Add applications foot note to data sheet, page 1.
*C
262949
RKF
See ECN
Added Automotive-E Specs
Added ΘJA and ΘJC values on Page #3.
*D
300091
RKF
See ECN
Added -20-ns Speed bin
*E
344595
SYT
See ECN
Added Pb-Free package on page #8
Removed shading for CY7C1049CV33-15ZSXE in the ordering Information on
page 9
*F
2615344
VKN/PYRS
12/03/08
Added Automotive-A information
Removed 8 ns and 20 ns speed bins,
Changed tPOWER spec from 1 μs to 100 μs,
Updated Ordering Information table.
*G
2841563
NXR/
Document #: 38-05006 Rev. *G
01/07/2010 Added CY7C1049CV33-10VXA to Ordering Info table.
Page 11 of 12
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CY7C1049CV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2002-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05006 Rev. *G
Revised January 07, 2010
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