IRF IRS24531DSTRPBF Integrated 600 v full-bridge gate driver Datasheet

February 18, 2009
IRS2453(1)D(S)
SELF-OSCILLATING FULL BRIDGE DRIVER IC
Features
•
•
•
•
•
•
•
•
•
•
•
Integrated 600 V full-bridge gate driver
CT, RT programmable oscillator
15.6V Zener clamp on VCC
Micropower startup
Logic level latched shutdown pin
Non-latched shutdown on CT pin (1/6th VCC)
Internal bootstrap FETs
Excellent latch immunity on all inputs & outputs
ESD protection on all pins
14-lead SOIC or PDIP package
0.5 or 1.0 μs (typ.) internal deadtime
•
RoHS compliant
Product Summary
Topology
VOFFSET
Io+ & I o- (typical)
Deadtime (typical)
Full-bridge
600 V
180 mA & 260 mA
1.0 μs (IRS2453D)
0.5 μs (IRS24531D)
Package Options
14 Lead PDIP
IRS2453DPbF
14 Lead SOIC
(Narrow Body)
IRS2453(1)DSPbF
Typical Connection Diagram
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© 2008 International Rectifier
IRS2453(1)D(S)
Table of Contents
Page
Description
3
Qualification Information
4
Absolute Maximum Ratings
5
Recommended Operating Conditions
6
Electrical Characteristics
7
Functional Block Diagram
9
Input/Output Pin Equivalent Circuit Diagram
10
Lead Definitions
11
Lead Assignments
11
Application Information and Additional Details
12
Package Details
15
Tape and Reel Details
16
Part Marking Information
17
Ordering Information
18
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© 2007 International Rectifier
2
IRS2453(1)D(S)
Description
The IRS2453(1)D is based on the popular IR2153 self-oscillating half-bridge gate driver IC, and incorporates a
high voltage full-bridge gate driver with a front end oscillator similar to the industry standard CMOS 555 timer.
HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The output driver
features a high pulse current buffer stage designed for minimum driver cross-conduction. Noise immunity is
achieved with low di/dt peak of the gate drivers, and with an undervoltage lockout hysteresis greater than 1.5 V.
The IRS2453(1)D also includes latched and non-latched shutdown pins.
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© 2007 International Rectifier
3
IRS2453(1)D(S)
†
Qualification Information
Qualification Level
Moisture Sensitivity Level
Machine Model
ESD
Human Body Model
IC Latch-Up Test
RoHS Compliant
†
††
†††
Industrial††
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification level is
granted by extension of the higher Industrial level.
MSL2††† 260°C
SOIC14
(per IPC/JEDEC J-STD-020)
Not applicable
PDIP14
(non-surface mount package style)
Class C
(per JEDEC standard JESD22-A115)
Class 2
(per EIA/JEDEC standard EIA/JESD22-A114)
Class I, Level A
(per JESD78)
Yes
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please contact
your International Rectifier sales representative for further information.
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
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© 2007 International Rectifier
4
IRS2453(1)D(S)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The
thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
VB1, VB2
High side floating supply voltage
VS1, VS2
-0.3
625
High side floating supply offset voltage
VB - 25
VB + 0.3
VHO1, VHO2
High side floating output voltage
VS - 0.3
VB + 0.3
VLO1, VLO2
Low side output voltage
-0.3
VCC + 0.3
VRT
RT pin voltage
-0.3
VCC + 0.3
VCT
CT pin voltage
-0.3
VCC + 0.3
VSD
SD pin voltage
-0.3
VCC + 0.3
IRT
RT pin current
-5
5
ICC
Supply current (†)
---
25
Allowable offset voltage slew rate
-50
50
PD
Maximum power dissipation @ TA ≤ +25 ºC, 8-Pin DIP
---
1.0
PD
Maximum power dissipation @ TA ≤ +25 ºC, 8-Pin SOIC
---
0.625
RθJA
Thermal resistance, junction to ambient, 8-Pin DIP
---
125
RθJA
Thermal resistance, junction to ambient, 8-Pin SOIC
---
200
TJ
Junction temperature
-55
150
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
---
300
dVS/dt
†
V
mA
V/ns
W
ºC/W
ºC
This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown
voltage of 15.6 V. Please note that this supply pin should not be driven by a DC, low impedance power
source greater than the VCLAMP specified in the Electrical Characteristics section.
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© 2007 International Rectifier
5
IRS2453(1)D(S)
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol
Definition
Min.
VBS1, VBS2
VCC - 0.7
VCLAMP
Steady state high side floating supply offset voltage
-3.0 (†)
600
VCC
Supply voltage
VCCUV+
VCLAMP
ICC
Supply current
(††)
5
VS1, VS2
†
††
Max.
High side floating supply voltage
Units
V
mA
TJ
Junction temperature
-25
125
ºC
It is recommended to avoid output switching conditions where negative-going spikes at the VS node would
decrease VS below ground by more than -5V.
Enough current should be supplied to the VCC pin of the IC to keep the internal 15.6 V zener diode
clamping the voltage at this pin.
Recommended Component Values
Symbol
Component
Min.
Max.
Units
RT
Timing resistor value
1
---
kΩ
CT
CT pin capacitor value
330
---
pF
VBIAS (VCC, VBS) = 14 V, VS=0 V and TA = 25 °C, CLO1=CLO2 = CHO1=CHO2 = 1 nF.
IRS2453(1)D
IRS2453DFrequency
Frequencyvs.
vs.RT
RT
1000000
CT Values
Frequency (Hz)
100000
330pf
470pF
10000
1nF
2.2nF
1000
4.7nF
10nF
100
10
1000
10000
100000
1000000
RT (Ohm)
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© 2007 International Rectifier
6
IRS2453(1)D(S)
Electrical Characteristics
VBIAS (VCC, VBS) = 14 V, CT = 1 nF and TA = 25 °C unless otherwise specified. The VO and IO parameters are
referenced to COM and are applicable to the respective output leads: HO or LO. CLO1=CLO2=CHO1=CHO2=1
nF.
Symbol
Definition
Min
Typ
Max
Units Test Conditions
Low Voltage Supply Characteristics
VCCUV+
Rising VCC undervoltage lockout threshold
10.0
11.0
12.0
VCCUV-
Falling VCC undervoltage lockout threshold
8.0
9.0
10.0
VCC undervoltage lockout hysteresis
1.5
2.0
2.4
Micropower startup VCC supply current
---
140
200
Quiescent VCC supply current
---
1.3
2.0
ICC_20K
VCC supply current at fosc (RT = 36.5 kΩ)
---
3.0
3.5
ICCFLT
VCC supply current when SD > VSD
---
360
500
µA
14.6
15.6
16.6
V
Micropower startup VBS supply current
---
3
10
Quiescent VBS supply current
---
30
100
VBS1UV+,
VBS2UV+
VBS supply undervoltage positive going
threshold
8.0
9.0
10.0
VBS1UV-,
VBS2UV-,
VBS supply undervoltage negative going
threshold
7.0
8.0
9.0
ILK1, ILK2
Offset supply leakage current
---
---
50
19.6
20.2
20.8
88
94
100
RT pin duty cycle
48
50
52
%
CT pin current
---
0.05
1.0
μA
ICTUV
UV-mode CT pin pulldown current
1
5
---
mA
VCT+
Upper CT ramp voltage threshold
---
9.3
---
VCT-
Lower CT ramp voltage threshold
---
4.7
---
---
10
50
---
100
300
---
10
50
---
100
300
---
0
100
VCCUVHYS
IQCCUV
IQCC
VCLAMP
VCC Zener clamp voltage
V
µA
VCC ≤ VCCUV-
mA
ICC = 5 mA
Floating Supply Characteristics
IQBS1UV,
IQBS2UV
IQBS1,
IQBS2
µA
VCC ≤ VCCUV-,
VCC = VBS
V
μA
VB = VS = 600
V
Oscillator I/O Characteristics
fOSC
d
ICT
VRT+
VRT-
VRTUV
Oscillator frequency
kHz
UV-mode RT output voltage
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RT = 7.15 kΩ
fo < 100 kHz
VCC = 7 V
V
High level RT output voltage, VCC - VRT
Low level RT output voltage
RT = 36.5 kΩ
mV
IRT = 100 μA
RT = 140 kΩ
IRT = 1 mA
RT = 14 kΩ
IRT = 100 μA
RT = 140 kΩ
IRT = 1 mA
RT = 14 kΩ
VCC ≤ VCCUV-
© 2007 International Rectifier
7
IRS2453(1)D(S)
Electrical Characteristics
VBIAS (VCC, VBS) = 14 V, CT = 1 nF and TA = 25 °C, unless otherwise specified. The VO and IO parameters are
referenced to COM and are applicable to the respective output leads: HO or LO. CLO1=CLO2=CHO1=CHO2=1
nF.
Symbol
Definition
Min
Typ
Max
Units Test Conditions
Gate Driver Output Characteristics
VOH
High level output voltage, VBIAS - VO
---
VCC
---
VOL
Low level output voltage, VO
---
COM
---
VOL_UV
UV-mode output voltage, VO
---
COM
---
tr
Output rise time
---
120
200
tf
Output fall time
---
50
100
tsd
Shutdown propagation delay
---
250
---
td
Output deadtime (HO or LO)
IRS2453D
0.8
1.0
1.40
IRS24531D
0.4
0.5
0.7
IO+
Output source current
---
180
---
IO-
Output sink current
---
260
---
Shutdown threshold at SD pin (latched)
1.8
2.0
2.3
CT voltage shutdown threshold (non latched)
2.2
2.3
2.5
---
10
50
IO = 0 A
V
IO = 0 A,
VCC ≤
VCCUV-
ns
μs
mA
Shutdown
VSD
VCTSD
VRTSD
SD mode RT output voltage, VCC - VRT
V
mV
Bootstrap FET Characteristics
VB1_ON
VB when the bootstrap FET is on
VB2_ON
IB1_CAP
VB source current when FET is on
IB2_CAP
IB1_10 V
VB source current when FET is on
IB2_10 V
---
100
300
13.7
14.0
---
40
55
---
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12
---
IRT = 1 mA,
RT = 14 kΩ
VCT = 0 V
V
mA
10
IRT = 100 μA,
RT = 140 kΩ
VCT = 0 V
CBS=0.1 μF
VB=10 V
© 2007 International Rectifier
8
IRS2453(1)D(S)
Functional Block Diagram
RT 4
14 VB1
R
Q
HV
Level
Shift
+
R
R
+
-
S
Q
DEAD
TIME
13 HO1
R
PULSE
FILTER
S
12 VS1
PULSE
GEN
BOOTSTRAP
DRIVE
Q
R/2
+
-
CT 3
R/2
SD 5
S Q
R1
R2 Q
S
2.0V
DEAD
TIME
DELAY
6
LO1
10 VB2
Q
R
HV
Level
Shift
PULSE
GEN
UV
DETECT
Q
PULSE
FILTER
R
9 HO2
S
8 VS2
BOOTSTRAP
DRIVE
15.4V
DELAY
1 VCC
7 LO2
2
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COM
© 2007 International Rectifier
9
IRS2453(1)D(S)
Input/Output Pin Equivalent Circuit Diagrams:
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© 2007 International Rectifier
10
IRS2453(1)D(S)
Lead Definitions
Pin
Symbol
Description
1
VCC
Logic and internal gate drive supply voltage
2
COM
IC power and signal ground
3
CT
Oscillator timing capacitor input
4
RT
Oscillator timing resistor input
5
SD
Shutdown input
6
LO1
Low side gate driver output
7
LO2
Low side gate driver output
8
VS2
High voltage floating supply return
9
HO2
High side gate driver output
10
VB2
High side gate driver floating supply
11
NC
No connect
12
VS1
High voltage floating supply return
13
HO1
High side gate driver output
14
VB1
High side gate driver floating supply
Lead Assignment
1
COM
2
CT
3
RT
4
SD
5
LO1
6
LO2
7
14
IRS2453(1)D(S)
VCC
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VB1
13 HO1
12
VS1
11
NC
10
VB2
9
HO2
8
VS2
© 2007 International Rectifier
11
IRS2453(1)D(S)
Application Information and Additional Details
Timing Diagram
Fault mode
VCT<1/6*VCC
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© 2007 International Rectifier
12
IRS2453(1)D(S)
Functional Description
Under-Voltage Lock-Out Mode (UVLO)
The under-voltage lockout mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on
threshold of the IC. The IRS2453(1)D under-voltage lock-out is designed to maintain an ultra low supply current
of less than 150 μA, and to guarantee the IC is fully functional before the high and low side output drivers are
activated. During under-voltage lock-out mode, the high and low side driver outputs LO1, LO2, HO1, HO2 are all
low. With VCC above the VCCUV+ threshold, the IC turns on and the output begin to oscillate.
Normal Operating Mode
Once VCC reaches the start-up threshold VCCUV+, the MOSFET M1 opens, RT increases to approximately VCC
(VCC-VRT+) and the external CT capacitor starts charging. Once the CT voltage reaches VCT- (about 1/3 of VCC),
established by an internal resistor ladder, LO1 and HO2 turn on with a delay equivalent to the deadtime (td).
Once the CT voltage reaches VCT+ (approximately 2/3 of VCC), LO1 and HO2 go low, RT goes down to
approximately ground (VRT-), the CT capacitor starts discharging and the deadtime circuit is activated. At the
end of the deadtime, LO2 and HO1 go high. Once the CT voltage reaches VCT-, LO2 and HO1 go low, RT goes
to high again, the deadtime is activated. At the end of the deadtime, LO1 and HO2 go high and the cycle starts
over again.
The frequency is best determined by the graph, Frequency vs. RT, page 3, for different values of CT. A first
order approximate of the oscillator frequency can also be calculated by the following formula::
1
f ≈
1.453 × RT × CT
This equation can vary slightly from actual measurements due to internal comparator over- and under-shoot
delays.
Bootstrap MOSFET
The internal bootstrap FET and supply capacitor (CBOOT) comprise the supply voltage for the high side driver
circuitry. The internal boostrap FET only turns on when the corresponding LO is high. To guarantee that the
high-side supply is charged up before the first pulse on HO1 and HO2, LO1 and LO2 are both on when CT
ramps between zero and 1/3*VCC. LO1 and LO2 are also on when CT is grounded below 1/6*VCC to ensure that
the bootstrap capacitor is charged when CT is brought back over 1/3*VCC.
Non-Latched Shutdown
If CT is pulled down below VCTSD (approximately 1/6 of VCC) by an external circuit, CT doesn’t charge up and
oscillation stops. All outputs are held low and the bootstrap FETs are off. Oscillation will resume once CT is able
to charge up again to VCT-.
Latched Shutdown
When the SD pin is brought above 2 V, the IC goes into fault mode and all outputs are low. VCC has to be
recycled below VCCUV- to restart the IC. The SD pin can be used for over-current or over-voltage protection using
appropriate external circuitry.
50%
HO1
50%
td_LO1
td_HO1
LO1
50%
50%
ton_LO
50%
Deadtime Waveform
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© 2007 International Rectifier
13
IRS2453(1)D(S)
tr
tf
90%
HO
LO
10%
Rise and Fall Time Waveform
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© 2007 International Rectifier
14
IRS2453(1)D(S)
Package Details
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© 2007 International Rectifier
15
IRS2453(1)D(S)
Tape and Reel Details
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR
Metric
Code
Min
Max
A
7.90
8.10
B
3.90
4.10
C
15.70
16.30
D
7.40
7.60
E
6.40
6.60
F
9.40
9.60
G
1.50
n/a
H
1.50
1.60
14SOICN
Imperial
Min
Max
0.311
0.318
0.153
0.161
0.618
0.641
0.291
0.299
0.252
0.260
0.370
0.378
0.059
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 14SOICN
Metric
Imperial
Code
Min
Max
Min
Max
A
329.60
330.25
12.976
13.001
B
20.95
21.45
0.824
0.844
C
12.80
13.20
0.503
0.519
D
1.95
2.45
0.767
0.096
E
98.00
102.00
3.858
4.015
F
n/a
22.40
n/a
0.881
G
18.50
21.10
0.728
0.830
H
16.40
18.40
0.645
0.724
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© 2007 International Rectifier
16
IRS2453(1)D(S)
Part Marking Information
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© 2007 International Rectifier
17
IRS2453(1)D(S)
Ordering Information
Standard Pack
Base Part Number
Package Type
PDIP14
IRS2453D(S)
IRS24531DS
SOIC14N
SOIC14N
Complete Part Number
Form
Quantity
Tube/Bulk
25
IRS2453DPBF
Tube/Bulk
55
IRS2453DSPBF
Tape and Reel
2500
IRS2453DSTRPBF
Tube/Bulk
55
IRS24531DSPBF
Tape and Reel
2500
IRS24531DSTRPBF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no
responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of
patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or
otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change
without notice. This document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
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© 2007 International Rectifier
18
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