OKI ML9092-02 Lcd driver with key scanner and ram Datasheet

OKI Semiconductor
ML9092-01/02/03/04
FEDL9092-01
Issue Date: Nov. 4, 2003
LCD Driver with Key Scanner and RAM
GENERAL DESCRIPTION
The ML9092-01/02/03/04 are LCD drivers that have internal RAM and a key scan function. They are best suited
for car audio displays.
Since 1-bit data of the display data RAM corresponds to the light-on or light-off of 1-dot of the LCD panel (a bit
map system), a flexible display is possible.
A graphic display system of a maximum of 60 × 10 dots (56 × 10 dots for ML9092-01, 60 × 10 dots for
ML9092-02/03/04). can be implemented.
The ML9092-01/02 do not require any power supply circuit to drive the LCD, because they have internal voltage
doublers. (If a large-sized panel is driven, use the ML9092-03, to which the LCD driving voltage is supplied
externally.)
The internal key scan circuit (5 × 5 key scanning for ML9092-01/04, 6 × 4 key scanning for ML9092-02/03) has
eliminated the needs of key scanning by the CPU, thereby enabling the efficient use of the CPU ports.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Logic voltage
LCD drive voltage
Segment output
Common output
Built-in bit-mapped RAM
: 4.5 to 5.5 V
: 4.5 to 16.5 V (positive voltage)
: 56 outputs for ML9092-01; 60 outputs for ML9092-02/03/04
: 10 outputs
: 60 × 10 = 600 bits (for ML9092-01 only: 56 × 10 = 560 bits for the RAM
display area)
4-pin serial interface with CPU: CS, CP, DI/O, KREQ
Built-in LCD drive bias resistors
Built-in voltage doubler circuit
For the ML9092-01/04, the built-in 5 × 5 key scanner makes it possible to read the status of 25 key switches and
1-channel rotary encoder. In addition, the ML9092-01/04 have an 8-bit, 3-channlel PWM circuit built in.
For the ML9092-02/03, the built-in 6 × 4 key scanner makes it possible to read the status of 24 key switches and
1-channel rotary encoder.
Port A output
: 1 pin, output current = –15 mA
: Can be used for LED driving
Port B output
: 3 pins, output current = –2 mA
: Applies to ML9092-01/04 (capable of PWM
output)
Port C output
: 5 pin, output current = –2 mA
: Applies to ML9092-01 only
Port D output
: 5 pins, output current = –2 mA
: Applies to ML9092-01 only
Temperature range
: –40 to +85°C
Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K)
(Product name: ML9092-01TB, ML9092-02TB, ML9092-03TB, ML9092-04TB)
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FEDL9092-01
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ML9092-01/02/03/04
Comparison between the ML9092-01, ML9092-02, ML9092-03, and ML9092-04
Item
Number of common outputs
Number of dots on the LCD screen
(selectable by program)
ML9092-01
ML9092-02
ML9092-03
ML9092-04
10 Max.
10 Max.
10 Max.
10 Max.
8 × 56
8 × 60
8 × 60
8 × 60
9 × 56
9 × 60
9 × 60
9 × 60
10 × 56
10 × 60
10 × 60
10 × 60
Number of port A outputs
1
1
1
1
Number of port B outputs
3
0
0
3
5 each
0
0
0
5 × 5 key scan
4 × 6 key scan
4 × 6 key scan
5 × 5 key scan
1 channel
1 channel
1 channel
1 channel
Yes
Yes
No
No
8-bit, 3-channel
No
No
8-bit, 3-channel
Number of port C and D outputs (see
note below)
Key scan (see note below)
Rotary encoder
Voltage doubler
PWM circuit
Note: The key scan function and port C/D cannot be used concurrently. Use either.
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
BLOCK DIAGRAM
ML9092-01
10 Output
Common
Drivers
Voltage
Doubler
PB2 SEG1
56 Output
Segment Drivers
3 Port
Drivers
Shift
Register
CS
CP
DI/O
Y Address Decoder
Y Address Counter
Y Address Register
Data Latch
Display Data RAM
56 × 10 Bit
I/O
Buffer
Control
Register
V2
LCD Bias
Voltage
Driving
Circuit
Input Output
Interface
V0
SEG56
Display Line Counter
VIN
VS1–
VC1+
VOUT
COM10 PB0
Line Address Decoder
COM1
X Address Decoder
X Address Counter
Timing
Generator
X Address Register
OSC1
OSC2
Oscillation
Circuit
5 × 5 Key Scan/10 Port Drivers
and Encoder Switch Interface
1 Port Driver
RESET
TEST
VDD
VSS
PA0
KPS
C0/ C1/
D0 D1
C2/ C3/
D2 D3
C4/ R0/ R1/ R2/ R3/ R4/ A
D4 C0 C1 C2 C3 C4
B KREQ
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FEDL9092-01
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ML9092-01/02/03/04
ML9092-02
CS
CP
DI/O
LCD Bias
Voltage
Driving
Circuit
Y Address Decoder
Data Latch
Y Address Counter
Shift Register
Display Data RAM
60 × 10 Bit
I/O Buffer
Display Line Counter
SEG60
60 Output Segment Drivers
Y Address Register
V2
SEG1
10 Output
Common Drivers
Control
Register
V0
Voltage
Doubler
Input Output
Interface
VIN
VS1–
VC1+
VOUT
COM10
Line Address Decoder
COM1
X Address Decoder
X Address Counter
Timing
Generator
X Address Register
OSC1
OSC2
Oscillation
Circuit
1 Port Driver
4 × 6 Key Scan
and Encoder Switch Interface
RESET
TEST
VDD
VSS
PA0
C0 C1 C2 C3 R0 R1 R2 R3 R4 R5
A B KREQ
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FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
ML9092-03
V0
V1
V2
SEG1
SEG60
10 Output
Common Drivers
60 Output Segment Drivers
Shift Register
Data Latch
LCD Bias
Voltage
Driving
Circuit
CP
DI/O
Y Address Decoder
Y Address Counter
Display Data RAM
60 × 10 BIT
I/O Buffer
Control
Register
CS
Input Output
Interface
Y Address Register
V3
Display Line Counter
VHIN
COM10
Line Address Decoder
COM1
X Address Decoder
X Address Counter
Timing
Generator
X Address Register
OSC1
OSC2
Oscillation
Circuit
1 Port Driver
4 × 6 Key Scan
and Encoder Switch Interface
RESET
TEST
VDD
VSS
PA0
C0 C1 C2 C3 R0 R1 R2 R3 R4 R5
A B KREQ
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FEDL9092-01
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ML9092-01/02/03/04
ML9092-04
DI/O
Y Address Decoder
Data Latch
Display Data RAM
60 × 10 Bit
I/O
Buffer
Control
Register
CP
Input Output
Interface
CS
SEG60
60 Output
Segment Drivers
Shift
Register
Y Address Register
V2
LCD Bias
Voltage
Driving
Circuit
3 Port
Drivers
Y Address Counter
V0
10 Output
Common
Drivers
PB2 SEG1
Display Line Counter
VHIN
COM10 PB0
Line Address Decoder
COM1
X Address Decoder
X Address Counter
Timing
Generator
X Address Register
OSC1
OSC2
Oscillation
Circuit
5 × 5 Key Scan
and Encoder Switch Interface
1 Port Driver
RESET
TEST
VDD
VSS
PA0
C0
C1
C2
C3
C4 R0
R1 R2
R3 R4 A
B KREQ
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FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
PIN CONFIGURATION (TOP VIEW)
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
PB0
PB1
PB2
PA0
KPS
TEST
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
VDD
SEG56
95
76
SEG55
96
OSC2
SEG54
97
OSC1
SEG53
98
77
SEG52
99
78
SEG51
100
ML9092-01
SEG50
1
75
VIN
SEG49
2
74
VC1+
SEG48
3
73
VS1-
SEG47
4
72
VOUT
SEG46
5
71
VO
SEG45
6
70
NC
SEG44
7
69
V2
SEG43
8
68
VSS
SEG42
9
67
RESET
SEG41
10
66
KREQ
SEG40
11
65
DI/O
SEG39
12
64
CP
SEG38
13
63
CS
SEG37
14
62
C0/D0
SEG36
15
61
C1/D1
SEG35
16
60
C2/D2
SEG34
17
59
C3/D3
SEG33
18
58
C4/D4
SEG32
19
57
R0/C0
SEG31
20
56
R1/C1
SEG30
21
55
R2/C2
SEG29
22
54
R3/C3
SEG28
23
53
R4/C4
SEG27
24
52
A
SEG26
25
51
B
38
39
40
41
42
43
44
45
46
47
48
49
50
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG18
SEG14
33
SEG19
37
32
SEG20
36
31
SEG21
SEG15
30
35
29
SEG22
SEG16
28
SEG23
34
27
SEG24
SEG17
26
SEG25
ML9092-01
100-Pin Plastic TQFP
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FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
PA0
TEST
OSC2
OSC1
VDD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
ML9092-02
SEG50
1
75
VIN
SEG49
2
74
VC1+
SEG48
3
73
VS1-
SEG47
4
72
VOUT
SEG46
5
71
VO
NC
SEG45
6
70
SEG44
7
69
V2
SEG43
8
68
VSS
SEG42
9
67
RESET
SEG41
10
66
KREQ
SEG40
11
65
DI/O
SEG39
12
64
CP
SEG38
13
63
CS
SEG37
14
62
C0
SEG36
15
61
C1
SEG35
16
60
C2
SEG34
17
59
C3
SEG33
18
58
R0
SEG32
19
57
R1
SEG31
20
56
R2
SEG30
21
55
R3
SEG29
22
54
R4
SEG28
23
53
R5
SEG27
24
52
A
SEG26
25
51
B
42
43
44
45
46
47
48
49
50
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG10 41
SEG11 40
SEG12 39
SEG13 38
SEG14 37
SEG15 36
SEG16 35
SEG17 34
SEG18 33
SEG19 32
SEG20 31
SEG21 30
SEG22 29
SEG23 28
SEG24 27
SEG25 26
ML9092-02
100-Pin Plastic TQFP
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FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
PA0
TEST
OSC2
OSC1
VDD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
ML9092-03
SEG50
1
75
NC
SEG49
2
74
VHIN
SEG48
3
73
V0
SEG47
4
72
V1
SEG46
5
71
NC
SEG45
6
70
V2
SEG44
7
69
V3
SEG43
8
68
VSS
SEG42
9
67
RESET
SEG41
10
66
KREQ
SEG40
11
65
DI/O
SEG39
12
64
CP
SEG38
13
63
CS
SEG37
14
62
C0
SEG36
15
61
C1
SEG35
16
60
C2
SEG34
17
59
C3
SEG33
18
58
R0
SEG32
19
57
R1
SEG31
20
56
R2
SEG30
21
55
R3
SEG29
22
54
R4
SEG28
23
53
R5
SEG27
24
52
A
SEG26
25
51
B
38
39
40
41
42
43
44
45
46
47
48
49
50
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG18
37
33
SEG14
32
SEG19
36
31
SEG20
SEG15
30
SEG21
35
29
SEG22
SEG16
28
SEG23
34
27
SEG24
SEG17
26
SEG25
ML9092-03
100-Pin Plastic TQFP
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FEDL9092-01
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ML9092-01/02/03/04
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
PB0
PB1
PB2
PA0
TEST
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
ML9092-04
SEG50
1
75
OSC2
SEG49
2
74
OSC1
SEG48
3
73
VDD
SEG47
4
72
VHIN
SEG46
5
71
Vo
SEG45
6
70
NC
SEG44
7
69
V2
SEG43
8
68
VSS
SEG42
9
67
RESET
SEG41
10
66
KREQ
SEG40
11
65
DI/O
SEG39
12
64
CP
SEG38
13
63
CS
SEG37
14
62
C0
SEG36
15
61
C1
SEG35
16
60
C2
SEG34
17
59
C3
SEG33
18
58
C4
SEG32
19
57
R0
SEG31
20
56
R1
SEG30
21
55
R2
SEG29
22
54
R3
SEG28
23
53
R4
SEG27
24
52
A
SEG26
25
51
B
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
ML9092-04
100-Pin Plastic TQFP
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FEDL9092-01
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ML9092-01/02/03/04
FUNCTIONAL DESCRIPTIONS
Pin Functional Descriptions
ML9092-01
Function
CPU interface
Pin
Symbol
Type
63
CS
I
Chip select signal input pin
64
CP
I
Shift clock signal input pin. This pin is
connected to the Schmitt circuit internally.
65
DI/O
I/O
Serial data signal I/O pin. This pin is
connected to the Schmitt circuit internally.
66
KREQ
O
Key scan read and rotary encoder read
READY signal output pin.
77
OSC1
I
78
OSC2
O
Oscillation
Port output
67
RESET
I
80
KPS
I
Input pin for switching between key
scanning and ports C and D
79
TEST
I
Test input pin. This pin is connected to the
VSS pin.
62–58
C0/D0–C4/D4
I/O
Input pins that detect status of key
switches/port D output pins. When used
as input pins, these pins are connected to
the Schmitt circuit internally.
57–53
R0/C0–R4/C4
O
Key switch scan signal output pins/port C
output pins
51, 52
A, B
I
Rotary encoder signal input pins.
These pins are connected to the Schmitt
circuit internally.
81
PA0
O
Port A output pin
84–82
PB0–PB2
O
Port B output pins
SEG1–SEG56
O
LCD segment driver output pins
94–85
COM1–COM10
O
LCD common driver output pins
76
VDD
—
Logic power supply pin
68
VSS
—
GND pin
75
VIN
—
Voltage doubler reference voltage input
pin
74, 73
VC1+, VS1–
—
Pins to connect a capacitor for voltage
doubler
72
VOUT
—
Voltage doubler output pin
71, 69
V0, V2
—
LCD bias pins
70
NC
—
Should be left open.
50–1
LCD driver output
Power supply
Connect external resistors with this pin.
This pin is connected to the Schmitt circuit
internally.
If using an external clock, input it from the
OSC1 pin and leave the OSC2 pin open.
Reset input. Initial settings can be
established by applying a “L” level to this
pin. This pin is connected to the Schmitt
circuit internally.
Control signal
Switch signal
Description
100–95
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FEDL9092-01
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ML9092-01/02/03/04
ML9092-02
Function
CPU interface
Pin
Symbol
Type
63
CS
I
Chip select signal input pin
64
CP
I
Shift clock signal input pin. This pin is
connected to the Schmitt circuit internally.
65
DI/O
I/O
Serial data signal I/O pin. This pin is
connected to the Schmitt circuit internally.
66
KREQ
O
Key scan read and rotary encoder read
READY signal output pin.
77
OSC1
I
78
OSC2
O
Oscillation
Port output
67
RESET
I
79
TEST
I
Test input pin. This pin is connected to the
VSS pin.
62–59
C0–C3
I
Input pins that detect status of key
switches. These pins are connected to the
Schmitt circuit internally.
58–53
R0–R5
O
Key switch scan signal output pins
51, 52
A, B
I
Rotary encoder signal input pins.
These pins are connected to the Schmitt
circuit internally.
80
PA0
O
Port A output pin
SEG1–SEG60
O
LCD segment driver output pins
50–1
LCD driver output
Power supply
Connect external resistors with this pin.
This pin is connected to the Schmitt circuit
internally.
If using an external clock, input it from the
OSC1 pin and leave the OSC2 pin open.
Reset input. Initial settings can be
established by applying a “L” level to this
pin. This pin is connected to the Schmitt
circuit internally.
Control signal
Switch signal
Description
100–91
90–81
COM1–COM10
O
LCD common driver output pins
76
VDD
—
Logic power supply pin
68
VSS
—
GND pin
75
VIN
—
Voltage doubler reference voltage input
pin
74, 73
VC1+, VS1–
—
Pins to connect a capacitor for voltage
doubler
72
VOUT
—
Voltage doubler output pin
71, 69
V0, V2
—
LCD bias pins
70
NC
—
Should be left open.
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FEDL9092-01
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ML9092-03
Function
CPU interface
Pin
Symbol
Type
63
CS
I
Chip select signal input pin
64
CP
I
Shift clock signal input pin. This pin is
connected to the Schmitt circuit internally.
65
DI/O
I/O
Serial data signal I/O pin. This pin is
connected to the Schmitt circuit internally.
66
KREQ
O
Key scan read and rotary encoder read
READY signal output pin.
77
OSC1
I
78
OSC2
O
Oscillation
Port output
67
RESET
I
79
TEST
I
Test input pin. This pin is connected to the
VSS pin.
62–59
C0–C3
I
Input pins that detect status of key
switches. These pins are connected to the
Schmitt circuit internally.
58–53
R0–R5
O
Key switch scan signal output pins
51, 52
A, B
I
Rotary encoder signal input pins.
These pins are connected to the Schmitt
circuit internally.
80
PA0
O
Port A output pin
SEG1–SEG60
O
LCD segment driver output pins
50–1,
LCD driver output
Power supply
Connect external resistors with this pin.
This pin is connected to the Schmitt circuit
internally.
If using an external clock, input it from the
OSC1 pin and leave the OSC2 pin open.
Reset input. Initial settings can be
established by applying a “L” level to this
pin. This pin is connected to the Schmitt
circuit internally.
Control signal
Switch signal
Description
100–91
90–81
COM1–COM10
O
LCD common driver output pins
76
VDD
—
Logic power supply pin
68
VSS
—
GND pin
74
VHIN
—
High-voltage power supply pin
73, 72, 70, 69
V0, V1, V2, V3
—
LCD bias pins
75, 71
NC
—
Should be left open.
13/66
FEDL9092-01
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ML9092-01/02/03/04
ML9092-04
Function
CPU interface
Pin
Symbol
Type
63
CS
I
Chip select signal input pin
64
CP
I
Shift clock signal input pin. This pin is
connected to the Schmitt circuit internally.
65
DI/O
I/O
Serial data signal I/O pin. This pin is
connected to the Schmitt circuit internally.
66
KREQ
O
Key scan read and rotary encoder read
READY signal output pin.
74
OSC1
I
75
OSC2
O
Oscillation
Port output
67
RESET
I
76
TEST
I
Test input pin. This pin is connected to the
VSS pin.
62–58
C0–C4
I
Input pins that detect status of key
switches. These pins are connected to the
Schmitt circuit internally.
57–53
R0–R4
O
Key switch scan signal output pins
51, 52
A, B
I
Rotary encoder signal input pins.
These pins are connected to the Schmitt
circuit internally.
77
PA0
80–78
PB0–PB2
50–1,
LCD driver output
Power supply
Connect external resistors with this pin.
This pin is connected to the Schmitt circuit
internally.
If using an external clock, input it from the
OSC1 pin and leave the OSC2 pin open.
Reset input. Initial settings can be
established by applying a “L” level to this
pin. This pin is connected to the Schmitt
circuit internally.
Control signal
Switch signal
Description
O
Port A output pin
Port B output pins
SEG1–SEG60
O
LCD segment driver output pins
90–81
COM1–COM10
O
LCD common driver output pins
73
VDD
—
Logic power supply pin
68
VSS
—
GND pin
72
VHIN
—
High-voltage power supply pin
71, 69
V0, V2
—
LCD bias pins
70
NC
—
Should be left open.
100–91
14/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
• CS
Chip select input pin. A Schmitt circuit is internally connected to this pin. An “L” level selects the chip, and an
“H” level does not select the chip. During the “L” level, internal registers can be accessed.
• CP
Clock input pin for serial interface data I/O. A Schmitt circuit is internally connected to this pin. Data input to the
DI/O pin is synchronized to the rising edge of the clock. Output from the DI/O pin is synchronized to the falling
edge of the clock.
• DI/O
Serial interface data I/O pin. A Schmitt circuit is internally connected to this pin. This pin is in the output state
only during the interval beginning when commands for key scan data read, RAM read or rotary encoder are written
until the CS signal rises. At all other times this pin is in the input state. (When reset, the input state is set.) The
relation between data level of this pin and operation is listed below.
Data level
LCD display
Key status
Rotary switch
“H”
Light ON
ON
Count value
“L”
Light OFF
OFF
Count value
• KREQ
Key scan read and rotary encoder read READY signal output pin.
• OSC1
Input pin for RC oscillation. A Schmitt circuit is internally connected to this pin. An oscillation circuit is
configured by connecting this pin and OSC2 with a resistor (R) placed across the connection (see figure below).
Make the wiring between this pin and the resistor as short as possible. If an external master oscillation clock is to
be input, input the master oscillation clock to this pin.
OSC1
R = 56 kΩ
(VDD = 4.5 to 5.5 V)
R
OSC2
• OSC2
Output pin for RC oscillation. A Schmitt circuit is internally connected to this pin. An oscillation circuit is
configured by connecting this pin and OSC1 with a resistor (R) placed across the connection (see figure above).
Make the wiring between this pin and the resistor as short as possible. If an external master oscillation clock is to
be input, leave this pin unconnected (open).
• RESET
Reset signal input pin. A Schmitt circuit is internally connected to this pin. The initial state can be set by pulling
this pin to an “L” level. Refer to the “Output, I/O and Register States in Response to Reset Input” page for the
initial states of each register and display.
An internal pull-up resistor is connected to this pin. Connecting an external capacitor enables power-on reset.
• TEST
Test signal input pin. Connect this pin to VSS.
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FEDL9092-01
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• R0/C0 to R4/C4 (ML9092-01), R0 to R5 (ML9092-02/03), R0 to R4 (ML9092-04)
Key switch scan signal output pins. During the scan operation, “L” level signals are output in the order of R0/C0,
R1/C1, ..., R4/C4 (ML9092-01) or R0, R1, ..., R5 (ML9092-02/03) or R0, R1, ..., R4 (ML9092-04). (Refer to the
description under the heading “Key scan” for details.) For the ML9092-01, R0 to R4 can be used as the output
ports for the general-purpose port C depending on the input signal to the KPS pin.
• C0/D0 to C4/D4 (ML9092-01), C0 to C3 (ML9092-02/03), C0 to C4 (ML9092-04)
Input pins that detect the key switch status. Pull-up resistors and a Schmitt circuit are internally connected to these
pins. Assemble a key matrix between these pins and the R0/C0 to R4/C4 (ML9092-01) or R0 to R5
(ML9092-02/03) or R0 to R4 (ML9092-04) pins. For the ML9092-01, C0 to C4 can be used as the output ports for
the general-purpose port D depending on the input signal to the KPS pin.
• KPS
Input pin that selects whether the R0/C0 to R4/C4 pins and C0/D0 to C4/D4 pins are used to detect the key switch
status or whether they are used as the output pins for the general-purpose ports C and D. When this pin is pulled to
a “H” level, the R0/C0 to R4/C4 pins and C0/D0 to C4/D4 pins function as pins that detect the key switch status.
When this pin is pulled to a “L” level, it functions as the output pin for the general-purpose ports C and D. This pin
must be fixed at either a “H” or “L” level.
This pin is provided only for the ML9092-01.
• A, B
Input pins for encoder format rotary switches. A Schmitt circuit is internally connected to these pins. When
turning the rotary switch clockwise, input to the A pin a signal more advancing in phase than the B pin. When
turning the rotary switch counterclockwise, input to the B pin a signal more advancing in phase than the A pin.
• PA0
General-purpose port A output pin. This pin can output a current of –15 mA. If this pin is used to drive an LED,
insert an external current limiting resistor in series with the LED. If this pin is not used, leave it unconnected
(open).
• PB0 to PB2
Port B pins, which are used for PWM outputs. These pins are provided for the ML9092-01/04. Any pins not to be
used should be left unconnected (open).
• SEG1 to SEG60(56)
Segment signal output pins for LCD driving. Any pins not to be used should be left unconnected (open). For the
ML9092-01, only SEG1 to SEG56 apply.
• COM1 to COM10
Common signal output pins for LCD driving. Any pins not to be used should be left unconnected (open).
• VDD
Logic power supply connection pin.
• VSS
Power supply GND connection pin.
• VIN
Voltage doubler reference voltage input pin. A voltage twice that which is input to this pin is output to the VOUT
pin. When the voltage doubler is not used, connect this pin to GND.
This pin is provided for the ML9092-01/02.
16/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
• VS1–
Negative connection pin for the capacitor for the voltage doubler. Connect a 4.7 µF (±30%) capacitor between this
pin and the VC1+ pin. When the voltage doubler is not used, leave this pin unconnected (open).
This pin is provided for the ML9092-01/02.
• VC1+
Positive connection pin for the capacitor for the voltage doubler. Connect a 4.7 µF (±30%) capacitor between this
pin and the VS1– pin. When the voltage doubler is not used, leave this pin unconnected (open).
This pin is provided for the ML9092-01/02.
• VOUT
A voltage twice that which is input to the VIN pin is output to this pin. Connect a 4.7 µF capacitor between this pin
and the VSS pin. When the internal voltage doubler is not used, input the specified voltage to this pin from the
outside. When built-in contrast adjustment (electronic volume) is used, leave the connection between this pin and
the V0 pin open. The LCD drive voltage will be output from the V0 pin according to the contrast adjustment value.
When built-in contrast adjustment is not used, connect this pin with the V0 pin.
This pin is provided for the ML9092-01/02.
• V0, V2
LCD bias pins. A bias dividing resistor is connected to these pins.
These pins are provided for the ML9092-01/02/04.
• VHIN
LCD drive high voltage power supply connection pin. When built-in contrast adjustment (electronic volume) is
used, input the LCD drive power supply voltage to this pin. The LCD drive voltage will be output from the V0 pin
according to the contrast adjustment value. When built-in contrast adjustment is not used, strap the VHIN pin and
V0 pin outside the IC, and input the LCD drive voltage into both pins.
This pin is provided for the ML9092-03/04.
• V0, V1, V2, V3
LCD bias pins. A bias dividing resistor is connected to these pins. When using a large-screen LCD, however,
input the LCD bias voltage from outside the IC to these pins.
This is applicable to the ML9092-03.
17/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Applicable Pins
Power Supply Voltage
VDD
Ta = 25°C
–0.3 to +6.5
V
VDD
High Power Supply Voltage
VH
Ta = 25°C
–0.3 to +18.0
V
VOUT, VHIN
Bias Voltage
VBI
Ta = 25°C
–0.3 to VOUT
(VHIN) + 0.3
V
VC1+, V0, V1, V2, V3
Voltage Doubler Reference
Voltage
VIN
Ta = 25°C
–0.3 to VDD + 0.3
V
VIN
CS, CP, DI/O, OSC1,
C0 to C3,
Input Voltage
Output Current
VI
IO
Ta = 25°C
–0.3 to VDD + 0.3
V
Ta = 25°C
–20 to +3
mA
Ta = 25°C
–3 to +4
mA
C0 to C4, C0/D0 to
C4/D4, KPS, A, B,
RESET
PA0
PB0 to PB2, R0/C0 to
R4/C4, C0/D0 to
C4/D4, R0 to R4,
R0 to R5, DI/O, KREQ
Power Dissipation
PD
Ta = 85°C
190
mW
—
Storage Temperature
Tstg
—
–55 to +150
°C
—
VSS is the reference voltage potential for all pins.
18/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Symbol
VDD
Condition
Range
Unit
Applicable Pins
—
4.5 to 5.5
V
VDD
4.5 to 16.5
V
VOUT
4.0 to 16.5
V
VOUT, V0
4.5 to 16.5
V
VHIN
4.0 to 16.5
V
VHIN, V0
Voltage doubler
not used
(Contrast
adjustment used)
Externally Input Power
Supply Voltage 1
VOUT
(Applies to ML9092-01/02)
Voltage doubler
not used & VOUT
pin connected
with V0 pin
(Contrast
adjustment not
used)
Contrast
adjustment used
Externally Input Power
Supply Voltage 2
VHIN
(Applies to ML9092-03/04)
Contrast
adjustment not
used
(VHIN pin
connected with
V0 pin)
Bias Voltage
V0
—
4.0 to 16.5
V
V0
Voltage Doubler Input
Voltage
VIN
—
0.8VDD to VDD
V
VIN
Operating Frequency of
External Clock
fOPE
—
210 to 445
kHz
OSC1
Oscillation Resistance
R
VDD = 4.5 to 5.5 V
56*1
kΩ
OSC1, OSC2
Operating Temperature
Top
—
–40 to +85
°C
—
VSS is the reference voltage potential for all pins.
*1:
Use a resistor with an accuracy of ±2 %
OSC1
R
OSC2
19/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
ELECTRICAL CHARACTERISTICS
Oscillating Frequency Characteristics
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85°C)
Parameter
Symbol
Oscillating Frequency
fOSC
Condition
56 kΩ
(resistor with accuracy within ±2%)
Min.
Typ.
Max.
Unit
Applicable Pins
210
306
445
kHz
OSC1, OSC2
DC Characteristics
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85°C)
Parameter
Symbol
“H” Input Voltage 1
VIH1
“H” Input Voltage 2
VIH2
“H” Input Voltage 3
VIH3
“H” Input Voltage 4
Condition
When input
externally
Min.
Typ.
Max.
Unit
Applicable Pins
0.85VDD
—
—
V
OSC1
—
0.85VDD
—
—
V
RESET
—
0.85VDD
—
—
V
C0/D0–C4/D4,C0–C4
CS, DI/O
VIH4
—
0.8VDD
—
—
V
KPS
“L” Input Voltage 1
VIL1
When input
externally
—
—
0.15VDD
V
OSC1
“L” Input Voltage 2
VIL2
—
—
—
0.15VDD
V
RESET
“L” Input Voltage 3
VIL3
—
—
—
0.15VDD
V
CP, A , B, CS, DI/O,
“L” Input Voltage 4
VIL4
—
—
—
0.2VDD
V
KPS
“L” Input Voltage 5
VIL5
—
—
—
0.23VDD
V
“H” Input Current 1
IIH1
VI = VDD
—
—
10
µA
“H” Input Current 2
IIH2
VI = VDD
—
—
10
µA
“H” Input Current 3
IIH3
DI/O = Input mode,
All ports = HiZ,
VI = VDD
—
—
10
µA
“H” Input Current 4
IIH4
VI = VDD
—
—
1
µA
CP, A, B, C0–C3,
C0/D0–C4/D4,C0–C3,
C0–C4
RESET
C0/D0–C4/D4,
C0–C3, C0–C4
DI/O, PA0, PB0–PB2,
R0/C0–R4/C4,
C0/D0–C4/D4
OSC1, CS, CP,
KPS , A , B
“L” Input Current 1
IIL1
VDD = 5 V, VI = 0 V
–0.1
–0.05
–0.02
mA
“L” Input Current 2
IIL2
VDD = 5 V, VI = 0 V
–0.9
–0.45
–0.18
mA
“L” Input Current 3
IIL3
DI/O = Input mode,
All ports = HiZ,
VI = 0 V
–10
—
—
µA
“L” Input Current 4
IIL4
VI = 0 V
–1
—
—
µA
RESET
C0/D0–C4/D4,
C0–C3,C0–C4
DI/O, PA0, PB0–PB2,
R0/C0–R4/C4,
C0/D–C4/D4
OSC1, CS, CP, KPS, A,
B
20/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Parameter
Symbol
VOH1
“H” Output Voltage 2
VOH2
“H” Output Voltage 3
VOH3
“H” Output Voltage 1
“H” Output Voltage 4
VOH4
“H” Output Voltage 5
VOH5
“L” Output Voltage 1
“L” Output Voltage 2
VOL1
VOL2
“L” Output Voltage 3
VOL3
“L” Output Voltage 4
VOL4
Condition
IO = –0.4 mA
IO = –40 µA
IO = –15 mA
IO = –2 mA
(When R0/C0–
R4/C4 and
C0/D0–C4/D4 are
used as ports C
and D)
IO = –50 µA
(When R0/C0–
R4/C4 are used
for key scanning)
IO = 0.4 mA
IO = 40 µA
IO = 1 mA
(When R0/C0–
R4/C4 and
C0/D0–C4/D4 are
used as ports C
and D)
IO = 2.7 mA
(When R0/C0–
R4/C4 are used
for key scanning)
Min.
VDD – 0.4
0.9VDD
VDD – 1.7
Typ.
—
—
—
Max.
—
—
—
Unit
V
V
V
Applicable Pins
DI/O, KREQ
OSC2
PA0
VDD – 1.2
—
—
V
Only applies to
ML9092-01.
PB0–PB2,
R0/C0–R4/C4,
C0/D0–C4/D4
VDD – 2.0
—
—
V
R0/C0–R4/C4(-01),
R0–R5 (-02, -03)
R0–R4 (-04)
—
—
—
—
0.4
0.1VDD
V
V
DI/O, KREQ
OSC2
—
—
0.4
V
PA0, PB0–PB2,
C0/D0–C4/D4,
R0/C0–R4/C4
—
—
0.3
V
R0/C–R4/C4 (-01),
R0–R5 (-02, -03)
R0–R4 (-04)
21/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85°C)
Parameter
Segment Output
Voltage 2
(1/5 bias)
Common Output
Voltage 1
(1/4 bias)
Supply Current 1
(Applies to
ML9092-01/02)
Supply Current 2
(Applies to
ML9092-01/02)
Supply Current 3
(Applies to
ML9092-01/02)
Supply Current 4
(Applies to
ML9092-01/02)
Supply Current 5
(Applies to
ML9092-03/04)
Supply Current 6
(Applies to
ML9092-03/04)
Supply Current 7
(Applies to
ML9092-03/04)
Supply Current 8
(Applies to
ML9092-03/04)
*1:
*2:
*3:
*4:
*5:
*6:
Symbol
Condition
Min.
Typ.
Max.
Unit
VOS0
IO = –10 µA
V0 – 0.6
—
—
V
VOS1
IO = ±10 µA
2/4V0 – 0.6
—
2/4V0 + 0.6
V
VOS2
IO = ±10 µA
2/4V0 – 0.6
—
2/4V0 + 0.6
V
Applicable
Pins
SEG1–SEG56
(SEG60 for
ML9092-02/03
/04)
VOS3
IO = +10 µA
—
—
VSS + 0.6
V
VOC0
IO = –10 µA
V0 – 0.3
—
—
V
VOC1
IO = ±10 µA
3/4V0 – 0.3
—
3/4V0 + 0.3
V
VOC2
IO = ±10 µA
1/4V0 – 0.3
—
1/4V0 + 0.3
V
VOC3
IO = +10 µA
—
—
VSS + 0.3
V
—
—
0.6
mA
VDD
—
—
0.6
mA
VDD
—
—
2
mA
VIN
—
—
1
mA
VOUT
—
—
0.6
mA
VDD
IDD1
IDD2
IVIN
IVHIN1
IDD3
R = 56 kΩ
Voltage doubler operating,
No load
*1
External clock = 445 kHz
Voltage doubler operating,
No load
*2
External clock = 445 kHz
Voltage doubler operating,
No load
*2
External clock = 445 kHz
Voltage doubler not operating,
No load
*3
R = 56 kΩ
No load
*4
COM1–
COM10
IDD4
External clock = 445 kHz
No load
*5
—
—
0.6
mA
VDD
IVHIN2
External clock = 445 kHz
No load
*5
—
—
1
mA
VHIN
IDD5
R = 56 kΩ
Voltage doubler not operating,
No load
*6
—
—
100
µA
VDD
Refer to the Current Measuring Circuit 1.
Refer to the Current Measuring Circuit 2.
Refer to the Current Measuring Circuit 3.
Refer to the Current Measuring Circuit 4.
Refer to the Current Measuring Circuit 5.
Refer to the Current Measuring Circuit 6.
22/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Parameter
Symbol
Voltage doubler
Voltage
VDB
VLCDMAX
LCD driving
voltage when
internal variable
resistor is used
VLCDMIN
LCD Driving
Bias Resistance
*1
*3
LBR
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85°C)
Applicable
Condition
Min.
Typ.
Max.
Unit
Pins
External clock = 210 kHz
9.8
VIN = 0.8 VDD to VDD
V
VOUT
VIN × 1.9 – 0.5
VIN × 2
*3
(*1)
VDD = 5 V, VOUT = 10 V
(Voltage doubler not
operating, but voltage
9.5
9.8
10
V
applied externally)
Contrast data = FH,
No load
V0 – VSS
VDD = 5 V, VOUT = 10 V
(Voltage doubler not
operating, but voltage
6.7
7
7.3
V
applied externally)
Contrast data = 0H,
No load
(*2)
5
9
14
kΩ
V0 – Vss
Refer to the Voltage Doubler Voltage Measuring Circuit.
VIN = 5 V, Ta = 25°C
LBR
*2
V0
V1
LBR
LBR
LBR
V2
V3
VSS
23/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Measuring Circuits
Voltage Doubler Voltage Measuring Circuit
Voltage is doubled
(1/4 bias)
OPEN
SEG1–SEG56(60)
VDD
VIN
COM1–COM10
VDD
VIN
VC1+
+
4.7µF
±30% –
A
B
VS1–
VSS
4.7µF ±30%
VOUT
+
VDB
KREQ
OPEN
PA0
OPEN
OSC2
OPEN
VO
V
100µA
OSC1
OPEN
V2
TEST
KPS
VDD
CP
DI/O
RESET
*1
CS
f = 210 kHz
VDD
(C0–C3)
C0/D0–C4/D4
PB0–PB2
(R0–R5)
R0/C0–R4/C4
OPEN
Current Measuring Circuit 1
Current Measuring Circuit 2
Voltage is doubled (external clock)
Voltage is doubled (internal oscillation)
IDD1
IDD2
OPEN
A
OPEN
A
5.5 V
SEG1–SEG56(60)
VDD
5.5 V +
4.7µF
±30% –
IVIN
B
VS1–
VSS
VOUT
VO
OPEN
SEG1–SEG56(60) COM1–COM10
A
VIN
VC1+
4.7 µF±30%
+
5.5 V
COM1–COM10
5.5 V –
4.7µF
±30% +
KREQ
OPEN
PA0
OPEN
OSC2
OSC1
V2
A
VDD
A
VIN
VC1+
B
VS1–
VSS
4.7 µF±30%
VOUT
+
R = 56 kΩ
±2%
VO
KPS
RESET
*1
CS
(C0–C3)
C0/D0–C4/D4
(R0–R5)
CP
R0/C0–R4/C4
DI/O PB0–PB2
OPEN
OPEN
PA0
OPEN
OSC2
OPEN
OSC1
OPEN
V2
TEST
TEST
VDD
KREQ
KPS
VDD
VDD
CS
CP
DI/O
RESET
*1
f = 445 kHz
VDD
(C0–C3)
C0/D0–C4/D4
PB0–PB2
(R0–R5)
R0/C0–R4/C4
OPEN
*1: For ML9092-01, these are SEG1–56, PB0–PB2, KPS, C0/D0–C4/D4, and R0/C0–R4/C4.
For ML9092-02, these are SEG1–60, C0–C3, and R0–R5; PB0–PB2 and KPS are not provided.
24/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Current Measuring Circuit 3
Current Measuring Circuit 4
External LCD voltage applied
(External clock)
External LCD voltage applied
(Internal oscillation)
IDD3
OPEN
OPEN
A
5.5 V
SEG1–SEG56(60)
VDD
OPEN
OPEN
SEG1–SEG60
COM1–COM10
VDD
A
A
VIN
VC1+
VS1–
IVHIN1
A
5.5 V
COM1–COM10
VOUT
VO
B
VHIN
B
VSS
VO
VSS
KREQ
OPEN
PA0
OPEN
OSC2
OPEN
OPEN V1
KREQ
OPEN
OPEN V2
PA0
OPEN
OPEN V3
OSC2
OSC1
OPEN V2
OSC1
f = 445 kHz
TEST
TEST
VDD
KPS
RESET
*1
CS
(C0–C3)
C0/D0–C4/D4
CP
(R0–R5)
R0/C0–R4/C4
DI/O PB0–PB2
VDD
VDD
OPEN
R = 56 kΩ
±2%
CS
CP
DI/O
*2
(C0–C4)
RESET
VDD
(R0–R4)
C0–C3
PB0–PB2
R0–R5
OPEN
Current Measuring Circuit 5
IDD4
External LCD voltage applied
(External clock)—2
OPEN
A
5.5 V
COM1–COM10
SEG1–SEG60
IVHIN2
A
VDD
A
VHIN
B
VO
VSS
OPEN V1
OPEN V2
OPEN V3
KREQ
OPEN
PA0
OPEN
OSC2
OPEN
OSC1
f = 445 kHz
TEST
RESET
VDD
CS
CP
DI/O
VDD
*2
(C0–C4)
PB0–PB2
(R0–R4)
C0–C3
R0–R5
OPEN
*1: For ML9092-01, these are SEG1–56, PB0–PB2, KPS, C0/D0–C4/D4, and R0/C0–R4/C4.
For ML9092-02, these are SEG1–60, C0–C3, and R0–R5; PB0–PB2 and KPS are not provided.
*2: For ML9092-03, these are C0–C3 and R0–R5; PB0–PB2 are not provided.
For ML9092-04, these are C0–C4 and R0–R4; PB0–PB2 are provided.
25/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Current Measuring Circuit 6
External LCD voltage applied
(Internal oscillation)
5.5 V
IDD5
OPEN
A
SEG1–SEG60
VDD
COM1–COM10
A
B
VSS
VHIN
KREQ
OPEN
PA0
OPEN
VO
OPEN V1
OSC2
OPEN V2
OSC1
OPEN V3
TEST
VDD
RESET
*2
CS
(R0–R4)
(C0–C4)
CP
R0–R5
C0–C3
PB0–PB2
DI/O
R = 56 kΩ
±2%
VDD
OPEN
*2: For ML9092-03, these are C0–C3 and R0–R5; PB0–PB2 are not provided.
For ML9092-04, these are C0–C4 and R0–R4; PB0–PB2 are provided.
26/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Switching Characteristics
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85°C)
Symbol
Condition
Min.
Max.
Unit
CP Clock Cycle Time
Parameter
tSYS
—
500
—
ns
CP “H” Pulse Width
tWH
—
200
—
ns
CP “L” Pulse Width
tWL
—
200
—
ns
CS “H” Pulse Width
tWCH
—
100
—
ns
CP Clock Rise/fall Time
tr, tf
—
—
50
ns
CS Setup Time
tCSU
—
30
—
ns
CS Hold Time
tCHD
—
150
—
ns
DI/O Setup Time
tDSU
—
50
—
ns
DI/O Hold Time
tDHD
—
50
—
ns
DI/O Output Delay Time
tDOD
CL = 50 pF
—
100
ns
DI/O Output OFF Delay Time
tDOFF
CL = 50 pF
—
100
ns
RESET Pulse Width
tWRE
—
2
—
µs
External Clock Cycle Time
tSES
—
1612
3389
ns
External Clock “H” Pulse Width
tWEH
—
645
—
ns
External Clock “L” Pulse Width
tWEL
—
645
—
ns
trE, tfE
—
—
50
ns
External Clock Rise/fall Time
Key Scan Characteristics
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85°C)
Parameter
Symbol
Register
setting
KT
Key Scan Period
Tscn
Oscillation frequency
Dividing ratio
210 kHz
Unit
306kHz
445 kHz
0
1/1536
7.3
5.0
3.5
1
1/3072
14.6
10.0
6.9
ms
Frame Frequency, PWM Frequency, and Voltage Doubler Frequency Characteristics
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85°C)
Model
Parameter
ML9092-
Frame
Frequency
01/02/03/04
ML909201/04
ML909201/02
Symbol
FRM
Display duty
Dividing ratio
1/8
Oscillation frequency
210 kHz
306 kHz
445 kHz
1/2560
82
120
174
1/9
1/2520
83
121
177
1/10
1/2560
82
120
174
PWM
Frequency
PWM
—
1/1020
205
300
436
Voltage
Doubler
Frequency
—
—
1/64
3281
4781
6953
Unit
Hz
27/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Switching Characteristics of Rotary Switch
Parameter
Phase Recognition Time (A to B)
Phase Recognition Time (B to A)
Phase Input Fixed Time
Symbol
tSAW
tSBW
tAB
(VDD = 4.5 to 5.5 V, VOUT (VHIN) = 4.5 to 16.5 V, Ta = –40 to +85°C)
Condition
Min.
Typ.
Max. Unit
950
—
—
µs
950
—
—
R = 56 kΩ ±2%,
µs
950
—
—
µs
28/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Clock synchronous serial interface timing diagrams
Clock synchronous serial interface input timing
tWCH
– VIH3
– VIL3
CS
tCSU
tSYS
tr tWH tf
tCHD
tWL
– VIH3
– VIL3
CP
tDHD
tDSU
– VIH3
– VIL3
DI/O
Clock synchronous serial interface input→output timing
tWCH
– VIH3
– VIL3
CS
tCSU
tCHD
tSYS
tr tWH tf
tWL
8th Clock
1st Clock
9th Clock
– VIH3
– VIL3
CP
VIH3
VIL3
DI/O
tDOFF
tDOD
tDHD
tDSU
VIH3
VIL3
Hiz
VOH1
VOL1
VOH1
VOL1
Reset timing
tWRE
RESET
– VIL2
External clock
trE tWEH tfE tWEL
– VIH1
– VIL1
OSC1
tSES
29/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Key scan timing
Tscn
–VDD
Rn
–VSS
Frame frequency
– V0
– V1
COM1
– V3
– VSS
1/FRM
1/FRM
PWM output frequency for port B (applies to ML9092-01/04)
1/PWM
PB0
PB1
PB2
Rotary switch input timing
A
B
tSAW
tAB
tSAW
tAB
tSBW
tAB
tSBW
tAB
30/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Instruction Code List (ML9092-01)
No.
Instruction
Instruction Code
Fixed bit R/W
Register No.
D7 D6 D5 D4 D3 D2 D1
Data
D0
D7
D6
D5
Description
D4
D3
D2
D1
D0
0
Key scan register read
1
1
1
0
0
0
0
0
ST2
ST1
ST0
S4
S3
S2
S1
S0
Reads scan read timing bits (ST0 to ST2) and key scan
data (S0 to S4) of the key scan register.
1
Display data RAM write
1
1
0
0
0
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Writes display data (D0 to D7) in the display data RAM
after setting the X address of Y address.
1
Display data RAM read
1
1
1
0
0
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Reads display data (D0 to D7) from the display data RAM
after setting the X address of Y address.
2
X address register set
1
1
0
0
0
0
1
0
–
–
–
–
X3
X2
X1
X0
Sets the X address (X0 to X3) of the display data RAM.
3
Y address register set
1
1
0
0
0
0
1
1
–
–
–
–
Y3
Y2
Y1
Y0
Sets the Y address (Y0 to Y3) of the display data RAM.
1
1
0
0
0
1
0
0
–
–
–
–
–
–
–
4
Port register A set
5
Port register B set
1
1
0
0
0
1
0
1
–
–
–
6
Port register C set
1
1
0
0
0
1
1
0
–
–
–
7
Port register D set
1
1
0
0
0
1
1
1
–
–
–
INC
WLS
KT
8
Control register 1 set
1
1
0
0
1
0
0
0
PTA0 Controls the output of the general-purpose port A (PTA0).
Controls the output of the general-purpose port B (PTB0
to PTB2).
Controls the output of the general-purpose port C (PTC0
to PTC4).
Controls the output of the general-purpose port D (PTD0
PTD4 PTD3 PTD2 PTD1 PTD0
to PTD4).
–
–
PTB2 PTB1 PTB0
PTC4 PTC3 PTC2 PTC1 PTC0
SHL
BE
PE
DTY1 DTY0
Sets the address increment X or Y direction (INC), display
data word length (WLS), key scan time (KT), common
driver shift direction (SHL), voltage doubler control (BE),
port control (PE), and display duty (DTY0, DTY1).
9
Control register 2 set
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
A
Rotary encoder read
1
1
1
0
1
0
1
0
Q4
Q4
Q4
Q4
Q4
Q3
Q2
Q1
B
Contrast ADJ set
1
1
0
0
1
0
1
1
–
–
–
–
CT3
CT2
CT1
Sets contrast adjustment values with the contrast
CT0 adjustment bits (CT0 to CT3).
C
PWM0 register set
1
1
0
0
1
1
0
0
PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00
D
PWM1 register set
1
1
0
0
1
1
0
1
Sets the pulse width to be output from general-purpose
PW17 PW16 PW15 PW14 PW13 PW12 PW11 PW10 port B (PTB1) with the bits (PW10 to PW17) of PWM1.
E
PWM2 register set
1
1
0
0
1
1
1
0
Sets the pulse width to be output from general-purpose
PW27 PW26 PW25 PW24 PW23 PW22 PW21 PW20 port B (PTB2) with the bits (PW20 to PW27) of PWM2.
F
Test register set
1
1
0
0
1
1
1
1
Notes:
R/W
ST0 to ST2
S0 to S4
D0 to D7
X0 to X3
Y0 to Y3
PTA0
PTB0 to PTB2
PTC0 to PTC4
PTD0 to PTD4
INC
WLS
KT
SHL
BE
–
–
: Read/write select bit
1:Read, 0: Write
: Key scan read count display bits
: Key scan data
: Write or read data of the display data RAM
: X addresses of the display data RAM
: Y addresses of the display data RAM
: Port A data
: Port B output control
1: Output enable, 0: Fixed at “L”
: Port C data
: Port D data
: Display data RAM address increment. 1: X direction, 0: Y direction
: Word length select bit
1: 6 bits, 0: 8 bits
: Key scan period select bit
1: 10 ms, 0: 0.5 ms
: Common driver shift direction select bit
1: COM10→COM1, 0: COM1→COM10
: Voltage doubler control bit
1: Voltage doubler enable
0: Voltage doubler disable
–
T5
PE
T4
T3
T2
DISP Sets display ON/OFF (DISP).
T1
Reads the counter bits (Q1 to Q4) of the rotary encoder.
Sets the pulse width to be output from general-purpose
port B (PTB0) with the bits (PW00 to PW07) of PWM0.
Test instruction exclusively used by manufacturer (T1 to
T5). Customers must not use this instruction.
DTY0, DTY1
DISP
Q1 to Q4
CT0 to CT3
PW00 to PW07
PW10 to PW17
PW20 to PW2
T1 to T5
: Port enable/disable select bit 1: All ports enable
0: All ports go into high impedance for output
: Display duty select bits (1/8, 1/9, 1/10)
: Display ON/OFF select bit
1: Display ON, 0: Display OFF
: Rotary encoder switch count bits (2’s complement)
: Contrast adjustment bit
: PWM0 setting bits
: PWM1 setting bits
: PWM2 setting bits
: Bits for test instruction. Customers should not access these bits.
–
: Don’t Care
31/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Instruction Code List (ML9092-02/03)
No.
Instruction
Instruction Code
Fixed bit R/W
Register No.
D7 D6 D5 D4 D3 D2 D1
Data
D0
D7
D6
D5
D4
Description
D3
D2
D1
D0
0
Key scan register read
1
1
1
0
0
0
0
0
ST2
ST1
ST0
0
S3
S2
S1
S0
Reads scan read timing bits (ST0 to ST2) and key scan
data (S0 to S4) of the key scan register.
1
Display data RAM write
1
1
0
0
0
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Writes display data (D0 to D7) in the display data RAM
after setting the X address of Y address.
1
Display data RAM read
1
1
1
0
0
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Reads display data (D0 to D7) from the display data RAM
after setting the X address of Y address.
2
X address register set
1
1
0
0
0
0
1
0
–
–
–
–
X3
X2
X1
X0
Sets the X address (X0 to X3) of the display data RAM.
3
Y address register set
1
1
0
0
0
0
1
1
–
–
–
–
Y3
Y2
Y1
Y0
Sets the Y address (Y0 to Y3) of the display data RAM.
–
4
Port register A set
1
1
0
0
0
1
0
0
–
–
–
–
–
–
8
Control register 1 set
1
1
0
0
1
0
0
0
INC
WLS
KT
SHL
(BE)
PE
9
Control register 2 set
1
1
0
0
1
0
0
1
0
0
0
0
0
0
A
Rotary encoder read
1
1
1
0
1
0
1
0
Q4
Q4
Q4
Q4
Q4
Q3
Q2
Q1
B
Contrast ADJ set
1
1
0
0
1
0
1
1
–
–
–
–
CT3
CT2
CT1
Sets contrast adjustment values with the contrast
CT0 adjustment bits (CT0 to CT3).
F
Test register set
1
1
0
0
1
1
1
1
–
–
–
T5
T4
T3
T2
Notes:
R/W
ST0 to ST2
S0 to S3
D0 to D7
X0 to X3
Y0 to Y3
PTA0
INC
WLS
KT
SHL
: Read/write select bit
1:Read, 0: Write
: Key scan read count display bits
: Key scan data
: Write or read data of the display data RAM
: X addresses of the display data RAM
: Y addresses of the display data RAM
: Port A data
: Display data RAM address increment. 1: X direction, 0: Y direction
: Word length select bit
1: 6 bits, 0: 8 bits
: Key scan period select bit
1: 10 ms, 0: 0.5 ms
: Common driver shift direction select bit
1: COM10→COM1, 0: COM1→COM10
BE (only applies to ML9092-02)
: Voltage doubler control bit
1: Voltage doubler enable
0: Voltage doubler disable
PTA0 Controls the output of the general-purpose port A (PTA0).
Sets the address increment X or Y direction (INC), display
data word length (WLS), key scan time (KT), common
driver shift direction (SHL), voltage doubler control (BE)
(only applies to ML9092-02), port control (PE), and display
duty (DTY0, DTY1).
Sets or releases standby mode (only applies to ML9092(STB) DISP
03) and also sets display ON/OFF (DISP).
DTY1 DTY0
T1
Reads the counter bits (Q1 to Q4) of the rotary encoder.
Test instruction exclusively used by manufacturer (T1 to
T5). Customers should not use this instruction.
PE
: Port enable/disable select bit 1: All ports enable
0: All ports go into high impedance for output
DTY0, DTY1
: Display duty select bits (1/8, 1/9, 1/10)
STB (only applies to ML9092-03)
: Standby mode/normal mode select bit
1: Standby mode, 0: Normal mode
DISP
Q1 to Q4
CT0 to CT3
: Display ON/OFF select bit
1: Display ON, 0: Display OFF
: Rotary encoder switch count bits (2’s complement)
: Contrast adjustment bit
T1 to T5
: Bits for test instruction. Customers should not access these bits.
–
: Don’t Care
32/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Instruction Code List (ML9092-04)
No.
Instruction
Instruction Code
Fixed bit R/W
Register No.
D7 D6 D5 D4 D3 D2 D1
Data
D0
D7
D6
D5
D4
Description
D3
D2
D1
D0
0
Key scan register read
1
1
1
0
0
0
0
0
ST2
ST1
ST0
S4
S3
S2
S1
S0
Reads scan read timing bits (ST0 to ST2) and key scan
data (S0 to S4) of the key scan register.
1
Display data RAM write
1
1
0
0
0
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Writes display data (D0 to D7) in the display data RAM
after setting the X address of Y address.
1
Display data RAM read
1
1
1
0
0
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Reads display data (D0 to D7) from the display data RAM
after setting the X address of Y address.
2
X address register set
1
1
0
0
0
0
1
0
–
–
–
–
X3
X2
X1
X0
Sets the X address (X0 to X3) of the display data RAM.
3
Y address register set
1
1
0
0
0
0
1
1
–
–
–
–
Y3
Y2
Y1
Y0
Sets the Y address (Y0 to Y3) of the display data RAM.
–
–
4
Port register A set
1
1
0
0
0
1
0
0
–
–
–
–
–
5
Port register B set
1
1
0
0
0
1
0
1
–
–
–
–
–
8
Control register 1 set
1
1
0
0
1
0
0
0
INC
WLS
KT
SHL
–
PE
9
Control register 2 set
1
1
0
0
1
0
0
1
0
0
0
0
0
0
A
Rotary encoder read
1
1
1
0
1
0
1
0
Q4
Q4
Q4
Q4
Q4
Q3
–
Q1
Reads the counter bits (Q1 to Q4) of the rotary encoder.
CT1
Sets contrast adjustment values with the contrast
CT0 adjustment bits (CT0 to CT3).
0
0
1
0
1
1
C
PWM0 register set
1
1
0
0
1
1
0
0
PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00
D
PWM1 register set
1
1
0
0
1
1
0
1
Sets the pulse width to be output from general-purpose
PW17 PW16 PW15 PW14 PW13 PW12 PW11 PW10 port B (PTB1) with the bits (PW10 to PW17) of PWM1.
E
PWM2 register set
1
1
0
0
1
1
1
0
Sets the pulse width to be output from general-purpose
PW27 PW26 PW25 PW24 PW23 PW22 PW21 PW20 port B (PTB2) with the bits (PW20 to PW27) of PWM2.
F
Test register set
1
1
0
0
1
1
1
1
: Read/write select bit
1:Read, 0: Write
: Key scan read count display bits
: Key scan data
: Write or read data of the display data RAM
: X addresses of the display data RAM
: Y addresses of the display data RAM
: Port A data
: Port B output control
1: Output enable, 0: Fixed at “L”
: Display data RAM address increment. 1: X direction, 0: Y direction
: Word length select bit
1: 6 bits, 0: 8 bits
: Key scan period select bit
1: 10 ms, 0: 0.5 ms
: Common driver shift direction select bit
1: COM10→COM1, 0: COM1→COM10
T5
PE
DTY0, DTY1
T4
CT2
Q2
1
–
CT3
Sets or releases standby mode and also sets display
ON/OFF (DISP).
1
–
–
STB DISP
Contrast ADJ set
–
–
Controls the output of the general-purpose port B (PTB0
to PTB2).
Sets the address increment X or Y direction (INC), display
data word length (WLS), key scan time (KT), common
DTY1 DTY0
driver shift direction (SHL), port control (PE), and display
duty (DTY0, DTY1).
PTB2 PTB1 PTB0
B
Notes:
R/W
ST0 to ST2
S0 to S4
D0 to D7
X0 to X3
Y0 to Y3
PTA0
PTB0 to PTB2
INC
WLS
KT
SHL
–
PTA0 Controls the output of the general-purpose port A (PTA0).
T3
T2
T1
Sets the pulse width to be output from general-purpose
port B (PTB0) with the bits (PW00 to PW07) of PWM0.
Test instruction exclusively used by manufacturer (T1 to
T5). Customers must not use this instruction.
: Port enable/disable select bit 1: All ports enable
0: All ports go into high impedance for output
: Display duty select bits (1/8, 1/9, 1/10)
STB
: Standby mode/normal mode select bit
1: Standby mode, 0: Normal mode
DISP
: Display ON/OFF select bit
1: Display ON, 0: Display OFF
Q1 to Q4
: Rotary encoder switch count bits (2’s complement)
CT0 to CT3
: Contrast adjustment bit
PW00 to PW07 : PWM0 setting bits
PW10 to PW17 : PWM1 setting bits
PW20 to PW2
: PWM2 setting bits
T1 to T5
: Bits for test instruction. Customers should not access these bits.
–
: Don’t Care
33/66
FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Clock Synchronous Serial Transfer Example (WRITE)
Transfer start
Transfer complete
CS
1
2
3
4
5
6
7
8
R/W D4
D3
D2
D1
D0
9 10 11 12 13 14 15 16
CP
DI/O
“1” “1”
D7
D6
D5
D4
D3
D2 D1
D0
Register bits
Instruction code
Data
Clock Synchronous Serial Continuous Data Transfer Example (WRITE: Example of display data RAM
write)
Transfer start
Transfer complete
CS
*1
1
2
7
8
9 10 15 16 17 18 23 24 41 42 47 48
CP
DI/O
Instruction code
*1:
Data 1
Data 2
Data 5
Be sure to write data in 8 bits. If the CS signal falls when data input operation in 8 bits is not
complete, the last 8-bit data write is invalid. (The previously written data is valid.)
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Clock Synchronous Serial Continuous Data Transfer Example (READ)
Transfer start
Transfer complete
CS
*2
1
2
8
9 10 11 15 16 17 18 23 24 41 42 47 48
CP
DI/O
Instruction code READ DATA1
Input state
*2:
READ DATA2
READ DATA5
Output state
A reading state appears only when the R/W bit is “1”. The read data is valid only when the register
is set to key scan read mode, rotary encoder read mode or display data read mode. Otherwise,
the read data is invalid (undefined data will be read out).
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Output Pin, I/O Pin and Register States When Reset Is Input
Pin and register states while the RESET input is pulled to a “L” level are listed below.
Output pin, I/O pin
State
DI/O
Input state
KREQ
“L” (VSS)
OSC2
Oscillating state
R0/C0 to R4/C4 (when these pins are used for key
scanning in ML9092-01);
R0 to R5 (ML9092-02/03);
“L” (VSS)
R0 toR4 (ML9092-04)
R0/C0 to R4/C4 (when these pins are used as port C
outputs in ML9092-01)
High impedance
C0/D0 to C4/D4 (when these pins are used as port D
outputs in ML9092-01)
High impedance (any pull-up resistors are turned off)
PA0
High impedance
PB0 to PB2 (ML9092-01/04)
High impedance
SEG1 to SEG56 (ML9092-01);
SEG1 to SEG60 (ML9092-02/03/04)
COM1 to COM10
VSS
VSS
Register
State
Key scan register
Reset to “0”
Display data register
Display data is retained
X address register
Reset to “0”
Y address register
Reset to “0”
Port A register
Reset to “0”
Port B register (ML9092-01/04)
Reset to “0”
Port C register
(When KPS = “0” in ML9092-01)
Port D register
(When KPS = “0” in ML9092-01)
Control register 1
Control register 2
Reset to “0”
Reset to “0”
Bits INC and KT are set to “1”.
Bits WLS, SHL, PE, DTY1 and DTY0 are reset to “0”.
Display OFF, normal mode
(Standby mode is released)
Rotary encoder read register
Reset to “0”
Contrast ADJ register
Set to “F”
PWM0 register (for ML9092-01/04)
Reset to “0”
PWM1 register (for ML9092-01/04)
Reset to “0”
PWM2 register (for ML9092-01/04)
Reset to “0”
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Power-On Reset
The capacitance of an external capacitor that is connected to the RESET pin must be CRST [µF] ≥ 12.5 × TR [s],
where TR is the rise time taken until the power supply voltage to be supplied to the ML9092-01/02/03/04 reaches
0.9VDD (4.5 V) from 0.1VDD, and CRST is the capacitance of an external capacitor connected to the RESET pin.
(For example, if TR = 10 [ms], then CRST ≥ 0.125 [µF])
The pulse width when an external reset signal is input should be TR or more.
Set an instruction at least 10 µs after the reset signal reaches 0.85VDD or more.
Thereafter, this IC is accessible.
TR
0.9VDD
(4.5 V)
VDD
0.1VDD
Recommended power supply
voltage (5 V)
0.85VDD
Accessible time
RESET
10 µs or more
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Serial Interface Operation
• Instruction code
A register that transfers display data, key scan data, etc. according to the content of the instruction code is selected
(see below).
D7
D6
D5
“1”
“1”
R/W
D4
D3
D2
D1
D0
Register number
(1) D7, D6 (fixed at “1”)
When selecting the start byte register, always write a “1” to bits D7 and D6.
(2) D5 (R/W) (Read mode/write mode select bit)
1: Read mode is selected
0: Write mode is selected
(3) D4 to D0 (Register number)
The correspondence between the start byte contents and the registers and display data RAM is shown in the table
below.
D7
D6
D5
D4
D3
D2
D1
D0
Register name
1
1
0
1
0
0
0
0
Key scan register
1
1
1
1/0
0
0
0
1
Display data RAM
1
1
0
0
0
0
1
0
X address register
1
1
0
0
0
0
1
1
Y address register
1
1
0
0
0
1
0
0
Port A register
1
1
0
0
0
1
0
1
Port B register
1
1
0
0
0
1
1
0
Port C register
1
1
0
0
0
1
1
1
Port D register
1
1
0
0
1
0
0
0
Control register1
1
1
0
0
1
0
0
1
Control register 2
1
1
1
0
1
0
1
0
Rotary encoder register
1
1
0
0
1
0
1
1
Contrast ADJ register
1
1
0
0
1
1
0
0
PWM0 register
1
1
0
0
1
1
0
1
PWM1 register
1
1
0
0
1
1
1
0
PWM2 register
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Description of the Data Section in Instructions
• Key scan register (KR)—Read (for ML9092-01/04)
D7
D6
D5
D4
D3
D2
D1
D0
ST2
ST1
ST0
S4
S3
S2
S1
S0
(1) D7 to D5 (ST2 to ST0) (Key scan read count display bits)
25-bit key scan data is divided into 5 groups and read. The read count is indicated by bits ST2 to ST0.
Every time key scan data is read, these bits are automatically incremented over the range of “000” to “100”. After
counting to “100”, this counter is reset to “000” and then again incremented from “000”, thereafter repeating this
cycle. If the CS signal is risen up during the cycle of counting, the scan read counter bits are returned to “000”.
If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
(2) D4 to D0 (S4 to S0) (Key scan read data bits)
These bits are read as 25-bit serial data that expresses the key switch status (1 = ON, 0 = OFF). Data is divided into
5 groups and read. (For the read order, refer to the description below.) The read count is indicated by bits ST2 to
ST0.
The correspondence between the scan read count data, key scan data and key matrix switches is shown below.
If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
ST2
ST1
ST0
S4
S3
S2
S1
S0
0
0
0
SW04
SW03
SW02
SW01
SW00
R0
0
0
1
SW14
SW13
SW12
SW11
SW10
R1
0
1
0
SW24
SW23
SW22
SW21
SW20
R2
0
1
1
SW34
SW33
SW32
SW31
SW30
R3
1
0
0
SW44
SW43
SW42
SW41
SW40
R4
Note: SW00 to SW44 indicate the corresponding switches in Figure 1.
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C0/D0
C0
C2/D2
C2
C1/D1
C1
C3/D3
C3
C4/D4
C4
R0/C0
R0
SW00
SW01
SW02
SW03
SW04
R1/C1
R1
SW10
SW11
SW12
SW13
SW14
R2/C2
R2
SW20
SW21
SW22
SW23
SW24
R3/C3
R3
SW30
SW31
SW32
SW33
SW34
R4/C4
R4
SW40
SW41
SW42
SW43
SW44
Figure 1
(Note)
To recognize simultaneous depression of three or more key switches, add a diode in series to
each key.
Cm/Dm
Cm
Rn/Cn
Rn
Rn + 1 / C n + 1
Rn+1
Connection with diodes
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• Key scan register (KR)—Read (for ML9092-02/03)
D7
D6
D5
D4
D3
D2
D1
D0
ST2
ST1
ST0
0
S3
S2
S1
S0
(1) D7 to D5 (ST2 to ST0) (Key scan read count display bits)
24-bit key scan data is divided into 6 groups and read. The read count is indicated by bits ST2 to ST0.
Every time key scan data is read, these bits are automatically incremented over the range of “000” to “101”. After
counting to “101”, this counter is reset to “000” and then again incremented from “000”, thereafter repeating this
cycle. If the CS signal is risen up during the cycle of counting, the scan read counter bits are returned to “000”.
If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
(2) D3 to D0 (S3 to S0) (Key scan read data bits)
These bits are read as 24-bit serial data that expresses the key switch status (1 = ON, 0 = OFF). Data is divided into
6 groups and read. (For the read order, refer to the description below.) The read count is indicated by bits ST2 to
ST0.
The correspondence between the scan read count data, key scan data and key matrix switches is shown below.
If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
ST2
ST1
ST0
S4
S3
S2
S1
S0
0
0
0
0
SW03
SW02
SW01
SW00
R0
0
0
1
0
SW13
SW12
SW11
SW10
R1
0
1
0
0
SW23
SW22
SW21
SW20
R2
0
1
1
0
SW33
SW32
SW31
SW30
R3
1
0
0
0
SW43
SW42
SW41
SW40
R4
1
0
1
0
SW53
SW52
SW51
SW50
R5
Note: SW00 to SW53 indicate the corresponding switches in Figure 2.
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C0
C1
C2
C3
R0
SW00
SW01
SW02
SW03
R1
SW10
SW11
SW12
SW13
R2
SW20
SW21
SW22
SW23
R3
SW30
SW31
SW32
SW33
R4
SW40
SW41
SW42
SW43
R5
SW50
SW51
SW52
SW53
Figure 2
(Note)
To recognize simultaneous depression of three or more key switches, add a diode in series to
each key.
Cm
Rn
Rn+1
Connection with diodes
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Key Scan
The key scanning starts when a key switch is pressed on and ends after all key switches are detected to be off.
After the key switch is turned on, when the same key is pressed for two cycles or more, the level of the KREQ
signal changes from a “L” to “H” level. In the same manner, the level of the KREQ signal changes from “H” to
“L” two cycles after all key switches are turned off.
This signal can be used as a flag. To use it as a flag, start key-scan reading when the KREQ signal has changed
from “L” to “H.”
While the KREQ signal is at a “H” level, carry out key-scan reading periodically. Carry out key scan reading also
when the KREQ signal has changed from “H” to “L”.
The KREQ signal (the KREQ signal that is sent when the key switch is turned on) is reset when all key switches are
detected to be off or when a “L” level is applied to the RESET pin.
Key switch
R0/C0
R1/C1
R2/C2
R3/C3
R4/C4
Key switch ON.
Scanning starts.
Key data reading
starts
Key switch OFF
Scanning stops
KREQ
Notes:
1. Even when the KREQ signal changes from “L” to “H”, chattering for more than one key scan cycle is
not absorbed. This should be handled by multiple data reads by software.
2. How simultaneous depression of two keys is processed should be handled by software.
3. When three or more key switches are pressed at the same time, the device may recognize that
key(s) that has not been actually pressed has been pressed. Therefore, to recognize simultaneous
depression of three or more key switches, add a diode in series to each key (see Figures 1 and 2).
To ignore simultaneous depression of three or more key switches, a program may be required to
ignore all key data which contains three or more consecutive “1” values.
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• Display data RAM (DRAM) read/write
D7
D6
0
0
D5
D4
D3
D2
D1
D0
8-bit DATA
6-bit DATA
The display data RAM read/write instruction writes and reads display data to and from the liquid crystal display
RAM. Data that is input to the address set by the X and Y address registers is written to or read from this register.
The bit length of display data can be selected by the WLS bit of control register 1. If 6-bit data has been selected,
writing to D7 and D6 is invalid, and if read, their values will always be “0”. D7 is the MSB (D5 in the case of 6-bit
data) and D0 is the LSB.
The X address and Y address should be set immediately before writing or reading display data (either X address or
Y address may be set first). However, in the case of successive writings or readings, only one-time settings of X
address and Y address are required immediately before the writing or reading, in which case X address and Y
address are automatically incremented every time data is written or read (see the description under the heading
“X•Y address Counter Auto Increment.”
The contents of this register will not change even if the RESET pin is pulled to a “L” level.
• X address register (XAD) set
D7
D6
D5
D4
D3
D2
—
D1
D0
XAD
—: don’t care
The X address register set instructions sets the X address for the liquid crystal display RAM.
The address setting range is 0 to 7 (00H to 07H) when 8-bit data is selected with the WLS bit (bit D6) of the control
register 1 (WLS = “0”). In this case, this register starts incrementing the X address from the set value each time
RAM is read or written. When the count value of this register returns to 0 from the maximum value 7, the Y
address is automatically incremented as well. Thereafter, the Y address is counted in a loop fashion from 0 to 7.
The address setting range is 0 to 9 (00H to 09H) when 6-bit data is selected (WLS = “1”). In this case this register
starts incrementing the X address from the set value. When the count value of this register returns to 0 from the
maximum value 9, the Y address is automatically incremented as well. Thereafter, the Y address loops from 0 to 9.
Proper operation is not guaranteed if values outside this range are set.
Writing to bits D7 through D4 is invalid. If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
• Y address register (YAD) set
D7
D6
D5
—
D4
D3
D2
D1
D0
YAD
—: don’t care
The Y address register set instruction sets a Y address of RAM for the liquid crystal display.
The Y address setting range varies according to the setting of the DTY bits (bits D1 and D0) of the control register
1 (described later).
The relation between the internal RAM areas and the display RAM areas is shown in the Table below. RAM areas
that are not displayed can be used as data RAM areas.
This register starts incrementing the Y address from the set value each time RAM is read or written. When the
register count returns to 0 from the maximum value (09H), the X address is also incremented automatically.
Thereafter, the Y address is counted in a loop fashion as shown in the Table below. However, if RAM areas that
are not displayed are used, the X address is not incremented automatically.
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Y register setting range
Duty
and loop range
Invalid address setting range
1/8
0 to 7 (00H to 07H)
0 to 7 (00H to 07H)
1/9
0 to 8 (00H to 08H)
0 to 8 (00H to 08H)
1/10
0 to 9 (00H to 09H)
0 to 9 (00H to 09H)
This register is reset to “0” when the RESET pin is made low.
• Port register A (PTA) set
D7
D6
D5
D4
D3
D2
D1
—
D0
PTA
—: don’t care
The port register A set instruction sets the output of port A.
When the PTA bit is set to “1”, a “H” level is output from the PA0 pin of general purpose port A. In the same way,
when the PTA bit is set to “0”, a “L” level is output from the PA0 pin. If the RESET pin is pulled to a “L” level, the
PE bit (bit D2) of the control register is reset to “0”, this register is reset to “0”, and the PA0 pin goes to high
impedance.
After the reset state is released, if the PTA bit of this register is set to “1” or “0” and then the PE bit is set to “1”, the
PA0 pin is released from its high impedance state and a “H” or “L” level that corresponds to the set status of the
PTA bit, is output from the PA0 pin.
• Port register B (PTB) set
D7
D6
D5
—
D4
D3
D2
D1
D0
PTB2
PTB1
PTB0
—: don’t care
The port register B set instruction sets the output of port B. (Applies to the ML9092-01/04.)
When each bit of PTB0 to PTB2 is set to “1”, the PWM signal set in the PWM0 to PWM2 registers is output from
each of the PB0 to PB2 pins of the general purpose port B. In the same way, when each bit of PTB0 to PTB2 is set
to “0”, each of the PB0 to PB2 pins are pulled to a “L” level. If the RESET pin is pulled to a “L” level, the PE bit
(bit D2) of the control register is reset to “0”, this register is reset to “0”, and the PB0 to PB2 pins go to high
impedance.
After the reset state is released, if the a PWM value is set in the PWM0 to PWM2 registers and then the PE bit is set
to “1”, the PB0 to PB2 registers are released from their high impedance state and a PWM waveform is output.
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• Port register C (PTC) set
D7
D6
D5
D4
D3
D2
D1
D0
—
—
—
PTC4
PTC3
PTC2
PTC1
PTC0
—: don’t care
The port register C set instruction sets the output of port C. (Applies to the ML9092-01 only.)
This register is enabled when a “L” level is applied to the KPS pin of ML9092-01 and the R0/C0 to R4/C4 pins are
set as port C.
When each bit of PTC4 to PTC0 is set to “1”, a “H” level is output from each of the R4/C4 to R0/C0 pins of the
general purpose port C. In the same way, when each bit of PTC4 to PTC0 is set to “0”, a “H” level is output from
each of the R4/C4 to R0/C0 pins. If the RESET pin is pulled to a “L” level, the PE bit (bit D2) of the control
register is reset to “0”, this register is reset to “0”, and the R4/C4 to R0/C0 pins go to high impedance.
After the reset state is released, if the PTC4 to PTC0 bits of this register are set to “1” or “0” and then the PE bit is
set to “1”, the R4/C4 to R0/C0 pins are released from its high impedance state and a “H” or “L” level that
corresponds to the set status of each bit of PTC4 to PTC0, is output from the R4/C4 to R0/C0 pins.
• Port register D (PTD) set
D7
D6
D5
D4
D3
D2
D1
D0
—
—
—
PTD4
PTD3
PTD2
PTD1
PTD0
—: don’t care
The port register D set instruction sets the output of port D. (Applies to the ML9092-01 only.)
This register is enabled when a “L” level is applied to the KPS pin of ML9092-01 and the C0/D0 to C4/D4 pins are
set as port C.
When each bit of PTD4 to PTD0 is set to “1”, a “H” level is output from each of the C4/D4 to C0/D0 pins of the
general purpose port D. In the same way, when each bit of PTD4 to PTD0 is set to “0”, a “H” level is output from
each of the C4/D4 to C0/D0 pins. If the RESET pin is pulled to a “L” level, the PE bit (bit D2) of the control
register is reset to “0”, this register is reset to “0”, and the C4/D4 to C0/D0 pins go to high impedance.
After the reset state is released, if the PTD4 to PTD0 bits of this register are set to “1” or “0” and then the PE bit is
set to “1”, the C4/D4 to C0/D0 pins are released from its high impedance state and a “H” or “L” level that
corresponds to the set status of each bit of PTD4 to PTD0, is output from the C4/D4 to C0/D0 pins.
• Control register 1 (FCR1)
D7
D6
D5
D4
D3
D2
D1
D0
INC
WLS
KT
SHL
BE
PE
DTY1
DTY0
(1) D7 (INC) Address increment direction
1: X direction address increment
0: Y direction address increment
This bit sets the address increment direction of the display RAM. The display RAM address is automatically
incremented by 1 every time data is written to the display data register. Writing a “1” to this bit sets “X address
increment,” and writing a “0” sets “Y address increment.” For further details regarding address incrementing,
refer to the page entitled “X, Y Address Counter Auto Increment.” This bit is set to “1” if the RESET pin is pulled
to a “L” level.
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(2) D6 (WLS) (Word Length Select)
1: 6-bit word length select
0: 8-bit word length select
This bit selects the word length of data to be written to and read from the display RAM. If “1” is written to this bit,
data will be read from and written to the display RAM in 6-bit units. If “0” is written to this bit, data will be read
from and written to the display RAM in 8-bit units. This bit is reset to “0” if the RESET pin is pulled to a “L” level.
(3) D5 (KT) (Key scan time) Key scan time select bit
1: 10 ms
0: 5 ms
This bit selects the key scan cycle time. In the case of a 306 kHz oscillating frequency, writing a “1” to this bit sets
the key scan cycle time at 10 ms (1/3072 divided frequency of the oscillating frequency), writing a “0” sets the key
scan cycle time at 5 ms (1/1536 divided frequency of the oscillating frequency). This bit is set to “1” if the RESET
pin is pulled to a “L” level.
(4) D4 (SHL) (Common driver shift direction select bit)
This bit selects the shift direction of common drivers.
The relationship between this bit and shift directions are shown below.
This bit is reset to “0” if the RESET pin is pulled to a “L” level.
SHL
1
0
Duty
Shift direction
1/8
COM8
→
COM1
1/9
COM9
→
COM1
1/10
COM10
→
COM1
1/8
COM1
→
COM8
1/9
COM1
→
COM9
1/10
COM1
→
COM10
(5) D3 (BE) (Voltage doubler operation control bit )
This bit controls the operation of the voltage doubler. (Applies to ML9092-01/02.)
1: Voltage doubler enable
0: Voltage doubler disable
This bit is reset to “0” if the RESET pin is pulled to a “L” level.
(6) D2 (PE) (General-purpose port output enable/disable select bit)
This bit selects high impedance output or output enable for the general-purpose port outputs A, B, C and D (C and
D apply to ML9092-01 only; B applies to ML9092-01/04).
1: Output enable
0: High-impedance output (output disable)
This bit is reset to “0” if the RESET pin is pulled to a “L” level.
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(7) D1, D0 (DTY1, DTY0) (Display duty select bits)
These bits select the display duty. The correspondence between each bit and display duty is shown in the chart
below. These bits are reset to “0” if the RESET pin is pulled to a “L” level.
DTY1
DTY0
Display duty
0
0
1/8
0
1
1/9
1
0
1/10
1
1
1/10
• Control register 2 (FCR2)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
STB
DISP
(1) D1 (STB) (Standby mode select bit)
This bit is used to control the standby and normal modes. (Applies to ML9092-03/04.)
1: Standby mode
0: Normal mode
This bit is reset to “0” if the RESET pin is pulled to a “L” level.
The LSI internal status and pin status during standby mode are as follows:
- RAM data is retained.
- Common output and segment output are VSS level.
- Electronic volume values are retained.
- Port output A is at a “L” level (applies to ML9092-03/04). The status before standby is maintained for port
output B (applies to ML9092-04).
- RC oscillation is stopped. (Oscillation is started with key input, maintained while the KREQ output is at a “H”
level, and stopped when all key switches are turned off and the KREQ output is at a “L” level.)
- Rotary encoder input signals (A and B) are ignored.
- Key input allowed.
- The microcontroller interface (CS, CP, DI/O, KREQ) is operable. (However, only with a KREQ signal from the
key scan, will the KREQ pin output a “H” level.)
- VHIN and VO should be set to VSS or the floating status.
Note: When there is a key input in a standby state, this IC will start oscillating and KREQ output will go to a “H”
level. Execute key scan reading periodically during this “H” level period. Also, execute key scan reading when
the KREQ signal changes from a “H” to “L” level.
(2) D0 (DISP) (Display ON/OFF mode bit)
1: Display ON mode
0: Display OFF mode
This bit selects whether the display is ON or OFF. Writing a “1” to this bit selects the display ON mode. Writing
a “0” to this bit selects the display OFF mode. At this time, the COM and SEG pins will be at the VSS level. Even
if this bit is set to “0”, the display RAM contents will not change. If the RESET pin is pulled to a “L” level, this
register is reset to “0”.
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• Rotary encoder (RE) read
D7
D6
D5
D4
D3
D2
D1
D0
Q4
Q4
Q4
Q4
Q4
Q3
Q2
Q1
The rotary encoder read instruction is used to read the count value from the rotary encoder switch input signal.
(Count values are in the 2’s complement format.)
(1) D7 to D0 (Q4 to Q1) (Count value bit)
The phase difference between the A signal and the B signal is recognized, and the value that is counted by the edge
of the signal with the slower phase is set. Count values range from negative 1000 (Q4, Q3, Q2, Q1) to positive
0111. If the count is less than negative 1000 or more than positive 0111, then it is ignored.
These bits are all reset to “0” when this instruction is executed or when the RESET pin is pulled to a “L” level.
If counterclockwise rotation is input after the count value is incremented by clockwise rotation, then count value
will be decremented. If counterclockwise rotation is further input after the count value reaches 0000, then the
count value will change to 1111 and the count value will be decremented. (The count value will remain 1000 even
if counterclockwise rotation is further input after the count value reaches negative 1000.)
After this, if clockwise rotation is input, then the count value will be incremented. If the count value reaches 1111
and clockwise rotation is further input, then the count value will become 0000 and the count value will be
incremented. (Even if clockwise rotation is further input after the count value reaches positive 0111, the count
value will maintain 0111.)
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Functional Description of the Rotary Encoder Switch
As shown in Figure 3, the rotary encoder switch circuit is made up of phase detection circuit, an interrupt
generation circuit, an up/down counter and a parallel-in/serial-out register.
A
B
Phase detection circuit
UP DOWN
Interrupt
generation circuit
To KREQ
Up/down counter
Q4
Q3
Q2
Q1
Parallel in/serial out
shift register
Output data
Figure 3 Rotary Encoder Switch Circuit
1) Phase Detection and Interrupt Generation Circuits
1-1) Clockwise Rotation
When the A and B signals are input as shown in Figure 4, the phase detection circuit outputs the UP
signal after the chattering absorption period. At this time, the KREQ output goes to a high level, so
that this signal can be used as the interrupt signal. The KREQ signal maintains a high level until the
rotary encoder read instruction is executed.
A
B
Chattering absorption period
UP (internal signal)
KREQ
Figure 4 Input/Output Timing for Clockwise Rotation
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1-2) Counterclockwise Rotation
When the A and B signals are input as shown in Figure 4, the phase detection circuit outputs the
DOWN signal after the chattering absorption period. At this time, the KREQ output goes to a
high level, so that this signal can be used as the interrupt signal. The KREQ signal maintains a
high level until the rotary encoder read instruction is executed.
A
B
Chattering absorption period
DOWN (internal signal)
KREQ
Figure 5 Input/Output Timing for Counterclockwise Rotation
2) UP/DOWN Counter
The UP/DOWN counter is incremented when an UP signal is input and decremented when a DOWN
signal is input. However, if the counter reaches “0111” and an UP signal is input, the UP/DOWN
counter will hold “0111”. In the same manner, if the UP/DOWN counter is at “1000” and a DOWN
signal is input, the UP/DOWN counter will hold “1000”.
A
B
Q4, Q3, Q2, Q1
0001
0010
0011
0100
0101
0110
0111
0111
Figure 6 When the Up Counter Overflows
A
B
Q4, Q3, Q2, Q1
1111
1110
1101
1100
1011
1010
1001
1000
1000
Figure 7 When the Down Counter Overflows
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3) Parallel-in/Serial-out Shift Register
The KREQ signal goes to a low level when the rotary encoder read instruction is executed, when the
UP/DOWN counter will be reset to “0”.
CS
1
2
8
9 10 11 12 13 14 15 16
CP
DI/O
Instruction code
Input state
READ DATA1
Output state
KREQ
Figure 8 Operation of KREQ Output
Notes:
1. The KREQ signal is output by a logical OR of the KREQ signal generated by a key scan and the
KREQ signal generated by the rotary encoder. The KREQ signal from the rotary encoder is reset by
executing the rotary encoder read instruction; however, the KREQ signal generated by a key scan is
not reset even if the key scan register read instruction is executed. Also, if the KREQ signal is
generated by a key scan, it will not be reset even if the rotary encoder read instruction is executed.
Although dependent on the components glued to this LSI, it is recommended that the rotary encoder
read instruction and key scan register read instruction be executed as a set when the KREQ signal
goes to a “H” level.
2. The maximum read cycle time for when the KREQ signal is at a “H” level is practically determined by
the signal input from the rotary encoder and the 3-bit counter built into this LSI. Therefore, make the
time taken before starting to execute the rotary encoder read instruction 12 ms or less.
3. Using a rotary encoder switch that has the click stabilizing points shown below is recommended.
A signal
B signal
Click stabilizing points
Waveform of a Recommended Rotary Encoder Switch
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• Contrast ADJ (CA) set
D7
D6
D5
D4
D3
D2
D1
D0
—
—
—
—
CT3
CT2
CT1
CT0
—: don’t care
This instruction is for adjusting the liquid crystal display voltage.
(1) D3 to D0 (CT3 to CT0) (Contrast adjustment value setting bits)
When FH is written to these bits, the liquid crystal display voltage (voltage between the V0 and VSS pins) becomes
a maximum.
When 0H is written, the liquid crystal display voltage becomes a minimum.
By setting the values from 0H to FH, the liquid crystal display voltage can be adjusted just like an electronic
volume control.
These bits are all reset to “0” if the RESET pin is pulled to a “L” level.
V0 Ouput Target Voltage for Contrast ADJ Setting Values
Contrast ADJ setting values
V0 output target voltage
CT3
CT2
CT1
CT0
ML9092-01/02
ML9092-03/04
1
1
1
1
0.980VOUT
0.980VHIN
1
1
1
0
0.973VOUT
0.973VHIN
1
1
0
1
0.947VOUT
0.947VHIN
1
1
0
0
0.923VOUT
0.923VHIN
1
0
1
1
0.900VOUT
0.900VHIN
1
0
1
0
0.878VOUT
0.878VHIN
1
0
0
1
0.857VOUT
0.857VHIN
1
0
0
0
0.837VOUT
0.837VHIN
0
1
1
1
0.818VOUT
0.818VHIN
0
1
1
0
0.800VOUT
0.800VHIN
0
1
0
1
0.783VOUT
0.783VHIN
0
1
0
0
0.766VOUT
0.766VHIN
0
0
1
1
0.750VOUT
0.750VHIN
0
0
1
0
0.735VOUT
0.735VHIN
0
0
0
1
0.720VOUT
0.720VHIN
0
0
0
0
0.700VOUT
0.700VHIN
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• PWM0/1/2 register (PWMR) set
D7
D6
D5
D4
D3
D2
D1
D0
PWx7
PWx6
PWx5
PWx4
PWx3
PWx2
PWx1
PWx0
Note: “x” stands for 0 for PB0 (port B0), 1 for PB1 (port B1) and 2 for PB2 (port B2).
This instruction sets the pulse width of the PWM signal output from port B. (Applies to ML9092-01/04.)
PWx0 is LSB and PWx7 is MSB.
This instruction should be used with a PWM data write cycle of 5.0 ms or longer.
These bits are all reset to “0” if the RESET pin is pulled to a “L” level.
Note: When inputting multiple PWM data items, be sure to input them in succession (i.e., without intervals).
PWxn = 00 H (0/255)
Fixed at “H”
State at the time of reset
PWxn = 01 H (1/255)
PWxn = 02 H (2/255)
…
PWxn = 03 H (3/255)
PWxn = FE H (254/255)
PWxn = FF H (255/255)
Fixed at “H”
Figure 9 PWM Output Waveform
• Test register (TEST) set
D7
D6
D5
D4
D3
D2
D1
D0
—
—
—
—
T4
T3
T2
T1
—: don’t care
This instruction is for testing by the manufacturer.
Customers should not use this register.
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Display Screen and Memory Address Allocation
The ML9092-01/02/03/04 has an internal display data RAM (60 bits by 10 bits) of a bitmap type.
The allocation of memory addresses varies according to the selected word length (6 bits or 8 bits) as shown in
Figure 10: 0 to 7 for selection of 8 bits per word or 0 to 9 for selection of 6 bits per word.
The X address 7 in the 6-bits/word mode has four display memory bits. The four bits (D7 to D4) starting from bit
D7 of the display data register are written in memory and the other bits (D3 to D0) are ignored.
Address Allocation in the 8-bits/word mode
Address Allocation in the 6-bits/word mode
(X address)
1
2
7
0
(Y address)
(Y address)
0
(X address)
0
1 (D7)
(D0)
(D7)
9
1 (D5)
(D0)
(6 bits)
(4 bits)
9
2
0
(D4)
(8 bits)
1
9
Figure 10 Display Memory Addresses
(COM1)
Y0
(COM2)
Y1
(COM10)
Y9
(SEG5)
(SEG6)
(SEG7)
(SEG8)
(SEG60)
X4
X5
X6
X7
X59
0
1
0
1
0
1
(D7)
(D5)
(SEG4)
X3
1
(SEG3)
0
(SEG2)
1
(SEG1)
X2
Y line
X1
Common
output
X0
X line
Segment
output
In the 8-bits/word mode, data to be displayed is written in display memory with the D7 data of the display data
register at address (Xn, Yn) and the D0 data at address (Xn + 7, Yn). Similarly, In the 6-bits/word mode, data to be
displayed is written in display memory with the D5 data of the display data register at address (Xn, Yn) and the D0
data at address (Xn + 5, Yn). See Figure 11.
Data “1” in display memory represents turning on the corresponding display segment and data “0” in display
memory represents turning off the corresponding display segment.
Note: In the ML9092-01, the X address range in the 8-bits/mode will be 0 to 6
(D0) For 8 bits per word
(D0) For 6 bits per word
RAM for 60 dots by 10 dots display
Figure 11 Display Screen Bit Allocation and Memory Addresses
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X•Y address Counter Auto Increment
The liquid crystal display RAM has an X-address counter and a Y-address counter. Each address counter has an
Auto Increment function.
When display data is read or written, this function increments either of these X- and Y-address counters (which is
selected by the INC bit (D7 bit) of the control register 1).
INC bit = “0” selects the Y-address counter.
INC bit = “1” selects the X-address counter.
The address counting cycle of the X address counter varies according to the selected word length (8 bits or 6 bits):
X address range of 0 to 6 (ML9092-01) or 0 to7 (ML9092-02/03/04) in the 8-bits/word mode or X address range of
0 to 9 in the 6-bits/word mode.
When the X address count returns to 0 from a maximum value (6 (ML9092-01) or 7 (ML9092-02/03/04) in the
8-bits/word mode, or 9 in the 6-bits/word mode), the Y address is also incremented automatically.
The relationship between display duties and Y address count ranges is shown below.
When the Y-address counter returns to 0 from a maximum value, the X address is also incremented automatically.
Model
ML9092-01/02/03/04
Y-address count range (cycle)
Maximum Y address count
1/8
0 to 7
7
1/9
0 to 8
8
1/10
0 to 9
9
If an invalid address (outside the address count range) is given to the X- or Y- address counter,
its counting will not be assured.
Example of incrementing the X-address
(8 bits per word and 1/10 duty)
Example of incrementing the Y-address
(8 bits per word and 1/10 duty)
0
0
1
X address
2
7
1
Y address
1
X address
1
0
7
0
Y address
Note:
Duty
2
9
9
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Liquid Crystal Driving Waveform Example (1)
1/8 duty (1/4 bias)
8 1
2
3 4
5
6
7
8
1 2
3
4
5
6 7
8
1
2
Common
line No.
3
V0
V1
V2
C0M1
V3
VSS
V0
V1
C0M2
V2
V3
VSS
V0
V1
V2
C0M8
V3
VSS
A non-selectable waveform is output from COM9 and COM10 outputs.
8 1
2 3
4
5
6
7 8
1
2 3
4
5 6
7
8 1
Common
line No.
2 3
V0
V1
V2
SEGn
V3
VSS
: Light ON
: Light OFF
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Liquid Crystal Driving Waveform Example (2)
1/9 duty (1/4 bias)
9
1 2
3 4 5
6
7 8
9
1 2
3
4 5
6
7 8
9
Common
line No.
1
V0
V1
C0M1
V2
V3
VSS
V0
V1
V2
C0M2
V3
VSS
V0
V1
C0M9
V2
V3
VSS
A non-selectable waveform is output from the COM10 output.
9 1 2
3
4 5
6 7 8
9
1 2
3
4 5
6
7 8
9
Common
line No.
1
V0
V1
SEGn
V2
V3
VSS
: Light ON
: Light OFF
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Liquid Crystal Driving Waveform Example (3)
1/10 duty (1/4 bias)
10 1
2
3
4
5 6
7
8 9 10 1 2
3
4
5 6 7
Common
line No.
8 9 10
V0
V1
V2
C0M1
V3
VSS
V0
V1
V2
C0M2
V3
VSS
V0
V1
C0M10
V2
V3
VSS
10 1
2
3
4 5
6
7 8
9 10 1
2
3 4
5
6 7
8
Common
line No.
9 10
V0
V1
V2
SEGn
V3
VSS
: Light ON
: Light OFF
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Flowchart for Setting the Standby Mode and Releasing the Standby Setting with KREQ by Key Input
(Applies to the ML9092-03/04)
Normal operaton
Make a setting for control
register 2
Turn external power supply (VHIN) OFF
Standby state
Setting of STB and DISP
LCD driving voltage: OFF
Pull VHIN and V0 to the VSS level
or put them into a floating state.
Standby state
Key input
NO
KREQ output =
“H” level ?
YES
Make a setting for control
register 2
Turn external power supply (VHIN) ON
Make a setting for control register
2 again
Make a setting for registers
again
NO
Release STB.
LCD driving voltage: ON
Make a setting of INC, WLS, KT,
SHL, BE, PE, DTY1, and DTY0
again
Make a setting for port register A
and display data RAM again
according to the specification.
Is initial screen
data input
complete?
YES
Set DISP of control register 2 to
“1”
Displaying of initial screen started
Settings completed
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Power-On Flowchart
Start
Turn on VDD
Turn on VIN
Input reset signal
Make a setting for control register 1
Make a setting for registers
No
External reset or power-on reset
Make a setting for INC, WLS, KT, SHL, BE,
PE, DTY1, and DTY0.
Make a setting for port register A, port
register B, port register C, port register D, and
display data RAM according to specifications.
Is input of initial
screen data
complete ?
Yes
Wait till the liquid crystal driving
voltage stabilization time is reached
Wait till the VOUT voltage stabilizes when the
voltage doubler is used.
Set DISP of control register 2 to
“1”
Displaying of initial screen started
Setting complete
Power-Off Flowchart
LCD driving state
Turn off VIN
Turn off VDD
[Caution]
• The lines between output pins, and between output pins and other pins (input pins, I/O pins or power supply
pins), should not be short circuited.
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PRECAUTIONS WHEN TURNING ON THE POWER SUPPLY
To prevent the device from malfunctioning, observe the following power-on/off sequence:
For power-on, first turn on the logic power supply (VDD), then turn on the voltage doubler reference voltage (VIN)
or high voltage (VOUT or VHIN).
For power-off, first turn off the voltage doubler reference voltage (VIN) or high voltage (VOUT or VHIN), then turn
off the logic power supply (VDD).
[Voltage]
VOUT or VHIN pin voltage
VDD pin voltage
VDD = 2.0 V
[Time]
Power-On Sequence
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APPLICATION CIRCUIT
Application Example—1/10 duty, 1/4 bias, voltage doubler used (internal contrast adjustment not used)
LCD panel
56 × 10 dots
graphic
VCC
Temperature
compensating and
stabilizing
circuits
COM1–COM10
VDD
VIN
4.7 µF
VC1+
+
KPS
VS1–
VSS
VOUT
+
VDD = 5 V
SEG1–56
PA0
V0
4.7 µF
OSC1
ML9092-01
56 kΩ
OSC2
CPU
TEST
CS
CP
RESET
DI/O
Port
or
serial port
KREQ
1 µF
R4/C4
R3/C3
R2/C2
Rotary
switch
L.P.F.
R1/C1
A, B
PB0–PB2
PWM output
ports
C0/D0 C1/D1
C2/D2
R0/C0
C3/D3 C4/D4
5 × 5 key matrix
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PACKAGE DIMENSIONS
(Unit: mm)
TQFP100-P-1414-0.50-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.55 TYP.
4/Oct. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
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REVISION HISTORY
Document No.
FEDL9092-01
Date
Nov. 4, 2003
Page
Previous Current
Edition
Edition
—
—
Description
First edition
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NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2003 Oki Electric Industry Co., Ltd.
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