Catalyst CAT5401 Quad digitally programmable potentiometers (dppâ ¢) with 64 taps and spi interface Datasheet

CAT5401
Quad Digitally Programmable Potentiometers
(DPP™) with 64 Taps and SPI Interface
FEATURES
DESCRIPTION
„ Four linear taper digitally programmable
potentiometers
„ 64 resistor taps per potentiometer
„ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
„ Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
„ Low wiper resistance, typically 80Ω
„ Nonvolatile memory storage for up to four
wiper settings for each potentiometer
„ Automatic recall of saved wiper settings at
power up
„ 2.5 to 6.0 volt operation
„ Standby current less than 1µA
„ 1,000,000 nonvolatile WRITE cycles
„ 100 year nonvolatile memory data retention
„ 24-lead SOIC and 24-lead TSSOP
„ Industrial temperature range
The CAT5401 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of 63 resistive elements connected
between two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DPP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register.
The CAT5401 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
For Ordering Information details, see page 14.
PIN CONFIGURATION
TSSOP Package (Y)
SOIC Package (W)
1
24
NC
2
23
RH0
RW0
3
22
RL3
RH3
4
21
CS
5
20
WP
6
SI
7
CAT 19
5401 18
A1
RL1
RH1
8
17
SCK
9
16
10
15
RL2
RH2
RW1
GND
11
14
12
13
VCC
RL0
RW3
A0
SO
HOLD
FUNCTIONAL DIAGRAM
SI
1
24
WP
A1
RL1
RH1
2
23
CS
3
22
4
21
RW0
RH0
RW1
GND
5
20
6
NC
7
CAT 19
5401 18
RW2
RH2
RL2
8
17
9
16
10
15
11
14
12
13
RW2
SCK
NC
HOLD
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
RH0
CS
SCK
SI
SO
SPI BUS
INTERFACE
RH1
RH2
RH3
WIPER CONTROL
REGISTERS
RW0
RW1
RL0
VCC
WP
A0
A1
NC
RL3
RH3
RW3
CONTROL LOGIC
NONVOLATILE
DATA
REGISTERS
RW2
RW3
RL0
A0
SO
1
RL1
RL2
RL3
Doc. No. MD-2012 Rev. G
CAT5401
PIN DESCRIPTIONS
Pin#
(SOIC)
Pin#
(TSSOP)
Name
1
19
VCC
2
20
RL0
3
21
RH0
4
22
RW0
5
6
7
8
23
24
1
2
¯¯¯
CS
¯¯¯
WP
SI
A1
9
3
RL1
10
4
RH1
11
5
RW1
12
13
6
7
GND
NC
14
8
RW2
15
9
RH2
16
10
RL2
17
18
19
20
11
12
13
14
SCK
¯¯¯¯¯
HOLD
SO
A0
21
15
RW3
22
16
RH3
23
17
RL3
24
18
NC
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5401. Input data is latched on the rising edge of the
serial clock.
Function
Supply Voltage
Low Reference Terminal
for Potentiometer 0
High Reference Terminal
for Potentiometer 0
Wiper Terminal for
Potentiometer 0
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5401. During a read cycle,
data is shifted out on the falling edge of the serial
clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5401. Opcodes, byte
addresses or data present on the SI pin are latched on
the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal
for Potentiometer 1
High Reference Terminal
for Potentiometer 1
Wiper Terminal for
Potentiometer 1
Ground
A0, A1: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of four devices can be
addressed on a single bus. A match in the slave
address must be made with the address input in order
to initiate communication with the CAT5401.
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to the
terminal connections on a mechanical potentiometer.
RW: Wiper
The four RW pins are equivalent to the wiper terminal of
a mechanical potentiometer.
¯¯¯
CS : Chip Select
¯¯¯
CS is the Chip select pin. ¯¯¯
CS low enables the
CAT5401 and ¯¯¯
CS high disables the CAT5401. ¯¯¯
CS
high takes the SO output pin to high impedance and
forces the devices into a Standby mode (unless an
internal write operation is underway). The CAT5401
draws ZERO current in the Standby mode. A high to
low transition on ¯¯¯
CS is required prior to any sequence
being initiated. A low to high transition on ¯¯¯
CS after a
valid write sequence is what initiates an internal write
cycle.
No Connect
Wiper Terminal for
Potentiometer 2
High Reference Terminal
for Potentiometer 2
Low Reference Terminal
for Potentiometer 2
Bus Serial Clock
Hold
Serial Data Output
Device Address, LSB
Wiper Terminal for
Potentiometer 3
High Reference Terminal
for Potentiometer 3
Low Reference Terminal
for Potentiometer 3
No Connect
¯¯¯
WP: Write Protect
¯¯¯
WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When
¯¯¯
WP is tied low, all non-volatile write operations to the Data registers are inhibited (change of wiper control register
is allowed). ¯¯¯
WP going low while ¯¯¯
CS is still low will interrupt a write to the registers. If the internal write cycle has
already been initiated, ¯¯¯
WP going low will have no effect on any write operation.
¯¯¯¯¯ : Hold
HOLD
The ¯¯¯¯¯
HOLD pin is used to pause transmission to the CAT5401 while in the middle of a serial sequence without
¯¯¯¯¯ must be brought low while SCK is low. The
having to retransmit entire sequence at a later time. To pause, HOLD
SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be
¯¯¯¯¯ is brought high, while SCK is low. (HOLD
¯¯¯¯¯ should be held high any
ignored. To resume communication, HOLD
¯¯¯¯¯ may be tied high directly to VCC or tied to VCC through a resistor.
time this function is not being used.) HOLD
Doc. No. MD-2012 Rev. G
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5401
SERIAL BUS PROTOCOL
After the device is selected with ¯¯¯
CS going low the first
byte will be received. The part is accessed via the SI
pin, with data being clocked in on the rising edge of
SCK. The first byte contains one of the six op-codes
that define the operation to be performed.
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5401 to interface directly with
many of today's popular microcontrollers. The
CAT5041 contains an 8-bit instruction register. The
instruction set and the operation codes are detailed in
the instruction set table 3.
DEVICE OPERATION
The CAT5401 is four resistor arrays integrated with
SPI serial interface logic, four 6-bit wiper control
registers and sixteen 6-bit, non-volatile memory data
registers. Each resistor array contains 63 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL).
RH and RL are symmetrical and may be interchanged.
The tap positions between and at the ends of the
series resistors are connected to the output wiper
terminals (RW) by a CMOS transistor switch. Only one
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
tap point for each potentiometer is connected to its
wiper terminal at a time and is determined by the
value of the wiper control register. Data can be read
or written to the wiper control registers or the nonvolatile memory data registers via the SPI bus.
Additional instructions allows data to be transferred
between the wiper control registers and each
respective potentiometer's non-volatile data registers.
Also, the device can be instructed to operate in an
"increment/decrement" mode.
3
Doc. No. MD-2012 Rev. G
CAT5401
Absolute Maximum Ratings(1)
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to VSS(1) (2)
VCC with Respect to Ground
Package Power Dissipation Capability (TA = 25ºC)
Lead Soldering Temperature (10s)
Wiper Current
Ratings
-55 to +125
-65 to +150
-2.0 to +VCC + 2.0
-0.2 to +7.0
1.0
300
±12
Units
ºC
°C
V
V
W
ºC
mA
Ratings
+2.5 to +6
-40 to +85
Units
V
°C
Recommended Operating Conditions
Parameters
VCC
Industrial Temperature
Potentiometer Characteristics
Over recommended operating conditions unless otherwise stated.
Symbol
RPOT
RPOT
RPOT
RPOT
IW
RW
RW
VTERM
VN
TCRPOT
TCRATIO
CH/CL/CW
fc
Parameter
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
Potentiometer Resistance
Tolerance
RPOT Matching
Power Rating
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any RH or RL Pin
Noise
Resolution
Absolute Linearity (5)
Relative Linearity (6)
Temperature Coefficient of RPOT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
Test Conditions
Min
Typ
Max
100
50
10
2.5
25°C, each pot
IW = ±3mA @ VCC = 3V
IW = ±3mA @ VCC = 5V
VSS = 0V
(4)
200
100
GND
kΩ
kΩ
kΩ
kΩ
±20
%
1
50
+3
300
150
VCC
%
mW
mA
Ω
Ω
V
0.4
RW(n)(actual) - R(n)(expected)(8)
RW(n+1) - [RW(n) + LSB](8)
(4)
(4)
(4)
RPOT = 50kΩ (4)
+1
+0.2
+300
20
10/10/25
0.4
Units
nV√Hz
%
LSB (7)
LSB (7)
ppm/ºC
ppm/ºC
pF
MHz
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
(7) LSB = RTOT / 255 or (RH - RL) / 255, single pot
(8) n = 0, 1, 2, ..., 255
Doc. No. MD-2012 Rev. G
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5401
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Test Conditions
ICC
Power Supply Current
ISB
ILI
Min
Max
Units
fSCL = 2MHz, SO = Open
Inputs = GND
1
mA
Standby Current (VCC = 5.0V)
VIN = GND or VCC, SO = Open
5
µA
Input Leakage Current
VIN = GND to VCC
10
µA
VOUT = GND to VCC
ILO
Output Leakage Current
10
µA
VIL
Input Low Voltage
-1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
VOL1
Output Low Voltage (VCC = 3.0V)
0.4
V
IOL = 3 mA
PIN Capacitance (1)
Available over recommended operating range from TA = 25ºC, f = 1.0MHz, VCC = 5V (unless otherwise noted).
Symbol
COUT
CIN
Test
Conditions
Max.
Units
Input/Output Capacitance (SDA)
VOUT = 0V
8
pF
Input Capacitance (A0, A1, A2, A3, SCL, ¯¯¯
WP)
VIN = 0V
6
pF
Max
Units
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Test Conditions
Min
Typ
tSU
Data Setup Time
50
ns
tH
Data Hold Time
50
ns
tWH
SCK High Time
125
ns
tWL
SCK Low Time
125
ns
fSCK
Clock Frequency
DC
tLZ
tRI(
1)
3
MHz
¯¯¯¯¯ to Output Low Z
HOLD
50
ns
Input Rise Time
2
µs
tFI(1)
Input Fall Time
2
µs
tHD
tCD
¯¯¯¯¯ Setup Time
HOLD
¯¯¯¯¯ Hold Time
HOLD
tWC
Write Cycle Time
10
ms
tV
Output Valid from Clock Low
250
ns
tHO
Output Hold Time
tDIS
Output Disable Time
250
ns
tHZ
¯¯¯¯¯ to Output High Z
HOLD
¯¯¯
CS High Time
100
ns
tCS
tCSS
tCSH
CL = 50pF
100
ns
100
ns
0
¯¯¯
CS Setup Time
¯¯¯
CS Hold Time
ns
250
ns
250
ns
250
ns
Note:
(1)
This parameter is tested initially and after a design or process change that affects the parameter.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-2012 Rev. G
CAT5401
Power Up Timing (1)(2)
Symbol
Max
Units
tPUR
Power-up to Read Operation
Parameter
1
ms
tPUW
Power-up to Write Operation
1
ms
Max
Units
5
ms
Write Cycle Limits
Symbol
tWR
Parameter
Write Cycle Time
Reliability Characteristics
Symbol
NEND
(3)
TDR(3)
VZAP(3)
ILTH(3)
Parameter
Reference Test Method
Min
Max
Units
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
Data Retention
MIL-STD-883, Test Method 1008
100
Years
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
V
Latch-Up
JEDEC Standard 17
100
mA
Figure 1. Synchronous Data Timing
tCS
VIH
CS
VIL
tCSH
tCSS
SCK
VIH
tH
tSU
VIH
SI
tWL
tWH
VIL
VALID IN
VIL
tRI
tFI
tV
SO
VOH
tHO
tDIS
HI-Z
HI-Z
VOL
¯¯¯¯¯ Timing
Figure 2. HOLD
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
HIGH IMPEDANCE
SO
tLZ
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Dashed Line = mode (1, 1) - - - - - - -
Doc. No. MD-2012 Rev. G
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5401
INSTRUCTION AND REGISTER
DESCRIPTION
INSTRUCTION BYTE
The next byte sent to the CAT5401 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I [3:0]. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of four Wiper
Control Registers. The format is shown in Table 2.
DEVICE TYPE / ADDRESS BYTE
The first byte sent to the CAT5401 from the master/
processor is called the Device Address Byte. The
most significant four bits of the Device Type address
are a device type identifier. These bits for the
CAT5401 are fixed at 0101[B] (refer to Table 1).
The two least significant bits in the slave address
byte, A1 - A0, are the internal slave address and must
match the physical device address which is defined by
the state of the A1 - A0 input pins for the CAT5401 to
successfully continue the command sequence. Only
the device which slave address matches the incoming
device address sent by the master executes the
instruction. The A1 - A0 inputs can be actively driven
by CMOS input signals or tied to VCC or VSS. The
remaining two bits in the device address byte must be
set to 0.
Data Register Selection
Data Register Selected
R1
R0
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
Table 1. Identification Byte Format
Device Type
Identifier
ID3
0
ID2
1
ID1
0
Slave Address
ID0
1
0
0
A1
(MSB)
A0
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
I3
(MSB)
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
I2
Data Register
Selection
I1
I0
R1
7
R0
WCR/Pot Selection
P1
P0
(LSB)
Doc. No. MD-2012 Rev. G
CAT5401
Registers is a non-volatile operation and will take a
maximum of 5ms.
Wiper Control and Data Registers
Wiper Control Register (WCR)
The CAT5401 contains four 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of 64
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written by
the host via Write Wiper Control Register instruction; it
may be written by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction, it can be modified one step at a
time by the Increment/decrement instruction (see
Instruction section for more details). Finally, it is
loaded with the content of its data register zero (DR0)
upon power-up.
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the ¯¯¯
CS input goes HIGH
after a write sequence is received. The status of the
internal write cycle can be monitored by issuing a
Read Status command to read the Write in Process
(WIP) bit.
Instructions
Four of the nine instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register – read the current
wiper position of the selected potentiometer in the
WCR
— Write Wiper Control Register – change current
wiper position in the WCR of the selected
potentiometer
— Read Data Register – read the contents of the
selected Data Register
— Write Data Register – write a new value to the
selected Data Register
— Read Status – Read the status of the WIP bit
which when set to "1" signifies a write cycle is in
progress.
The Wiper Control Register is a volatile register that
loses its contents when the CAT5401 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Data Registers (DR)
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data
Table 3. Instruction Set
Note: 1/0 = data is one or zero
Instruction Set
Instruction
Read Wiper Control
Register
Write Wiper Control
Register
Read Data Register
I3
I2
I1
I0
R1
R0
WCR1/ P1
WCR0/ P0
1
0
0
1
0
0
1/0
1/0
Read the contents of the Wiper Control
Register pointed to by P1-P0
1
0
1
0
0
0
1/0
1/0
Write new value to the Wiper Control
Register pointed to by P1-P0
1
0
1
1
1/0
1/0
1/0
1/0
Write Data Register
1
1
0
0
1/0
1/0
1/0
1/0
XFR Data Register to
Wiper Control Register
1
1
0
1
1/0
1/0
1/0
1/0
XFR Wiper Control
Register to Data
Register
Global XFR Data
Registers to Wiper
Control Registers
Global XFR Wiper
Control Registers to
Data Register
Increment/Decrement
Wiper Control Register
Read Status (WIP bit)
1
1
1
0
1/0
1/0
1/0
1/0
Read the contents of the Data Register
pointed to by P1-P0 and R1-R0
Write new value to the Data Register
pointed to by P1-P0 and R1-R0
Transfer the contents of the Data Register
pointed to by P1-P0 and R1-R0 to its
associated Wiper Control Register
Transfer the contents of the Wiper Control
Register pointed to by P1-P0 to the Data
Register pointed to by R1-R0
0
0
0
1
1/0
1/0
0
0
Transfer the contents of the Data Registers
pointed to by R1-R0 of all four pots to their
respective Wiper Control Registers
1
0
0
0
1/0
1/0
0
0
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1-R0 of all four pots
0
0
1
0
0
0
1/0
1/0
Enable Increment/decrement of the Control
Latch pointed to by P1-P0
0
1
0
1
0
0
0
1
Doc. No. MD-2012 Rev. G
8
Operation
Read WIP bit to check internal write cycle
status
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5401
— Gang XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Gang XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be
delayed by tWRL. A transfer from the WCR (current
wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the
four potentiometers and one of its associated
registers; or the transfer can occur between all
potentiometers and one associated register.
Increment/Decrement Command
The final command is Increment/Decrement (Figure
5). The Increment/Decrement command is different
from the other commands. Once the command is
issued the master can clock the selected wiper up
and/or down in one segment steps; thereby providing
a fine tuning capability to the host. For each SCK
clock pulse (tHIGH) while SI is HIGH, the selected wiper
will move one resistor segment towards the RH
terminal. Similarly, for each SCK clock pulse while SI
is LOW, the selected wiper will move one resistor
segment towards the RL terminal.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 3. These instructions
transfer data between the host/processor and the
CAT5401; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
See Instructions format for more detail.
Figure 3. Two-Byte Instruction Sequence
SI
0
1
0
1
0
ID3 ID2 ID1 ID0 A3
0
A2 A1 A0 I3
Internal
Address
Device ID
I2
I1
R1 R0 P1 P0
I0
Instruction
Opcode
Register
Address
Pot/WCR
Address
Figure 4. Three-Byte Instruction Sequence
SI
0
1
0
1
0
0
A2
ID3 ID2 ID1 ID0 A3
A1
A0 I3
Internal
Address
Device ID
I2
I1 I0
R1 R0 P1 P0
Instruction
Opcode
D7 D6 D5 D4 D3 D2 D1 D0
Data
Pot/WCR
Register Address
Address
WCR[7:0]
or
Data Register D[7:0]
Figure 5. Increment/Decrement Instruction Sequence
SI
0
1
0
1
0
ID3 ID2 ID1 ID0
A3
Device ID
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
0
A2 A1 A0
Internal
Address
I3
I2
I1
I0
Instruction
Opcode
9
R1 R0 P1 P0
I
N
Pot/WCR C
Data
Register Address 1
Address
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
Doc. No. MD-2012 Rev. G
CAT5401
Figure 6. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
tWRID
SCK
SI
Voltage Out
RW
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
DEVICE ADDRESSES
¯¯¯
CS
0
1
0
1
0
0
A1
INSTRUCTION
A0
1
0
0
1
0
0
DATA
P1
P0
7
0
6
0
5
4
3
2
1
0
2
1
0
2
1
0
2
1
0
¯¯¯
CS
Write Wiper Control Register (WCR)
DEVICE ADDRESSES
¯¯¯
CS
0
1
0
1
0
0
A1
INSTRUCTION
A0
1
0
1
0
0
0
DATA
P1
P0
7
0
6
0
5
4
3
¯¯¯
CS
Read Data Register (DR)
DEVICE ADDRESSES
¯¯¯
CS
0
1
0
1
0
0
A1
INSTRUCTION
A0
1
0
1
1
R1
R0
DATA
P1
P0
7
6
5
4
3
¯¯¯
CS
Write Data Register (DR)
DEVICE ADDRESSES
¯¯¯
CS
0
1
0
1
0
0
A1
INSTRUCTION
A0
1
1
0
0
R1
R0
DATA
P1
P0
7
6
5
4
3
¯¯¯
CS
High
Voltage
Write
Cycle
Read (WIP) Status
DEVICE ADDRESSES
¯¯¯
CS
0
1
0
Doc. No. MD-2012 Rev. G
1
0
0
A1
INSTRUCTION
A0
0
1
0
1
0
0
10
DATA
0
1
7
0
6
0
5
0
4
0
3
0
2
0
1
0
W
I
P
¯¯¯
CS
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5401
INSTRUCTION FORMAT (continued)
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
¯¯¯
CS
0
1
0
1
0
0
A1
INSTRUCTION
A0
0
0
0
1
R1
R0
0
0
¯¯¯
CS
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
¯¯¯
CS
0
1
0
1
0
0
A1
INSTRUCTION
A0
1
0
0
0
R1
R0
0
0
¯¯¯
CS
High
Voltage
Write
Cycle
¯¯¯
CS
High
Voltage
Write
Cycle
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
¯¯¯
CS
0
1
0
1
0
0
A1
INSTRUCTION
A0
1
1
1
0
R1
R0
P1
P0
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
¯¯¯
CS
0
1
0
1
0
0
A1
INSTRUCTION
A0
1
1
0
1
R1
R0
P1
P0
P1
P0
¯¯¯
CS
Increment (I)/Decrement (D) Wiper Control Register (WCR)
DEVICE ADDRESSES
¯¯¯
CS
0
1
0
1
0
0
A1
INSTRUCTION
A0
0
0
1
0
0
0
DATA
I/D
I/D
...
I/D
I/D
¯¯¯
CS
Note:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after ¯¯¯
CS goes high.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. MD-2012 Rev. G
CAT5401
PACKAGE OUTLINES
SOIC 24-Lead 300mils (W) (1)(2)
E1
SYMBOL
MIN
A
2.35
2.65
A1
0.10
0.30
A2
2.05
2.55
b
0.31
0.51
c
0.20
0.33
D
15.20
15.40
E
10.11
10.51
E1
7.34
E
e
b
e
PIN#1 IDENTIFICATION
NOM
MAX
7.60
1.27 BSC
h
0.25
0.75
L
0.40
1.27
θ
0°
8°
θ1
5°
15°
TOP VIEW
h
D
A2
A
h
θ1
θ
θ1
L
A1
SIDE VIEW
c
END VIEW
2HFor current Tape and Reel information, download the PDF file
from:
Notes:
(1) All dimensions are in millimeters, angles in degrees.
(2) Complies with JEDEC standard MO-013.
Doc. No. MD-2012 Rev. G
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5401
TSSOP 24-Lead 4.4mm (Y)
(1)(2)
b
SYMBOL
MIN
NOM
MAX
A
E1
E
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
D
7.70
0.20
7.80
7.90
E
6.25
6.40
6.55
E1
4.30
4.40
4.50
e
0.65 BSC
L
1.00 REF
L1
0.50
θ1
0°
0.60
0.70
8°
e
TOP VIEW
D
c
A2
A
θ1
L1
A1
L
SIDE VIEW
END VIEW
3HFor current Tape and Reel information, download the PDF file
from:
Notes:
(1) All dimensions are in millimeters, angles in degrees.
(2) Complies with JEDEC standard MO-153.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. MD-2012 Rev. G
CAT5401
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
CAT
5401
Company ID
W
Package
W: SOIC
Y: TSSOP
I
Temperature Range
I = Industrial (-40ºC to 85ºC)
-00
- T1
Resistance
25: 2.5kΩ
10: 10kΩ
50: 50kΩ
00: 100kΩ
Tape & Reel
T: Tape & Reel
1: 1000/Reel - SOIC
2: 2000/Reel - TSSOP
Product Number
5401
Notes:
(1)
All packages are RoHS-compliant (Lead-free, Halogen-free).
(2)
The device used in the above example is a CAT5401WI-00-T1 (SOIC, Industrial Temperature, 100kΩ, Tape & Reel).
(3)
The lead finish is Matte-Tin.
Ordering Part Number
CAT5401WI-25
CAT5401WI-10
CAT5401WI-50
CAT5401WI-00
CAT5401YI-25
CAT5401YI-10
CAT5401YI-50
CAT5401YI-00
Doc. No. MD-2012 Rev. G
14
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
REVISION HISTORY
Date
Rev.
03/31/2004
F
10/16/2007
G
Reason
Changed Preliminary designation to Final
Eliminated Commercial temp range in all areas
Updated Potentiometer characteristics notes
Updated Pin Descriptions (A0, A1 and ¯¯¯
WP)
Updated notes for Absolute Max Ratings 80
and Potentiometer Characteristics
Added Example of Ordering Information
Deleted BGA package
Added MD- to document number
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal
injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax:
408.542.1200
1Hwww.catsemi.com
Document No: MD-2012
Revision:
G
Issue date:
10/16/07
Similar pages