Cherry CS8140YDWR24 5v, 500ma linear regulator with enable, , and watchdog reset Datasheet

CS8140/1
CS8140/1
5V, 500mA Linear Regulator with
ENABLE, RESET , and Watchdog
Description
The CS8140 is a 5V Watchdog
Regulator with protection circuitry and
three logic control functions that allow
a microprocessor to control its own
power supply. The CS8140 is designed
for use in automotive, switch mode
power supply post regulator, and battery powered systems.
Basic regulator performance characteristics include a low noise, low drift, 5V
± 4% precision output voltage with low
dropout voltage (1.25V @ IOUT = 500mA)
and low quiescent current (7mA @ IOUT
= 500mA). On board short circuit, thermal, and overvoltage protection make it
possible to use this regulator in particularly harsh operating environments.
The Watchdog logic function monitors
an input signal (WDI) from the microprocessor or other signal source. When
the signal frequency moves outside
externally programmable window limits, a RESET signal is generated
( RESET ). An external capacitor
(CDELAY) programs the watchdog window frequency limits as well as the
power on reset (POR) and RESET delay.
The RESET function is activated by any
Features
of three conditions: the watchdog signal moves outside of its preset limits;
the output voltage drops out of regulation by more than 4.5%; or the IC is in
its power up sequence. The RESET signal is independent of VIN and reliable
down to VOUT = 1V.
In conjunction with the Watchdog, the
ENABLE function controls the regulatorÕs power consumption. The CS8140Õs
output stage and its attendant circuitry
are enabled by setting the ENABLE
lead high. The regulator goes into sleep
mode (IOUT = 250µA) when the
ENABLE lead goes low and the watchdog signal moves outside its preset
window limits. This unique combination of control functions in the CS8140
gives the microprocessor control over
its own power down sequence: i.e. it
gives the microprocessor the flexibility
to perform housekeeping functions
before it powers down.
■ 5V ± 4%, 500mA Output
Voltage
■ µP Compatible Control
Functions
Watchdog
RESET
ENABLE
■ Low Dropout Voltage
(1.25V @ 500mA)
■ Low Quiescent Current
(7mA @ 500mA)
■ Low Noise, Low Drift
■ Low Current SLEEP Mode
(IQ = 250µA)
■ Fault Protection
Thermal Shutdown
Short Circuit
60V Peak Transient
Voltage
Package Options
The CS8141 has the same features as the
CS8140, except that the CS8141 only
responds to input signals (WDI) which
are below the preset watchdog frequency threshold.
24 Lead SOIC Wide
NC
Block Diagram
VIN
Reference
& Bias
Overvoltage
Overtemperature
Regulation
ENABLE
WDI
Control Logic
ENABLE
RESET
Delay
ENABLE
WDI
NC
VOUT
VIN
Sense
Gnd
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Gnd
NC
14 Lead PDIP
VOUT
Short Circuit
*
Undervoltage
Gnd
RESET
1
Delay
*NOTE: shorted together
on 7 Lead TO-220
Sense
Watchdog
RESET
Delay
WDI
1
7 Lead TO-220
Tab (Gnd)
RESET
ENABLE
VOUT
VIN
Sense
Gnd
NC
NC
NC
NC
NC
NC
Delay
1
2
3
4
5
6
7
VIN
ENABLE
RESET
Gnd
Delay
WDI
VOUT
1
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
Rev. 2/23/99
1
A
¨
Company
CS8140/1
Absolute Maximum Ratings
Input Voltage
Operating Range .................................................................................................................................................-0.5 to +26V
Peak Transient Voltage (46V Load Dump @ 14V VBAT) ..............................................................................................60V
Electrostatic Discharge
(Human Body Model)...............................................................................................................................................4kV
WDI Input Signal Range ...............................................................................................................................................-0.3 to +7V
Internal Power Dissipation ..............................................................................................................................Internally limited
Junction Temperature Range (TJ) .......................................................................................................................-40¡C to +150¡C
Storage Temperature Range ................................................................................................................................-65¡C to +150¡C
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260¡C peak
Reflow (SMD styles only) ......................................................................................60 sec. max above 183¡C, 230¡C peak
ENABLE .......................................................................................................................................................................-0.3V to VIN
Electrical Characteristics: 7V ² VIN ² 26V, 5mA ² IOUT ² 500mA, -40ûC ² TJ ² +150ûC, -40ûC ² TA ² 125ûC
unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.8
5.0
5.2
V
■ Output Stage (VOUT)
Output Voltage, VOUT
7V ² VIN ² 26V
5mA < IOUT < 500mA
Dropout Voltage (VIN - VOUT)
IOUT = 500mA
1.25
1.50
V
Line Regulation
IOUT = 50mA,
7V ² VIN ² 26V
5
25
mV
Load Regulation
VIN = 14V,
50mA ² IOUT ² 500mA
5
80
mV
Output Impedance, ROUT
500mA DC and 10mA AC ,
100Hz ² f ² 10kHz
200
0 ² IOUT ² 500mA, 7V ² VIN ² 26V
IOUT = 0mA, VIN = 13V, ENABLE = 0V
7.00
0.25
Quiescent Current, (IQ)
Active Mode
Sleep Mode
Ripple Rejection
15.00
0.50
mA
mA
60
75
Current Limit
700
1200
Thermal Shutdown
150
180
30
34
38
V
4.05
3.95
4.50
3.50
V
V
Overvoltage Shutdown
7 ² VIN ² 17V, IOUT = 250mA,
f = 120Hz
m½
VOUT < 1V
dB
2000
mA
¡C
■ ENABLE
Threshold
HIGH
LOW
Threshold Hysteresis
VOUT ³ 0.5V, (VOUT(ON))
VOUT < 0.5V, (VOUT(OFF))
(HIGH - LOW)
100
2
mV
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
■ RESET
Threshold
HIGH VR(HI)
VOUT increasing
4.65
4.90
VOUT - 0.05
V
LOW VR(LOW)
VOUT decreasing
4.50
4.70
4.90
V
Threshold Hysteresis(VRH)
(HIGH - LOW)
150
200
250
mV
Reset Output Leakage
VOUT ³ VR(HI)
25
µA
0.1
0.4
V
0.6
1.0
V
47.5
1.0
65.0
1.5
ms
ms
0.8
V
V
0
10
µA
77
262
96
326
Hz
Hz
RESET = HIGH
Output Voltage
Low(VL(LOW) )
Low (VRpeak )
1V ² VOUT ² VR(LOW)
Rp = 2.7k½*
VOUT, Power up, Power down
CDELAY = 0.1µF
Delay Times
tPOR
tWDI( RESET )
30.0
0.5
■ Watchdog
Input Voltage
HIGH
LOW
2.0
Input Current
WDI ² VOUT
Threshold Frequency
fWDILOWER
fWDI(UPPER)**
CDELAY = 0.1µF
64
218
* RP is connected to RESET and VOUT.
** CS8140 only
To observe safe operating junction temperature, low duty cycle pulse testing is used on tests where applicable.
Package Lead Description
Package Lead #
Lead Symbol
7 Lead
TO-220
1
24 Lead *
SOIC Wide
21
14 Lead
PDIP
12
2
23
3
Function
VIN
Supply voltage to IC, usually direct from the battery.
13
ENABLE
CMOS compatible logical input. VOUT is disabled when
ENABLE is LOW and WDI is beyond its preset limits.
24
14
RESET
CMOS compatible output lead. RESET goes low whenever
VOUT drops below 4.5% of its typical value for more than
2µs or WDI signal falls outside itÕs window limits.
4
12, 20
11
Gnd
Ground connection.
5
2
1
Delay
Timing capacitor for Watchdog and RESET functions.
6
3
2
WDI
CMOS compatible input lead. The Watchdog function monitors the falling edge of the incoming digital pulse train. The
signal is usually generated by the system microprocessor.
7
4
3
VOUT
Regulated output voltage, 5V (typ).
N/A
5
4
Sense
Kelvin connection which allows remote sensing of output
voltage for improved regulation.
1,6-11,13-19,22
5-10
NC
No connection.
* The CS8141 uses a fused lead package. Leads 6-8 and 17-19 are fused together through the lead frame. These leads are
electrically connected to IC ground and should be connected to system ground for a good thermal connection.
3
CS8140/1
Electrical Characteristics: continued
CS8140/1
Typical Performance Characteristics
VOUT vs. VIN over RLOAD; T = 25ûC
VOUT vs. VIN over Temperature; RLOAD = 25½
5.5
5.5
VENABLE = VIN
VENABLE = VIN
5.0
5.0
4.5
4.5
Rload = NO LOAD
4.0
TEMP = 125°C
4.0
TEMP = -40 °C
Rload = 6.67W
VOUT (V)
VOUT (V)
3.5
Rload = 10W
3.0
2.5
3.5
TEMP = 25°C
3.0
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
0.0
0
1
2
3
4
5
6
7
8
9
0
10
1
2
3
4
5
VIN (V)
7
8
9
10
VIN (V)
Dropout Voltage vs. Output Current over Temperature
Load Regulation vs. Output Current over Temperature
3.5
1800
-40°C
0
1600
25°C
-3.5
LOAD REGULATION (mV)
1400
Dropout Voltage (mV)
6
1200
-40°C
1000
125°C
25°C
800
600
400
-7.0
-10.5
-14.0
VIN = 14V
-17.5
-21.0
125°C
-24.5
-28.0
200
-31.5
0
-35.0
0
100
200
300
400
500
600
700
800
0
100
200
300
IOUT (mA)
Line Regulation vs. Output Current over Temperature
500
600
700
800
Quiescent Current vs. Output Current over Temperature
10
18
VIN = 14V
VIN = 14V
16
9
14
-40°C
12
8
10
-40°C
8
IQ (mA)
LINE REGULATION (mV)
400
IOUT (mA)
6
25°C
4
7
125°C
2
6
0
25°C
125°C
-2
5
-4
-6
4
0
100
200
300
400
500
600
700
800
0
IOUT (mA)
100
200
300
400
IOUT (mA)
4
500
600
700
800
CS8140/1
Typical Performance Characteristics: continued
Quiescent Current vs. VIN over RLOAD; T = 25¡C
Quiescent Current vs. VIN over Temperature; RLOAD = 25½
20
20
VENABLE = VIN
VENABLE = VIN
18
18
16
16
14
14
12
12
IQ (mA)
IQ (mA)
TEMP = 25°C
Rload = 6.67
10
10
8
Rload = 25
8
6
Rload = NO LOAD
6
TEMP =- 40°C
TEMP = 125°C
4
4
2
2
0
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
VIN (V)
5
6
7
8
9
10
VIN (V)
Watchdog Frequency Thresholds vs. Temperature
Watchdog Frequency Threshold vs CDELAY
107
300
280
106
260
Upper Threshold
105
220
WDI THRESHOLD
FREQUENCY (Hz)
240
200
CDELAY = 0.1mF
180
160
140
120
104
Upper Threshold
103
Lower Threshold
102
Lower Threshold
100
80
101
60
-40 -30 -20 -10
0
10
20 30 40 50 60 70 80
90 100 110 120 130 140 150
100
101
TJ (°C)
102
103
104
105
106
107
CAPACITANCE (pF)
Ripple Rejection vs Frequency
RESET Output Voltage vs Output Current
90
RESET OUTPUT VOLTAGE (mV)
80
2000
IO =250mA
REJECTION (dB)
70
CO = 10mF, ESR=1&0.1mF, ESR=0
60
50
40
30
CO = 10mF,ESR=1W
20
CO = 10mF, ESR=10W
10
0
100
1800
VIN = 5V
1600
1400
1200
1000
800
600
400
200
0
101
102
103
104
105
106
107
108
1
5
10
15
20
25
RESET OUTPUT CURRENT (mA)
FREQUENCY (Hz)
5
30
35
40
CS8140/1
Definition of Terms
Dropout Voltage
The input-output voltage differential at which the circuit
ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped
100mV from the nominal value obtained at 14V input,
dropout voltage is dependent upon load current and junction temperature.
Input Voltage
The DC voltage applied to the input terminals with respect
to ground.
Line Regulation
The change in output voltage for a change in the input
voltage. The measurement is made under conditions of
low dissipation or by using pulse techniques such that the
average chip temperature is not significantly affected.
Load Regulation
The change in output voltage for a change in load current
at constant chip temperature.
Quiescent Current
The part of the positive input current that does not contribute to the positive load current. The regulator ground
lead current.
Ripple Rejection
The ratio of the peak-to-peak input ripple voltage to the
peak-to-peak output ripple voltage.
Current Limit
Peak current that can be delivered to the output.
Circuit Description
circuitry insures that the output current never exceeds a
preset limit.
Voltage Reference and Output Circuitry
Precision Voltage Reference
The regulated output voltage depends on the precision
band gap voltage reference in the IC. By adding an error
amplifier into the feedback loop , the output voltage is maintained within ±4% over temperature and supply variation.
> 30V
VIN
VOUT
Output Stage
The composite PNP-NPN output structure (Figure1) provides 500mA (min) of output current while maintaining a
low drop out voltage (1.25V) and drawing little quiescent
current (7mA).
IO
VIN
Load
Dump
Thermal
Shutdown
Short
Circuit
Figure 2: Typical Circuit Waveforms for Output Stage Protection.
Should the junction temperature of the power device
exceed 180ûC (typ), the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
VOUT
Figure 1: Composite Output Stage of the CS8140/1
Regulator Control Functions
The NPN pass device prevents deep saturation of the output stage which in turn improves the ICÕs efficiency by
preventing excess current from being used and dissipated
by the IC.
The CS8140 differs from all other linear regulators in its
unique combination of control features.
Watchdog and ENABLE Functions
VOUT is controlled by the logic functions ENABLE and
Watchdog (Table 1).
Output Stage Protection
The output stage is protected against overvoltage, short
circuit and thermal runaway conditions (Figure 2).
VOUT (V)
If the input voltage rises above 30V (e.g. load dump), the
output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage
transients.
ENABLE
H
L
Using an emitter sense scheme, the amount of current
through the NPN pass transistor is monitored. Feedback
Slow
5
0
Normal
5
5
WDI
Fast
5
0
High
5
0
Table 1: VOUT as a Function of ENABLE and Watchdog
6
Low
5
0
3a: VOUT when Watchdog is held high and ENABLE = HIGH.
Battery
VIN
Battery
ENABLE
WDI 0V
RESET 0V
VOUT 0V
POR
Normal Operation
WDI held High
3b: VOUT when Watchdog is held low and ENABLE = HIGH.
Battery
VIN
Battery
ENABLE
WDI 0V
RESET 0V
VOUT 0V
POR
Normal Operation
WDI held Low
3c: VOUT when Watchdog is too slow and ENABLE = HIGH.
Battery
VIN
Battery
ENABLE
WDI 0V
RESET 0V
VOUT 0V
POR
Normal Operation
Slow WDI signal
3d: VOUT when Watchdog is too fast and ENABLE = HIGH.
Battery
VIN
Battery
ENABLE
WDI 0V
RESET 0V
VOUT 0V
POR
Normal Operation
Fast WDI signal
3e: WDI held high after a normal period of operation; ENABLE = LOW.
Battery
VIN
Battery
ENABLE
WDI 0V
RESET 0V
VOUT 0V
POR
Normal Operation
WDI
high
Sleep Mode
POR
Normal Operation
3f: WDI held low or is too slow after a normal period of operation; ENABLE = LOW.
Battery
VIN
Battery
ENABLE
WDI 0V
RESET 0V
VOUT 0V
POR
Normal Operation
WDI
low
Sleep Mode
POR
Normal Operation
3g: WDI frequency rises above the upper frequency threshold after a normal period of operation; ENABLE = LOW
(for the CS8140 only).
Battery
VIN
Battery
ENABLE
WDI 0V
RESET 0V
VOUT 0V
POR
Normal Operation
Sleep Mode
7
POR
Normal Operation
CS8140/1
Figure 3: Timing Diagrams for Watchdog and ENABLE Functions
CS8140/1
Circuit Description: continued
As long as ENABLE is high or ENABLE is low and the
Watchdog signal is normal, VOUT will be at 5V (typ). If
ENABLE is low and the Watchdog signal moves outside
programmable limits, the output transistor turns off and
the IC goes into SLEEP mode. Only the ENABLE circuitry
in the IC remains powered up, drawing a quiescent current of 250µA.
RESET Circuit Waveforms with Delays Indicated
VOUT
VRHI
VRLO
RESET
The Watchdog monitors the frequency of an incoming
WDI signal. If the signal falls outside of the WDI window,
a frequency programmable pulse train is generated at the
RESET lead (Figure 3) until the correct Watchdog input
signal reappears at the lead (ENABLE = HIGH).
VRLO
VRPEAK
tPOR
The lower and upper window threshold limits of the
watchdog function are set by the value of CDELAY. The limits are determined according to the following equations for
the CS8140:
(a)
4a: Power RESET and Power Down
VOUT
tWDILOWER = (1.3 x 105)CDELAY or
VOUT -4.5%
<2mS
f WDI(LOWER) = (7.69 x 10-6)CDELAY-1
(b)
³2ms
t WDI(UPPER) = (3.82 x 10-4)CDELAY or
fWDI(UPPER) = (2.62 x 10-5)CDELAY-1
RESET
5V
For the CS8141 the lower limit is determined by the equations in (a) above.
The capacitor CDELAY also determines the frequency of the
RESET signal and the POWER-ON- RESET (POR) delay
period.
tPOR
4b: Undervoltage Triggered RESET
If an undervoltage condition exists, the voltage on the
RESET lead goes low and the delay capacitor, CDELAY, is
discharged. RESET remains low until output is in regulation, the voltage on CDELAY exceeds the upper switching
threshold and the Watchdog input signal is within its set
window limits (Figure 4). The delay after the output is in
regulation is:
tPOR(typ) = (4.75 x 10 5) CDELAY
RESET Function
The RESET function is activated when the Watchdog signal is outside of its preset window (Figure 3), when the
regulator is in its power up state (Figure 4a) or when VOUT
drops below VOUT -4.5% for more than 2µs (Figure 4b.)
If the Watchdog signal falls outside of the preset voltage
and frequency window, a frequency programmable pulse
train is generated at the RESET lead (Figure 3) until the
correct Watchdog input signal reappears at the lead. The
duration of the RESET pulse is determined by CDELAY
according to the following equation:
The RESET delay circuit is also programmed with the
external cap CDELAY.
The output of the reset circuit is an open collector NPN.
RESET is operational down to VOUT = 1V. Both RESET and
its delay are governed by comparators with hysteresis to
avoid undesirable oscillations.
tWDI(RESET) = (1 x10 4)CDELAY
Application Notes
Assume that the reset delay must be 200ms minimum.
From the CS8140 data sheet the reset delay has a ±37% tolerance due to the regulator.
Assume the capacitor tolerance is ±10%.
tPOR (min) = (4.75 x 105 x 0.63) x CDELAY x 0.9
CS8140 Design Example
The CS8140 with its unique integration of linear regulator
and control features: RESET , ENABLE and WATCHDOG,
provides a single IC solution for a microprocessor power
supply. The reset delay, reset duration and watchdog frequency limits are all determined by a single capacitor. For
a particular microprocessor the overriding requirement is
usually the reset delay (also known as power on reset).
The capacitor is chosen to meet this requirement and the
reset duration and watchdog frequency follow.
The reset delay is given by:
tPOR(typ) = (4.75 x 105)CDELAY
CDELAY (min) =
tPOR (min)
2.69 x 105
CDELAY = (min) = 0.743 µF
Closest standard value is 0.82µF.
Minimum and maximum delays using 0.82µF are 220ms
and 586ms.
8
The duration of the reset pulse is given by:
TWDI(RESET)(typ) = (1 x 104) x CDELAY
This has a tolerance of ±50% due to the IC, and ±10% due
to the capacitor.
The duration of the reset pulse ranges from 3.69ms to
13.5ms.
The watchdog signal can be expressed as a frequency or
time. From a programmers point of view, time is more
useful since they must ensure that a watchdog signal is
issued consistently several times per second.
The maximum and minimum watchdog times are given
by:
tWDI(LOWER) = (1.3 x 105)CDELAY
tWDI(UPPER) = (3.82 x 104)CDELAY
Energy Conservation and Smart Features
Energy conservation is another benefit of using a regulator
with integrated microprocessor control features. Using the
CS8140 or CS8141 as indicated in Figure 8, the microprocessor can control its own power down sequence. The
momentary contact switch quickly charges C1 through R1.
When the voltage across C1 reaches 3.95V ( the enable
threshold), the output switches on and VOUT rises to 5V.
After a delay period determined by CDelay, a frequency
programmable reset pulse train is generated at the reset
output. The pulse train continues until the correct watchdog signal appears at the WDI lead. C1 is now left to discharge through the input impedance of the enable lead
(approximately 150k½) and the enable signal disappears.
The output voltage remains at 5V as long as the CS8140
continues to receive the correct watchdog signal.
The microprocessor can power itself down by terminating
its watchdog signal. When the microprocessor finishes its
housekeeping or power down software routine, it stops
sending a watchdog signal. In response, the regulator
generates a reset signal and goes into a sleep mode where
VOUT drops to 0V, shutting down the microprocessor.
There is a tolerance of ±20% due to the CS8140.
With a capacitor tolerance of ±10%:
tWDI(LOWER) = (1.3 x 105) x 1.20 x 1.1 x CDELAY
tWDI(UPPER) = (3.82 x 104) x 0.8 x 0.9 x CDELAY
tWDI(LOWER) = 141ms(max)
tWDI(UPPER) = 22.5ms (max)
Stability Considerations
The output or compensation capacitor C2 in Figure 7 helps
determine three main characteristics of a linear regulator:
start-up delay, load transient response and loop stability.
tWDI(LOWER) = (1.3 x 105) x 0.8 x 0.9 x CDELAY
tWDI(UPPER) = (3.82 x 104) x 1.2 x 1.1 x CDELAY
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25¡C to -40¡C), both the value and ESR of the
capacitor will vary considerably. The capacitor manufacturers data sheet usually provide this information.
tWDI(LOWER) = 76ms(min)
tWDI(UPPER) = 41ms (min)
The software must be written so that a watchdog signal
arrives at least every 76ms but not faster than every 41ms
(Figure 5).
PASS
FAIL
The value for the output capacitor C2 in Figure 7 should
work for most applications, however it is not necessarily
the optimized solution.
FAIL
Hz
7
9
13
24
32
44
ms
141
107
76
41
31
22.5
To determine an acceptable value for C2 for a particular
application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part.
C = 0.1mF ± 10%
Figure 5: WDI signal for CDelay = 0.82µF using CS8140.
Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade
box outside the chamber, the small resistance added by the
longer leads is negligible.
The CS8141 is identical to the CS8140 except that the
CS8141 only has a lower watchdog frequency threshold.
The designer using this part need only be concerned with
tWDI(LOWER) as shown in Figure 6.
FAIL
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load
while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to
ensure a stable design under steady state conditions.
PASS
Hz
7
13
ms
141
76
Figure 6: WDI signal for CDelay = 0.82µF using CS8141.
9
CS8140/1
Application Notes
CS8140/1
Application Diagrams
Battery
C1 *
0.1mF
(optional)
5V
VOUT
VIN
C2**
10mF*
2.7kW
CS8140
ENABLE
Ignition
RESET
DELAY
0.1mF
RESET
WATCHDOG
PORT
WDI
Gnd
Vcc
R***
MICROPROCESSOR
*C1 is required if regulator is located far from the power source filter.
**C2 required for stability
***R ² 80k½
Figure 7. Application Diagram
9V
VOUT
VIN
CS8140/1
Switch
R1
110K
RESET
C1
0.1mF
WDI
ENABLE
CDelay
Gnd
C2
0.1mF
Vcc
10mF
2.7k
MICROPROCESSOR
RESET
WATCHDOG PORT
Figure 8. Applications diagram for CS8140. The CS8140 provides a 5V tightly regulated supply and control function to the microprocessor. In this
application, the microprocessor controls its own power down sequence (see text).
10
CS8140/1
Application Notes: continued
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that
cause the greatest oscillation. This represents the worst
case load conditions for the regulator at low temperature.
IIN
VIN
}
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage conditions.
IOUT
VOUT
Control
Features
IQ
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard capacitor value.
Figure 9: Single output regulator with key performance parameters
labeled.
Once the value of PD(max) is known, the maximum permissible value of RQJA can be calculated:
RQJA =
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
150¡C - TA
PD
(2)
The value of RQJA can then be compared with those in
the package section of the data sheet. Those packages
with RQJA's less than the calculated value in equation 2 will
keep the die temperature below 150¡C.
Step 7: Remove the unit from the environmental chamber
and heat the IC with a heat gun. Vary the load current as
instructed in step 5 to test for any oscillations.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for
the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic
capacitors have a tolerance of +/- 20% so the minimum
value found should be increased by at least 50% to allow
for this tolerance plus the variation which will occur at
low temperatures. The ESR of the capacitor should be less
than 50% of the maximum allowable ESR found in step 3
above.
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed
to determine the value of RQJA:
Calculating Power Dissipation
in a Single Output Linear Regulator
RQJA = RQJC + RQCS + RQSA
The maximum power dissipation for a single output regulator (Figure 9) is:
PD(max) = {VIN(max) - VOUT(min)}IOUT(max) + VIN(max)IQ
Smart
Regulator
(3)
where:
RQJC = the junctionÐtoÐcase thermal resistance,
RQCS = the caseÐtoÐheatsink thermal resistance, and
RQSA = the heatsinkÐtoÐambient thermal resistance.
(1)
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current for the application, and
IQ is the quiescent current the regulator consumes at
IOUT(max).
RQJC appears in the package section of the data sheet. Like
RQJA, it too is a function of package type. RQCS and RQSA
are functions of the package type, heatsink and the interface between them. These values appear in heatsink data
sheets of heatsink manufacturers.
11
CS8140/1
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
D
Lead Count
Metric
Max
Min
15.60
15.20
19.69
18.67
24 Lead SOIC Wide
14 Lead PDIP
Thermal
Data
English
Max
Min
.614 .598
.775 .735
24L
24L (Fused) 14 L
CS8140
CS8141
PDIP
RQJC typ
1.6
16
9
48
ûC/W
RQJA typ
50
80
55
85
ûC/W
7 Lead TO-220 (T) Straight
Surface Mount Wide Body (DW); 300 mil wide
7.60 (.299)
7.40 (.291)
7L
TO-220
10.65 (.419)
10.00 (.394)
1.40 (.055)
1.14 (.045)
4.83 (.190)
4.06 (.160)
10.54 (.415)
9.78 (.385)
2.87 (.113)
2.62 (.103)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
2.49 (.098)
2.24 (.088)
1.27 (.050)
0.40 (.016)
6.55 (.258)
5.94 (.234)
14.99 (.590)
14.22 (.560)
3.96 (.156)
3.71 (.146)
2.65 (.104)
2.35 (.093)
0.32 (.013)
0.23 (.009)
D
REF: JEDEC MS-013
14.22 (.560)
13.72 (.540)
0.30 (.012)
0.10 (.004)
Plastic DIP (N); 300 mil wide
0.94 (.037)
0.58 (.023)
1.40 (.055)
1.14 (.045)
7.11 (.280)
6.10 (.240)
0.56 (.022)
0.36 (.014)
0.64 (.025)
0.38 (.015)
7.75 (.305)
7.49 (.295)
1.77 (.070)
1.14 (.045)
8.26 (.325)
7.62 (.300)
2.92 (.115)
2.29 (.090)
2.54 (.100) BSC
7 Lead TO-220 (TVA) Vertical
3.68 (.145)
2.92 (.115)
10.54 (.415)
9.78 (.385)
1.40 (.055)
1.14 (.045)
3.96 (.156)
3.71 (.146)
2.87 (.113)
2.62 (.103)
0.39 (.015)
MIN.
.356 (.014)
.203 (.008)
.558 (.022)
.356 (.014)
REF: JEDEC MS-001
D
14.99 (.590)
14.22 (.560)
6.55 (.258)
5.94 (.234)
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
11.86 (.467)
2.03 (.080)
Ordering Information
Part Number
CS8140YT7
CS8140YTVA7
CS8140YTHA7
CS8140YDW24
CS8140YDWR24
CS8140YN14
CS8141YT7
CS8141YTVA7
CS8141YTHA7
CS8141YDWF24
CS8141YDWFR24
CS8141YN14
Rev. 2/23/99
Description
7L TO-220 Straight
7L TO-220 Vertical
7L TO-220 Horizontal
24L SO
24L SO (tape & reel)
14L PDIP
7L TO-220 Straight
7L TO-220 Vertical
7L TO-220 Horizontal
24L SO (internally fused leads)
24L SO (internally fused leads)
(tape & reel)
14L PDIP
2.92 (.115)
2.29 (.090)
2.92
(.115)
8.26
(.325)
0.81
(.030)
7.62 (.300)
0.56 (.022)
0.36 (.014)
1.27
(.050)
TYP
4.34
(.171)
7.52 (.296)
4.83 (.190)
4.06 (.160)
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
12
© 1999 Cherry Semiconductor Corporation
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