Semtech ACS8510 Synchronous equipment timing source for sonet or sdh network element Datasheet

ACS8510 SETS
Synchronous Equipment Timing Source
for SONET or SDH Network Elements
FINAL
ADVANCED COMMUNCIATIONS
Description
Features
The ACS8510 is a highly integrated, single-chip
solution for the Synchronous Equipment Timing
Source (SETS) function in a SONET or SDH Network Element. The device generates SONET or
SDH Equipment Clocks (SEC) and frame synchronization clocks. The ACS8510 is fully compliant
with the required specifications and standards.
•Suitable for Stratum 3E*, 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
•Meets AT&T, ITU-T, ETSI and Telcordia specifications
•Accepts 14 individual input reference clocks
•Generates 11 output clocks
•Supports Free-Run, Locked and Holdover
modes of operation
•Robust input clock source quality monitoring on
all inputs
•Automatic “hit-less” source switchover on loss
of input
•Phase build-out for output clock phase continuity during input switchover and mode transitions
•Microprocessor interface - Intel, Motorola,
Serial, Multiplexed, EEPROM
•Programmable wander and jitter tracking/
attenuation 0.1 Hz to 20 Hz
•Support for Master/Slave device configuration
alignment and hot/standby redundancy
•IEEE 1149.1 JTAG Boundary Scan
•Single 3.3 v operation. 5 v I/O compatible
•Operating temperature (ambient) -40°C to
+85°C
•Available in 100 pin LQFP package
The device supports Free-Run, Locked and
Holdover modes. It also supports all three types
of reference clock source: recovered line clock,
PDH network, and node synchronization. The
ACS8510 generates independent SEC and BITS
clocks, an 8 kHz Frame Synchronization clock
and a 2 kHz Multi-Frame Synchronization clock.
Two ACS8510 devices can be used together in a
Master/Slave configuration mode allowing system protection against a single ACS8510 failure.
A microprocessor port is incorporated, providing
access to the configuration and status registers
for device setup and monitoring. The ACS8510
supports IEEE 1149.1 JTAG boundary scan.
* Meets Holdover requirements, lowest bandwidth 0.1 Hz.
Block Diagram
14 Inp ut
Reference
Source
includin g:
AM I 64/8 kHz
2 kHz
8 kHz
N x 8 kHz
1.544 MHz
2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
Input
Ports
TOUT4
selector
Div ider
PFD
Output
Ports
DTO
2xT OUT4
DPLL/F req. Synthesis
6xT IN1
4xT IN2
Dig ital
Loop
Filter
Monitors
4xT IN3
7xT OUT0
TOUT0
selector
MFrSync
PFD
Div ider
Dig ital
Loop
Filter
DTO
DPLL/Freq. S ynthesis
T CK
TDI
TMS
T RST
TDO
IEEE
1149.1
JTAG
Chip C lock
Generator
Priority
Table
Register
Set
APLL
Frequency
Dividers
MFrSync
FrSync
11 Outp ut Ports
includin g:
1.544/2.048 M Hz
3.088/4.096 M Hz
6.176/8.182 M Hz
12.352/16.384 M Hz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
AM I 64/8 kHz
2 kHz MFrSy nc
8 kHz FrSy nc
Micropro cessor
Port
TCXO (*OCXO)
CLK
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Table of Contents
Pin diagram................................................................................................................................................3
Pin descriptions.........................................................................................................................................4
Functional description...............................................................................................................................7
Local oscillator clock..........................................................................................................................................................8
Input Interfaces..................................................................................................................................................................8
Over voltage protection.......................................................................................................................................................8
Input reference clock ports................................................................................................................................................9
Input wander and jitter tolerance...................................................................................................................................11
Output clock ports...........................................................................................................................................................13
Output wander and jitter..................................................................................................................................................14
Phase variation.................................................................................................................................................................16
Phase build-out.................................................................................................................................................................17
Microprocessor interface................................................................................................................................................17
Interrupt enable and clear...............................................................................................................................................19
Register map description.................................................................................................................................................21
Register map description.................................................................................................................................................25
Selection of input reference clock source.....................................................................................................................33
Clock quality monitoring..................................................................................................................................................34
Activity monitoring...........................................................................................................................................................35
Modes of operation..........................................................................................................................................................38
Protection facility.............................................................................................................................................................39
JTAG..............................................................................................................................................................................42
Power on reset - PORB.....................................................................................................................................................42
Electrical specification............................................................................................................................45
Absolute maximum range...............................................................................................................................................45
Operating conditions.......................................................................................................................................................45
TTL DC characterisitics...................................................................................................................................................45
PECL DC characteristics..................................................................................................................................................47
LVDS DC characteristics..................................................................................................................................................48
AMI DC characteristics....................................................................................................................................................49
Jitter characteristics........................................................................................................................................................52
JTAG timing........................................................................................................................................................................55
Microprocessor interface timing characteristics.......................................................................................56
Motorola mode..................................................................................................................................................................56
Intel mode................................................................................................................................................................58
Multiplexed mode.............................................................................................................................................................60
Serial mode.......................................................................................................................................................................62
EEPROM mode.................................................................................................................................................................64
Package information................................................................................................................................65
Application information............................................................................................................................67
Simplified application schematic...................................................................................................................................67
Revision History.......................................................................................................................................68
Order information....................................................................................................................................69
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Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AGND
TRST
IC
NC
AGND
VA1+
TMS
INTREQ
TCK
REFCLK
DGND
VD+
VD+
DGND
DGND
VD+
NC
SRCSW
VA2+
AGND
TDO
IC
TDI
I1
I2
VAMI+
TO8NEG
TO8POS
GND_AMI
FrSync
MFrSync
GND_DIFF
VDD_DIFF
TO6POS
TO6NEG
TO7POS
TO7NEG
GND_DIFF
VDD_DIFF
I5POS
I5NEG
I6POS
I6NEG
VDD5
SYNC2K
I3
I4
I7
DGND
VDD
1
ACS8510
SDH/SONET SETS
Rev 2.x
Figure 1: Top view of 100 pin LQFP package.
NC - Not Connected; leave to Float. IC - Internally Connected; leave to Float.
Revision 2.07/Jan 2001 ã2001 Semtech Corp
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100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SONSDHB
MSTSLVB
IC
IC
IC
TO9
TO5
TO4
DGND
VDD
TO3
TO2
TO1
DGND
VDD
VDD
DGND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
RDY
PORB
ALE
RDB
WRB
CSB
A0
A1
A2
A3
A4
A5
A6
DGND
VDD
UPSEL0
UPSEL1
UPSEL2
I14
I13
I12
I11
I10
I9
I8
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Pin Descriptions
Power
PIN
SYM B OL
IO
T YPE
N A M E /DE SCR I P T I O N
12, 13, 16
VD+
P
-
S u p p l y v ol t ag e: Digital sup p ly to gates in analog section, +3.3
Volts. +/- 10%
26
VAMI+
P
-
S u p p l y v ol t ag e : Digital sup p ly to AMI outp ut, +3.3 Volts. +/- 10%
33, 39
VDD_DIFF
P
-
S u p p l y v ol t ag e : Digital sup p ly for differential p or ts, +3.3 Volts.
+/- 10%
44
VDD5
P
-
V D D 5: Digital sup p ly for +5 Volts tolerance to inp ut p ins. Connect
to +5 volts (+/- 10%) for clamp ing to +5 v. Connect to VDD for
clamp ing to +3.3 v. Leave floating for no clamp ing, inp ut p ins
tolerant up to +5.5 v.
50, 61, 85,
86, 91
VDD
P
-
S u p p l y v ol t ag e : Digital sup p ly to logic, +3.3 Volts. +/- 10%
6
VA1+
P
-
S u p p l y v ol t ag e: Analog sup p ly to clock multip ying PLL, +3.3 Volts.
+/- 10%
19
VA2+
P
-
S u p p l y v ol t ag e : Analog sup p ly to outp ut PLL, +3.3 Volts. +/- 10%
11, 14, 15,
49, 62, 84,
87, 92
DGN D
P
-
S u p p l y G r ou n d : Digital ground for logic
29
GN D_AMI
P
-
S u p p l y G r ou n d : Digital ground for AMI outp ut
32, 38
GN D_DIFF
P
-
S u p p l y G r ou n d : Digital ground for differential p or ts
1, 5, 20
AGN D
P
-
S u p p l y G r ou n d : Analog ground
No connections
PIN
SYM B OL
IO
T YPE
N A M E /DE SCR I P T I O N
4, 17
NC
-
-
N ot C on n ect ed : Leave to Float
3, 22, 96,
97,98
IC
-
-
I n t er n al l y C on n ect ed : Leave to Float
Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor
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Others
PIN
SYM B OL
IO
T YPE
N A M E /DE SCR I P T I O N
2
TRST
I
T T LD
J TA G C o n t r o l R e se t I n p u t : TRST = 1 to enab le JTA G Bound ary
Scan mod e. TRST = 0 for normal d evice op eration (JTA G logic
transp arent). If not used connect to GN D or leave floating.
7
T MS
I
T T LU
J TA G Te st M o d e S e l e ct : Bound ary Scan enab le. Samp led on
rising ed ge of TCK. If not used connect to V DD or leave floating.
8
IN T R E Q
O
TTL
CMOS
I n t e r r u p t R e q u e st : A ctive h igh softw are Interrup t outp ut
9
TCK
I
T T LD
J TA G C l o ck : Bound ary Scan clock inp ut. If not used connect to
GN D or leave floating. Th is p in may req uire a cap acitor p laced
b etw een th e p in and th e nearest GN D, to red uce noise p ickup . A
value of 10 p F sh ould b e ad eq uate, b ut th e value is d ep end ent on
PCB layout.
10
REFCLK
I
TTL
R e f e r e n ce C l o ck : 12.8 MHz (refer to section h ead ed Local
Oscillator Clock)
18
SRCSW
I
T T LD
S o u r ce S w i t ch i n g : Force Fast Source Sw itch ing
21
TDO
O
TTL
CMOS
23
TDI
I
T T LU
J TA G I n p u t : Serial test d ata Inp ut. Samp led on rising ed ge of TCK.
If not used connect to V DD or leave floating.
24
I1
I
A MI
I n p u t r e f e r e n ce 1: comp osite clock 64 kHz + 8 kHz
25
I2
I
A MI
I n p u t r e f e r e n ce 2: comp osite clock 64 kHz + 8 kHz
27
TO8N EG
O
A MI
O u t p u t r e f e r e n ce 8: comp osite clock, 64 kHz + 8 kHz negative
p ulse
28
TO8POS
O
A MI
O u t p u t r e f e r e n ce 8: comp osite clock, 64 kHz + 8 kHz p ositive
p ulse
30
FrSync
O
TTL
CMOS
O u t p u t r e f e r e n ce 10: 8 kHz Frame Sync clock outp ut (sq uare
w ave)
31
MFrSync
O
TTL
CMOS
O u t p u t r e f e r e n ce 11: 2 kHz Multi-Frame Sync clock outp ut
(sq uare w ave)
34
35
TO6POS
TO6N EG
O
PECL/
LV DS
O u t p u t r e f e r e n ce 6: d efault 38.88 MHz. A lso Dig1 (1.544
MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 155.52 MHz, 311.04
MHz. Default typ e LV DS.
36
37
TO7POS
TO7N EG
O
LV DS/
PECL
O u t p u t r e f e r e n ce 7: d efault 19.44 MHz. A lso 51.84 MHz, 77.76
MHz, 155.52 MHz. Default typ e PECL.
40
41
I5POS
I5N EG
I
LV DS
PECL
I n p u t r e f e r e n ce 5: d efault 19.44 MHz, d efault typ e LV DS
42
43
I6POS
I6N EG
I
PECL
LV DS
I n p u t r e f e r e n ce 6: d efault 19.44 MHz, d efault typ e PECL
Revision 2.07/Jan 2001 ã2001 Semtech Corp
J TA G O u t p u t : Serial test d ata outp ut. Up d ated on falling ed ge of
TCK. If not used leave floating.
5
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PIN
SYM B OL
IO
T YPE
N A M E /DE SCR I P T I O N
45
SYN C2K
I
T T LD
S y n ch r o n i se 2 k H z : Connect to 2 kHz Multi-Frame Sync outp ut of
p ar tner A CS8510 in red und ancy system
46
I3
I
T T LD
I n p u t r e f e r e n ce 3: p rogrammab le, d efault 8 kHz
47
I4
I
T T LD
I n p u t r e f e r e n ce 4: p rogrammab le, d efault 8 kHz
48
I7
I
T T LD
I n p u t r e f e r e n ce 7: p rogrammab le, d efault 19.44 MHz
51
I8
I
T T LD
I n p u t r e f e r e n ce 8: p rogrammab le, d efault 19.44 MHz
52
I9
I
T T LD
I n p u t r e f e r e n ce 9: p rogrammab le, d efault 19.44 MHz
53
I10
I
T T LD
I n p u t r e f e r e n ce 10: p rogrammab le, d efault 19.44 MHz.
54
I11
I
T T LD
I n p u t r e f e r e n ce 11: p rogrammab le,
d efault (master mod e)1.544/2.048 MHz,
d efault (slave mod e) 6.48 MHz
55
I12
I
T T LD
I n p u t r e f e r e n ce 12: p rogrammab le, d efault 1.544/2.048 MHz.
56
I13
I
T T LD
I n p u t r e f e r e n ce 13: p rogrammab le, d efault 1.544/2.048 MHz.
57
I14
I
T T LD
I n p u t r e f e r e n ce 14: p rogrammab le, d efault 1.544/2.048 MHz.
58 - 60
UPSEL(2:0)
I
T T LD
M i cr o p r o ce sso r se l e ct : Configures th e inter face for a p ar ticular
microp rocessor typ e.
63 - 69
A (6:0)
I
T T LD
M i cr o p r o ce sso r I n t e r f ace A d d r e ss: A d d ress b us for th e
microp rocessor inter face registers. A (0) is SDI in Serial mod e.
70
CSB
I
T T LU
C h i p S e l e ct ( A ct i v e L o w ) : Th is p in is asser ted Low b y th e
microp rocessor to enab le th e microp rocessor inter face.
71
WRB
I
T T LU
W r i t e ( A ct i v e L o w ) : Th is p in is asser ted Low b y th e
microp rocessor to initiate a w rite cycle. In Motorola mod e, WRB = 1
for Read .
72
RDB
I
T T LU
R e ad ( A ct i v e L o w ) : Th is p in is asser ted Low b y th e
microp rocessor to initiate a read cycle.
73
A LE
I
T T LD
A d d r e ss L at ch E n ab l e : Th is p in b ecomes th e ad d ress latch
enab le from th e microp rocessor. Wh en th is p in transitions from
High to Low, th e ad d ress b us inp uts are latch ed into th e internal
registers. A LE = SCLK in Serial mod e.
74
PORB
I
T T LU
P o w e r O n R e se t : Master reset. If PORB is forced Low, all internal
states are reset. b ack to d efault values.
75
RDY
O
TTL
CMOS
R e ad y / D at a ack n o w l e d g e : Th is p in is asser ted High to ind icate
th e d evice h as comp leted a read or w rite op eration.
76 - 83
A D(7:0)
IO
T T LD
A d d r e ss/ D at a: Multip lexed d ata/ad d ress b us d ep end ing on th e
microp rocessor mod e selection. A D(0) is SDO in Serial mod e
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PIN
SYM B OL
IO
T YPE
88
TO1
O
TTL
CMOS
O u t p u t r ef er en ce 1: default 6.48 MHz. Also Dig1 (1.544
MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 25.92 MHz
89
TO2
O
TTL
CMOS
O u t p u t r ef er en ce 2: default 38.88 MHz. Also Dig2 (1.544
MHz/2.048 MHz and 2, 4, 8 x), 25.92 MHz, 51.84 MHz
90
TO3
O
TTL
CMOS
O u t p u t r ef er en ce 3: 19.44 MHz - fixed.
93
TO4
O
TTL
CMOS
O u t p u t r ef er en ce 4: 38.88 MHz - fixed.
94
TO5
O
TTL
CMOS
O u t p u t r ef er en ce 5: 77.76 MHz - fixed.
95
TO9
O
TTL
CMOS
O u t p u t r ef er en ce 9: 1.544/2.048 MHz. (T4 BITS)
99
MSTSLVB
I
TTL
100
SON SDHB
I
U
T T LD
N A M E /DE SCR I P T I O N
M A S T E R S L AV E B : Master slave select: sets the initial p ow er up
state (or state after a PORB) of the Master/Slave selection register,
addr 34, b it 1. The register state can b e changed after p ow er up b y
softw are.
S O N E T S D H B : SON ET or SDH frequency select: sets the initial
p ow er up state (or state after a PORB) of the SON ET/SDH
frequency selection registers, addr 34h, b it 2 and addr 38, b it 5.
The register states can b e changed after p ow er up b y softw are.
Functional description
The ACS8510 is a highly integrated, single-chip
solution for the SETS function in a SONET/SDH
Network Element, for the generation of SEC
and frame synchronisation pulses. In Free-Run
mode, the ACS8510 generates a stable, lownoise clock signal from an internal oscillator.
In Locked mode, the ACS8510 selects the most
appropriate input reference source and
generates a stable, low-noise clock signal locked
to the selected reference. In Holdover mode,
the ACS8510 generates a stable, low-noise
clock signal from the internal oscillator,
adjusted to match the last-known-good
frequency of the last-selected reference source.
In all modes, the frequency accuracy, jitter and
drift performance of the clock meet the
requirements of ITU G.812, G.813, G.823, GR
1244-CORE.
Revision 2.07/Jan 2001 ã2001 Semtech Corp
7
The ACS8510 supports all three types of
reference clock source: recovered line clock
(TIN1), PDH network synchronisation timing (TIN2)
and node synchronisation (TIN3). The ACS8510
generates independent TOUT0 and TOUT4 clocks,
an 8 kHz Frame Synchronisation clock and a 2
kHz Multi-Frame Synchronisation clock.
The ACS8510 has a high tolerance to input
jitter and wander. The output jitter and wander
are low, where the wander transfer is
programmable (0.1 Hz up to 20 Hz cut-off
points).
The ACS8510 supports protection. Two
ACS8510 devices can be configured to provide
protection against a single ACS8510 failure.
The protection maintains alignment of the two
ACS8510 devices (Master and Slave) and
ensures that both ACS8510 devices maintain
the same priority table, choose the same
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reference input and generate the TOUT0 clock,
the 8 kHz Frame Synchronisation clock and
the 2 kHz Multi-Frame Synchronisation clock
with the same phase. The ACS8510 includes a
microprocessor port, providing access to the
configuration and status registers for device
setup and monitoring.
Local Oscillator Clock
The Master system clock on the ACS8510
should be provided by an external clock oscillator
of frequency 12.80 MHz. The clock specification
is important for meeting the ITU/ETSI and
Telcordia performance requirements in Holdover
mode. ITU and ETSI specifications permit a
combined drift characteristic, at constant
temperature, of all non-temperature-related
parameters, of up to 10 ppb per day. The same
specifications allow a drift of 1 ppm over a
temperature range of 0 to 70 Celsius. Telcordia
specifications are somewhat tighter, requiring
a non-temperature-related drift of less than 40
ppb per day and a drift of 280 ppb over the
temperature range 0 to 50 Celsius.
ITU and ETSI specification
Tolerance:
+/- 4.6 ppm over 20 year life time.
Drift*:
+/- 0.05 ppm/15 seconds @ constant temp.
+/- 1 ppm over temp. range 0-70 Celsius
*Frequency drift over supply voltage range of 2.7 V to 3.3 V.
Telcordia GR-1244 CORE specification
+/- 4.6 ppm over 20 year life time.
Drift*:
+/- 0.05 ppm/15 seconds @ constant temp.
For example, if the crystal was oscillating at
12.8 MHz + 5 ppm, then the calibration value
in the register to give a -5 ppm adjustment in
output frequencies to compensate for the
crystal inaccuracy, would be : 39321 - (5 /
0.02) = 39071 (decimal).
The ACS8510 supports up to fourteen input
reference clock sources from input types TIN1,
TIN2 and TIN3 using TTL, CMOS, PECL, LVDS and
AMI buffer I/O technologies. These interface
technologies support 3.3 V and 5 V operation.
Over-Voltage Protection
+/- 0.04 ppm/day @ constant temp.
+/- 0.28 ppm over temp. range 0-50 Celsius
*Frequency drift over supply voltage range of 2.7 V to 3.3 V.
Please contact Semtech for information on
crystal oscillator suppliers.
Revision 2.07/Jan 2001 ã2001 Semtech Corp
The absolute crystal frequency accuracy is less
important than the stability since any frequency
offset can be compensated by adjustment of
register values in the IC. This allows for
calibration and compensation of any crystal
frequency variation away from its nominal value.
+/- 50 ppm adjustment would be sufficient to
cope with most crystals, in fact the range is an
order of magnitude larger due to the use of
two 8 bit register locations. The setting of the
conf_nominal_frequency register allows for this
adjustment. An increase in the register value
increases the output frequencies by 0.02 ppm
for each LSB step. The default value (in decimal)
is 39321. The minimum being 0 and the
maximum 65535, gives a +500 ppm to -700
ppm adjustment range of the output
frequencies.
Input Interfaces
+/- 0.01 ppm/day @ constant temp.
Tolerance:
Crystal Frequency Calibration
8
The ACS8510 may require Over-Voltage
Protection on input reference clock ports
according to the ITU Recommendation K.41.
Semtech recommends the use of their
protection devices for this purpose (see
separate Semtech data book).
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Input Reference Clock Ports
Table 1 gives details of the input reference
ports, showing the input technologies and the
range of frequencies supported on each port;
the default spot frequencies and default
priorities assigned to each port on power-up or
by reset are also shown. Note that SDH and
SONET networks use different default
frequencies; the network type is pin-selectable
(using the SONSDHB pin). Specific frequencies
and priorities are set by configuration.
Although each input port is shown as belonging
to one of the types, TIN1, TIN2 or TIN3, they are
fully interchangeable as long as the selected
speed is within the maximum operating speed
of the input port technology.
SDH and SONET networks use different default
frequencies; the network type is selectable
using the config_mode register 34 Hex, bit 2.
For SONET, config_mode register 34 Hex, bit 2
= 1, for SDH config_mode register 34 Hex, bit
2 = 0. On power-up or by reset, the default will
be set by the state of the SONSDHB pin (pin
100). Specific frequencies and priorities are set
by configuration.
TTL ports (compatible also with CMOS signals)
support clock speeds up to 100 MHz, with the
highest spot frequency being 77.76 MHz. The
actual spot frequencies supported are; 8 kHz
(and N x 8 kHz), 1.544 MHz/2.048 MHz, 6.48
MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,
51.84 MHz, 77.76 MHz. The frequency
selection
is
programmed
via
the
cnfg_ref_source_frequency register. The
internal DPLL will normally lock to the selected
input at the frequency of the input, eg. 19.44
MHz will lock the DPLL phase comparisons at
19.44 MHz. It is, however, possible to utilise
an internal pre-divider to the DPLL to divide the
input frequency before it is used for phase
comparisons in the DPLL. This pre-divider can
be used in one of 2 ways:
Revision 2.07/Jan 2001 ã2001 Semtech Corp
9
(i) any of the supported spot frequencies can be divided
to 8 kHz by setting the "lock8K" bit (bit 6) in the
appropriate cnfg_ref_source_frequency register
location
(ii) any multiple of 8 kHz between 1544 kHz to 100
MHz can be supported by using the "DivN" feature (bit
7 of the cnfg_ref_source_frequency register). Any
reference input can be set to use DivN independently
of the frequencies and configurations of the other
inputs.
Any reference input with the "DivN" bit set in
the cnfg_ref_source_frequency register will
employ the internal pre-divider prior to the DPLL
locking. The cnfg_freq_divn register contains
the divider ratio N where the reference input
will get divided by (N+1) where 0<N<214-1. The
cnfg_ref_source_frequency register must be set
to the closest supported spot frequency to the
input frequency, but must be lower than the
input frequency. When using the "DivN" feature
the post-divider frequency must be 8 kHz, which
is indicated by setting the ‘lock8k’ bit high (bit
6 in ‘cnfg_ref_source_ frequency’ register). Any
input set to DivN must have the frequency
monitors disabled (If the frequency monitors
are disabled, they are disabled for all inputs
regardless of the input configurations, in this
case only activity monitoring will take place).
Whilst any number of inputs can be set to use
the "DivN" feature, only one N can be
programmed, hence all inputs using the "DivN"
feature must require the same division to get
to 8 kHz.
PECL and LVDS ports support the spot clock
frequencies listed above plus 155.52 MHz and
311.04 MHz. The choice of PECL or LVDS
compatibility is programmed via the
cnfg_differential_inputs register. Unused PECL/
LVDS differential inputs should be fixed with
one input high (VDD) and the other input low
(GND), or set in LVDS mode and left floating, in
which case one input is internally pulled high
and the other low.
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P or t
N u m b er
C h an n e l
N u m b er
P or t
Ty p e
I n p u t P or t
Te c h n o l o g y
I_1
0001
T IN 3
A MI
64/8kHz (comp osite clock, 64kHz + 8kHz)
Default (SON ET):
64/8kHz
Default (SDH):
64/8kHz
2
I_2
0010
T IN 3
A MI
64/8kHz (comp osite clock, 64kHz + 8kHz)
Default (SON ET):
64/8kHz
Default (SDH):
64/8kHz
3
I_3
0011
T IN 3
TTL/CMOS
Up to 100MHz (see N ote 1)
Default (SON ET):
8kHz
Default (SDH):
8kHz
4
I_4
0100
T IN 3
TTL/CMOS
Up to 100MHz (see N ote 1)
Default (SON ET):
8kHz
Default (SDH):
8kHz
5
I_5
0101
T IN 1
LVDS/PECL
LVDS default
Up to 155.52MHz (see N ote 2)
Default (SON ET):
19.44MHz
Default (SDH):
19.44MHz
6
I_6
0110
T IN 1
PECL/LVDS
PECL default
Up to 155.52MHz (see N ote 2)
Default (SON ET):
19.44MHz
Default (SDH):
19.44MHz
7
I_7
0111
T IN 1
TTL/CMOS
Up to 100MHz (see N ote 1)
Default (SON ET):
19.44MHz
Default (SDH):
19.44MHz
8
I_8
1000
T IN 1
TTL/CMOS
Up to 100MHz (see N ote 1)
Default (SON ET):
19.44MHz
Default (SDH):
19.44MHz
9
I_9
1001
T IN 1
TTL/CMOS
Up to 100MHz (see N ote 1)
Default (SON ET):
19.44MHz
Default (SDH):
19.44MHz
10
I_10
1010
T IN 1
TTL/CMOS
Up to 100MHz (see N ote 1)
Default (SON ET):
19.44MHz
Default (SDH):
19.44MHz
11
12/1
(N ote 3)
Fr eq u en ci es S u p p or t ed
D e f au l t
P ri ori t y
I_11
1011
T IN 2
TTL/CMOS
Up to 100MHz (see N ote 1)
Default (Master) (SON ET): 1.544MHz
Default (Master) (SDH):
2.048MHz
Default (Slave)
6.48MHz
I_12
1100
T IN 2
TTL/CMOS
Up to 100MHz (see N ote 1)
Default (SON ET):
1.544MHz
Default (SDH):
2.048MHz
13
I_13
1101
T IN 2
TTL/CMOS
Up to 100MHz (see N ote 1)
Default (SON ET):
1.544MHz
Default (SDH):
2.048MHz
14
I_14
1110
T IN 2
TTL/CMOS
Up to 100MHz (see N ote 1)
Default (SON ET):
1.544MHz
Default (SDH):
2.048MHz
15
Table 1: Input Reference Source Selection and Priority Table
Revision 2.07/Jan 2001 ã2001 Semtech Corp
10
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Notes for Table 1.
Note 1: TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot
frequency being 77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz, 1.544 MHz/2.048 MHz, 6.48 MHz,
19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. There are different output clock frequencies available
for SONET and SDH applications. SONSDHB controls the default frequency output. F1/F2 means that the output
frequency is F1 when the SONSDHB pin is High and F2 when SONSDHB pin is Low.
Note 2: PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz and 311.04 MHz.
Note 3: Input port <I_11> is set at 12 on the Master SETS IC and 1 on the Slave SETS IC, as default on power up (or
PORB). The default setup of Master or Slave <I_11> priority is determined by the MSTSLVB pin.
DivN examples
To lock to 2.000 MHz.
(1) The cnfg_ref_source_frequency register is set to 11XX0001 (binary) to set the DivN, lock8k bits, and the
frequency to E1/T1. (XX = “leaky bucket” ID for this input).
(2) The cnfg_mode register (34Hex) bit 2 needs to be set to 1 to select SONET frequencies (T1).
(3) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1.
(4) the DivN register is set to F9 Hex (249 decimal).
To lock to 10.000 MHz.
(1) The cnfg_ref_source_frequency register is set to 11XX0010 (binary) to set the DivN, lock8k bits, and the
frequency to 6.48 MHz. (XX = “leaky bucket” ID for this input).
(2) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1.
(3) the DivN register is set to 4E1 Hex (1249 decimal).
An AMI port supports a composite clock,
consisting of a 64 kHz AMI clock with 8 kHz
boundaries marked by deliberate violations of
the AMI coding rules, as specified in ITU
recommendation G.703. Departures from the
nominal pattern are detected within the
ACS8510, and may cause reference-switching
if too frequent. See Figure 9 for more details.
Input Wander and Jitter Tolerance
The ACS8510 is compliant to the requirements
of all relevant standards, principally ITU
Recommendation G.825, ANSI T1.101-1994
and ETS 300 462-5 (1997).
All reference clock inputs have a tight frequency
tolerance but a generous jitter tolerance. PullRevision 2.07/Jan 2001 ã2001 Semtech Corp
11
in, hold-in and pull-out ranges are specified for
each input port in Table 2. Minimum jitter
tolerance masks are specified in Figures 1 and
2, and Tables 3 and 4, respectively. The
ACS8510 will tolerate wander and jitter
components greater than those shown in Figure
1 and Figure 2, up to a limit determined by a
combination of the apparent long-term
frequency offset caused by wander and the
eye-closure caused by jitter (the input source
will be rejected if the offset pushes the
frequency outside the hold-in range for long
enough to be detected, whilst the signal will
also be rejected if the eye closes sufficiently to
affect the signal purity). The ‘8klocking’ mode
should be engaged for high jitter tolerance
according to these masks. All reference clock
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ports are monitored for quality, including
frequency offset and general activity. Single
short-term interruptions in selected reference
clocks may not cause rearrangements, whilst
longer interruptions, or multiple, short-term
interruptions, will cause rearrangements, as will
frequency offsets which are sufficiently large
or sufficiently long to cause loss-of-lock in the
phase-locked loop. The failed reference source
will be removed from the priority table and
declared as unserviceable, until its perceived
quality has been restored to an acceptable
level.
The registers reg sts_curr_inc_offset (address
0C, 0D, 07) report the frequency of the DPLL
J i t t er
To l e r a n c e
Fr eq u en cy M on i t or
A c c e p t an c e R an g e
G.703
G.783
G.823
+/- 16.6 p p m
GR-1244-CORE
with respect to the external TCXO frequency.
This is a 19 bit signed number with one LSB
representing 0.0003 ppm (range of +/- 80
ppm). Reading this regularly can show how the
currently locked source is varying in value e.g.
due to wander on its input.
The ACS8510 performs automatic frequency
monitoring with an acceptable input frequency
offset range of +/- 16.6 ppm. The ACS8510
DPLL has a programmable frequency limit of
+/- 80 ppm. If the range is programmed to be
> 16.6 ppm, the frequency monitors should be
disabled so the input reference source is not
automatically rejected as out of frequency
range.
Fr eq u en cy
A c c e p t an c e R an g e
( Pull-in)
Fr eq u en cy
A c c e p t an c e
R an g e ( H o l d - i n )
Fr eq u en cy
A c c e p t an c e R an g e
( P u l l - ou t )
+/- 4.6 p p m
(see N ote 1)
+/- 4.6 p p m
(see N ote 1)
+/- 4.6 p p m
(see N ote 1)
+/- 9.2 p p m
(see N ote 2)
+/- 9.2 p p m
(see N ote 2)
+/- 9.2 p p m
(see N ote 2)
Table 2: Input Reference Source Jitter Tolerance.
Notes for Table 2.
Note 1. The frequency acceptance and generation range will be +/-4.6 ppm around the required frequency when the
external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm.
Note 2. The fundamental acceptance range and generation range is +/- 9.2 ppm with an exact external crystal
frequency of 12.8 MHz.
Note 3. The power up default PDLL range is as stated in note 2, but the range is also programmable from 0 to 80 ppm
in 0.08 ppm steps.
Revision 2.07/Jan 2001 ã2001 Semtech Corp
12
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$
$
$
$
$
-LWWHUDQGZDQGHUIUHTXHQF\ ORJVFDOH
I
I
I
I
I
I
I
I
I
Figure 1: Minimum Input Jitter Tolerance for inputs supporting G.783 compliant sources
ST M
l evel
STM-1
P e ak t o p e ak am p l i t u d e
( u n i t I n t e r v al )
Fr eq u en cy ( H z )
A0
A1
A2
A3
A4
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
2800
311
39
1.5
0.15
12u
178u
1.6m
15.6m
0.125
19.3
500
6.5k
65k
1.3m
Table 3: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.783 compliant sources
Output Clock Ports
Low-speed Output Clock (T OUT4 )
The device supports a set of main output clocks,
TOUT0 and TOUT4, and a pair of secondary output
clocks, 'Frame-Sync' and 'Multi-Frame-Sync'. The
two main output clocks, T OUT0 and TOUT4, are
independent of each other and are individuallyselectable. The two secondary output clocks,
'Frame-Sync' and 'Multi-Frame-Sync', are derived
from TOUT0. The frequencies of the output clocks
are selectable from a range of pre-defined spot
frequencies and a variety of output technologies
are supported, as defined in Table 5.
The TOUT4 clock is supplied on two output ports,
TO8 and TO9. The former port will provide an AMI
signal carrying a composite clock of 64 kHz
and 8 kHz, according to ITU Recommendation
G.703. The latter port will provide a TTL/CMOS
signal at either 1.544 MHz or 2.048 MHz,
depending on the setting of the SONSDHB pin.
Performance-wise, the output ports are
specified in Figures 3, 4 and 5, in terms of
jitter, MTIE (and TDEV) and Phase Error,
respectively.
Revision 2.07/Jan 2001 ã2001 Semtech Corp
13
High-speed Output Clock (Part of T OUT0)
The TOUT0 port has multiple outputs. Outputs TO1
and TO2 are TTL/CMOS output with a choice of
11 different frequencies up to 51.84 MHz.
Outputs TO3 to TO5 are all TTL/CMOS outputs
with fixed frequencies of 19.44 MHz, 38.88
MHz and 77.76 MHz, respectively. Output TO6
is differential and can support clocks up to
155.52 MHz. Output TO7 is also differential
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3HDNWRSHDNMLWWHUDQGZDQGHUDPSOLWXGH ORJ
VFDOH
$
$
-LWWHUDQGZDQGHUIUHTXHQF\ ORJVFDOH
I
I
I
I
Figure 2: Minimum Input Jitter Tolerance for inputs supporting G.703 compliant sources
Ty p e
S p ec.
A mp litud e
( U I p k-p k)
Fr e q u e n cy
( Hz )
A1
A2
F1
F2
F3
F4
DS1
G R - 1244- C O R E
5
0.1
10
500
8k
40k
E1
I T U G. 823
1.5
0.2
20
2.4k
18k
100k
Table 4: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.703 compliant sources
and can support clocks up to 155.52 MHz.
Each output is individually configured to operate
at the frequencies shown in Table 5
(configuration must be consistent between
ACS8510 devices for protection-switching to be
effective - output clocks will be phase-aligned
between
devices).
Using
the
cnfg_differential_outputs register, outputs TO6
and T O7 can be made to be LVDS or PECL
compatible.
Frame Sync and Multi-Frame Sync Clocks (Part of
T OUT0)
Frame Sync (8 kHz) and Multi-Frame Sync (2
kHz) clocks will be provided on outputs TO10
(FrSync) and TO11 (MFrSync). The FrSync and
MFrSync clocks have a 50:50 mark space ratio.
Revision 2.07/Jan 2001 ã2001 Semtech Corp
14
These will be driven from the TOUT0 clock. They
will be synchronised with their counterparts in
a second ACS8510 device (if used), using the
technique described later.
Output Wander and Jitter
Wander and jitter present on the output clocks
are dependent on:
The magnitude of wander and jitter on the
selected input reference clock (in Locked mode);
The internal wander and jitter transfer
characteristic (in Locked mode);
The jitter on the local oscillator clock;
The wander on the local oscillator clock (in
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Holdover mode).
Wander and jitter are treated in different ways
to reflect their differing impacts on network
design. Jitter is always strongly attenuated,
whilst wander attenuation can be varied to suit
the application and operating state. Wander and
jitter attenuation is performed using a digital
phase locked loop (DPLL) with a programmable
bandwidth. This gives a transfer characteristic
of a low pass filter, with a programmable pole.
It is sometimes necessary to change the filter
dynamics to suit particular circumstances - one
example being when locking to a new source,
the filter can be opened up to reduce locking
time and can then be gradually tightened again
to remove wander. Since wander represents a
relatively long-term deviation from the nominal
operating frequency, it affects the rate of supply
of data to the network element. Strong wander
attenuation limits the rate of consumption of
data to within a smaller range, so a larger buffer
P or t
N am e
O u t p u t P or t
Te c h n o l o g y
T01
TTL/CMOS
1.544 MHz/2.048 MHz, 3.088 MHz/4.096 MHz, 6.176 MHz/8.192 MHz,
6.48 MHz (d efault), 12.352 MHz/16.384 MHz, 19.44 MHz, 25.92 MHz
T02
TTL/CMOS
1.544 MHz/2.048 MHz, 3.088 MHz/4.096 MHz, 6.176 MHz/8.192 MHz,
12.352 MHz/16.384 MHz, 25.92 MHz, 38.88 MHz (d efault), 51.84 MHz
T03
TTL/CMOS
19.44 MHz - fixed
T04
TTL/CMOS
38.88 MHz - fixed
T05
TTL/CMOS
77.76 MHz - fixed
T06
PECL/LV DS
(LV DS d efault)
1.544 MHz/2.048 MHz, 3.088 MHz/4.096 MHz, 6.176 MHz/8.192 MHz,
12.352 MHz/16.384 MHz, 19.44 MHz, 38.88 MHz (d efault), 155.52 MHz,
311.04 MHz
T07
LV DS/PECL
(PECL d efault)
19.44 MHz (d efault), 51.84 MHz, 77.76 MHz, 155.52 MHz
T08
A MI
T09
TTL/CMOS
1.544 MHz/2.048 MHz
T010
TTL/CMOS
FrSync, 8 kHz - w ith a 50:50 MSR
T011
TTL/CMOS
MFrSync, 2 kHz - w ith a 50:50 MSR
Fr e q u e n ci e s S u p p o r t e d
64/8 kHz (comp osite clock, 64 kHz + 8 kHz)
Table 5: Output Reference Source Selection Table
Note for Table 5.
Frequencies supported: There are different output clock frequencies available for SONET and SDH applications. SONSDHB
controls the default frequency output. F1/F2 means that the output frequency is F1 when the SONSDHB pin is High and F2
when SONSDHB pin is Low.
Revision 2.07/Jan 2001 ã2001 Semtech Corp
15
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store is required to prevent data loss. But, since
any buffer store potentially increases latency,
wander may often only need to be removed at
specific points within a network where buffer
stores are acceptable, such as at digital cross
connects. Otherwise, wander is sometimes not
required to be attenuated and can be passed
through transparently. The ACS8510 has
programmable wander transfer characteristics
in a range from 0.1 Hz to 20 Hz. The wander
and jitter transfer characteristic is shown in
Figure 3.
Wander on the local oscillator clock will not
have significant effect on the output clock whilst
in Locked mode, so long as the DPLL bandwidth
is set high enough so that the DPLL can
compensate quickly enough for any frequency
changes in the crystal. In Free-Running or
Holdover mode wander on the crystal is more
significant. Variation in crystal temperature or
supply voltage both cause drifts in operating
frequency, as does ageing. These effects must
3HDNWRSHDNMLWWHUDQGZDQGHUDPSOLWXGH
ORJVFDOH
be limited by careful selection of a suitable
component for the local oscillator, as specified
in the section ‘Local Oscillator Clock’.
Phase Variation
There will be a phase shift across the ACS8510
between the selected input reference source
and the output clock. This phase shift may vary
over time but will be constrained to lie within
specified limits. The phase shift is characterised
using two parameters, MTIE (Maximum Time
Interval Error), and TDEV (Time Deviation), which,
although being specified in all relevent
specifications, differ in acceptable limits in each
one. Typical measurements for the ACS8510
are shown in Figures 4 and 5, for Locked mode
operation. Figure 6 shows a typical
measurement of Phase Error accumulation in
Holdover mode operation.
The required performance for phase variation
during Holdover is specified in several ways
depending upon the particular circumstances
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8,#I
G%
G%
-LWWHUDQGZDQGHUIUHTXHQF\ ORJVFDOH
Figure 3: Wander and Jitter Transfer Characteristsics
Revision 2.07/Jan 2001 ã2001 Semtech Corp
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pertaining:
Lost_Phase mode is entered.
1. ETSI 300 462-5, Section 9.1, requires that the shortterm phase error during switchover (i.e., Locked to Holdover
to Locked) be limited to an accumulation rate no greater
than 0.05 ppm during a 15 second interval.
The typical phase disturbance on clock
reference source switching will be less than 12
ns on the ACS8510. For clock reference
switching caused by the main input failing or
being disconnected, then the phase disturbance
on the output will still be less than the 120 ns
allowed for in the G.813 spec. The actual value
is dependant on the frequency being locked to.
2. ETSI 300 462-5, Section 9.2, requires that the longterm phase error in the Holdover mode should not exceed
{(a1+a2)S+0.5bS2+c}, where
a1 = 50 ns/s (allowance for initial frequency offset)
a2 = 2000 ns/s (allowance for temperature variation)
b = 1.16x10 ns/s (allowance for ageing)
-4
2
c = 120 ns (allowance for entry into Holdover mode).
3. ANSI Tin1.101-1994, Section 8.2.2, requires that the
phase variation be limited so that no more than 255 slips
(of 125 µs each) occur during the first day of Holdover.
This requires a frequency accuracy better than:
((24x60x60)+(255x125µs))/(24x60x60) = 0.37 ppm.
Temperature variation is not restricted, except to within
the normal bounds of 0 to 50 Celsius.
4. Telcordia GR.1244.CORE, Section 5.2. Table 4. shows
that an initial frequency offset of 50 ppb is permitted on
entering Holdover, whilst a drift over temperature of 280
ppb is allowed; an allowance of 40 ppb is permitted for all
other effects.
5. ITU G.822, Section 2.6, requires that the slip rate during
category(b) operation (interpreted as being applicable to
Holdover mode operation) be limited to less than 30 slips
(of 125 µs each) per hour
((((60 x 60)/30)+125µs)/(60x60)) = 1.042 ppm.
Phase Build Out
The PBO requirement, as specified in Telcordia
GR1244-CORE, Section 5.7, is that a phase
transient of greater than 3.5 µs occuring in
less than 0.1 seconds should be absorbed. This
will be implemented on a future version.
ITU-T G.813 states that the max allowable short
term phase transient response, resulting from
a switch from one clock source to another,
with Holdover mode entered in between, should
be a maximum of 1 µs over a 15 second
interval. The maximum phase transient or jump
should be less than 120 ns at a rate of change
of less than 7.5 ppm and the Holdover
performance should be better than 0.05 ppm.
On the ACS8510, PBO can be enabled, disabled
or frozen using the µP interface. By default, it
is enabled. When PBO is enabled, it can also
be frozen, which will disable the PBO operation
on the next input reference switch, but will
remain with the current offset. If PBO is disabled
while the device is in the Locked mode, there
will be a phase jump on the output SEC clocks
as the DPLL locks back to 0 degree phase
error.
Phase Transient Response and Holdover
Phase Build Out (PBO) is the function to minimise
phase transients on the output SEC clock during
input reference switching. If the currently
selected input reference clock source is lost
(due to a short interruption, out of frequency
detection, or complete loss of reference), the
second, next highest priority reference source
will be selected. During this transition, the
Revision 2.07/Jan 2001 ã2001 Semtech Corp
17
Micro-Processor Interface
The ACS8510 incorporates a microprocessor
interface, which can be configured for the
following modes via the bus interface mode
control pins UPSEL(2:0) as defined in Table 6.
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1 00
G .8 13 o ption 1 , co nstan t te m pe rature w a nder lim it
Tim e
(n s)
10
1
M T IE m e as ure m en t o n 1 55 M H z ou tp ut, 1 9.44 M H z i/p (8 kH z locking),
V e ctron 6 6 64 xtal
0.1
0 .01
0.01
0 .1
1
10
1 00 0
10 00 0
O b serva tio n interva l (s)
1 00
Figure 4: Maximum Time Interval Error of TOUT0 output port
10
G .8 13 optio n 1 con s tan t tem perature w ander lim it
T im e
(ns)
1
0 .1
T D E V m ea su rem e nt on 1 55 M H z ou tpu t, 19.44 M H z i/p (8kH z locking),
V ectron 6 664 xtal
0.01
0.01
0.1
1
10
1 00
1 000
100 00
O bs erva tio n interval (s )
Figure 5: Time Deviation of TOUT0 output port
10000000
Phase Error (ns)
1000000
P e rm itte d P h a s e E rr o r L im it
100000
10000
1000
100
T y p ic a l m e a s u r e m e n t, 2 5 ° C c o n s ta n t te m p e r a tu re
10000
1000
100000
O b s e r v a tio n in te rv a l ( s )
Figure 6: Phase error accumulation of TOUT0 output port in hold-over mode
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UPSEL(2:0)
Mode
Description
111
110
101
100
011
010
001
000
OFF
OFF
SERIAL
MOTOROLA
INTEL
MULTIPLEXED
EPROM
OFF
Interface disabled
Interface disabled
Serial uP bus interface
Motorola interface
Intel compatible bus interface
Multiplexed bus interface
EPROM read mode
Interface disabled
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
right most bit. Some registers carry several
individual data fields of various sizes, from
single-bit values (e.g. flags) upwards. Several
data fields are spread across multiple registers;
their organisation is shown in the register map,
Table 7.
Configuration Registers
Table 6: Microprocessor Interface Mode Selection
Motorola Mode
Parallel data + address: this mode is suitable
for use with Motorola's 68x0 type bus.
Intel Mode
Parallel data + address: this mode is suitable
for use with Intel's 80x86 type bus.
Multiplexed Mode
Data/address: this mode is suitable for use
with microprocessors which share bus signals
between address and data (e.g., Intel's 80x86
family).
Serial Mode
This mode is suitable for use with
microprocessor which use a serial interface.
EPROM Mode
This mode is suitable for use with an EPROM,
in which configuration data is stored (one-way
communication - status information will not be
accessible). A state machine internal to the
ACS8510 device will perform numerous EPROM
read operations to pull the data out of the
EPROM.
Each configuration register reverts to a default
value on power-up or following a reset. Most
default values are fixed, but some will be pinsettable. All configuration registers can be read
out over the microprocessor port.
Status Registers
The Status Registers contain readable registers.
They may all be read from outside the chip but
are not writeable from outside the chip (except
for a clearing operation). All status registers
are read via shadow registers to avoid data
hits due to dynamic operation. Each individual
status register has a unique location.
Register Access
Most registers are of one of two types,
configuration registers or status registers, the
exceptions being the Chip_ID and Chip_revision
registers. Configuration registers may be written
to or read from at any time (the complete 8-bit
register must be written, even if only one bit is
being modified). All status registers may be read
at any time and, in some status registers (such
as the ‘sts_interrupts’ register), any individual
data field may be cleared by writing a "1" into
each bit of the field (writing a "0" value into a
bit will not affect the value of the bit). A
description of each register follows.
Register Set
Interrupt Enable and Clear
All registers are 8-bits wide, organised with the
most-significant bit positioned in the left-most
bit, with bit-significance decreasing towards the
Interrupt requests are flagged on pin INTREQ
(active High).
Revision 2.07/Jan 2001 ã2001 Semtech Corp
19
Bits in the interrupt status register are set (high)
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by the following conditions;
(i) any reference source becoming valid or going invalid
(ii) a change in the operating state (eg. locked, holdover
etc.)
(iii) brief loss of the currently selected reference source
(iv) AMI input error
All interrupt sources are maskable via the mask
register, each one being enabled by writing a
'1' to the appropriate bit.
Any unmasked bit set in the interrupt status
register will cause the interrupt request pin to
be asserted (high).
All interrupts are cleared by writing a '1' to the
bit(s) to be cleared in the status register.
When all pending unmasked interrupts are
cleared the interrupt pin will go inactive (low).
The loss of the currently selected reference
source will eventually cause the input to be
considered invalid, triggering an interrupt. The
time taken to raise this interrupt is dependant
on the leaky bucket configuration of the activity
monitors. The very fastest leaky bucket setting
will still take up to 128 ms to trigger the
interrupt. The interrupt caused by the brief
loss of the currently selected reference source
is provided to facilitate very fast source failure
detection if desired. It is triggered after missing
just a couple of cycles of the reference source.
Some applications require the facility to switch
downstream devices based on the status of
the reference sources. In order to provide extra
flexibility, it is possible to flag the "main
reference failed" interrupt (addr 06, bit 6) on
the pin TDO. This is simply a copy of the status
bit in the interrupt register and is independent
of the mask register settings. The bit is reset
by writing to the interrupt status register in the
normal way. This feature can be enabled and
disabled by writing to bit 6 of register 48Hex.
This section left blank
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Register map
Shaded areas in the map are ‘don’t care’ and writing either 0 or 1 will not affect any function of
the device.
Bits labelled ‘Set to 0’ or ‘Set to 1’ must be set as stated during initialisation of the device,
either following power up, or after a power on reset (POR). Failure to correctly set these bits may
result in the device operating in an unexpected way.
Some registers do not appear in this list. These are either not used, or have test functionality. Do
not write to any undefined registers as this may cause the device to operate in a test mode. If an
undefined register has been inadvertently addressed, the device should be reset to ensure the
undefined registers are at default values.
A d d r. P ar am et er N am e
( Hex )
D at a B i t
7 ( m sb )
00
6
5
4
ch ip _id
(read only)
chip _revision
(read only)
03
cnfg_control1
(read/w rite)
04
cnfg_control2
(read/w rite)
05
sts_interrup ts
(read /w rite)
06
08
sts_T4_inp uts
(read /w rite)
09
sts_op erating_mode
(read only)
0A
sts_p riority_tab le
(read only)
0D
0F
0 ( l sb )
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '1'
Set to '0'
Ch ip revision numb er (7:0)
Analog
div sync
Set to '0'
Set to '0'
Ph ase loss flag limit
<I_8> valid
change
<I_7> valid
change
<I_6> valid
change
<I_5> valid
change
<I_4> valid
ch ange
<I_3> valid
change
<I_2> valid
change
<I_1> valid
ch ange
Op erating
mode
Main ref.
failed
<I_14> valid
change
<I_13> valid
change
<I_12> valid
ch ange
<I_11> valid
change
<I_10> valid
change
<I_9> valid
ch ange
T4 ref failed
A mi 2
Violation
A mi 2
L.O.S.
A mi 1
Violation
A mi 1
L.O.S.
Op erating mode (2:0)
High est p riority valid source
Currently selected reference source
3rd high est p riority valid source
2nd high est p riority valid source
sts_curr_inc_offset
(read only)
Current increment offset (7:0)
Current increment offset (15:8)
07
0E
1
Device p ar t numb er (15:8)
02
0C
2
Device p ar t numb er (7:0)
01
0B
3
Current increment offset (18:16)
sts_sources_valid
(read only)
<I_8>
Revision 2.07/Jan 2001 ã2001 Semtech Corp
<I_7>
<I_6>
<I_5>
<I_4>
<I_3>
<I_2>
<I_1>
<I_14>
<I_13>
<I_12>
<I_11>
<I_10>
<I_9>
21
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A d d r. P ar am et er N am e
( Hex )
D at a B i t
7 ( m sb )
10
sts_reference_sources
(read/w rite)
6
5
4
3
2
1
status <I_2>
status <I_1>
11
status <I_4>
status <I_3>
12
status <I_6>
status <I_5>
13
status <I_8>
status <I_7>
14
status <I_10>
status <I_9>
15
status <I_12>
status <I_11>
16
status <I_14>
status <I_13>
p rogrammed_p riority <I_2>
p rogrammed_p riority <I_1>
19
p rogrammed_p riority <I_4>
p rogrammed_p riority <I_3>
1A
p rogrammed_p riority <I_6>
p rogrammed_p riority <I_5>
1B
p rogrammed_p riority <I_8>
p rogrammed_p riority <I_7>
1C
p rogrammed_p riority <I_10>
p rogrammed_p riority <I_9>
1D
p rogrammed_p riority <I_12>
p rogrammed_p riority <I_11>
1E
p rogrammed_p riority <I_14>
p rogrammed_p riority <I_13>
18
20
cnfg_ref_selection_p riority
(read/w rite)
cnfg_ref_source_frequency
(read/w rite)
0 ( l sb )
divn
lock8k
b ucket_id <I_1>(1:0)
reference_source_frequency <I_1>(3:0)
21
divn
lock8k
b ucket_id <I_2>(1:0)
reference_source_frequency <I_2>(3:0)
22
divn
lock8k
b ucket_id <I_3>(1:0)
reference_source_frequency <I_3>(3:0)
23
divn
lock8k
b ucket_id <I_4>(1:0)
reference_source_frequency <I_4>(3:0)
24
divn
lock8k
b ucket_id <I_5>(1:0)
reference_source_frequency <I_5>(3:0)
25
divn
lock8k
b ucket_id <I_6>(1:0)
reference_source_frequency <I_6>(3:0)
26
divn
lock8k
b ucket_id <I_7>(1:0)
reference_source_frequency <I_7>(3:0)
27
divn
lock8k
b ucket_id <I_8>(1:0)
reference_source_frequency <I_8>(3:0)
28
divn
lock8k
b ucket_id <I_9>(1:0)
reference_source_frequency <I_9>(3:0)
29
divn
lock8k
b ucket_id <I_10>(1:0)
reference_source_frequency <I_10>(3:0)
2A
divn
lock8k
b ucket_id <I_11>(1:0)
reference_source_frequency <I_11>(3:0)
2B
divn
lock8k
b ucket_id <I_12>(1:0)
reference_source_frequency <I_12>(3:0)
2C
divn
lock8k
b ucket_id <I_13>(1:0)
reference_source_frequency <I_13>(3:0)
2D
divn
lock8k
b ucket_id <I_14>(1:0)
reference_source_frequency <I_14>(3:0)
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ACS8510 SETS
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A d d r. P ar am e t e r N am e
( Hex )
D at a B i t
7 ( m sb )
30
31
6
5
4
cnfg_sts_remote_sources_
valid
(read /w rite)
32
cnfg_op erating_mode
(read /w rite)
33
cnfg_ref_selection
(read /w rite)
34
cnfg_mode
(read /w rite)
35
cnfg_T4
(read /w rite)
36
cnfg_d ifferential_inp uts
(read /w rite)
37
cnfg_uPsel_p ins
(read only)
38
cnfg_T0_outp ut_enab le
(read /w rite)
39
cnfg_T0_outp ut_freq uencies
(read /w rite)
3A
cnfg_d ifferential_outp uts
(read /w rite)
3B
cnfg_b and w id th
(read /w rite)
3C
cnfg_nominal_freq uency
(read /w rite)
1
Forced op erating mod e
force_select_reference_source
A u to
external
2K enab le
Ph ase
alarm
timeout
enab le
Clock ed ge
Hold over
Offset
enab le
Sq uelch
Select
T0/T1
SON ET/
SDH
I/P
External 2K
Sync enab le
Master/
Slave
Force T1 inp ut source selection
(only valid for inp uts I_5 to I_10)
<I_6>
PECL
<I_5>
PECL
Micro-p rocessor typ e
311.04MHz
on T06
1=SON ET
0=SDH
for Dig2
1=SON ET
0=SDH
for Dig1
T01
Digital2
Digital1
T07 Freq uency
selection
T06 Freq uency
selection
A uto b /w
sw itch
A cq /lock
T03
19.44MHz
T02
T04
38.88MHz
T02
A cq uisition b and w id th
T07 LV DS
enab le
T07 PECL
enab le
Set to '0'
T05
77.76MHz
T01
T06 LV DS
enab le
T06 PECL
enab le
N ormal/locked b and w id th
N ominal freq uency (7:0)
cnfg_h old over_offset
(read /w rite)
Hold over offset (7:0)
Hold over offset (15:8)
A u to
Hold over
A veraging
Hold over offset (18:16)
cnfg_freq _limit
(read /w rite)
DPLL Freq uency offset limit (7:0)
42
DPLL Freq uency offset
limit (9:8)
cnfg_interrup t_mask
(read /w rite)
44
<I_8> valid
ch ange
<I_7> valid
ch ange
<I_6> valid
ch ange
<I_5> valid
ch ange
<I_4> valid
ch ange
<I_3> valid
ch ange
<I_2> valid
ch ange
<I_1> valid
ch ange
Op erating
mod e
Main ref.
failed
<I_14> valid
ch ange
<I_13> valid
ch ange
<I_12> valid
ch ange
<I_11> valid
ch ange
<I_10> valid
ch ange
<I_9> valid
ch ange
T4 ref
A mi 2
V iolation
A mi 2
L.O.S
A mi 1
V iolation
A mi 1
L.O.S
45
46
Reversion
mod e
N ominal freq uency (15:8)
40
43
0 ( l sb )
Remote status, ch annels <14:9>
3F
41
2
Remote status, ch annels <8:1>
3D
3E
3
cnfg_freq _d ivn
(read /w rite)
Divid e-inp ut-b y-n ratio (7:0)
47
Revision 2.07/Jan 2001 ã2001 Semtech Corp
Divid e-inp ut-b y-n ratio (13:8)
23
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ACS8510 SETS
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A d d r. P ar am et er N am e
( Hex )
D at a B i t
7 ( m sb )
6
5
4
3
2
Flag ref lost
on TDO
Ultra-fast
sw itching
External
source
sw itch
enab le
Freeze p hase
b uildout
Phase
b uildout
enab le
48
cnfg_monitors
(read/w rite)
50
cnfg_activ_up p er_threshold0
(read/w rite)
Configuration 0: Activity alarm set threshold (7:0)
51
cnfg_activ_low er_threshold0
(read/w rite)
Configuration 0: Activity alarm reset threshold (7:0)
52
cnfg_b ucket_size0
(read/w rite)
53
cnfg_decay_rate0
(read/w rite)
54
cnfg_activ_up p er_threshold1
(read/w rite)
Configuration 1: Activity alarm set threshold (7:0)
55
cnfg_activ_low er_threshold1
(read/w rite)
Configuration 1: Activity alarm reset threshold (7:0)
56
cnfg_b ucket_size1
(read/w rite)
57
cnfg_decay_rate1
(read/w rite)
58
cnfg_activ_up p er_threshold2
(read/w rite)
Configuration 2: Activity alarm set threshold (7:0)
59
cnfg_activ_low er_threshold2
(read/w rite)
Configuration 2: Activity alarm reset threshold (7:0)
5A
cnfg_b ucket_size2
(read/w rite)
5B
cnfg_decay_rate2
(read/w rite)
5C
cnfg_activ_up p er_threshold3
(read/w rite)
Configuration 3: Activity alarm set threshold (7:0)
5D
cnfg_activ_low er_threshold3
(read/w rite)
Configuration 3: Activity alarm reset threshold (7:0)
5E
cnfg_b ucket_size3
(read/w rite)
5F
cnfg_decay_rate3
(read/w rite)
7F
cnfg_uPsel
(read/w rite)
Revision 2.07/Jan 2001 ã2001 Semtech Corp
1
0 ( l sb )
Frequency monitors
configuration (1:0)
Configuration 0: Activity alarm b ucket size (7:0)
Cfg 0:decay_rate (1:0)
Configuration 1: Activity alarm b ucket size (7:0)
Cfg 1:decay_rate (1:0)
Configuration 2: Activity alarm b ucket size (7:0)
Cfg 2:decay_rate (1:0)
Configuration 3: Activity alarm b ucket size (7:0)
Cfg 3:decay_rate (1:0)
Micro-p rocessor typ e
24
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Register map description
Addr. Parameter N ame
(H ex)
00
chi p_i d
01
02
D escription
D efault
Value (bin)
Thi s read-only regi ster contai ns the devi ce ID .
Address 00 Least-si gni fi cant byte: 3E(hex)
Address 01 Most-si gni fi cant byte: 21(hex)
213E(hex) = 8510(dec)
chi p_revi si on
Thi s read only regi ster contai ns the chi p revi si on number
cnfg_control1
Bi ts (3:0) & 5 are test controls and should be ei ther set at '0' duri ng i ni ti ali sati on or left
unchanged.
00111110
00100001
00000001
Bi t 4, when set hi gh, synchroni ses the di vi ders i n the output APLL secti on to the di vi ders i n the
D PLL secti on such that thei r phases ali gn. Thi s i s necessary to have the phase ali gnment
between the i nputs and output clocks at OC 3 deri ved rates (6.48 MHz to 77.76 MHz). By
default, synchroni sati on occurs for 2 seconds after power up and i s then turned off. Setti ng thi s
bi t hi gh keeps synchroni sati on on, whi ch may be necessary to avoi d the di vi ders getti ng out of
sync when qui ck changes i n frequency occur such as a force i nto freerun mode.
03
cnfg_control2
Bi ts (2:0) are test controls and should be set at '010' duri ng i ni ti ali sati on or left unchanged.
Bi ts (5:3) defi ne the phase loss flag li mi t. By default set to 4 (100) whi ch corresponds to
approxi mately 140°. A lower value sets a correspondi ng lower phase li mi t. The flag li mi t
determi nes the value at whi ch the D PLL i ndi cates phase lost as a result of i nput ji tter, a phase
jump, or a frequency jump on the i nput
04
sts_i nterrupts
X X 000000
X X 100010
Thi s 16 bi t regi ster contai ns one bi t for each bi t of sts_sources_vali d, one for loss of reference
the devi ce was locked to, and another for the operati ng mode. All bi ts are acti ve hi gh.
All bi ts except the mai n_ref_fai led bi t (bi t14) are set on a "change" i n the state of the relevent
status bi t, i .e. i f a source becomes vali d, or goes i nvali d i t wi ll tri gger an i nterrupt. If the FSM
changes state at all the i nterrupt wi ll be generated.
Bi t 14 (mai n_ref_fai led) of the i nterrupt status regi ster i s used to flag i nacti vi ty on the reference
that the devi ce i s locked to much more qui ckly than the acti vi ty moni tors can support. If bi t 6 of
the cnfg_moni tors regi ster (flag ref loss on TD O) i s set, then the state of thi s bi t i s dri ven onto
the TD O pi n of the devi ce.
All bi ts are maskable by the bi ts i n the cnfg_i nterrupt_mask regi ster. Each bi t may be cleared
i ndi vi dually by wri ti ng a '1' to that bi t, thus resetti ng the i nterrupt. Any number of bi ts can be
cleared wi th a si ngle wri te operati on. Wri ti ng '0's wi ll have no effect.
05
Least-si gni fi cant byte (7:0)
00000000
06
Most-si gni fi cant byte (15:8)
00000000
Thi s regi ster holds the status flags of the AMI i nputs and the TOUT4 reference. The alarms
once set wi ll hold thei r state unti l reset. Each bi t may be cleared i ndi vi dually by wri ti ng a '1' to
that bi t, thus resetti ng the i nterrupt. Wri ti ng '0's wi ll have no effect. These bi ts can also generate
i nterrupts.
Bit
C ontent
0:
'1' = Ami 1 Loss of si gnal; '0' = Ami 1 clear
1:
'1' = Ami 1 Vi olati on detected; '0' = Ami 1 clear
2:
'1' = Ami 2 Loss of si gnal; '0' = Ami 2 clear
3:
'1' = Ami 2 Vi olati on detected; '0' = Ami 2 clear
4:
'1' = T4 reference fai led - no vali d TIN1 i nput (<I_10>:<I_5>), T4 D PLL cannot lock
to source;
'0' = T4 reference good - vali d TIN1 i nput avai lable
(5:7)
unused (value: x)
X X X 10000
sts_T4_i nputs
08
sts_operati ng_mode
09
Thi s read-only regi ster holds the current operati ng state of the mai n state machi ne. Fi gure 7
show how the values of the 'operati ng state' vari able match wi th the i ndi vi dual states.
Bit
C ontent
2:0
Operati ng state (2:0)
Bi ts (2:0) State
001
freerun
010
holdover
100
locked
110
pre-locked
101
pre-locked2
111
phase lost
(3:7)
X X X X X 001
unused
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Addr. Parameter N ame
(H ex)
sts_pri ori ty_table
D escription
D efault
Value (bin)
Thi s i s a 16-bi t read-only regi ster, taki ng two addresses.
C urrently-selected reference source: thi s i s the channel number of the i nput reference source
whi ch i s currently connected to the SETG functi on.
Hi ghest-pri ori ty vali d source: thi s i s the channel number of the i nput reference source whi ch i s
vali d and has the hi ghest pri ori ty; i t may not be the same as the currently-selected reference
source (due to fai lure hi story or changes i n programmed pri ori ty).
Second-hi ghest pri ori ty vali d source: thi s i s the channel number of the i nput reference source
whi ch i s vali d and has the next-hi ghest pri ori ty to the hi ghest-pri ori ty vali d source.
Thi rd-hi ghest pri ori ty vali d source: thi s i s the channel number of the i nput reference source
whi ch i s vali d and has the next-hi ghest pri ori ty to the second-hi ghest-pri ori ty vali d source.
Note that these regi sters are updated by the state machi ne i n response to the contents of the
cnfg_ref_selecti on_pri ori ty regi ster and the ongoi ng status of i ndi vi dual channels; channel
number '0000', appeari ng i n any of these regi sters, i ndi cates that no channel i s avai lable for
that pri ori ty.
Bit
C ontent
0A
(7:4)
(3:0)
Hi ghest-pri ori ty vali d source
C urrently selected reference source
00000000
0B
(7:4)
(3:0)
3rd-hi ghest-pri ori ty vali d source
2nd-hi ghest-pri ori ty vali d source
00000000
sts_curr_i nc_offset
Thi s read-only regi ster contai ns a si gned-i nteger value representi ng the 19 bi ts of the current
i ncrement offset of the di gi tal PLL. The regi ster may be read peri odi cally to bui ld up a hi stori cal
database for later use duri ng holdover peri ods (thi s would only be necessary i f an external
osci llator whi ch di d not meet the stabi li ty cri teri a descri bed i n Local Osci llator C lock secti on i s
used). The regi ster wi ll read 00000000 i mmedi ately after reset.
0C
Least si gni fi cant byte of offset value
00000000
0D
Next si gni fi cant byte of offset value
00000000
07
Bi ts (7:4) unused
Bi ts (2:0) 3 most si gni fi cant bi ts of offset value
0E
sts_sources_vali d
0F
X X X X X 000
Thi s 14 bi t regi ster contai ns copi es of bi t 3 from all the status_reference_sources bytes. Thi s
allows the user to get the ‘ vali di ty’ of all sources i n just 2 reads.
X X 000000
Thi s regi ster only i ndi cates whether or not a source has passed all cri teri a.
sts_reference_sources
00000000
Thi s i s a 7-byte regi ster whi ch holds the status of each of the 14 i nput reference sources. The
status of each reference source i s shown i n a 4-bi t fi eld. Each bi t i s acti ve hi gh.To ai d status
checki ng, a copy of each status bi t 3 i s provi ded i n the sts_sources_vali d regi ster. The status i s
reported as follows: (Each bi t may be cleared i ndi vi dually)
Status
Status
Status
Status
bi t 0
bi t 1
bi t 2
bi t 3
= phase lock alarm
= no acti vi ty alarm
= out-of-band alarm
= Source vali d (no alarms) (bi t 3 i s combi nati on of bi ts (2:0))
The organi sati on of the regi ster i s shown below and i n the regi ster map.
Bit
C ontent
10
(3:0)
(7:4)
Status of i nput reference source <I-1>
Status of i nput reference source <I_2>
01000100
11
(3:0)
(7:4)
Status of i nput reference source <I_3>
Status of i nput reference source <I_4>
01100110
12
(3:0)
(7:4)
Status of i nput reference source <I_5>
Status of i nput reference source <I_6>
01100110
13
(3:0)
(7:4)
Status of i nput reference source <I_7>
Status of i nput reference source <I_8>
01000100
14
(3:0)
(7:4)
Status of i nput reference source <I_9>
Status of i nput reference source <I_10>
01000100
15
(3:0)
(7:4)
Status of i nput reference source <I_11>
Status of i nput reference source <I_12>
01000100
16
(3:0)
(7:4)
Status of i nput reference source <I_13>
Status of i nput reference source <I_14>
01000100
Revision 2.07/Jan 2001 ã2001 Semtech Corp
26
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ACS8510 SETS
FINAL
ADVANCED COMMUNCIATIONS
Addr. Parameter N ame
(H ex)
cnfg_ref_selecti on_pri ori ty
D escription
D efault
Value (bin)
Thi s i s a 7-byte regi ster whi ch holds the pri ori ty of each of the 14 i nput reference sources. The pri ori ty values
are all relati ve to each other, wi th lower-valued numbers taki ng hi gher pri ori ti es. Only the values 1 to 15 (dec)
are vali d - 0 di sables the reference source. Each reference source should be gi ven a uni que number,
however two sources gi ven the same pri ori ty number wi ll be assi gned on a fi rst i n fi rst out basi s.
It i s sensi ble to reserve the value '1' i n case i t i s necessary to re-order the pri ori ti es on the fly - therefore, the
range 2 to 15 would normally be used (i n a slave devi ce, the value 1 i s automati cally used for the protecti on
source, i nput #11). All values should be i n hexadeci mal.
The organi sati on of the regi ster i s shown below and i n the regi ster map.
* The default value gi ven i s vali d when MSTSLVB pi n i s left unconnected or ti ed hi gh. If MSTSLVB i s ti ed low,
the default value i s D C (hex).
Bit
C ontent
18
(3:0)
(7:0)
Programmed pri ori ty of i nput reference source <I_1>
Programmed pri ori ty of i nput reference source <I_2>
00110010
19
(3:0)
(7:4)
Programmed pri ori ty of i nput reference source <I_3>
Programmed pri ori ty of i nput reference source <I_4>
01010100
1A
(3:0)
(7:4)
Programmed pri ori ty of i nput reference source <I_5>
Programmed pri ori ty of i nput reference source <I_6>
01110110
1B
(3:0)
(7:4)
Programmed pri ori ty of i nput reference source <I_7>
Programmed pri ori ty of i nput reference source <I_8>
10011000
1C
(3:0)
(7:4)
Programmed pri ori ty of i nput reference source <I_9>
Programmed pri ori ty of i nput reference source <I_10>
10111010
1D
(3:0)
(7:4)
Programmed pri ori ty of i nput reference source <I_11>
Programmed pri ori ty of i nput reference source <I_12>
11010001*
1E
(3:0)
(7:4)
Programmed pri ori ty of i nput reference source <I_13>
Programmed pri ori ty of i nput reference source <I_14>
11111110
cnfg_ref_source_frequency
Thi s i s a 14-byte regi ster whi ch holds the keys to the frequenci es of each of the 14 i nput reference sources,
as li sted below.
Bi ts (3:0) of each byte defi ne the frequency of the reference source i n accordance wi th the followi ng key:
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
8 kHz
1544 kHz (SONET) / 2048 kHz (SD H) (As defi ned by Regi ster 34, bi t 2)
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
2 kHz
4 kHz
Bi ts (5:4) of each byte together defi ne whi ch leaky bucket setti ngs (0-3) are used, as defi ned i n regi sters 50
(hex) to 5F (hex).
Bi ts (7:6) of each byte defi ne the operati on undertaken on the i nput frequency, i n accordance wi th the
followi ng key:
00
01
10
11
The i nput frequency i s fed di rectly i nto the D PLL.
The i nput frequency i s i nternally di vi ded down to 8 kHz, before bei ng fed i nto the D PLL. Thi s
gi ves excellent ji tter tolerance.
Unsupported confi gurati on - do not use.
Uses the di vi si on coeffi ci ent stored i n regi ster cnfg_freq_di vn to di vi de the i nput by thi s value
pri or to goi ng to the D PLL. The frequency moni tors must be di sabled. The di vi ded down
frequency should equal 8kHz. The frequency (3:0) should be set to the nearest spot frequency
just below the actual i nput frequency. The D i vN feature works for i nput frequenci es between
1.544 MHz and 100 MHz.
* The default value gi ven i s vali d when MSTSLVB pi n i s left unconnected or ti ed hi gh. If MSTSLVB i s ti ed low,
the default value i s 03 (hex).
20
Frequency of reference source <I_1> - fi xed at 00000000 for 8kHz only
00000000
21
Frequency of reference source <I_2> - fi xed at 00000000 for 8kHz only
00000000
22
Frequency of reference source <I_3>
00000000
23
Frequency of reference source <I_4>
00000000
Revision 2.07/Jan 2001 ã2001 Semtech Corp
27
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ACS8510 SETS
FINAL
ADVANCED COMMUNCIATIONS
Addr. Parameter N ame
(H ex)
D escription
D efault
Value (bin)
24
Frequency of reference source <I_5>
00000011
25
Frequency of reference source <I_6>
00000011
26
Frequency of reference source <I_7>
00000011
27
Frequency of reference source <I_8>
00000011
28
Frequency of reference source <I_9>
00000011
29
Frequency of reference source <I_10>
00000011
2A
Frequency of reference source <I_11>
00000010*
2B
Frequency of reference source <I_12>
00000001
2C
Frequency of reference source <I_13>
00000001
Frequency of reference source <I_14>
00000001
2D
cnfg_sts_remote_sources_
vali d
Thi s 14-bi t regi ster holds the status of the reference sources suppli ed to another devi ce.It i s a
copy of the other devi ce's sts_sources_vali d regi ster. The regi ster i s part of the protecti on
mechani sm. The regi ster i s organi sed as follows:
30
Bit
(7:0)
Reference source
<I_8>:<I_1>
11111111
31
Bit
(5:0)
(7:6)
Reference source
<I_14>:<I_9>
unused
XX111111
cnfg_operati ng_mode
32
Thi s 3-bi t regi ster occupi es the enti re 8-bi t space at address 32(hex). It i s used to force the
devi ce i nto a desi red operati ng state, represented by the bi nary values shown i n Fi gure 8.
Value 0 (hex) allows the control state machi ne to operate automati cally.
Bit
(2:0)
(7:3)
cnfg_ref_selecti on
Reference source
D esi red operati ng state (as per Fi gure 8)
Unused
Thi s 4-bi t regi ster occupi es the enti re 8-bi t space at address 33(hex). It i s used to force the
devi ce to select a parti cular i nput reference source, i rrespecti ve of i ts pri ori ty.
Wri ti ng to thi s regi ster temporari ly rai ses the selected i nput to pri ori ty '1'. Provi ded no other
i nput i s already programmed wi th pri ori ty '1', and reverti ve mode i s on, thi s source wi ll be
selected, i f i t has been vali dated by the frequency and acti vi ty moni tors.
33
X X X X X 000
XXXX1111*
Wri ti ng X0(hex) or XF(hex) wi ll di sable all i nput reference sources. * The default i s XF.
Bit
(3:0)
(7:4)
cnfg_mode
34
Informati on
D esi red reference source
Unused
Thi s 7-bi t regi ster occupi es the enti re 8-bi t space at address 34(hex). It contai ns several
i ndi vi dual confi gurati on fi elds, as detai led below:
Bit 0
= 0 Non-reverti ve Mode: The devi ce wi ll retai n the presently selected source. Thi s i s the
default state.
= 1 Reverti ve Mode: The devi ce wi ll swi tch to the hi ghest pri ori ty source avai lable shown i n
the sts_pri ori ty_table regi ster(7:4) (at address 0A(hex)).
11001000
Bit 1
= 0 Slave Mode:The devi ce wi ll adopt the slave mode and wi ll follow the master devi ce.
= 1 Master Mode:The devi ce wi ll adopt the master mode and make the acti ve deci si ons of
whi ch source to select, etc. Thi s bi t i s wri teable, but i ts default value i s determi ned by the pi n,
MSTSLVB.
Revision 2.07/Jan 2001 ã2001 Semtech Corp
28
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ACS8510 SETS
FINAL
ADVANCED COMMUNCIATIONS
Addr. Parameter N ame
(H ex)
cnfg_mode
D escription
D efault
Value (bin)
Bit 2
= 0 SD H Mode:The devi ce expects the i nput frequency of any i nput channel gi ven the value
'0001' i n the cnfg_ref_source_frequency regi ster to be 2048 kHz. Thi s bi t i s wri teable, but i ts
default value i s determi ned by the pi n, SONSD HB.
= 1 SONET Mode:The devi ce expects the i nput frequency of any i nput channel gi ven the value
'0001' i n the cnfg_ref_source_frequency regi ster to be 1544 kHz. Thi s bi t i s wri teable, but i ts
default value i s determi ned by the pi n, SONSD HB.
Bit 3
= 0 External 2 kHz Sync D i sable: The devi ce wi ll i gnore the Sync2k pi n.
= 1 External 2 kHz Sync Enable: The devi ce wi ll ali gn the phase of i ts i nternally-generated
Frame Sync si gnal (8 kHz) and Multi -Frame Sync si gnal (2 kHz) wi th that of the si gnal
suppli ed to the Sync2K pi n. The devi ce should be locked to a 6.48 MHz output from another
AC S8510. Thi s i s the default state.
Bit 4
= 0 Holdover Offset D i sable: The devi ce wi ll i gnore the value and holdover wi ll use the current
PLL i ntegral path value. Thi s i s the default state.
= 1 Holdover Offset Enable: The devi ce wi ll adopt the Holdover Offset value stored i n the
cnfg_holdover_offset regi ster. Thi s value i s then used to set the frequency i n Holdover mode.
34
cont
11001000
Bit 5
= 0 Falli ng C lock Edge Selected: The devi ce wi ll reference to the falli ng edge of the external
osci llator si gnal. Thi s i s the default state.
= 1 Ri si ng C lock Edge Selected: The devi ce wi ll reference to the ri si ng edge of the external
osci llator si gnal.
Bit 6
= 0 Phase Alarm Ti meout D i sable: The phase alarm wi ll not ti meout and must be reset
externally.
= 1 Phase Alarm Ti meout Enable: The phase alarm wi ll ti me out after 100 seconds. Thi s i s
the default state.
Bit 7
= 0 Auto 2 kHz Sync D i sable:The user controls thi s functi on usi ng bi t 3 of thi s regi ster, as
descri bed above.
= 1 Auto 2 kHz Sync Enable: External 2 kHz Sync wi ll be enabled only when the source i s
locked to 6.48 MHz. Otherwi se i t wi ll be di sabled. Thi s i s the default state.
cnfg_T4
Thi s 6-bi t regi ster occupi es the enti re 8-bi t space at address 35(hex). It contai ns several
i ndi vi dual confi gurati on fi elds, as detai led below:
Bit
(3:0)
4
5
6
7
35
C onfi gurati on fi eld
TIN1 i nput source selecti on
'1' = Select TOUT0
'0' = Select TIN1
'1' = Squelch
'0' = Non-Squelch (D efault)
Unused
Unused
X X 000000
TIN1 i nput source selecti on: The devi ce wi ll swi tch to the source shown i n thi s fi eld for the
generati on of the TOUT4 si gnal. If '0' i t wi ll select the hi ghest pri ori ty acti ve TIN1.
Select TOUT0/TIN1: The devi ce wi ll generate the TOUT4 si gnal from the TOUT0 path or the TIN1 path,
accordi ng to the status of thi s bi t.
Squelch/Non-Squelch: If thi s bi t i s set hi gh the devi ce wi ll squelch the TOUT4 si gnal, causi ng i t
to stop toggli ng and remai n at ei ther '1' or '0', If set low i t wi ll not squelch the TOUT4 si gnal.
cnfg_di fferenti al_i nputs
36
Thi s 2-bi t regi ster occupi es the enti re 8-bi t space at address 36(hex). It contai ns two
i ndi vi dual confi gurati on fi elds, as detai led below:
Bit
0
1
(7:2)
Revision 2.07/Jan 2001 ã2001 Semtech Corp
C onfi gurati on fi eld
'1' = Input <I_5> i s PEC L-compati ble
'0' = Input <I_5> i s LVD S-compati ble (D efault)
'1' = Input <I_6> i s PEC L-compati ble (D efault)
'0' = Input <I_6> i s LVD S-compati ble
Unused
29
X X X X X X 10
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ACS8510 SETS
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ADVANCED COMMUNCIATIONS
Addr. Parameter N ame
(H ex)
cnfg_uPsel_pi ns
D escription
Thi s 3-bi t regi ster occupi es the enti re 8-bi t space at address 37(hex). It holds the key for the
selecti on of the mi croprocessor type. It i s read-only, the value bei ng appli ed on the uPSel pi ns
and adopted on power-up or reset. After power-up the pi ns are i gnored but can sti ll be read
vi a thi s regi ster.
Bi t (2:0)
000
001
010
011
100
101
110
111
37
cnfg_T0_output_enable
38
D efault
Value (bin)
Mi croprocessor type
OFF (i nterface di sabled)
EPROM
MULTIPLEXED
INTEL
MOTOROLA
SERIAL
OFF (i nterface di sabled)
OFF (i nterface di sabled)
Bi ts(7:3)=
XXXXX
Bi ts(2:0)=
Pi n dependent
Thi s 8-bi t regi ster occupi es the enti re 8-bi t space at address 38(hex). It contai ns several
i ndi vi dual confi gurati on fi elds, as detai led below:
Bit
0
C onfi gurati on fi eld
'1' = Output port T05 enabled (77.76 MHz)
'0' = Output port T05 di sabled
1
'1' = Output port T04 enabled (38.88 MHz)
'0' = Output port T04 di sabled
2
'1' = Output port T03 enabled (19.44 MHz)
'0' = Output port T03 di sabled
3
'1' = Output port T02 enabled
'0' = Output port T02 di sabled
- see regi ster cnfg_T0_output_frequenci es
4
'1' = Output port T01 enabled
'0' = Output port T01 di sabled
- see regi ster cnfg_T0_output_frequenci es
5
'1' = Sonet mode selected for D i g1
'0' = SD H mode selected for D i g1
- see regi ster cnfg_T0_output_frequenci es
6
'1' = Sonet mode selected for D i g2
'0' = SD H mode selected for D i g2
- see regi ster cnfg_T0_output_frequenci es
7
'1' = T06 output frequency set to 311.04 MHz
'0' = T06 output frequency set by Address 3A (5:4)
00011111
Note: "D i sabled" means that the output port holds a stati c logi c value (the port i s not Tri stated).
cnfg_T0_output_frequenci es
39
Thi s regi ster holds the frequency selecti ons for each output port, as detai led below.
Bit
(1:0)
00
01
10
11
C onfi gurati on fi eld
T01
6.48 MHz*
25.92 MHz
19.44 MHz
D i g1
Bit
(3:2)
00
01
10
11
C onfi gurati on fi eld
T02
25.92 MHz
51.84 MHz
38.88 MHz*
D i g2
(5:4)
00
01
10
11
* = default
D i g1
1544 kHz/2048 kHz*
3088 kHz/4096 kHz
6176 kHz/8192 kHz
12352 kHz/16384 kHz
(7:6)
00
01
10
11
D i g2
1544 kHz/2048 kHz*
3088 kHz/4096 kHz
6176 kHz/8192 kHz
12352 kHz/16384 kHz
00001000
- For both D i g1 and D i g2, the left most frequency values are for Sonet mode and the others
are for SD H mode. They are selected vi a the SONET/SD H bi ts i n regi ster
cnfg_T0_output_enable.
Revision 2.07/Jan 2001 ã2001 Semtech Corp
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ACS8510 SETS
FINAL
ADVANCED COMMUNCIATIONS
Addr. P arameter N ame
(H ex)
cnfg_di fferenti al_outputs
3A
cnfg_bandwi dth
3B
cnfg_nomi nal_frequency
D escription
D efault
Value (bin)
Thi s regi ster holds the frequency selecti ons and the port-technology type for the di fferenti al
outputs, T06 and T07, as detai led below.
Bit
(1:0)
00
01
10
11
C onfi gurati on fi eld
T06
P ort di sabled
P E C L-compati ble
LV D S -compati ble*
unused
Bit
(3:2)
00
01
10
11
C onfi gurati on fi eld
T07
P ort di sabled
P E C L-compati ble*
LV D S -compati ble
unused
(5:4)
00
01
10
11
* = default
T06
38.88 MHz*
19.44 MHz
155.52 MHz
D i g1.
(7:6)
00
01
10
11
T07
155.52 MHz
51.84 MHz
77.76 MHz
19.44 MHz*
11000110
Thi s regi ster contai ns i nformati on used to control the operati on of the di gi tal P LL. When
bandwi dth selecti on i s set to automati c, the D P LL wi ll use the acqui si ti on bandwi dth setti ng
when out of lock, and the normal/locked bandwi dth setti ng when i n lock. When set to manual,
the D P LL wi ll alway use the normal/locked bandwi dth setti ng.
B i t (2:0)
000
001
010
011
100
101
110
111
Loop bandwi dth
0.1 Hz
0.3 Hz
0.6 Hz
1.2 Hz
2.5 Hz
5.0 Hz
10 Hz
20 Hz
(6:4)
000
001
010
011
100
101
110
111
A cqui si ti on bandwi dth
0.1 Hz
0.3 Hz
0.6 Hz
1.2 Hz
2.5 Hz
5.0 Hz
10 Hz
20 Hz
3
unused
7
B andwi dth selecti on
'0'= Manual operati on
'1'= A utomati c operati on
0111X 101
Thi s regi ster holds a 16 bi t unsi gned i nteger representi ng the desi red nomi nal frequency.
Thi s i s avai lable to opti onally cali brate the nomi nal output frequency to compensate agai nst
vari ati on i n the external crystal frequenci es.
Least-si gni fi cant byte.
3C
10011001
Most-si gni fi cant byte.
3D
cnfg_holdover_offset
3E
3F
10011001
Thi s 16-bi t regi ster uses addresses 3E (hex) to 40(hex). It holds a 16 bi t si gned i nteger,
representi ng the holdover offset value, whi ch can be used to set the holdover mode frequency
when enabled vi a the holdover offset enabled bi t i n the cnfg_mode regi ster.
B i t (7:0)
Holdover offset (7:0)
B i t (7:0)
Holdover offset (15:8)
00000000
00000000
B i t (2:0) Holdover offset (18:16)
B i t 7 i s A uto Holdover A veragi ng enable - default 1. Thi s enables the frequency average to
be taken from 32 samples. One sample taken every 32 seconds, after the frequency has
been confi rmed to be i n-band by the frequency moni tors, gi vi ng a 17 mi nute hi story of the
currently locked to reference source for use i n Holdover.
B i t (6:3) Unused
40
cnfg_freq_li mi t
1X X X X 000
Thi s regi ster holds a 10 bi t unsi gned i nteger representi ng the pull-i n range of the D P LL. It
should be set accordi ng to the accuracy of crystal i mplemented i n the appli cati on, usi ng the
followi ng formula:
Frequency range +/- (ppm) = (cnfg_freq_li mi t x 0.0785)+0.01647 or
cnfg_freq_li mi t = (Frequency range - 0.01647) / 0.0785
D efault value when S RC S W i s left unconnected or ti ed low i s ±9.2 ppm. D efault value when
S RC S W i s hi gh i sthe full range of around ±80 ppm.
41
42
01110110
(S RC S W low)
11111111
(S RC S W hi gh)
Least si gni fi cant byte
(7:2) Unused
(1:0) Most si gni fi cant byte
Revision 2.07/Jan 2001 ã2001 Semtech Corp
X X X X X X 00
(S RC S W low)
X X X X X X 11
(S RC S W hi gh)
31
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ACS8510 SETS
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ADVANCED COMMUNCIATIONS
Addr. Parameter N ame
(H ex)
43
cnfg_i nterrupt_mask
44
D escription
D efault
Value (bin)
Each bi t of thi s 21 bi t regi ster, i f set to zero, wi ll di sable the appropri ate i nterrupt source i n
ei ther the i nterrupt status regi ster or the sts_T4_i nputs regi ster.
11111111
11111111
45
XXX11111
cnfg_freq_di vn
Thi s 14 bi t i nteger i s used as the di vi sor for any i nput appli ed to <I_14>:<I_1> to get the phase
locki ng frequency desi red. Only acti ve for i nputs wi th the D i vN bi t set to ‘ 1’ . Thi s wi ll cause
the i nput frequency to be di vi ded by (N+1) pri or to phase compari son, e.g. program N to:
((i nput freq)/ 8 kHz) -1
The reference_source_frequency bi ts should be set to reflect the closest spot frequency to the
i nput frequency, but must be lower than the i nput frequency.
46
47
cnfg_moni tors
Least-si gni fi cant byte.
00000000
Most-si gni fi cant 6 bi ts.
X X 000000
Thi s 7 bi t regi ster allows global confi gurati on of moni tors and control of phase bui ld out.
Bi ts (1:0) are for confi guri ng frequency moni tors- 00 = off, 01 = 15 ppm, others are reserved
for future use.
Bi t 2 Phase bui ldout en enables phasebui ldout. If di sabled, the D PLL wi ll always lock to 0
degrees.
Bi t 3 Freeze phase bui ldout (when phase bui ldout i s enabled) wi ll effecti vely di sable any future
phase bui ldout events but remai n wi th the current phase offset.
Bi t 4 External protecti on swi tchi ng enables the SrcSwi t pi n to force the locki ng to ei ther i nput 4
or 3.
48
X 0000101*
Bi t 5 Ultra-fast swi tchi ng enables the dpll to rai se an i nacti vi ty alarm on the currently selected
source after mi ssi ng only a few cycles. Thi s wi ll enable very fast swi tchi ng away from the
selected source i n a protecti on type appli cati on. Thi s i s tri ggered by the mai n_ref_fai led
i nterrupt mechani sm.
Bi t 6 Flag reference loss on TD O wi ll enable the value of the mai n_ref_fai led i nterrupt to be
dri ven out of the TD O pi n of the devi ce.
* The default value gi ven i s vali d when SRC SWT pi n i s left unconnected or ti ed low. If
SRC SWT i s ti ed hi gh, the default value i s 15 (hex).
50
51
52
cnfg_acti v_upper_threshold0 Thi s 8 bi t regi ster sets the value i n the leaky bucket that causes the acti vi ty alarm to be rai sed.
cnfg_acti v_lower_threshold0 Thi s 8 bi t regi ster sets the value i n the leaky bucket that causes the acti vi ty alarm to be
cleared.
54
55
56
57
00000100
cnfg_bucket_si ze0
Thi s 8 bi t regi ster sets the maxi mum value that the leaky bucket can reach gi ven an i nacti ve
i nput.
cnfg_decay_rate0
Thi s 2 bi t regi ster controls the leak rate of the leaky bucket. The fi ll-rate of the bucket i s +1 for
every 128 ms i nterval that has experi enced some level of i nacti vi ty. The decay rate i s
programmable i n rati os of the fi ll rate. The rati o can be set to 1:1, 2:1, 4:1, 8:1 by usi ng values
of 00, 01, 10, 11 respecti vely. However, these buckets are not ‘ true’ leaky buckets i n nature.
The bucket stops ‘ leaki ng’ when i t i s bei ng fi lled. Thi s means that the fi ll and decay rates can
be the same (00 = 1:1) wi th the net effect that an acti ve i nput can be recogni sed at the same
rate as an i nacti ve one.
53
cnfg_acti v_upper_threshold1 Thi s 8 bi t regi ster sets the value i n the leaky bucket that causes the acti vi ty alarm to be rai sed.
cnfg_acti v_lower_threshold1 Thi s 8 bi t regi ster sets the value i n the leaky bucket that causes the acti vi ty alarm to be
cleared.
Thi s 8 bi t regi ster sets the maxi mum value that the leaky bucket can reach gi ven an i nacti ve
i nput.
cnfg_decay_rate1
As for regi ster 53(hex) but for bucket 1.
32
00001000
X X X X X X 01
00000110
00000100
cnfg_bucket_si ze1
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00000110
00001000
X X X X X X 01
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Addr. Parameter N ame
(H ex)
58
D escription
D efault
Value (bin)
cnfg_acti v_upper_threshold2 Thi s 8 bi t regi ster sets the value i n the leaky bucket that causes the acti vi ty alarm to be rai sed.
00000110
cnfg_acti v_lower_threshold2
Thi s 8 bi t regi ster sets the value i n the leaky bucket that causes the acti vi ty alarm to be
cleared.
00000100
cnfg_bucket_si ze2
Thi s 8 bi t regi ster sets the maxi mum value that the leaky bucket can reach gi ven an i nacti ve
i nput.
00001000
5B
cnfg_decay_rate2
As for regi ster 53(hex) but for bucket 2.
5C
cnfg_acti v_upper_threshold3 Thi s 8 bi t regi ster sets the value i n the leaky bucket that causes the acti vi ty alarm to be rai sed.
59
5A
5D
5E
5F
X X X X X X 01
00000110
cnfg_acti v_lower_threshold3
Thi s 8 bi t regi ster sets the value i n the leaky bucket that causes the acti vi ty alarm to be
cleared.
00000100
cnfg_bucket_si ze3
Thi s 8 bi t regi ster sets the maxi mum value that the leaky bucket can reach gi ven an i nacti ve
i nput.
00001000
cnfg_decay_rate3
As for regi ster 53(hex) but for bucket 3.
cnfg_uPsel
Thi s 3 bi t regi ster i s used to control the mode of the mi croprocessor i nterface. Thi s wi ll
power-up wi th the value on the µPsel pi ns. Subsequently, the regi ster can be wri tten to put the
mi cro-processor i nterface i nto another mode. Thi s wi ll support booti ng from EPROM and
subsequently communi cati ng vi a another mode. The value on the pi ns can always be read vi a
the cnfg_uPsel_pi ns regi ster. These 3 pi ns can be used as general purpose i nputs for the µP
i f necessary after booti ng.
7F
Selection
Source
of
Input
Reference
Clock
Under normal operation, the input reference
sources are selected automatically by an order
of priority. But, for special circumstances, such
as chip or board testing, the selection may be
forced by configuration.
Automatic operation selects a reference source
based on its pre-defined priority and its current
availability. A table is maintained which lists all
reference sources in the order of priority. This
is initially downloaded into the ACS8510 via
the micro-processor interface by the Network
Manager, and is subsequently modified by the
results of the ongoing quality monitoring. In this
way, when all the defined sources are active
and valid, the source with the highest
programmed priority is selected but, if this
source fails, the next-highest source is selected,
and so on.
Restoration of repaired reference sources is
handled carefully to avoid inadvertent
disturbance of the output clock. The ACS8510
has two modes of operation; Revertive and
Non-Revertive. In Revertive mode, if a reRevision 2.07/Jan 2001 ã2001 Semtech Corp
33
X X X X X X 01
Bi ts(7:3)=
XXXXX
Bi ts(2:0)=
Pi n dependent
validated (or newly validated) source has a
higher priority than the reference source which
is currently selected, a switch over will take
place. Many applications prefer to minimise the
clock switching events and choose NonRevertive mode. In Non-Revertive mode , when
a re-validated (or newly validated) source has a
higher priority then the selected source will be
maintained. The re-validation of the reference
source will be flagged in the sts_sources_valid
register and, if not masked, will generate an
interrupt. Selection of the re-validated source
can only take place under software control the software should briefly enable Revertive
mode to affect a switch-over to the higher
priority source. If the selected source fails under
these conditions the device will still not select
the higher priority source until instructed to do
so by the software, by briefly setting the
Revertive mode bit. When there is a reference
available with higher priority than the selected
reference, there will be NO change of reference
source as long as the Non-Revertive mode
remains on. This is the case even of there are
lower priority references available or the
currently selected reference fails. When the
ONLY valid reference sources that are available
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have a lower priority than the selected
reference, a failure of the selected reference
will always trigger a switch-over regardless of
whether Revertive or Non-revertive mode has
been chosen.
Also, in a Master/Slave redundancy-protection
scheme, the Slave device(s) must follow the
Master device. The alignment of the Master
and Slave devices is part of the protection
mechanism. The availability of each source is
determined by a combination of local and
remote monitoring of each source. Each input
reference source supplied to each ACS8510
device is monitored locally and the results are
made available to other devices.
Forced Control Selection
A configuration register, 'cnfg_ref_selection',
controls both the choice of automatic or forced
selection and the selection itself (when forced
selection is required). The forced selection of
an input reference source occurs when the
'cnfg_ref_selection' variable contains a non-zero
value, the value then representing the input
port required to be selected. This is not the
normal mode of operation, and the
'cnfg_ref_selection' variable is defaulted to the
all-zero value on reset, thereby adopting the
automatic selection of the reference source.
Automatic Control Selection
When an automatic selection is required, the
'cnfg_ref_selection' register must be set to allzero.
The
configuration
registers,
'cnfg_ref_selection_priority', held in the µP port
block, consists of seven, 8 bit registers
organised as one 4 bit register per input
reference port. Each register holds a 4-bit value
which represents the desired priority of that
particular port. Unused ports should be given
the value, '0000' or '1111', in the relevant
register to indicate they are not to be included
in the priority table. On power-up, or following a
reset, the whole of the configuration file will be
defaulted to the values defined by Table 1. The
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34
selection priority values are all relative to each
other, with lower-valued numbers taking higher
priorities. Each reference source should be given
a unique number, the valid values are 1 to 15
(dec). A value of 0 disables the reference
source. However if two or more inputs are given
the same priority number those inputs will be
selected on a first in, first out basis. If the first
of two same priority number sources goes
invalid the second will be switched in. If the
first then becomes valid again, it becomes the
second source on the first in, first out basis,
and there will not be a switch. If a third source
with the same priority number as the other two
becomes valid, it joins the priority list on the
same first in, first out basis. There is no implied
priority based on the channel numbers.
The input port <I_11> is for the connection of
the synchronous clock of the TOUT0 output of
the Master device (or the active-Slave device),
to be used to align the TOUT0 output with the
Master (or active-Slave) device if this device is
acting in a subordinate-Slave or subordinateMaster role.
Clock Quality Monitoring
Clock quality is monitored and used to modify
the priority tables of the local and remote
ACS8510 devices. The following parameters are
monitored:
- Activity (toggling)
- Frequency (This monitoring is only performed when there
is no irregular operation of the clock or loss of clock
condition)
In addition, input ports <I_1> and <I_2> carry
AMI-encoded composite clocks which are
monitored by the AMI-decoder blocks. Loss of
signal is declared by the decoders when either
the signal amplitude falls below 0.3 v or there
is no activity for 1 ms.
Any reference source which suffers a loss-ofwww.semtech.com
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signal, loss-of-activity, loss-of-regularity or clockout-of-band condition will be declared as
unavailable.
Clock quality monitoring is a continuous process
which is used to identify clock problems. There
is a difference in dynamics between the
selected clock and the other reference clocks.
Anomalies occurring on non-selected reference
sources affect only that source's suitability for
selection, whereas anomalies occurring on the
selected clock could have a detrimental impact
on the accuracy of the output clock.
Anomalies, whether affecting signal-purity or
signal frequency, could induce jitter or frequency
offsets in the output clock, leading to
anomalous behaviour. Anomalies on the
selected clock, therefore, have to be detected
as they occur and the phase locked loop must
be temporarily isolated until the clock is once
again pure. The clock monitoring process cannot
be used for this because the high degree of
accuracy required dictates that the process be
slow. To achieve the immediacy required by the
phase locked loop requires an alternative
mechanism. The phase locked loop itself
contains appropriate circuitry, based around the
phase detector, and isolates itself from the
selected reference source as soon as a signal
impurity is detected. It can likewise respond to
frequency offsets outside the permitted range
since these result in saturation of the phase
detector. When the phase locked loop is isolated
from the reference source, it is essentially
operating in a Hold-Over state; this is preferable
to feeding the loop with a standby source, either
temporarily or permanently, since excessive
phase excursions on the output clock are
avoided.
Anomalies detected by the phase detector are
integrated in a leaky bucket accumulator.
Occasional anomalies do not cause the
accumulator to cross the alarm-setting
threshold, so the selected reference source is
retained. Persistent anomalies cause the alarmsetting threshold to be crossed and result in
the selected reference source being rejected.
Activity Monitoring
The ACS8510 has a combined inactivity and
irregularity monitor. The ACS8510 uses a "leaky
bucket" accumulator, which is a digital circuit
which mimics the operation of an analog
integrator, in which input pulses increase the
inactivities/irregularities
reference
source
bucket_size
leaky bucket
response
upper_threshold
lower_threshold
programmable fall slopes
(all programmable)
alarm
Figure 7: Inactivity and irregularity monitoring
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output amplitude but die away over time. Such
integrators are used when alarms have to be
triggered either by fairly regular defect events,
which occur sufficiently close together, or by
defect events which occur in bursts. Events
which are sufficiently spread out should not
trigger the alarm. By adjusting the alarm-setting
threshold, the point at which the alarm is
triggered can be controlled. The point at which
the alarm is cleared depends upon the decay
rate and the alarm-clearing threshold. On the
alarm-setting side, if several events occur close
together, each event adds to the amplitude
and the alarm will be triggered quickly; if events
occur a little more spread out, but still
sufficiently close together to overcome the
decay, the alarm will be triggered eventually. If
events occur at a rate which is not sufficient to
overcome the decay, the alarm will not be
triggered. On the alarm-clearing side, if no defect
events occur for a sufficient time, the amplitude
will decay gradually and the alarm will be cleared
when the amplitude falls below the alarm-
clearing threshold. The ability to decay the
amplitude over time allows the importance of
defect events to be reduced as time passes
by. This means that, in the case of isolated
events, the alarm will not be set, whereas, once
the alarm becomes set, it will be held on until
normal operation has persisted for a suitable
time (but if the operation is still erratic, the
alarm will remain set). See Figure 7.
The "leaky bucket" accumulators are
programmable for size, alarm set & reset
thresholds and decay rate. Each source is
monitored over a 128 ms period. If, within a
128 ms period, an irregularity occurs that is
not deemed to be due to allowable jitter/wander,
then the accumulator is incremented. The
accumulator will continue to increment up to
the point that it reaches the programmed
bucket size. The "fill rate" of the leaky bucket
is, therefore, 8 units/second. The "leak rate"
of the leaky bucket is programmable to be in
multiples of the fill rate (x1, x0.5, x0.25 and
x0.125) to give a programmable leak rate from
Leaky bucket timing
The time taken to raise an inactivity alarm on a reference source that has previously been fully active (leaky
bucket empty) will be:
(cnfg_activ_upper_threshold N)
secs
8
where N is the number of the relevent leaky bucket configuration. If an input is intermittently inactive then
this time can be longer. The default setting of cnfg_activ_upper_threshold is 6, therefore the default time is
0.75 s.
The time taken to cancel the activity alarm on a previously completely inactive reference source is calculated
as:
(cnfg_decay_rate N)
2
x ((cnfg_bucket_size N) - (cnfg_activ_lower_thrshold N))
secs
8
where N is the number of the relevent leaky bucket configuration in each case. The default setting are shown
in the following:
1
2
x (8-4)
= 1.0 s
8
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8 units/sec down to 1 unit/sec. A conflict
between trying to ‘leak’ at the same time as a
‘fill’ is avoided by preventing a ‘leak’ when a
‘fill’ event occurs.
Disqualification of a non-selected reference
source is based on inactivity, or on an out of
band result from the frequency monitors. The
currently selected reference source can be
disqualified for phase, frequency, inactivity or if
the source is outside the DPLL lock range. If
the currently selected reference source is
disqualified, the next highest priority, active
reference source is selected.
Ultra Fast Switching
A reference source is normally disqualified after
the leaky bucket monitor thresholds have been
crossed. An option for a faster disqualification
has been implemented, whereby if register 48H,
bit 5 (Ultra Fast Switching), is set then a loss of
activity of just a few reference clock cycles will
set the ‘no activity alarm’ and cause a
reference switch. This can be chosen to cause
an interrupt to occur instead of or as well as
causing the reference switch.
The sts_interrupts register 05 Hex Bit 15
(main_ref_failed) of the interrupt status register
is used to flag inactivity on the reference that
the device is locked to much faster than the
activity monitors can support. If bit 6 of the
cnfg_monitors register (flag ref loss on TDO) is
set, then the state of this bit is driven onto the
TDO pin of the device.
The flagging of the loss of the main reference
failure on TDO is simply allowing the status of
the sts_interrupt bit 15 to be reflected in the
state of the TDO output pin. The pin will,
therefore remain High until the interrupt is
cleared. This functionality is not enabled by
default so the usual JTAG functions can be
used. When JTAG is normally used straight out
of power-up, then this feature will have no
bearing on the functionality. The TDO flagging
feature will need to be disabled if JTAG is not
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enabled on power-up and the feature has since
been enabled.
When the TDO output from the ACS8510 is
connected to the TDI pin of the next device in
the JTAG scan chain, the implementation should
be such that a logic change caused by the
action of the interrupt on the TDI input should
not effect the operation when JTAG is not
active.
External Protection Switching
Fast external switching between inputs <I_3>
and <I_4> can also be triggered directly from a
dedicated pin (SRCSW). This mode can be
activated either by holding this pin high during
reset, or by writing to bit 4 of register address
48Hex. Once external protection switching is
enabled, then the value of this pin directly
selects either <I_3> (SRCSW high) or <I_4>
(SRCSW low). If this mode is activated at reset
by pulling the SRCSW pin high, then it configures
the default frequency tolerance of <I_3> and
<I_4> to +/- 80 ppm (register address 41Hex
and 42Hex). Any of these registers can be
subsequently set by external software if
required.
When external protection switching is enabled,
the device will operate as a simple switch. All
clock monitoring is disabled and the DPLL will
simply be forced to try to lock on to the
indicated reference source.
Frequency Monitoring
The ACS8510 performs frequency monitoring
to identify reference sources which have drifted
outside the acceptable frequency range of +/16.6 ppm (measured with respect to the output
clock). The sts_reference sources out-of-band
alarm for a particular reference source is raised
when the reference source is outside the
acceptable frequency range. The ACS8510
DPLL has a programmable frequency limit of
+/- 80 ppm. If the range is programmed to be
> 16.6 ppm, the activity monitors should be
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disabled so the input reference source is not
automatically rejected as out of frequency
range.
device cannot achieve lock within 100 seconds,
it reverts to Free-Run mode and another
reference source is selected.
Modes of Operation
Locked mode
The ACS8510 has three primary modes of
operation (Free-Run, Locked and Holdover)
supported by three secondary, temporary
modes (Pre-Locked, Lost_Phase and PreLocked2). These are shown in the State
Transition Diagram, Figure 8.
The Locked mode is used when an input
reference source has been selected and the
PLL has had time to lock. When the Locked
mode is achieved, the output signal is in phase
and locked to the selected input reference
source. The selected input reference source is
determined by the priority table. When the
ACS8510 is in Locked mode, the output
frequency and phase follows that of the
selected input reference source. Variations of
the external crystal frequency have a minimal
effect on the output frequency. Only the
minimum to maximum frequency range is
affected. Note that the term, 'in phase', is not
applied in the conventional sense when the
ACS8510 is used as a frequency translator (e.g.,
when the input frequency is 2.048 MHz and
the output frequency is 19.44 MHz) as the input
and output cycles will be constantly moving past
each other; however, this variation will itself be
cyclical over time unless the input and output
are not locked.
The ACS8510 can operate in Forced or
Automatic control. On reset, the ACS8510
reverts to Automatic Control, where transitions
between states are controlled completely
automatically. Forced Control can be invoked
by configuration, allowing transitions to be
performed under external control. This is not
the normal mode of operation, but is provided
for special occasions such as testing, or where
a high degree of hands-on control is required.
Free-Run mode
The Free-Run mode is typically used following a
power-on-reset or a device reset before
network synchronisation has been achieved. In
the Free-Run mode, the timing and
synchronisation signals generated from the
ACS8510 are based on the Master clock
frequency provided from the external oscillator
and are not synchronised to an input reference
source. The frequency of the output clock is a
fixed multiple of the frequency of the external
oscillator, and the accuracy of the output clock
is equal to the accuracy of the Master clock.
The transition from Free-Run to Pre-locked(1)
occurs when the ACS8510 selects a reference
source.
Pre-Locked(1) mode
The ACS8510 will enter the Locked state in a
maximum of 100 seconds, as defined by GR1244-CORE specification, if the selected
reference source is of good quality. If the
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Lost_Phase mode
Lost_Phase mode is used whenever the
selected reference source suffers most kinds
of anomalous behaviour. Clock generation is
performed in the same way as in the Holdover
mode. If the leaky bucket accumulator
calculates that the anomaly is serious, the
device rejects the reference source and one of
the following transitions takes place:
Go to Pre-Locked(2);
- If a known-good standby source is available.
Go to Hold-Over;
- If no standby sources are available.
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Holdover mode
The Holdover mode is used when the ACS8510
was in Locked mode for long enough to acquire
stable frequency data, but the final selected
reference source has become unavailable and
a replacement has not yet been qualified for
selection.
In Holdover mode, the ACS8510 provides the
timing and synchronisation signals to maintain
the Network Element (NE), but they are not
phase locked to any input reference source.
The timing is based on a stored value of the
frequency ratio obtained during the last Locked
mode period.
The Holdover performance is mainly limited by
what is happening to the TCXO. The ACS8510
has 3 ways of determining Holdover, either;
1. By external frequency setting (cnfg_holdover_offset
register)
important - the stability of the output clock in
Hold-Over is directly related to the stability of
the external oscillator.
Pre-Locked(2) mode
This state is very similar to the Pre-Locked(1)
state. It is entered from the Holdover state
when a reference source has been selected
and applied to the phase locked loop. It is also
entered if the device is operating in revertive
mode and a higher-priority reference source is
restored.
Upon applying a reference source to the phase
locked loop, the ACS8510 will enter the Locked
state in a maximum of 100 seconds, as defined
by GR-1244-CORE specification, if the selected
reference source is of good quality.
If the device cannot achieve lock within 100
seconds, it reverts to Holdover mode and
another reference source is selected.
2. By an internal frequency measuring and averaging
system which averages the last 20 minutes
3. By just using the last frequency (as reported by the
sts_curr_inc_offset register). This value can be read out
of the device and used to build up a longer term average
using an external averaging circuit. This value can then to
readback into the device and used as the Holdover offset
(via cnfg_holdover_offset register).
By default it uses the internal averager. This
means that if the TCXO frequency is varying
due to temperature fluctuations in the room,
then the instantaneous value can be different
from the average value, and then it may be
possible to exceed the 0.05 ppm limit
(depending on how extreme the temperature
flucuations are). It is advantageous to shield
the TCXO to slow down frequency changes due
to drift and external temperature fluctuations.
The frequency accuracy of Holdover mode has
to meet the ITU-T, ETSI and Telcordia
performance requirements. The performance
of the external oscillator clock is critical in this
mode, although only the frequency stability is
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Protection Facility
The ACS8510 supports redundancy protection.
The primary functions of this include:
- Alignment of the priority tables of both Master
and Slave ACS8510 devices so as to align the
selection of reference sources of both Master
and Slave ACS8510 devices.
- Alignment of the phases of the 8 kHz and 2
kHz clocks in both Master and Slave ACS8510
devices to within one cycle of the 77.76 MHz
internal clock.
When two ACS8510 devices are to be used in
a redundancy-protection scheme within an NE,
one will be designated as the Master and the
other as the Slave. It is expected that an NE
will use the T OUT0 output for its internal
operations because the TOUT4 output is intended
to feed an SSU/BITS system. An SSU/BITS will
not be bothered by phase differences between
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signals arriving from different sources because
it typically incorporates line build-out functions
to absorb phase differences on reference
inputs. This means that the phasing of the
composite clocks between two ACS8510
devices do not have to be mutually-aligned. The
same is not true, however, of the TOUT0 output
signals (T01 - T07, Frame clock and Multi-Frame
clock). It is usually important to align the phases
of all equivalent T OUT0 signals generated by
different sources so that switch-over from one
device to another does not affect the internal
operations of the NE. Both ACS8510 devices
will produce the same signals, which will be
routed around the NE to the various consumers
(clock sinks). With the possible exception of a
through-timing mode, the signals from the
Master device will be used by all consumers,
unless the Master device fails, when each
consumer will switch over to the signals
generated by the Slave device.
Switchover to a new TOUT0 clock should be as
hitless as possible. This requires the signals of
both ACS8510 devices to be phase aligned at
each consumer. Phase alignment requires
frequency alignment. To ensure that both
devices can generate output clocks locked to
the same source, both devices are supplied
with the same reference sources on the same
input ports and will have identical priority tables.
Failures of selected reference sources will result
in both ACS8510 devices making the same
updates to their priority tables as availability
information will be updated in both devices.
Although, in principle, the priority tables will be
the same if the same reference sources are
used on the same input port on each device, in
practice, this is only true if the reference
sources actually arrive at each device - failures
of a source seen only by one device and not by
the other, such as could be caused, for example,
by a backplane connector failure, would result
in the priority tables becoming misaligned. It is
thus necessary to force the priority tables to
Revision 2.07/Jan 2001 ã2001 Semtech Corp
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be aligned under normal operating conditions
so that the devices can make the same
decisions - this can be achieved by loading the
availability seen by one device (via the
sts_reference_sources register) into the
cnfg_sts_remote_sources_valid register of the
other device. Another factor which could affect
hit-less switching is the frequency of the local
oscillator clock used by each ACS8510 device:
these clocks are not mutually aligned and,
whilst this has no impact on the frequency of
the output clocks during locked mode, it could
cause the output frequencies to diverge during
Holdover mode if no action were taken to avoid
it. In order to maintain alignment of the output
frequencies of each ACS8510 device even
during Holdover, the Master device's 6.48 MHz
output is fed into the Slave device on its <I_11>
pin, whilst the Multi-Frame Sync (2 kHz) output
is fed to the Sync2k input of the Slave. In this
way, the Slave locks to the master's output
and remains locked whilst the Master moves
between operating states. Only when the
Master fails does the Slave use its own
reference inputs - should the Master have been
in the Holdover state, the Slave device will see
the same lack of reference sources and also
enter the Holdover state. This scheme also
provides a convenient way to phase-align all
TOUT0 output clocks in Master and Slave devices,
and also to detect the failure of the Master
device.
If a Master device fails, the Slave has to take
over responsibility for the generation of the
output clocks, including the 8 kHz and 2 kHz
Frame and Multi-Frame clocks. The Slave device
is also given responsibility for building the priority
table and performing the reference switching
operations. The Slave device, therefore, adopts
a more active role when the Master has failed.
The cnfg_mode register 34 (Hex) Bit 1 contains
the "Master/Slave" control bit to determine the
designation of the device.
To restore redundancy protection, the Master
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has to be repaired and replaced. When this
occurs, the new Master cannot immediately
adopt its normal role because it must not cause
phase hits on the output clocks. It has,
therefore, to adopt a subordinate role to the
active Slave device, at least until such time as
it has acquired alignment to the 8 kHz and 2
kHz frame and Multi-Frame clocks and the
priority table of the Slave device; then, when a
switch-back (restoration) is ordered, the Master
can take over responsibility. These activities, in
Master or Slave operation, are detailed in Table
8.
Alignment of priority tables in Master and Slave
ACS8510
Correct protection will only be achieved by
connecting individual reference sources to the
same input ports on each device and priority
tables in each device must be aligned to each
other.
The Master device must take account of the
availability of each reference source seen by
another device and a Slave device must adopt
the same order of priority as the Master device
(except that the slave's highest-priority input is
<I_11>). Both devices monitor the reference
sources and decide the availability of each
source; if the failure of a reference source is
seen by both devices, they will both update
their priority tables - however, if the reference
source failure is only seen by one device and
not by both, the priority tables could get out of
step: this could be catastrophic if it resulted in
two devices choosing different reference
sources since any slight differences in frequency
variation over time (e.g. wander) would mis-align
the phase of the 8 kHz Frame and 2 kHz MultiFrame clocks produced by the individual
devices, resulting in phase hits on switch-over.
It is therefore important that the same priority
table be built by each device, using the
reference source availability seen by each
device.
Revision 2.07/Jan 2001 ã2001 Semtech Corp
41
The monitoring of the reference sources
performed by a Master ACS8510 results in a
list of available sources being placed in a
sts_valid_sources register. This information is
used within the device as one of the masks
used to build the device's priority table. The
information is passed to the Slave device and
used
to
configure
the
cnfg_sts_remote_sources_valid register so that
it can use it as a mask in building its own priority
tables. The information is passed between
devices using the microprocessor port.
Alignment of the selection of reference sources
for T OUT4 generation in the Master and Slave
ACS8510
As stated previously, there is no need to align
the phases of the TOUT4 outputs in Master and
Slave devices. There is a need, however, to
ensure that all devices select the same
reference source. But, since there is no
Holdover mode required for the generation of
the TOUT4 clock, and every reference source is
continuously monitored within each device, it is
permissible to rely on external intelligence to
command a switch-over to an alternative source
should the selected one fail. The time delay
involved in detecting the failure, indicating it to
the outside and selecting a new source, will
result only in the SSU/BITS entering its HoldOver mode for a short time.
Alignment of the phases of the 8kHz and 2kHz
clocks in both Master and Slave ACS8510
In addition to aligning the edges of the TOUT0
outputs of Master and Slave devices, it is
necessary to align the edges of the Frame and
Multi-Frame clocks. If this is not performed,
frame alignment may be lost in distant
equipment on switch-over to an alternative
device, resulting in anomalous network
operation of a very serious nature.
In accordance with the alignment mechanism
used with the main TOUT0 clock (described in the
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opening paragraphs of this section), whereby
the 6.48 MHz output of the Master device is
supplied to the Slave device, the alignment of
both the 8 kHz and 2 kHz clocks is
accomplished (they are already synchronous to
the TOUT0 clocks) by feeding the 2 kHz clock of
the Master device into the Slave device. The
Multi-Frame Sync clock output of the Slave
device is also fed to the Sync2K input of the
Master device. Alignment of the Multi-Frame
Sync input occurs only when cnfg_mode
register, bit 3, address 34Hex External 2 kHz
Sync Enable is set to 1.
JTAG
The JTAG connections on the ACS8510 allow a
full boundary scan to be made. The JTAG
implementation is fully compliant to IEEE
1149.1, with the following minor exceptions,
and the user should refer to the standard for
further information.
1. The output boundary scan cells do not capture data
from the core, and so do not support EXTEST. However
this does not affect board testing.
2. In common with some other manufacturers, pin TRST
is internally pulled low to disable JTAG by default. The
standard is to pull high. The polarity of TRST is as the
standard: TRST high to enable JTAG boundary scan mode,
TRST low for normal operation.
3. The device does not support the optional tri-state
capability (HIGHZ). This will be supported on the next
revision of the device.
The JTAG timing diagram is shown on page 53.
PORB
The Power On Reset (PORB) pin resets the
device if forced Low for a power-on-reset to be
initiated. The reset is asynchronous, the
minimum Low pulse width is 5 ns. Reset is
needed to initialize all of the register values to
their defaults. Asserting Reset (POR) is required
at power on, and may be re-asserted at any
time to restore defaults. This is implemented
most simplistically by an external capacitor to
GND along with the internal pull-up resistor.
The ACS8510 is held in a reset state for 250
ms after the PORB pin has been pulled High. In
normal operation PORB should be held High.
Notes to Table 8
Note 1: Both ACS8510 must build a common priority table so that the Slave ACS8510 can select the same input reference
source as the Master ACS8510 if the Master fails (when the Master is OK, the Slave locks to the Master's output).
Note 2: Slave ACS8510 uses common priority table, built before Master ACS8510 failed - priority table can be modified as
status of the input reference sources changes
Note 3: Slave ACS8510 outputs must remain in phase with those of Master ACS8510
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TCXO
VDD
MASTER
6.48 MHz
MSTSLVB
T 01
SEC1
I_1
T 02
SEC2
I_2
T 03
SEC3
I_3
.
.
.
T 04
.
.
.
I_11
.
.
.
I_14
T 07
.
.
.
T 011
SEC14
MFr Sync
SYNC2K
6.48 MHz
TCXO
SLAVE
GND
MSTSLVB
T 01
SEC1
I_1
T 02
SEC2
I_2
T 03
SEC3
I_3
.
.
.
T 04
.
.
.
I_11
.
.
.
I_14
T 07
.
.
.
T 011
SEC13
MFr Sync
SYNC2K
SYNC2K_EN=1
34Bit3
R e f _ so u r ce s t o
M ast e r A C S 8510
R e f _ so u r ce s t o
S l av e A C S 8510
M ast e r A C S 8510
s t at u s
S l av e A C S 8510
s t at u s
M ast e r A C S 8510
S l av e A C S 8510
ou t p u t
Com m en t s
A ll good
A ll good
Good
Good
Locked (ref_x)
Locked to master
N ote 1
Some failed
Some oth ers failed
Good
Good
Locked (ref_y)
Locked to master
N ote 1
Good
Good
Good
Failed
Locked (ref_x)
Dead
Good
Good
Failed
Good
Dead
Locked (ref_x)
Good
Good
Failed
Failed
Dead
Dead
Failed
Failed
Failed
Good
Hold over
Locked to master
Failed
Failed
Good
Failed
Hold over
Dead
Failed
Failed
Failed
Good
Dead
Hold over
Failed
Failed
Failed
Failed
Dead
Dead
N ote 2
N ote 3
N ote 4
Table 8: Master-Slave ACS8510 Relationship
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(1)Reset
free-run
select ref
(state 001)
(2) all refs evaluated
&
at least one ref valid
(3) no valid standby ref
&
(main ref invalid
or out of lock >100s)
Reference sources are flagged as ’valid’ when
active, ’in-band’ and have no phase alarm set.
(4) valid standby ref
&
[ main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock >100s]
pre-locked
w ait for up to 100s
(state 110)
(5) selected ref
phase locked
All sources are continuously checked for
activity and frequency.
Only the main source is checked for phase.
A phase lock alarm is only raised on a
reference when that reference has lost phase
whilst being used as the main reference. The
micro-processor can reset the phase lock
alarm.
A source is considered to have phase locked
when it has b een continuously in phase lock
for between 1 and 2 seconds
locked
keep ref
(state 100)
(10) selected source phase
locked
(9) valid standby ref
&
[ main ref invalid or
(higher-priority ref valid
& in revertive mode) ]
pre-locked2
w ait for up to 100s
(state 101)
(12) valid standby ref
&
(main ref invalid
or out of lock >100s)
(8) phase
regained within
100s
(6) no valid standby ref
&
main ref invalid
(7) phase lost
on main ref
Lost phase
w ait for up to 100s
(state 111)
(11) no valid standby ref
&
(main ref invalid
or out of lock >100s)
holdover
select ref
(state 010)
(13) no valid standby ref
&
(main ref invalid
or out of lock >100s)
(15) valid standby ref
&
[ main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock >100s]
(14) all refs evaluated
&
at least one ref valid
Figure 8: Automatic Mode Control State Diagram.
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Electrical Specification
Important Note: The "Absolute Maximum Ratings" are stress ratings only, and functional operation
of the device at conditions other than those indicated in the "Operating Conditions" sections of
this specification are not implied. Exposure to the absolute maximum ratings for an extended
period may reduce the reliability or useful lifetime of the product.
ABSOLUTE MAXIMUM RATINGS
PA RA MET ER
SYM B OL
MIN
MA X
U N IT S
Sup p ly Voltage
V DD, V D+, V A1+,V A2+
V DD
-0.5
3.6
V
Inp ut Voltage
(non-sup p ly p ins)
V in
-
5.5
V
Outp ut Voltage
(non-sup p ly p ins)
Vout
-
5.5
V
TA
-40
85
°C
Tstor
-50
150
°C
A mb ient Op erating Temp erature
Range
Storage Temp erature
OPERATING CONDITIONS
PA RA MET ER
SYM B OL
MIN
T YP
MA X
U N IT S
Pow er Sup p ly (d c voltage)
V DD, V D+,VA 1+, VA 2+, VA MI+,
V DD_DIFF
V DD
3.0
3.3
3.6
V
Pow er Sup p ly (d c voltage)
V DD5
V DD5
3.0
3.3/5.0
5.5
V
A mb ient temp erature Range
TA
-40
-
85
°C
Sup p ly current
IDD
-
110
200
mA
Total p ow er d issip ation
PTOT
-
360
720
mW
(Typ ical - one 19 MHz outp ut)
DC CHARACTERISTICS: TTL Input pad.
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V in High
V ih
2.0
-
-
V
Vin Low
V il
-
-
0.8
V
Inp ut current
Ii n
-
-
10
µA
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DC CHARACTERISTICS: TTL Input pad with internal pull-up.
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V in High
V ih
2.0
-
-
V
Vin Low
V il
-
-
0.8
V
Pull-up resistor
PU
30
-
80
kW
Inp ut current
Ii n
-
-
120
µA
DC CHARACTERISTICS: TTL Input pad with internal pull-down.
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V in High
V ih
2.0
-
-
V
Vin Low
V il
-
-
0.8
V
Pull-ud ow n resistor
PD
30
-
80
kW
Inp ut current
Ii n
-
-
120
µA
DC CHARACTERISTICS: TTL Output pad.
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
Vout Low
Iol = 4mA
Vol
0
-
0.4
V
Vout High
Ioh = 4mA
Voh
2.4
-
Drive current
ID
-
-
Revision 2.07/Jan 2001 ã2001 Semtech Corp
46
V
4
mA
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DC CHARACTERISTICS: PECL Input/Output pad.
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V ILPECL
V DD-2.5
-
V DD-0.5
V
Differential inp uts (N ote 1)
V IHPECL
V DD-2.4
-
V DD-0.4
V
Inp ut Differential voltage
V IDPECL
0.1
-
1.4
V
V ILPECL_S
V DD-2.4
-
V DD-1.5
V
V IHPECL_S
V DD-1.3
-
V DD-0.5
V
IIHPECL
-10
-
+10
µA
IILPECL
-10
-
+10
µA
V OLPECL
V DD-2.10
-
V DD-1.62
V
V OHPECL
V DD-1.25
-
V DD-0.88
V
V ODPECL
580
-
900
mV
PECL Inp ut Low voltage
Differential inp uts (N ote 1)
PECL Inp ut High voltage
PECL Inp ut Low voltage
Single end ed inp ut (N ote 2)
PECL Inp ut High voltage
Single end ed inp ut (N ote 2)
Inp ut High current
Inp ut d ifferential voltage
V ID = 1.4v
Inp ut Low current
Inp ut d ifferential voltage
V ID = 1.4v
PECL Outp ut Low voltage
(N ote 3)
PECL Outp ut High voltage
(N ote 3)
PECL Outp ut Differential voltage
(N ote 1)
Notes:
Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs
tied to VDD and GND respectively.
Note 1. Assuming a differential input voltage of at least 100 mV.
Note 2. Unused differential input terminated to VDD-1.4v.
Note 3. With 50W load on each pin to VDD-2v. i.e. 82W to GND and 130W to VDD.
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V DD
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
ZO=50Ω
V DD
130R
ZO=50Ω
I5POS
ZO=50Ω
130R
82R
130R
T06POS
ZO=50Ω
I5NEG
130R
82R
T06NEG
82R
82R
GND
GND
V DD
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
ZO=50Ω
ZO=50Ω
V DD
130R
ZO=50Ω
I6POS
T07POS
I6NEG
T07NEG
130R
82R
19.44, 38.88, 155.52,
311.04 MHz & DIG1
ZO=50Ω
130R
130R
82R
82R
19.44, 51.84, 77.76,
155.52 MHz
82R
GND
GND
Recommended line termination for PECL Input/Output ports for VDD = 3.3V
DC CHARACTERISTICS: LVDS Input/Output pad.
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V VRLVDS
0
-
2.40
V
VDITH
-100
-
+100
mV
VIDLVDS
0.1
-
1.4
V
R T E RM
95
100
105
W
V OHLVDS
-
-
1.585
V
V OLLVDS
0.885
-
-
V
V ODLVDS
250
-
450
mV
V DOSLVDS
-
-
25
mV
V OSLVDS
1.125
-
1.275
V
LV DS Inp ut voltage range
Differential inp ut voltage = 100 mV
LV DS Differential inp ut th resh old
LV DS Inp ut Differential voltage
LV DS Inp ut termination resistance
Must b e p laced externally across th e
LV DS+/- inp ut p ins of A CS8510.
Resistor sh ould b e 100W w ith 5%
tolerance
LV DS Outp ut h igh voltage
(N ote 1)
LV DS Outp ut low voltage
(N ote 1)
LV DS Differential outp ut voltage
(N ote 1)
LV DS Ch arge in magnitud e of
d ifferential outp ut voltage for
comp limentary states
(N ote 1)
LV DS outp ut offset voltage
Temp erature = 25°C
(N ote 1)
Note 1. With 100W load between the differential outputs.
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ZO=50Ω
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
ZO=50Ω
ZO=50Ω
I5POS
T06POS
I5NEG
T06NEG
I6POS
T07POS
I6NEG
T07NEG
100R
ZO=50Ω
ZO=50Ω
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
ZO=50Ω
100R
19.44, 38.88, 155.52,
311.04 MHz & DIG1
ZO=50Ω
100R
ZO=50Ω
100R
19.44, 51.84, 77.76,
155.52 MHz
Recommended line termination for LVDS Input/Output ports
DC CHARACTERISTICS: AMI Input/Output pad.
Across operating conditions, unless otherwise stated
The Alternate Mark Inversion (AMI) signal is DC balanced and consists of positive and negative
pulses with a peak to peak voltage of 2.0 +/- 0.2V.
The electrical specifications are taken from option a) of Table 2/G.703 - Digital 64kbit/s centralized
clock interface, from ITU G.703.
PA R A M E T E R
T IMIN G
N ominally rectangular, w ith rise
and fall times < 1µ s
Pulse sh ap e
N ominal test load imp ed ence
110 Oh ms
Peak voltage of a "mark" (p ulse)
1.0 +/- 0.1V
Peak value of a "sp ace"
0.0 +/- 0.1V
N ominal p ulse w id th
7.8µ s
The electrical characteristics of 64kbits/s interface are as follows;
Nominal bit rate: 64kbit/s. The tolerance is determined by the network clock stability.
There should be a symmetrical pair carrying the composite timing signal (64kHz and 8kHz). The
use of transformers is recommended.
Over-voltage protection requirement; refer to Recommendation K.41.
Code conversion rules;
The data signals are coded in AMI code with 100% duty cycle. The composite clock timing signals
convey the 64kHz bit-timing information using AMI coding with a 50% to 70% duty ratio and the
8kHz octet phase information by introducing violations in the code rule. The structure of the
signals and voltage levels are shown in Figure 9 and Figure 10.
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15.6us
7.8us
+1.0VIH
1V
2Vp-p
0VIM
1V
-1.0VIL
Figure 9: Signal structure of 64 kHz/8 kHz central clock interface after suitable input/output transformer (also
see Figure 6/G.703).
15.6us
Signal structure of 64 kHz/
8 kHz central clock interface
after suitable transformer.
7.8us
+VDD
15.6us
7.8us
+1.0VIH
0V
I_1
1V
2Vp-p
TO8POS
C1
0VIM
C2
15.6us
-1.0VIL
1V
I_2
TO8NEG
7.8us
+VDD
C1
0V
Figure 10: AMI input and output signal levels.
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AMI input
signal
Turns
ratio
1:1
<I_1>
C1
C2
AMI input
signal
<I_2>
AMI output signal
to external devices
TO8POS
R load
TO8NEG
C3
GND
C1
NOTE: For 1:1 turn ratio, a 3:1 potential
divider R load is required to give AMI
output with 1 V pp for positive and
negative pulses.
Recommended line termination for AMI Input/Output ports
The AMI inputs <I_1> and <I_2> should be connected to the external AMI clock source by 470 nF coupling
capacitor C1.
The AMI differential output O8POS/O8NEG should be coupled to a line transformer with a turns ration of 3:1.
Components C2 = 470 pF and C3 = 2 nF. If a transformer with a turns ratio of 1:1 is used, a 3:1 ratio potential
divider Rload must be used to achieve the required 1 V pp voltage level for the positive and negative pulses.
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DC CHARACTERISTICS: Output Jitter Generation
Across operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8MHz
TCXO on ICT Flexacom + 10MHz reference from Wavetek 905.
Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m e asu r e m e n t o n A C S 8510
R ev 2
G813 for 155.52 MHz op tion 1
500 Hz to 1.3 MHz
UIpp = 0.5
0.058 (N ote 2)
G813 for 155.52 MHz op tion 1
65 kHz to 1.3 MHz
UIpp = 0.1
0.048 (N ote 3)
0.048 (N ote 2)
0.053 (N ote 4)
0.053 (N ote 5)
0.058 (N ote 6)
0.053 (N ote 7)
G813 for 155.52 MHz op tion 2
12 kHz to 1.3 MHz
UIpp = 0.1
0.053 (N ote 2)
0.058 (N ote 3)
0.057 (N ote 8)
0.055 (N ote 9)
0.057 (N ote 10)
0.057 (N ote 11)
0.057 (N ote 12)
0.053 (N ote 13)
G813 & G812 for 2.048 MHz
op tion 1
20 Hz to 100 kHz
UIpp = 0.05
0.046 (N ote 14)
Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m e asu r e m e n t o n A C S 8510
R ev 2
G812 for 1.544 MHz
10 Hz to 40 kHz
UIpp = 0.05
0.036 (N ote 14)
G812 for 155.52 MHz electrical
500 Hz to 1.3 MHz
UIpp = 0.5
0.058 (N ote 15)
G812 for 2.048 MHz electrical
65 kHz to 1.3 MHz
U Ip p =
0.075
0.048 (N ote 15)
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Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m e asu r e m e n t o n A C S 8510
R ev 2
ETS-300-462-3 for 2.048 MHz
SEC
20 Hz to 100 kHz
UIpp = 0.5
0.046 (N ote 14)
ETS-300-462-3 for 2.048 MHz
SEC
(Filter sp ec 49 Hz to 100 kHz)
20 Hz to 100 kHz
UIpp = 0.2
0.046 (N ote 14)
ETS-300-462-3 for 2.048 MHz
SSU
20 Hz to 100 kHz
UIpp = 0.05
0.046 (N ote 14)
ETS-300-462-3 for 155.52 MHz
500 Hz to 1.3 MHz
UIpp = 0.5
0.058 (N ote 15)
ETS-300-462-3 for 155.52 MHz
65 kHz to 1.3 MHz
UIpp = 0.1
0.048 (N ote 15)
Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m easu r em en t on A C S 8510
R ev 2
GR-253-CORE net i/f, 51.84
MHz
100 Hz to 400 kHz
UIpp = 1.5
0.022 (N ote 15)
GR-253-CORE net i/f, 51.84
MHz
(Filter sp ec 20 kHz to 400 kHz)
18 kHz to 400 kHz
UIpp = 0.15
0.019 (N ote 15)
GR-253-CORE net i/f, 155.52
MHz
500 Hz to 1.3 MHz
UIpp = 1.5
0.058 (N ote 15)
GR-253-CORE net i/f, 155.52
MHz
65 kHz to 1.3 MHz
UIpp = 0.15
0.048 (N ote 15)
UIpp = 0.1
0.057 (N ote 15)
UIrms = 0.01
0.006 (N ote 15)
UIpp = 0.1
0.017 (N ote 15)
UIrms = 0.01
0.003 (N ote 15)
UIpp = 0.1
0.036 (N ote 14)
UIrms = 0.01
0.0055 (N ote 14)
GR-253-CORE cat II elect i/f,
155.52 MHz
12 kHz to 400 kHz
GR-253-CORE cat II elect i/f,
51.84 MHz
12 kHz to 1.3 MHz
GR-253-CORE DS1 i/f, 1.544
MHz
10 Hz to 40 kHz
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Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m e asu r e m e n t o n A C S 8510
R ev 2
AT&T 62411 for 1.544 MHz
(Filter sp ec 10 Hz to 8 kHz)
10 Hz to 40 kHz
UIrms = 0.02
0.0055 (N ote 14)
AT&T 62411 for 1.544 MHz
10 Hz to 40 kHz
UIrms =
0.025
0.0055 (N ote 14)
AT&T 62411 for 1.544 MHz
10 Hz to 40 kHz
UIrms =
0.025
0.0055 (N ote 14)
AT&T 62411 for 1.544 MHz
Broad b and
UIrms = 0.05
0.0055 (N ote 14)
Te s t d e f i n i t i o n
F i l t e r u se d
U I sp ec
U I m easu r em en t on A C S 8510
R ev 2
G-742 for 2.048 MHz
DC to 100 kHz
UIpp = 0.25
0.047 (N ote 14)
G-742 for 2.048 MHz
(Filter sp ec 18 kHz to 100 kHz)
20 Hz to 100 kHz
UIpp = 0.05
0.046 (N ote 14)
G-742 for 2.048 MHz
20 Hz to 100 kHz
UIpp = 0.05
0.046 (N ote 14)
Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m easu r em en t on A C S 8510
R ev 2
TR-N WT-000499 & G824 for
1.544 MHz
10 Hz to 40 kHz
UIpp = 5.0
0.036 (N ote 14)
TR-N WT-000499 & G824 for
1.544 MHz
(Filter sp ec 8 kHz to 40 kHz)
10 Hz to 40 kHz
UIpp = 0.1
0.036 (N ote 14)
Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m e asu r e m e n t o n A C S 8510
R ev 2
GR-1244-CORE for 1.544 MHz
>10 Hz
UIpp = 0.05
0.036 (N ote 14)
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Notes for the output jitter generation tables
Note 1.
Filter used is that defined by test definition unless otherwise stated
Note 2.
5 Hz bandwidth, 19.44 MHz direct lock
Note 3.
5 Hz bandwidth, 8 kHz lock
Note 4.
20 Hz bandwidth, 19.44 MHz direct lock
Note 5.
20 Hz bandwidth, 8 kHz lock
Note 6.
10 Hz bandwidth, 19.44 MHz direct lock
Note 7.
10 Hz bandwidth, 8 kHz lock
Note 8.
2.5 Hz bandwidth, 19.44 MHz direct lock
Note 9.
2.5 Hz bandwidth, 8 kHz lock
Note 10.
1.2 Hz bandwidth, 19.44 MHz direct lock
Note 11.
1.2 Hz bandwidth, 8 kHz lock
Note 12.
0.6 Hz bandwidth, 19.44 MHz direct lock
Note 13.
0.6 Hz bandwidth, 8 kHz lock
Note 14.
5 Hz bandwidth, 8 kHz lock, 2.048 MHz input
Note 15.
5 Hz bandwidth, 8 kHz lock, 19.44 MHz input
JTAG Timing
t CYC
TCK
t S UR
t HT
TM S
TDI
t D OD
TDO
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
Cycle time
tCYC
50
-
-
ns
TMS/TDI to TCK rising edge
t i me
tSUR
3
-
-
ns
TCK rising to TMS/TDI hold
t i me
tHT
23
-
-
ns
TCK falling to TDO valid
tDOD
-
-
5
ns
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Microprocessor interface timing
MOTOROLA Mode
In MOTOROLA mode, the device is configured to interface with a microprocessor using a 680x0
type bus. The following figures show the timing diagrams of write and read accesses for this
mode.
t pw1
CSB
t su2
WRB
t h2
X
X
t h1
t su1
A
X
address
X
t d1
AD
t d3
Z
t d2
RDY
(DTACK)
Z
data
t pw2
t h3
t d4
Z
Z
S y m b ol
P ar am e t e r
MIN
T YP
MA X
tsu1
Setup A valid to CSBfalling edge
0 ns
-
-
tsu2
Setup WRB valid to CSBfalling edge
0 ns
-
-
td 1
Delay CSBfalling edge to AD valid
-
-
177 ns
td 2
Delay CSBfalling edge to DTACKrising edge
-
-
13 ns
td 3
Delay CSBrising edge to AD high-Z
-
-
0 ns
td 4
Delay CSBrising edge to RDY high-Z
-
-
7 ns
tp w 1
CSB low time
485 ns(1)
-
-
tp w 2
DTACK high time
310 ns
-
472 ns
th 1
Hold A valid after CSBrising edge
3 ns
-
-
th 2
Hold WRB high after CSBrising edge
0 ns
-
-
th 3
Hold CSB low after DTACKfalling edge
0 ns
-
-
tp
Time b etw een consecutive accesses (CSBrising edge to CSBfalling edge)
320 ns
-
-
Read access timing in MOTOROLA Mode.
Note 1: Timing with RDY. If RDY not used, tpw1 becomes 178 ns.
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t pw1
CSB
t su2
WRB
t h2
X
X
t h1
t su1
A
address
X
X
t h4
t su3
AD
X
data
t d2
RDY
(DTACK)
t pw2
X
t h3
t d4
Z
Z
S y m b ol
P ar am e t e r
MIN
T YP
MA X
tsu1
Setup A valid to CSBfalling edge
0 ns
-
-
tsu2
Setup WRB valid to CSBfalling edge
0 ns
-
-
tsu3
Setup AD valid b efore CSBrising edge
3 ns
-
-
td 2
Delay CSBfalling edge to DTACKrising edge
-
-
13 ns
td 4
Delay CSBrising edge to RDY high-Z
-
-
7 ns
tp w 1
CSB low time
485 ns(1)
-
-
tp w 2
DTACK high time
310 ns
-
472 ns
th 1
Hold A valid after CSBrising edge
3 ns
-
-
th 2
Hold WRB low after CSBrising edge
0 ns
-
-
th 3
Hold CSB low after DTACKfalling edge
0 ns
-
-
th 4
Hold AD valid after CSBrising edge
4 ns
tp
Time b etw een consecutive accesses (CSBrising edge to CSBfalling edge)
-
-
320 ns
Write access timing in MOTOROLA Mode.
Note 1: Timing with RDY. If RDY not used, tpw1 becomes 178 ns.
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INTEL Mode
In INTEL mode, the device is configured to interface with a microprocessor using a 80x86 type bus. The following
figures show the timing diagrams of write and read accesses for this mode.
CSB
WRB
t su2
t pw 1
t h2
RDB
t su1
t h1
A
a d dre ss
t d4
t d1
AD
Z
t d2
RDY
tsu2
t d3
t pw2
t h3
t d5
Z
Z
S y m b ol
tsu1
Z
d ata
P ar am e t e r
Setup A valid to CSBfalling edge
Setup CSBfalling edge to RDBfalling edge
MIN
T YP
MA X
0 ns
-
-
0 ns
-
-
td 1
Delay RDBfalling edge to A D valid
-
-
177 ns
td 2
Delay CSBfalling edge to RDY active
-
-
13 ns
td 3
Delay RDBrising edge to RDYfalling edge
-
-
14 ns
td 4
Delay RDBrising edge to A D h igh -Z
-
-
10 ns
td 5
Delay CSBrising edge to RDY h igh -Z
tp w 1
RDB low time
486 ns(1)
-
-
tp w 2
RDY low time
310 ns
-
472 ns
th 1
Hold A valid after RDBrising edge
0 ns
-
-
th 2
Hold CSB low after RDBrising edge
0 ns
-
-
th 3
Hold RDB low after RDYrising edge
0 ns
-
-
tp
Time b etw een consecutive accesses (RDBrising edge to RDBfalling edge , or
RDBrising edge to WRBfalling edge)
320 ns
-
-
9 ns
Read access timing in INTEL Mode.
Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns.
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CSB
t su2
t pw1
t h2
WRB
RDB
t su1
t h1
A
address
t su3
AD
data
t d2
RDY
tsu2
t d3
t pw2
t h3
t d5
Z
Sy m b ol
tsu1
t h4
Z
P ar am e t e r
Setup A valid to CSBfalling edge
Setup CSBfalling edge to WRBfalling edge
MIN
T YP
MA X
0 ns
-
-
0 ns
-
-
tsu3
Setup A D valid to WRBrising edge
3 ns
-
-
td 2
Delay CSBfalling edge to RDY active
-
-
13 ns
td 3
Delay WRBfalling edge to RDYfalling edge
-
-
14 ns
td 5
Delay CSBrising edge to RDY h igh -Z
tp w 1
WRB low time
486 ns(1)
-
-
tp w 2
RDY low time
310 ns
-
472 ns
th 1
Hold A valid after WRBrising edge
170 ns(2)
-
-
th 2
Hold CSB low after WRBrising edge
0 ns
-
-
th 3
Hold WRB low after RDYrising edge
0 ns
-
-
th 4
Hold A D valid after WRBrising edge
4 ns
tp
Time b etw een consecutive accesses (WRBrising edge to WRBfalling edge , or
WRBrising edge to RDBfalling edge)
-
-
9 ns
320 ns
Write access timing in INTEL Mode.
Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns.
Note 2: Timing if th2 is greater than 170 ns, otherwise 5 ns after CSB rising edge.
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MULTIPLEXED Mode
In MULTIPLEXED mode, the device is configured to interface with a microprocessor using a multiplexed address/
data bus. The following figures show the timing diagrams of write and read accesses for this mode.
t
t
pw 3
p1
ALE
t
t
su1
h1
CSB
t
su2
WRB
t
t
pw 1
h2
RDB
t
a d d re s s
AD
RDY
t
d2
d3
t
X
t
pw 2
t
h3
Z
d5
Z
S y m b ol
tsu1
d4
d a ta
X
t
t
d1
P ar am e t e r
Setup A D ad d ress valid to A LEfalling edge
MIN
T YP
MA X
2 ns
-
-
tsu2
Setup CSBfalling edge to RDBfalling edge
0 ns
-
-
td 1
Delay RDBfalling edge to A D d ata valid
-
-
177 ns
td 2
Delay CSBfalling edge to RDY active
-
-
13 ns
td 3
Delay RDBfalling edge to RDYfalling edge
-
-
15 ns
td 4
Delay RDBrising edge to A D d ata h igh -Z
-
-
9 ns
td 5
Delay CSBrising edge to RDY h igh -Z
-
-
10 ns
tp w 1
RDB low time
-
-
tp w 2
RDY low time
310 ns
-
472 ns
tp w 3
A LE h i gh t i me
2 ns
th 1
Hold A D ad d ress valid after A LEfalling edge
3 ns
-
-
th 2
Hold CSB low after RDBrising edge
0 ns
-
-
th 3
Hold RDB low after RDYrising edge
0 ns
-
-
tp 1
Time b etw een A LEfalling edge and RDBfalling edge
0 ns
-
-
tp 2
Time b etw een consecutive accesses (RDBrising edge to A LErising edge)
320 ns
-
-
487 ns
(1)
Read access timing in MULTIPLEXED Mode.
Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns.
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t
t
pw 3
p1
ALE
t
t
su1
h1
CSB
t
t
su 2
t
pw 1
h2
W RB
RDB
t
a d d re s s
AD
RDY
Sy m b ol
tsu1
h4
d a ta
X
t
t
su3
t
d2
d3
t
X
t
pw 2
t
h3
Z
d5
Z
P ar am e t e r
Setup A D ad d ress valid to A LEfalling edge
MIN
T YP
MA X
2 ns
-
-
tsu2
Setup CSBfalling edge to WRBfalling edge
0 ns
-
-
tsu3
Setup A D d ata valid to WRBrising edge
3 ns
-
-
td 2
Delay CSBfalling edge to RDY active
-
-
13 ns
td 3
Delay WRBfalling edge to RDYfalling edge
-
-
15 ns
td 5
Delay CSBrising edge to RDY h igh -Z
tp w 1
WRB low time
487 ns(1)
-
-
tp w 2
RDY low time
310 ns
-
472 ns
tp w 3
A LE h i gh t i me
2 ns
-
-
th 1
Hold A D ad d ress valid after A LEfalling edge
3 ns
-
-
th 2
Hold CSB low after WRBrising edge
0 ns
-
-
th 3
Hold WRB low after RDYrising edge
0 ns
-
-
th 4
A D d ata h old valid after WRBrising edge
4 ns
tp 1
Time b etw een A LEfalling edge and WRBfalling edge
0 ns
-
-
tp 2
Time b etw een consecutive accesses (WRBrising edge to A LErising edge)
320 ns
-
-
9 ns
Write access timing in MULTIPLEXED Mode.
Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns.
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SERIAL Mode
In SERIAL mode, the device is configured to interface with a serial microprocessor bus. The following figures
show the timing diagrams of write and read accesses for this mode.
During read access the output data SDO (AD(0)) is clocked out on the rising edge of SCLK (ALE) when the active
edge selection control bit CLKE (A(1)) is 0 and on the falling edge when CLKE = 1.
Address, read/write control bit and write data are always clocked into the interface on the rising edge of SCLK.
Both input data SDI and clock SCLK are oversampled, filtered and synchronized to the 6MHz internal clock.
The serial interface clock (SCLK) is not required to run between accesses (i.e., when CSB = 1).
CLKE = 0; SDO data is clocked out on the rising edge of SCLK
CSB
t su2
t h2
t pw2
ALE=SCLK
A(0)=SDI
t pw1
t h1
t su1
_
R/W
A0
A1
A2
A3
A4
A5
A6
t d1
D0
AD(0)=SDO
t d2
D1
D2
D3
D4
D5
D6
D7
CLKE = 1; SDO data is clocked out on the falling edge of SCLK
CSB
t h2
ALE=SCLK
A(0)=SDI
_
R/W
A0
A1
A2
A3
A4
A5
A6
t d2
t d1
D0
AD(0)=SDO
D1
D2
D3
D4
D5
D6
D7
Read access timing in SERIAL Mode.
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S y m b ol
tsu1
tsu2
P ar am e t e r
Setup SDI valid to SCLKrising edge
Setup CSBfalling edge to SCLKrising edge
MIN
T YP
MA X
0 ns
-
-
160 ns
-
-
td 1
Delay SCLKrising edge (SCLKfalling edge for CLKE = 1)to SDO valid
-
-
17 ns
td 2
Delay CSBrising edge to SDO h igh -Z
-
-
10 ns
tp w 1
SCLK low time
180 ns
-
-
tp w 2
SCLK h igh time
180 ns
-
-
th 1
Hold SDI valid after SCLKrising edge
170 ns
-
-
th 2
Hold CSB low after SCLKrising edge, for CLKE = 0
Hold CSB low after SCLKfalling edge, for CLKE = 1
5 ns
-
-
tp
Time b etw een consecutive accesses (CSBrising edge to CSBfalling edge)
160 ns
-
-
Read access timing in SERIAL Mode.
CSB
t su2
t h2
t pw2
ALE=SCLK
A(0)=SDI
t pw1
t h1
t su1
_
R/W
A0
A1
A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6
D7
D(0)=SDO
S y m b ol
P ar am e t e r
MIN
T YP
MA X
0 ns
-
-
tsu1
Setup SDI valid to SCLKrising edge
tsu2
Setup CSBfalling edge to SCLKrising edge
160 ns
-
-
tp w 1
SCLK low time
180 ns
-
-
tp w 2
SCLK high time
180 ns
-
-
th 1
Hold SDI valid after SCLKrising edge
170 ns
-
-
th 2
Hold CSB low after SCLKrising edge
5 ns
-
-
tp
Time betw een consecutive accesses (CSBrising edge to CSBfalling edge)
160 ns
-
-
Write access timing in SERIAL Mode.
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EPROM Mode
In EPROM mode, the ACS8510 takes control of the bus as Master, and reads the device set-up from an AMD
AM27C64 type EPROM at lowest speed (250ns), after device start-up (system reset). The EPROM access state
machine in the up interface sequences the accesses.
Further details can be found in the AMD AM27C64 data sheet.
CSB (=OEB)
A
address
t acc
AD
Z
S y m b ol
tacc
Z
data
P ar am e t e r
Delay CSBfalling edge or A change to AD valid
MIN
T YP
MA X
-
-
920 ns
Read access timing in EPROM Mode.
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Package information
D
2
D1 1
3
AN2
AN3
1
Section A-A
R1
S
E
2
R2
B
AN1
E1
1
A
A
B
3
AN4
L
4
L1
5
1 2 3
b
Section B-B
7
e
A
A2
c
c1
7
7
Seating plane
A1 6
b1 7
b
8
Notes
1
The top package body may be smaller than the bottom package body by as much as 0.15 mm.
2
To be determined at seating plane.
3
Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side.
D1 and E1 are maximum plastic body size dimensions including mold mismatch.
4
Details of pin 1 identifier are optional but will be located within the zone indicated.
5
Exact shape of corners can vary.
6
A1 is defined as the distance from the seating plane to the lowest point of the package body.
7
These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
8
Shows plating.
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100 L Q F P
P ac k ag e
D i m e n si o n s
in mm
D/E
D 1/ E 1
Mi n
N om
16.00
14.00
Max
A
A1
A2
1.40 0.05
1.35
1.50
0.10
1.40
1.60
0.15
1.45
e
0.50
AN1
AN2
AN3
AN4
R1
R2
L
11°
11°
0°
0°
0.08
0.08
0.45
12°
12°
-
3.5°
-
-
0.60
13°
13°
-
7°
-
0.20
0.75
L1
1.00
(ref)
S
b
b1
c
c1
0.20
0.17
0.17
0.09
0.09
-
0.22
0.20
-
-
-
0.27
0.23
0.20
0.16
Thermal conditions
The device is rated for full temperature range when this package is used with a 4 layer or more
PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum
operating temperature must be reduced when the device is used with a PCB with less than these
requirements.
Notes
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Application information
A simplified Application Schematic for the ACS8510 is illustrated in Figure 11.
Typical power
supply
L1
VDD
VDD3
VDD5v
P1
VDDA
IC2
3 VIN
1 GND
5v
0v
VOUT
L2
2
(+)
ZD1
C2
(+)
100uF 100nF
C4
C3
VDD2
L3
EZ1086
term_connect
10uF_TANT (+)
L4 C5
10uF_TANT
ZD1
C6
100nF
C7
100nF
DGND2
L5
Optional Processor
interface
L6
DGND
AGND
DGND3
Int ALE WRB
SrcSwit RDY RDB CSB
VDD
O1
100nF
C9
O2
Optional boot
EPROM
O3
DGND
11
12
13
15
16
17
18
19
O5
optn 4
3 gnd1
R1
10R
R7
10R
DGND
VDD3
C11
100nF
DGND3
C12
100nF
ACS8510
VDD5v
DGND
DGND
A[0:7]
VDD
100nF
C13
Optional
Processor
interface type
selection
DGND
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD(AMI)
O8NEG
O8POS
GND(AMI)
O10
O11
VSS_DIFFa
VDD_DIFFa
O6POS
O6NEG
O7POS
O7NEG
VSS_DIFFb
VDD_DIFFb
I5POS
I5NEG
I6POS
I6NEG
VDD5
SYNC2K
I3
I4
I7
VSSe
VDDe
AGND
IC1
28
VDDA
GND
gnd2 5
12.8MHz
_txco
VDD
DGND
C1
100nF
10
9
8
7
6
5
4
3
25
24
21
23
2
output 1
C8
1nF
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
2 vdd
RDY 75
PORB 74
ALE 73
RDB 72
WRB 71
CSB 70
A(0) 69
A(1) 68
A(2) 67
A(3) 66
A(4) 65
A(5) 64
A(6) 63
VSSd 62
VDDd 61
UPSEL(0) 60
UPSEL(1) 59
UPSEL(2) 58
I14 57
I13 56
I12 55
I11 54
I10 53
I9 52
I8 51
P_B 27
C10
100nF
IC3
CE_B 20
OE_B 22
1 GND(GR)
2 BSMODE
3 IREF1
4 NC
5 GND(A1)
6 VA1+
7 TMS
8 Int
9 TCK
10 REFCLK
11 GND(D1)
12 VD+(D1)
13 VD+(D3)
14 GND(D3)
15 GND(D2)
16 VD+(D2)
17 NC
18 SrcSwit
19 VA2+
20 GND(A2)
21 TDO
22 IREF2
23 TDI
24 I1
25 I2
AGND
X1
Am27c64
AD(7)
AD(6)
AD(5)
AD(4)
AD(3)
AD(2)
AD(1)
AD(0)
VSSc
VDDc
VDDb
VSSb
O1
O2
O3
VDDa
VSSa
O4
O5
O9
TSCAN
TEST1
TEST2
MSTSLVB
SDHB
DGND
VDD
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
O9
14
O4
AD[0:7]
VDD
C14
100nF
C21
VDD
440pF
5
6
C17
470nF
C15
100nF
8
7
C16
470nF
C20
100nF
DGND
VDD2
DGND
DGND2
2nF
C22
I1
I2
DGND
O8
O10
O11
O6P O6N
O7P
O7N
I5P
I5N
I6P
I6N
SYNC2K
I3
I4
DGND2
I10
I8
I7
I9
I12
I11
I14
I13
DGND
Figure 11: A simplified Application Schematic.
Revision 2.07/Jan 2001 ã2001 Semtech Corp
67
www.semtech.com
ACS8510 SETS
FINAL
ADVANCED COMMUNCIATIONS
Revision History
Changes from revision 2.06 to 2.07. January 2001.
I t em
S e ct i o n
P ag e
D e scr i p t i o n
1
Tab le of contents
2
Inclusion of Revision History
2
Pin descrip tions
5
Pins 34/35 and 36/37 corrected for LVDS/PECL defaults
3
Tab le 5
15
Por ts T06 and T07 corrected for LVDS/PECL defaults
4
Register
descrip tion
25
sts_interrup ts register re-formatted and address error removed
5
Register
descrip tion
26
sts_curr_inc_offset register corrected for errors
6
Register
descrip tion
28
cnfg_sts_remote_sources_valid register re-formatted
7
Register
descrip tion
28
cnfg_op erating_mode register error corrected
8
Register
descrip tion
31
cnfg_freq_limit register re-formatted and re-w ritten
9
Leaky b ucket
timing b ox
36
Omission corrected in default setting equation
10
Holdover mode
39
Sp elling error corrected
11
Revision History
68
Section added
Revision 2.07/Jan 2001 ã2001 Semtech Corp
68
www.semtech.com
ACS8510 SETS
FINAL
ADVANCED COMMUNCIATIONS
Ordering information
PA R T N U M B E R
DE SCR I P T I O N
A CS8510
SON ET/SDH Synch ronisation, 100 p in LQFP
Disclaimers
Life support - This product is not designed or intended for use in life suport equipment, devices or
systems, or other critical applications. This product is not authorized or warranted by Semtech
Corporation for such use.
Right to change - Semtech Corporation reserves the right to make changes, without notice, to this
product. Customers are advised to obtain the latest version of the relevant information before
placing orders.
For additional information, contact the following:
Semtech Corporation Advanced Communications Products
E-Mail:
[email protected]
Internet:
http://www.semtech.com
USA:
652 Mitchell Road, Newbury Park, CA 91320-2289
Tel: +1 805 498 2111, Fax: +1 805 498 3804
FAR EAST:
11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C.
Tel: +886 2 2748 3380, Fax: +886 2 2748 3390
EUROPE:
Delta House, Chilworth Science Park, Southampton, Hants, SO16 7NS, UK
Tel: +44 23 80 769008, Fax: +44 23 80 768612
ISO9001
CERTIFIED
Revision 2.07/Jan 2001 ã2001 Semtech Corp
69
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