AD ADE7933 Isolated energy metering chipset for polyphase shunt meter Datasheet

Isolated Energy Metering Chipset
for Polyphase Shunt Meters
ADE7978/ADE7933/ADE7932
Data Sheet
FEATURES
Operating temperature: −40°C to +85°C
Flexible I2C, SPI, and HSDC serial interfaces
Safety and regulatory approvals (pending)
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
IEC 61010-1: 400 V rms
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 846 V peak
Enables shunt current sensors in polyphase energy meters
Immune to magnetic tampering
Highly accurate; supports EN 50470-1, EN 50470-3,
IEC 62053-21, IEC 62053-22, IEC 62053-23, ANSI C12.20,
and IEEE 1459 standards
Compatible with 3-phase, 3- or 4-wire (delta or wye) meters
and other 3-phase services
Computes active, reactive, and apparent energy on each
phase and on the overall system
Less than 0.2% error in active and reactive energy over
a dynamic range of 2000 to 1 at TA = 25°C
Less than 0.1% error in voltage rms over a dynamic range
of 500 to 1 at TA = 25°C
Less than 0.25% error in current rms over a dynamic range
of 500 to 1 at TA = 25°C
Power quality measurements including THD
Single 3.3 V supply
APPLICATIONS
Shunt-based polyphase meters
Power quality monitoring
Solar inverters
Process monitoring
Protective devices
Isolated sensor interfaces
Industrial PLCs
TYPICAL APPLICATION CIRCUIT
NEUTRAL
PHASE
A
PHASE
B
PHASE
C
ISOLATION
BARRIER
3.3V
V1P
VM
IM PHASE A
IP
ADE7932/
ADE7933
V2P
GNDISO_A
GNDMCU
3.3V
V1P
VM
ADE7932/
ADE7933
V2P
GNDISO_B
GNDMCU
3.3V
V1P
VM
IM PHASE C
IP
ADE7932/
ADE7933
3.3V
ADE7978
ENERGY
METERING
IC
I2C/HSDC
OR SPI
IRQ0, IRQ1
SYSTEM
MICROCONTROLLER
IP
DIGITAL INTERFACE
IM PHASE B
GNDMCU
3.3V
GNDMCU
V2P
GNDISO_C
GNDMCU
3.3V
V1P
VM NEUTRAL
LINE
IM
ADE7932/
ADE7933
IP
(OPTIONAL)
V2P
GNDISO_N
GNDMCU
11116-001
LOAD
EARTH
Figure 1. 3-Phase, 4-Wire Meter with Four ADE7933/ADE7932 Devices and One ADE7978
1
Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329; 6,262,600; 7,489,526; and 7,558,080. Other patents are pending.
Rev. 0
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ADE7978/ADE7933/ADE7932
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Active Power Calculation .............................................................. 52
Applications ....................................................................................... 1
Total Active Power Calculation ................................................ 52
Typical Application Circuit ............................................................. 1
Fundamental Active Power Calculation.................................. 53
Revision History ............................................................................... 3
Active Power Gain Calibration ................................................. 53
General Description ......................................................................... 4
Active Power Offset Calibration............................................... 54
Functional Block Diagrams ............................................................. 5
Sign of Active Power Calculation ............................................. 54
Specifications..................................................................................... 7
Active Energy Calculation ........................................................ 54
System Specifications, ADE7978 and ADE7933/ADE7932 ... 7
Integration Time Under Steady Load ...................................... 55
ADE7978 Specifications .............................................................. 9
Energy Accumulation Modes ................................................... 56
ADE7933/ADE7932 Specifications .......................................... 13
Line Cycle Active Energy Accumulation Mode ..................... 56
Absolute Maximum Ratings .......................................................... 16
Reactive Power Calculation .......................................................... 58
Thermal Resistance .................................................................... 16
Total Reactive Power Calculation ............................................ 58
ESD Caution ................................................................................ 16
Fundamental Reactive Power Calculation .............................. 58
Pin Configurations and Function Descriptions ......................... 17
Reactive Power Gain Calibration ............................................. 58
Typical Performance Characteristics ........................................... 21
Reactive Power Offset Calibration ........................................... 58
Test Circuit ...................................................................................... 26
Sign of Reactive Power Calculation ......................................... 59
Terminology .................................................................................... 27
Reactive Energy Calculation ..................................................... 59
Theory of Operation ...................................................................... 30
Integration Time Under Steady Load ...................................... 60
ADE7933/ADE7932 Analog Inputs ......................................... 30
Energy Accumulation Modes ................................................... 61
Analog-to-Digital Conversion .................................................. 30
Line Cycle Reactive Energy Accumulation Mode ................. 61
Current Channel ADC............................................................... 32
Apparent Power Calculation ......................................................... 62
Voltage Channel ADCs .............................................................. 35
Apparent Power Gain Calibration............................................ 62
Changing the Phase Voltage Datapath .................................... 39
Apparent Power Offset Calibration ......................................... 62
Reference Circuits ...................................................................... 39
Apparent Power Calculation Using VNOM ........................... 62
Phase Compensation.................................................................. 40
Apparent Energy Calculation ................................................... 63
Digital Signal Processor ............................................................. 41
Integration Time Under Steady Load ...................................... 64
Power Quality Measurements ....................................................... 42
Energy Accumulation Mode ..................................................... 64
Zero-Crossing Detection ........................................................... 42
Line Cycle Apparent Energy Accumulation Mode ................ 64
Period Measurement .................................................................. 44
Phase Voltage Sag Detection ..................................................... 45
Power Factor Calculation and Total Harmonic
Distortion Calculation ................................................................... 65
Peak Detection ............................................................................ 46
Power Factor Calculation .......................................................... 65
Overvoltage and Overcurrent Detection................................. 47
Total Harmonic Distortion Calculation .................................. 66
Neutral Current Mismatch ........................................................ 48
Waveform Sampling Mode ............................................................ 67
Root Mean Square Measurement ................................................. 49
Energy-to-Frequency Conversion ................................................ 68
Current RMS Calculation .......................................................... 49
TERMSELx[2:0] Bits .................................................................. 68
Voltage RMS Calculation .......................................................... 50
CFxSEL[2:0] Bits ........................................................................ 68
Voltage RMS in Delta Configurations ..................................... 51
Energy-to-Frequency Conversion Process ............................. 69
Rev. 0 | Page 2 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Synchronizing Energy Registers with the CFx Outputs ........69
Applications Information ............................................................... 82
Energy Registers and CFx Outputs for Various
Accumulation Modes .................................................................70
ADE7978 and ADE7933/ADE7932 in Polyphase
Energy Meters.............................................................................. 82
Sign of Sum of Phase Powers in the CFx Datapath ................72
ADE7978 Quick Setup as an Energy Meter ............................ 85
No Load Condition .........................................................................73
Bit Stream Communication Between the ADE7978
and the ADE7933/ADE7932 ..................................................... 86
No Load Detection Based on Total Active
and Reactive Powers ...................................................................73
ADE7978 and ADE7933/ADE7932 Clocks ............................. 87
No Load Detection Based on Fundamental
Active and Reactive Powers .......................................................73
Insulation Lifetime ...................................................................... 87
No Load Detection Based on Apparent Power .......................74
ADE7978 and ADE7933/ADE7932 Evaluation Board .......... 90
Interrupts ..........................................................................................75
ADE7978 Die Version ................................................................ 90
Using the Interrupts with an MCU...........................................76
Serial Interfaces ............................................................................... 91
Power Management.........................................................................77
Serial Interface Selection ............................................................ 91
DC-to-DC Converter .................................................................77
Communication Verification .................................................... 91
Magnetic Field Immunity ..........................................................78
I2C-Compatible Interface ........................................................... 91
Power-Up Procedure ..................................................................79
SPI-Compatible Interface........................................................... 94
Initializing the Chipset ...............................................................79
HSDC Interface ........................................................................... 96
Hardware Reset............................................................................80
Checksum Register ..................................................................... 98
ADE7978/ADE7933/ADE7932 Chipset Software Reset........81
Register List...................................................................................... 99
ADE7933/ADE7932 Software Reset.........................................81
Outline Dimensions ......................................................................118
Low Power Mode.........................................................................81
Ordering Guide .........................................................................118
Layout Guidelines ....................................................................... 88
REVISION HISTORY
11/13—Revision 0: Initial Version
Rev. 0 | Page 3 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
GENERAL DESCRIPTION
The ADE7978 and the ADE7933/ADE7932 form a chipset
dedicated to measuring 3-phase electrical energy using shunts
as current sensors.
The ADE7933/ADE7932 are isolated, 3-channel sigma-delta
analog-to-digital converters (Σ-Δ ADCs) for polyphase energy
metering applications that use shunt current sensors. The
ADE7932 features two 24-bit ADCs, and the ADE7933 features
three 24-bit ADCs. One channel is dedicated to measuring the
voltage across the shunt when a shunt is used for current sensing.
This channel provides a signal-to-noise ratio (SNR) of 67 dB over
a 3.3 kHz signal bandwidth. Up to two additional channels are
dedicated to measuring voltages, which are usually sensed using
resistor dividers. These channels provide an SNR of 75 dB over
a 3.3 kHz signal bandwidth. One voltage channel can be used to
measure the temperature of the die via an internal sensor. The
ADE7933 includes three channels: one current channel and two
voltage channels. The ADE7932 includes one current channel and
one voltage channel, but is otherwise identical to the ADE7933.
The ADE7933/ADE7932 include isoPower®, an integrated,
isolated dc-to-dc converter. Based on the Analog Devices, Inc.,
iCoupler® technology, the dc-to-dc converter provides the regulated power required by the first stage of the ADCs at a 3.3 V
input supply. The ADE7933/ADE7932 eliminate the need for an
external dc-to-dc isolation block. The iCoupler chip scale transformer technology is used to isolate the logic signals between the
first and second stages of the ADC. The result is a small form
factor, total isolation solution.
The ADE7933/ADE7932 contain a digital interface that is specially
designed to interface with the ADE7978. Using this interface, the
ADE7978 accesses the ADC outputs and configuration settings
of the ADE7933/ADE7932.
The ADE7933/ADE7932 are available in a 20-lead, Pb-free, widebody SOIC package with increased creepage.
The ADE7978 is a high accuracy, 3-phase electrical energy
measurement IC with serial interfaces and three flexible pulse
outputs. The ADE7978 can interface with up to four ADE7933/
ADE7932 devices. The ADE7978 incorporates all the signal
processing required to perform total (fundamental and harmonic)
active, reactive, and apparent energy measurement and rms
calculations, as well as fundamental-only active and reactive
energy measurement and rms calculations. A fixed function
digital signal processor (DSP) executes this signal processing.
The ADE7978 measures the active, reactive, and apparent energy
in various 3-phase configurations, such as wye or delta services,
with both three and four wires. The ADE7978 provides system
calibration features for each phase, gain calibration, and optional
offset correction. Phase compensation is also available, but it is
not necessary because the currents are sensed using shunts. The
CF1, CF2, and CF3 logic outputs provide a wide selection of
power information: total active, reactive, and apparent powers;
the sum of the current rms values; and fundamental active and
reactive powers.
The ADE7978 incorporates power quality measurements, such
as short duration low or high voltage detection, short duration
high current variations, line voltage period measurement, and
angles between phase voltages and currents. Two serial interfaces,
SPI and I2C, can be used to communicate with the ADE7978.
A dedicated high speed interface—the high speed data capture
(HSDC) port—can be used in conjunction with I2C to provide
access to the ADC outputs and real-time power information.
The ADE7978 also has two interrupt request pins, IRQ0 and
IRQ1, to indicate that an enabled interrupt event has occurred.
The ADE7978 is available in a 28-lead, Pb-free LFCSP package.
Note that throughout this data sheet, multifunction pins, such
as SCLK/SCL, are referred to by the entire pin name or by a
single function of the pin, for example, SCLK, when only that
function is relevant.
Rev. 0 | Page 4 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
FUNCTIONAL BLOCK DIAGRAMS
RESET
VDD
GND
12
21
20
LDO DGND
22
23
ADE7978
POR
LDO
AV2RMSOS
HPFEN
BIT
AV2GAIN
HPF
27
X2
AV2RMS
LPF
XTALIN 25
ATEMP
AIRMSOS
XTALOUT 24
SELECTION BIT
VB/TEMP SENSOR
ATGAIN
APGAIN
X2
ATEMP0
211
VT_B 1
AIRMS
LPF
TEMPCO
ATEMPOS
DATA_B 2
X2
1
AVRMS
LPF
AIGAIN HPFEN BIT
CF1DEN
AVRMSOS
RESET_EN 3
APGAIN
HPF
CLKOUT 4
:
DFC
AWATTOS
13 CF1
CF2DEN
DIGITAL
BLOCK
HPFEN BIT
APHCAL
LPF
HPF
VT_C 6
APGAIN
AV1GAIN
DATA_C 7
VT_N 8
ACTIVE/REACTIVE/APPARENT
TOTAL ENERGIES AND
VOLTAGE/CURRENT RMS
CALCULATION FOR PHASE B
(SEE PHASE A FOR DETAILED
DATAPATH)
DATA_A 28
ACTIVE/REACTIVE/APPARENT
TOTAL ENERGIES AND
VOLTAGE/CURRENT RMS
CALCULATION FOR PHASE C
(SEE PHASE A FOR DETAILED
DATAPATH)
NIGAIN
HPFEN
BIT
HPF
:
DFC
14 CF2
CF3DEN
DFC
APGAIN
:
15 CF3/HSCLK
26 ZX/DREADY
AFWATTOS
10 IRQ0
11 IRQ1
COMPUTATIONAL
BLOCK FOR
FUNDAMENTAL
ACTIVE AND
REACTIVE POWER
DATA_N 9
VT_A 27
AVAROS
COMPUTATIONAL
BLOCK FOR TOTAL
REACTIVE POWER
PHASE A,
PHASE B,
PHASE C
DATA
APGAIN
AFVAROS
DIGITAL SIGNAL
PROCESSOR
TEMPCO
NTEMP
17 SCLK/SCL
SPI OR
I2C AND
HSDC
19 MOSI/SDA
18 MISO/HSD
16 SS/HSA
NTEMP0
NIRMSOS
1
X2
NIRMS
LPF
Figure 2. ADE7978 Functional Block Diagram
Rev. 0 | Page 5 of 120
11116-002
SYNC 5
ADE7978/ADE7933/ADE7932
Data Sheet
ISOLATION
BARRIER
2
20
POWER
ISOLATION
8
LDO
18
ADC
DATA
4
V1P
ADC
7
IP
9
REF
CLOCK
CLOCK
ADC
17
DATA
DATA
ISOLATION
6
IM
GND
LDO
5
VM
VDD
TEMP
SENSOR
3
V2P
19
DIGITAL
BLOCK
AND
ADE7978
INTERFACE
16
15
14
13
12
VREF
10
11
EMI_CTRL
V2/TEMP
RESET_EN
DATA
XTAL2
XTAL1
SYNC
11116-003
GNDISO
GNDISO
ADE7933
1
VDDISO
GND
Figure 3. ADE7933 Functional Block Diagram
ISOLATION
BARRIER
GNDISO
LDO
V2P
VM
V1P
IM
IP
REF
GNDISO
ADE7932
1
2
8
3
5
4
20
POWER
ISOLATION
9
VDD
GND
LDO
TEMP
SENSOR
18
ADC
DATA
ADC
CLOCK
ADC
17
DATA
DATA
ISOLATION
6
7
19
CLOCK
DIGITAL
BLOCK
AND
ADE7978
INTERFACE
16
15
14
13
12
VREF
10
11
Figure 4. ADE7932 Functional Block Diagram
Rev. 0 | Page 6 of 120
EMI_CTRL
V2/TEMP
RESET_EN
DATA
XTAL2
XTAL1
SYNC
GND
11116-004
VDDISO
Data Sheet
ADE7978/ADE7933/ADE7932
SPECIFICATIONS
SYSTEM SPECIFICATIONS, ADE7978 AND ADE7933/ADE7932
VDD = 3.3 V ± 10%, GND = DGND = 0 V, ADE7978 XTALIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C, TTYP = 25°C.
Table 1.
Parameter 1, 2
ACTIVE ENERGY MEASUREMENT
Measurement Error (per Phase)
Total Active Energy
Unit
Test Conditions/Comments
0.1
%
0.2
0.1
%
%
0.2
%
Over a dynamic range of 500 to 1, power
factor (PF) = 1, gain compensation only
Over a dynamic range of 2000 to 1, PF = 1
Over a dynamic range of 500 to 1, PF = 1,
gain compensation only
Over a dynamic range of 2000 to 1, PF = 1
VDD = 3.3 V + 120 mV rms at 50 Hz/100 Hz,
IP = 6.25 mV rms, V1P = V2P = 100 mV rms
Output Frequency Variation
DC Power Supply Rejection
0.01
%
Output Frequency Variation
Total Active Energy Measurement
Bandwidth
REACTIVE ENERGY MEASUREMENT
Measurement Error (per Phase)
Total Reactive Power
0.01
3.3
%
kHz
0.1
%
0.2
0.1
%
%
0.2
%
0.01
%
Fundamental Active Power
Min
Typ
Max
AC Power Supply Rejection
Fundamental Reactive Power
VDD = 3.3 V ± 330 mV dc, IP = 6.25 mV rms,
V1P = V2P = 100 mV rms
AC Power Supply Rejection
Output Frequency Variation
DC Power Supply Rejection
Output Frequency Variation
Total Reactive Energy Measurement
Bandwidth
RMS MEASUREMENTS
Measurement Bandwidth
V rms Measurement Error
I rms Measurement Error
Fundamental V rms Measurement Error
Fundamental I rms Measurement Error
WAVEFORM SAMPLING
Current Channels
Signal-to-Noise Ratio, SNR
Signal-to-Noise-and-Distortion
(SINAD) Ratio
Total Harmonic Distortion, THD
Spurious-Free Dynamic Range, SFDR
Over a dynamic range of 500 to 1, PF = 0,
gain compensation only
Over a dynamic range of 2000 to 1, PF = 0
Over a dynamic range of 500 to 1, PF = 0,
gain compensation only
Over a dynamic range of 2000 to 1, PF = 0
VDD = 3.3 V + 120 mV rms at 50 Hz/100 Hz,
IP = 6.25 mV rms, V1P = V2P = 100 mV rms
VDD = 3.3 V ± 330 mV dc, IP = 6.25 mV rms,
V1P = V2P = 100 mV rms
0.01
3.3
%
kHz
3.3
0.1
0.25
0.1
0.25
kHz
%
%
%
%
67
67
dB
dB
−85
88
dB
dBFS
Rev. 0 | Page 7 of 120
I rms and V rms
Over a dynamic range of 500 to 1
Over a dynamic range of 500 to 1
Over a dynamic range of 500 to 1
Over a dynamic range of 500 to 1
Sampling CLKIN/2048 (16.384 MHz/2048 =
8 kSPS)
See the Waveform Sampling Mode section
ADE7978/ADE7933/ADE7932
Parameter 1, 2
Voltage Channels
Signal-to-Noise Ratio, SNR
Signal-to-Noise-and-Distortion
(SINAD) Ratio
Total Harmonic Distortion, THD
Spurious-Free Dynamic Range, SFDR
Bandwidth (−3 dB)
TIME INTERVAL BETWEEN PHASE SIGNALS
Measurement Error
CF1, CF2, CF3 PULSE OUTPUTS
Maximum Output Frequency
Min
Duty Cycle
Data Sheet
Typ
Max
1
2
Test Conditions/Comments
75
74
dB
dB
−81
81
3.3
dB
dBFS
kHz
0.3
Degrees
Line frequency = 45 Hz to 65 Hz, HPF on
68.8
kHz
50
%
WTHR = VARTHR = VATHR = 3, CFxDEN = 1,
full scale current and voltage, PF = 1, one
phase only
CF1, CF2, or CF3 frequency > 6.25 Hz,
CFxDEN is even and > 1
CF1, CF2, or CF3 frequency > 6.25 Hz,
CFxDEN is odd and > 1
CF1, CF2, or CF3 frequency < 6.25 Hz
CF1, CF2, or CF3 frequency = 1 Hz, nominal
phase currents larger than 10% of full scale
(1 + 1/CFxDEN) × 50
Active Low Pulse Width
Jitter
Unit
80
0.04
See the Typical Performance Characteristics section.
See the Terminology section for definitions of the parameters.
Rev. 0 | Page 8 of 120
%
ms
%
Data Sheet
ADE7978/ADE7933/ADE7932
ADE7978 SPECIFICATIONS
VDD = 3.3 V ± 10%, GND = DGND = 0 V, XTALIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C, TTYP = 25°C.
Table 2.
Parameter 1, 2
CLOCK INPUT
Input Clock Frequency, CLKIN
XTALIN Logic Inputs
Input High Voltage, VINH
Input Low Voltage, VINL
XTALIN Total Capacitance 3
XTALOUT Total Capacitance3
CLOCK OUTPUT
Output Clock Frequency at CLKOUT Pin
Duty Cycle
Output High Voltage, VOH
ISOURCE
Output Low Voltage, VOL
ISINK
LOGIC INPUTS—MOSI/SDA, SCLK/SCL,
SS/HSA, DATA_A, DATA_B, DATA_C,
DATA_N
Input High Voltage, VINH
Input Current, IIN
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
LOGIC INPUT—RESET
Input High Voltage, VINH
Input Current, IIN
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
LOGIC OUTPUTS—IRQ0, IRQ1, MISO/HSD,
CLKOUT, SYNC, VT_A, VT_B, VT_C, VT_N,
ZX/DREADY, RESET_EN
Output High Voltage, VOH
ISOURCE
Output Low Voltage, VOL
ISINK
CF1, CF2, CF3/HSCLK
Output High Voltage, VOH
ISOURCE
Output Low Voltage, VOL
ISINK
POWER SUPPLY
VDD Pin
IDD
Min
Typ
Max
Unit
16.22
16.384
16.55
MHz
2.4
0.8
40
40
4.096
50
4.8
0.4
4.8
40
0.8
180
10
V
nA
V
nA
pF
VDD = 3.3 V ± 10%
Input = VDD = 3.3 V
VDD = 3.3 V ± 10%
Input = 0 V, VDD = 3.3 V
160
0.8
+11
10
V
nA
V
µA
pF
VDD = 3.3 V ± 10%
Input = VDD = 3.3 V
VDD = 3.3 V ± 10%
Input = 0 V, VDD = 3.3 V
2.4
5
2.4
80
−8
V
V
pF
pF
MHz
%
V
mA
V
mA
2.4
2
Test Conditions/Comments
All specifications for CLKIN = 16.384 MHz
Minimum = 16.384 MHz − 1%; maximum
= 16.384 MHz + 1%
VDD = 3.3 V ± 10%
2.4
4.8
0.4
4.8
V
mA
V
mA
8
0.4
8.5
V
mA
V
mA
3.63
V
15.5
mA
2.4
2.97
10.6
VDD = 3.3 V
VDD = 3.3 V ± 10%
VDD = 3.3 V ± 10%
VDD = 3.3 V ± 10%
For specified performance
Minimum = 3.3 V − 10%; maximum = 3.3 V
+ 10%
See the Typical Performance Characteristics section.
See the Terminology section for a definition of the parameters.
3
XTALIN/XTALOUT total capacitances refer to the net capacitances on each pin. Each capacitance is the sum of the parasitic capacitance at the pin and the capacitance
of the ceramic capacitor connected between the pin and GND. See the ADE7978 and ADE7933/ADE7932 Clocks section for more information.
1
2
Rev. 0 | Page 9 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
I2C Interface Timing Parameters
VDD = 3.3 V ± 10%, GND = DGND = 0 V, XTALIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C.
Table 3.
Parameter
SCL Clock Frequency
Hold Time for Start and Repeated Start Conditions
Low Period of SCL Clock
High Period of SCL Clock
Set-Up Time for Repeated Start Condition
Data Hold Time
Data Setup Time
Rise Time of SDA and SCL Signals
Fall Time of SDA and SCL Signals
Setup Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Pulse Width of Suppressed Spikes
Min
0
4.0
4.7
4.0
4.7
0
250
Standard Mode
Max
100
3.45
1000
300
4.0
4.7
N/A 1
Min
0
0.6
1.3
0.6
0.6
0
100
20
20
0.6
1.3
Fast Mode
Max
400
0.9
300
300
50
Unit
kHz
μs
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
N/A means not applicable.
SDA
tSU;DAT
tF
tLOW
tR
tHD;STA
tSP
tr
tBUF
tF
SCL
tHD;STA
START
CONDITION
tHD;DAT
tHIGH
tSU;STA
REPEATED START
CONDITION
Figure 5. I2C Interface Timing
Rev. 0 | Page 10 of 120
tSU;STO
STOP
START
CONDITION CONDITION
11116-005
1
Symbol
fSCL
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tR
tF
tSU;STO
tBUF
tSP
Data Sheet
ADE7978/ADE7933/ADE7932
SPI Interface Timing Parameters
VDD = 3.3 V ± 10%, GND = DGND = 0 V, XTALIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C.
Table 4.
Parameter
SS to SCLK Edge
SCLK Period
SCLK Low Pulse Width
SCLK High Pulse Width
Data Output Valid After SCLK Edge
Data Input Setup Time Before SCLK Edge
Data Input Hold Time After SCLK Edge
Data Output Fall Time
Data Output Rise Time
SCLK Rise Time
SCLK Fall Time
MISO Disable After SS Rising Edge
SS High After SCLK Edge
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDIS
tSFS
Min
50
0.4
175
175
Max
Unit
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
40001
130
100
50
20
20
20
20
1
100
Guaranteed by design.
SS
tSS
tSFS
SCLK
tSL
tSH
tDAV
tSF
tSR
tDIS
MSB
MISO
INTERMEDIATE BITS
tDF
LSB
tDR
INTERMEDIATE BITS
LSB IN
MSB IN
MOSI
tDSU
11116-006
1
Symbol
tSS
tDHD
Figure 6. SPI Interface Timing
Rev. 0 | Page 11 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
HSDC Interface Timing Parameters
VDD = 3.3 V ± 10%, GND = DGND = 0 V, XTALIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C.
Table 5.
Parameter
HSA to HSCLK Edge
HSCLK Period
HSCLK Low Pulse Width
HSCLK High Pulse Width
Data Output Valid After HSCLK Edge
Data Output Fall Time
Data Output Rise Time
HSCLK Rise Time
HSCLK Fall Time
HSD Disable After HSA Rising Edge
HSA High After HSCLK Edge
Symbol
tSS
Min
0
125
50
50
tSL
tSH
tDAV
tDF
tDR
tSR
tSF
tDIS
tSFS
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
20
20
10
10
5
0
HSA
tSS
tSFS
HSCLK
tSL
tDAV
tSH
tSF
tSR
tDIS
INTERMEDIATE BITS
LSB
tDR
tDF
Figure 7. HSDC Interface Timing
2mA
TO OUTPUT
PIN
IOL
1.6V
CL
50pF
800µA
IOH
Figure 8. Load Circuit for Timing Specifications
Rev. 0 | Page 12 of 120
11116-007
MSB
11116-009
HSD
Data Sheet
ADE7978/ADE7933/ADE7932
ADE7933/ADE7932 SPECIFICATIONS
VDD1 = 3.3 V ± 10%, GND = 0 V, on-chip reference, XTAL1 = 4.096 MHz, TMIN to TMAX = −40°C to +85°C, TTYP = 25°C.
Table 6.
Parameter 1
ANALOG INPUTS
Pseudo Differential Signal Voltage Range
Between IP and IM Pins
Between V1P and VM Pins and
Between V2P and VM Pins
Maximum VM and IM Voltage
Crosstalk
Input Impedance to GNDISO (DC)
IP, IM, V1P, and V2P Pins
VM Pin
Current Channel ADC Offset Error
Voltage Channel ADC Offset Error
ADC Offset Drift over Temperature
Gain Error
Gain Drift over Temperature
Min
Typ
Max
Unit
Test Conditions/Comments
+31.25
+500
mV peak
mV peak
IM pin connected to GNDISO
Pseudo differential inputs between V1P
and VM pins and between V2P and VM pins,
VM pin connected to GNDISO
+25
−90
mV
dB
−105
dB
−31.25
−500
−25
AC Power Supply Rejection
−90
kΩ
kΩ
mV
mV
ppm/°C
%
ppm/°C
ppm/°C
dB
DC Power Supply Rejection
−80
dB
±5
°C
TEMPERATURE SENSOR
Accuracy
CLOCK INPUT
Input Clock Frequency, XTAL1
XTAL1 Duty Cycle
XTAL1 Logic Inputs
Input High Voltage, VINH
Input Low Voltage, VINL
XTAL1 Total Capacitance 2
XTAL2 Total Capacitance2
LOGIC INPUTS—SYNC, V2/TEMP, RESET_EN,
EMI_CTRL
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
LOGIC OUTPUTS—DATA
Output High Voltage, VOH
Output Low Voltage, VOL
480
280
−2
−35
−500
−4
−135
−65
+500
+4
+135
+65
3.6
4.096
4.21
MHz
45
50
55
%
2.4
0.8
40
40
2.4
V
V
nA
pF
0.4
V
V
Rev. 0 | Page 13 of 120
V2 channel applies to the ADE7933 only
V1 channel only
Current channel
V1 and V2 channels
VDD = 3.3 V + 120 mV rms at 50 Hz/100 Hz,
IP = V1P = V2P = GNDISO
VDD = 3.3 V ± 330 mV dc, IP = 6.25 mV rms,
V1P = V2P = 100 mV rms
All specifications for XTAL1 = 4.096 MHz
Nominal value provided by the ADE7978;
min and max values apply if the ADE7933/
ADE7932 are used without the ADE7978
Values apply if the ADE7933/ADE7932 are
used without the ADE7978
V
V
pF
pF
0.8
15
10
2.5
IP and IM inputs set to 0 V (GNDISO), V1P and
V2P inputs at full scale
V2P or V1P and VM inputs set to 0 V (GNDISO),
IP and V1P or V2P inputs at full scale
ISOURCE = 800 µA
ISINK = 2 mA
ADE7978/ADE7933/ADE7932
Parameter 1
POWER SUPPLY
VDD Pin
Data Sheet
Min
2.97
IDD
1
2
Typ
12.5
50
Max
Unit
3.63
V
19
mA
µA
Test Conditions/Comments
For specified performance
Minimum = 3.3 V − 10%; maximum = 3.3 V
+ 10%
Bit 6 (CLKOUT_DIS) and Bit 7 (ADE7933_
SWRST) in the CONFIG3 register set to 1
See the Terminology section for definitions of the parameters.
XTAL1/XTAL2 total capacitances refer to the net capacitances on each pin. Each capacitance is the sum of the parasitic capacitance at the pin and the capacitance of
the ceramic capacitor connected between the pin and GND. See the ADE7978 and ADE7933/ADE7932 Clocks section for more information.
Regulatory Approvals (Pending)
The ADE7933/ADE7932 are pending approval by the organizations listed in Table 7. See Table 12 and the Insulation Lifetime section for
more information about the recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 7.
UL
Recognized under UL 1577 component
recognition program 1
Single protection, 5000 V rms isolation
voltage
1
2
CSA
Approved under CSA Component Acceptance
Notice #5A
Basic insulation per IEC 61010-1, 400 V rms
(564 V peak) maximum working voltage
VDE
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 2
Reinforced insulation, 846 V peak
In accordance with UL 1577, each ADE7933/ADE7932 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 sec (current leakage detection limit = 10 µA).
In accordance with DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, each ADE7933/ADE7932 is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 sec
(partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 approval.
Insulation and Safety Related Specifications
Table 8. Critical Safety Related Dimensions and Material Properties
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
5000
8.3
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
8.3
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.017 min
>600
II
mm
V
Rev. 0 | Page 14 of 120
Test Conditions/Comments
1-minute duration
Measured from input terminals to output
terminals, shortest distance through air
along the PCB mounting plane, as an aid
to PCB layout
Measured from input terminals to output
terminals, shortest distance path along body
Insulation distance through insulation
IEC 60112
Material Group DIN VDE 0110, 1/89, Table 1
Data Sheet
ADE7978/ADE7933/ADE7932
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics
The ADE7933/ADE7932 are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is
ensured by the protective circuits.
Table 9.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Test Conditions/Comments
VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
Symbol
Characteristic
Unit
VIORM
Vpd(m)
I to IV
I to IV
I to III
40/105/21
2
846
1592
V peak
V peak
1273
V peak
1018
V peak
VIOTM
VIOSM
6000
6000
V peak
V peak
TS
PS
RS
150
2.78
>109
°C
W
Ω
Vpd(m)
VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
After Input and/or Safety Tests Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage
Safety Limiting Values
VPEAK = 10 kV; 1.2 µs rise time; 50 µs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 9)
Maximum Junction Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
VIO = 500 V
3.0
SAFE LIMITING POWER (W)
2.5
2.0
1.5
1.0
0
0
50
100
150
AMBIENT TEMPERATURE (ºC)
200
11116-010
0.5
Figure 9. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
Rev. 0 | Page 15 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
−0.3 V to +3.7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−0.3 V to +3.7 V
−2 V to +2 V
θJA and θJC are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−100 kV/µs to +100 kV/µs
Package Type
28-Lead LFCSP (ADE7978)
20-Lead SOIC (ADE7933/ADE7932)
Table 10.
Parameter
ADE7978
VDD to GND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
ADE7933/ADE7932
VDD to GND
Analog Input Voltage to GNDISO,
IP, IM, V1P, V2P, VM
Reference Input Voltage to GNDISO
Digital Input Voltage to GND
Digital Output Voltage to GND
Common-Mode Transients1
Operating Temperature
Industrial Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)2
ADE7978
ADE7933/ADE7932
Rating
−40°C to +85°C
−65°C to +150°C
THERMAL RESISTANCE
Table 11. Thermal Resistance
θJA
29.3
48.0
ESD CAUTION
300°C
260°C
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up
or permanent damage.
2
Analog Devices recommends that reflow profiles used in soldering RoHS
compliant parts conform to JEDEC J-STD 20. For the latest revision of this
standard, refer to JEDEC.
1
Table 12. ADE7933/ADE7932 Maximum Continuous Working Voltage Supporting a 50-Year Minimum Lifetime1
Parameter
AC Voltage, Bipolar Waveform
DC Voltage
Basic Insulation
1
Max
564
Unit
V peak
600
V peak
Applicable Certification
All certifications, 50-year operation
Refers to the continuous voltage magnitude imposed across the isolation barrier. For more information, see the Insulation Lifetime section.
Rev. 0 | Page 16 of 120
θJC
1.8
6.2
Unit
°C/W
°C/W
Data Sheet
ADE7978/ADE7933/ADE7932
23 DGND
22 LDO
26 ZX/DREADY
25 XTALIN
24 XTALOUT
28 DATA_A
27 VT_A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
21 VDD
VT_B 1
DATA_B 2
CLKOUT 4
SYNC 5
20 GND
19 MOSI/SDA
ADE7978
18 MISO/HSD
17 SCLK/SCL
TOP VIEW
(Not to Scale)
VT_C 6
16 SS/HSA
DATA_C 7
CF1 13
CF2 14
RESET 12
IRQ0 10
IRQ1 11
VT_N
DATA_N
8
9
15 CF3/HSCLK
NOTES
1. CREATE A SIMILAR PAD ON THE PCB UNDER THE
EXPOSED PAD. SOLDER THE EXPOSED PAD TO
THE PAD ON THE PCB TO CONFER MECHANICAL
STRENGTH TO THE PACKAGE. CONNECT THE
PADS TO DGND AND GND.
11116-011
RESET_EN 3
Figure 10. Pin Configuration, ADE7978
Table 13. Pin Function Descriptions, ADE7978
Pin No.
1
Mnemonic
VT_B
2
DATA_B
3
RESET_EN
4
5
CLKOUT
SYNC
6
VT_C
7
DATA_C
8
VT_N
9
DATA_N
10, 11
IRQ0, IRQ1
12
RESET
13, 14, 15
CF1, CF2,
CF3/HSCLK
SS/HSA
SCLK/SCL
16
17
Description
Selects the second voltage input (V2P) or the temperature measurement on the Phase B ADE7933/ADE7932.
Connect this pin to the V2/TEMP pin of the Phase B ADE7933/ADE7932. If no ADE7933/ADE7932 is used to
sense Phase B—as in the 3-phase, 3-wire delta configuration—leave this pin unconnected.
Receives the bit streams from the Phase B ADE7933/ADE7932. Connect this pin to the DATA pin of the Phase B
ADE7933/ADE7932. If no ADE7933/ADE7932 is used to sense Phase B—as in the 3-phase, 3-wire delta
configuration—connect this pin to VDD.
Reset Output Enable. Connect this pin to the RESET_EN pins of the ADE7933/ADE7932 devices. This pin is used
by the ADE7978 to reset the ADE7933/ADE7932 devices (see the Hardware Reset section).
4.096 MHz Output Clock Signal. Connect this pin to the XTAL1 pins of the ADE7933/ADE7932 devices.
Clock Output (1.024 MHz). This pin is the clock for serial communication with the ADE7933/ADE7932 devices.
Connect this pin to the SYNC pins of the ADE7933/ADE7932 devices.
Selects the second voltage input (V2P) or the temperature measurement on the Phase C ADE7933/ADE7932.
Connect this pin to the V2/TEMP pin of the Phase C ADE7933/ADE7932. If no ADE7933/ADE7932 is used to
sense Phase C, leave this pin unconnected.
Receives the bit streams from the Phase C ADE7933/ADE7932. Connect this pin to the DATA pin of the Phase C
ADE7933/ADE7932. If no ADE7933/ADE7932 is used to sense Phase C, connect this pin to VDD.
Selects the second voltage input (V2P) or the temperature measurement on the neutral line ADE7933/ADE7932.
Connect this pin to the V2/TEMP pin of the neutral line ADE7933/ADE7932. If no ADE7933/ADE7932 is used to
sense the neutral line, leave this pin unconnected.
Receives the bit streams from the neutral line ADE7933/ADE7932. Connect this pin to the DATA pin of the neutral
line ADE7933/ADE7932. If no ADE7933/ADE7932 is used to sense the neutral line, connect this pin to VDD.
Interrupt Request Outputs. These pins are active low logic outputs. For information about the events that can
trigger an interrupt, see the Interrupts section.
Reset Input, Active Low. Set this pin low for at least 10 µs to trigger a hardware reset (see the Hardware Reset
section).
Calibration Frequency (CF) Logic Outputs. These outputs provide power information and are used for operational and calibration purposes. CF3 is multiplexed with the serial clock output of the HSDC port.
Slave Select for the SPI Port/HSDC Port Active.
Serial Clock Input for the SPI Port/Serial Clock Input for the I2C Port. This pin has a Schmitt trigger input for
use with clock sources that have a slow edge transition time, for example, opto-isolator outputs. The default
functionality of this pin is SCL.
Rev. 0 | Page 17 of 120
ADE7978/ADE7933/ADE7932
Pin No.
18
19
20
21
Mnemonic
MISO/HSD
MOSI/SDA
GND
VDD
22
LDO
23
24
DGND
XTALOUT
25
XTALIN
26
ZX/DREADY
27
VT_A
28
DATA_A
EP
Exposed Pad
Data Sheet
Description
Data Output for the SPI Port/Data Output for the HSDC Port.
Data Input for the SPI Port/Data Output for the I2C Port. The default functionality of this pin is SDA.
Ground Reference for the Input Circuitry.
Supply Voltage. This pin provides the supply voltage. For specified operation, maintain the supply voltage at
3.3 V ± 10%. Decouple this pin to GND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
1.8 V Output of the Digital Low Dropout (LDO) Regulator. Decouple this pin with a 4.7 µF capacitor in parallel
with a ceramic 100 nF capacitor. Do not connect active external circuitry to this pin.
Ground Reference for the Digital Circuitry.
A crystal with a maximum drive level of 0.5 mW and an equivalent series resistance (ESR) of 20 Ω can be
connected across this pin and the XTALIN pin to provide a clock source for the ADE7978.
Master Clock. An external clock can be provided at this logic input. Alternatively, a crystal with a maximum
drive level of 0.5 mW and an ESR of 20 Ω can be connected across XTALIN and XTALOUT to provide a clock
source for the ADE7978. The clock frequency for specified operation is 16.384 MHz. For more information, see
the ADE7978 and ADE7933/ADE7932 Clocks section.
Zero-Crossing (ZX) Output Pin. The ZX pin goes high on the positive-going edge of the selected phase voltage
zero crossing; the pin goes low on the negative-going edge of the zero crossing (see the Zero-Crossing
Detection section for more information).
DREADY is an active low signal that is generated approximately 70 ns after Bit 17 (DREADY) in the STATUS0 register
is set to 1. This pin has a frequency of 8 kHz and stays low for 10 µs every period. The default functionality of
this pin is DREADY.
Selects the second voltage input (V2P) or the temperature measurement on the Phase A ADE7933/ADE7932.
Connect this pin to the V2/TEMP pin of the Phase A ADE7933/ADE7932. If no ADE7933/ADE7932 is used to
sense Phase A, leave this pin unconnected.
Receives the bit streams from the Phase A ADE7933/ADE7932. Connect this pin to the DATA pin of the Phase A
ADE7933/ADE7932. If no ADE7933/ADE7932 is used to sense Phase A, connect this pin to VDD.
Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad on the PCB to
confer mechanical strength to the package. Connect the pads to DGND and GND.
Rev. 0 | Page 18 of 120
ADE7978/ADE7933/ADE7932
VDDISO 1
20
GND
GNDISO 2
19
VDD
V2P 3
18
EMI_CTRL
17
V2/TEMP
16
RESET_EN
15
DATA
IP 7
14
XTAL2
LDO 8
13
XTAL1
REF 9
12
SYNC
GNDISO 10
11
GND
ADE7932/
ADE7933
V1P 4
VM 5
TOP VIEW
(Not to Scale)
IM 6
11116-012
Data Sheet
Figure 11. Pin Configuration, ADE7933/ADE7932
Table 14. Pin Function Descriptions, ADE7933/ADE7932
Pin No.
1
Mnemonic
VDDISO
2, 10
GNDISO
3, 4, 5
V2P, V1P, VM
6, 7
IM, IP
8
LDO
9
REF
11, 20
12
GND
SYNC
13
XTAL1
14
XTAL2
15
DATA
16
RESET_EN
17
V2/TEMP
Description
Isolated Secondary Side Supply Voltage. This pin provides access to the 3.3 V on-chip isolated power supply.
Do not connect active external circuitry to this pin. Decouple this pin with a 10 µF capacitor in parallel with a
ceramic 0.1 µF capacitor.
Ground Reference for the Isolated Secondary Side. This pin provides the ground reference for the analog
circuitry. Use this quiet ground reference for all analog circuitry.
Analog Inputs for the Voltage Channels. These channels are used with voltage transducers and are referred to in
this data sheet as the voltage channels. These inputs are pseudo differential voltage inputs with a maximum
signal level of ±0.5 V with respect to VM for specified operation. Use these pins with the related input circuitry,
as shown in Figure 34. The second voltage channel (V2P) is available on the ADE7933 only. If the V1P or V2P pin
is not used on the ADE7933, connect the pin to the VM pin. On the ADE7932, the V2P pin must always be
connected to the VM pin.
Analog Inputs for the Current Channel. This channel is used with shunts and is referred to in this data sheet as
the current channel. These inputs are pseudo differential voltage inputs with a maximum differential level of
±31.25 mV. Use these pins with the related input circuitry, as shown in Figure 34.
2.5 V Output of the Analog Low Dropout (LDO) Regulator. Decouple this pin with a 4.7 µF capacitor in parallel
with a ceramic 100 nF capacitor using GNDISO (Pin 10). Do not connect active external circuitry to this pin.
Voltage Reference. This pin provides access to the on-chip voltage reference. The on-chip reference has a
nominal value of 1.2 V. Decouple this pin to GNDISO (Pin 10) with a 4.7 µF capacitor in parallel with a ceramic
100 nF capacitor.
Primary Ground Reference.
Synchronization Pin. The 4.096 MHz clock signal generated by the ADE7978 is used for serial communication
between the ADE7933/ADE7932 and the ADE7978. Connect the ADE7933/ADE7932 SYNC pin to the SYNC pin
of the ADE7978.
Master Clock. Connect this pin to the ADE7978 CLKOUT pin. The clock frequency for specified operation is
4.096 MHz. When the ADE7933/ADE7932 and the ADE7978 are used as a chipset, the ADE7933/ADE7932 must
function synchronously with the ADE7978; therefore, the XTAL1 pin of the ADE7933/ADE7932 must be connected to
the CLKOUT pin of the ADE7978. If the ADE7933/ADE7932 are used as standalone chips, a crystal with a maximum drive level of 0.5 mW and an ESR of 20 Ω can be connected across XTAL1 and XTAL2 to provide a clock source
for the ADE7933/ADE7932. The clock frequency for specified operation is 4.096 MHz, but lower frequencies
down to 3.6 MHz can be used. For more information, see the ADE7978 and ADE7933/ADE7932 Clocks section.
Leave this pin open when the ADE7933/ADE7932 are used with the ADE7978. If the ADE7933/ADE7932 are used
as standalone chips, a crystal with a maximum drive level of 0.5 mW and an ESR of 20 Ω can be connected across
XTAL1 and XTAL2 to provide a clock source for the ADE7933/ADE7932.
Data Output for Communication with the ADE7978. Connect the DATA pin to one of the following pins on the
ADE7978: DATA_A, DATA_B, DATA_C, or DATA_N. Connect the DATA pin of the Phase A ADE7933/ADE7932 to
the DATA_A pin of the ADE7978, and so on.
Reset Input Enable, Active Low. The ADE7933/ADE7932 is reset by setting the RESET_EN pin low and toggling
the V2/TEMP pin four times with a frequency of 4.096 MHz. The reset ends when this pin and the V2/TEMP pin
are set high (see the Hardware Reset section).
This input pin selects the signal that is converted at the second voltage channel of the ADE7933. (In the
ADE7932, the temperature sensor is always converted by the second voltage channel.) When this pin is high,
the voltage input V2P is sensed; when this pin is low, the temperature sensor is measured. The V2/TEMP pin is
also used during the ADE7933/ADE7932 reset procedure. For both the ADE7933 and ADE7932, the V2/TEMP
pin must always be connected to one of the following pins on the ADE7978: VT_A, VT_B, VT_C, or VT_N.
Connect the V2/TEMP pin of the Phase A ADE7933/ADE7932 to the VT_A pin of the ADE7978, and so on. For
more information, see the Second Voltage Channel and Temperature Measurement section.
Rev. 0 | Page 19 of 120
ADE7978/ADE7933/ADE7932
Pin No.
18
Mnemonic
EMI_CTRL
19
VDD
Data Sheet
Description
Emissions Control Pin. This pin manages the emissions of the ADE7933/ADE7932. When the pin is connected to
GND, the PWM control block of the dc-to-dc converter generates pulses during Slot 0, Slot 2, Slot 4, and Slot 6.
When the pin is connected to VDD, the PWM control block of the dc-to-dc converter generates pulses during
Slot 1, Slot 3, Slot 5, and Slot 7. (For more information, see the DC-to-DC Converter section.) Do not leave this
pin floating.
Primary Supply Voltage. This pin provides the supply voltage for the ADE7933/ADE7932. For specified operation,
maintain the supply voltage at 3.3 V ± 10%. Decouple this pin to GND with a 10 µF capacitor in parallel with a
ceramic 100 nF capacitor.
Rev. 0 | Page 20 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 12 through Figure 17 were generated using the following conditions: sinusoidal voltage with an amplitude of 50% of full scale and a
frequency of 50 Hz; sinusoidal current with variable amplitudes from 100% of full scale down to 0.033% of full scale and with a frequency
of 50 Hz; offset compensation executed.
1.0
0
–0.5
–0.5
–1.0
–1.0
–1.5
0.01
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
–1.5
0.01
1.5
1.0
1.5
TA = –40°C
TA = +25°C
TA = +85°C
1.0
–1.0
–1.0
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
–1.5
0.01
11116-114
ERROR (%)
ERROR (%)
–0.5
VDD = 2.97V
VDD = 3.30V
VDD = 3.63V
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 13. Total Reactive Energy Error as a Percentage of Reading
over Temperature, PF = 0
Figure 16. Total Reactive Energy Error as a Percentage of Reading
over Power Supply, PF = 0, TA = 25°C
1.5
TA = –40°C
TA = +25°C
TA = +85°C
1.0
VDD = 2.97V
VDD = 3.30V
VDD = 3.63V
0.5
ERROR (%)
0.5
0
0
–0.5
–1.0
–1.0
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
11116-115
–0.5
–1.5
0.1
100
0
–0.5
1.0
10
0.5
0
1.5
1
Figure 15. Total Active Energy Error as a Percentage of Reading
over Power Supply, PF = 1, TA = 25°C
0.5
–1.5
0.01
0.1
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 12. Total Active Energy Error as a Percentage of Reading
over Temperature, PF = 1
ERROR (%)
0
11116-120
ERROR (%)
0.5
11116-113
ERROR (%)
0.5
VDD = 2.97V
VDD = 3.30V
VDD = 3.63V
11116-121
1.0
1.5
TA = –40°C
TA = +25°C
TA = +85°C
Figure 14. Apparent Energy Error as a Percentage of Reading
over Temperature, PF = 1
–1.5
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 17. Apparent Energy Error as a Percentage of Reading
over Power Supply, PF = 1, TA = 25°C
Rev. 0 | Page 21 of 120
11116-122
1.5
ADE7978/ADE7933/ADE7932
Data Sheet
Figure 18 through Figure 23 were generated using the following conditions: fundamental voltage component in phase with 5th harmonic;
current with a 50 Hz component that has variable amplitudes from 100% of full scale down to 0.033% of full scale and a 5th harmonic with a
constant amplitude of 17% of full scale; power factor equal to 1 or 0 on the fundamental and 5th harmonic. Figure 18, Figure 19, Figure 21,
and Figure 22 were generated using a voltage with a 50 Hz component that has an amplitude of 50% of full scale and a 5th harmonic with an
amplitude of 5% of full scale. Figure 20 and Figure 23 were generated using a voltage with a 50 Hz component that has variable amplitudes
from 100% of full scale down to 0.033% of full scale and a 5th harmonic with an amplitude of 5% of full scale.
1.0
0
–0.5
–0.5
–1.0
–1.0
–1.5
0.01
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 18. Fundamental Active Energy Error as a Percentage of Reading
over Temperature, PF = 1
1.5
1.0
–1.5
0.01
1.5
1.0
–1.0
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
–1.5
0.01
11116-123
ERROR (%)
ERROR (%)
–1.0
Figure 19. Fundamental Active Energy Error as a Percentage of Reading
over Power Supply, PF = 1, TA = 25°C
VDD = 2.97V
VDD = 3.30V
VDD = 3.63V
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 22. Fundamental Reactive Energy Error as a Percentage of Reading
over Power Supply, PF = 0, TA = 25°C
1.5
TA = –40°C
TA = +25°C
TA = +85°C
1.0
TA = –40°C
TA = +25°C
TA = +85°C
0.5
ERROR (%)
0.5
0
0
–0.5
–0.5
–1.0
–1.0
1
10
PERCENTAGE OF FULL-SCALE CURRENT (%)
100
–1.5
0.1
11116-127
–1.5
0.1
100
0
–0.5
1.0
10
0.5
–0.5
1.5
1
Figure 21. Fundamental Reactive Energy Error as a Percentage of Reading
over Temperature, PF = 0
VDD = 2.97V
VDD = 3.30V
VDD = 3.63V
0
–1.5
0.01
0.1
PERCENTAGE OF FULL-SCALE CURRENT (%)
0.5
ERROR (%)
0
11116-117
ERROR (%)
0.5
11116-116
ERROR (%)
0.5
TA = –40°C
TA = +25°C
TA = +85°C
11116-124
1.0
1.5
TA = –40°C
TA = +25°C
TA = +85°C
Figure 20. Fundamental Current RMS Error as a Percentage of Reading
over Temperature, PF = 1
1
10
PERCENTAGE OF FULL-SCALE VOLTAGE (%)
100
11116-128
1.5
Figure 23. Fundamental Voltage RMS Error as a Percentage of Reading
over Temperature, PF = 1
Rev. 0 | Page 22 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Figure 24 and Figure 25 were generated using the following conditions: sinusoidal voltage with a constant amplitude of 50% of full scale;
sinusoidal current with a constant amplitude of 10% of full scale; variable frequency between 45 Hz and 65 Hz.
0.08
0.06
0.04
0.04
0.02
0.02
ERROR (%)
0.06
0
–0.02
0
–0.04
–0.06
–0.06
–0.08
–0.08
–0.10
40
45
50
55
60
65
70
LINE FREQUENCY (Hz)
Figure 24. Total Active Energy Error as a Percentage of Reading
over Frequency, PF = −0.5, +0.5, and +1
POWER FACTOR = –0.866
POWER FACTOR = 0
POWER FACTOR = +0.866
–0.02
–0.04
11116-118
ERROR (%)
0.08
0.10
POWER FACTOR = –0.5
POWER FACTOR = +1
POWER FACTOR = +0.5
–0.10
40
45
50
55
60
65
70
LINE FREQUENCY (Hz)
Figure 25. Total Reactive Energy Error as a Percentage of Reading
over Frequency, PF = −0.866, 0, and +0.866
Rev. 0 | Page 23 of 120
11116-119
0.10
ADE7978/ADE7933/ADE7932
Data Sheet
Figure 26 through Figure 29 were generated using the following conditions: sinusoidal current and voltage with variable amplitudes from
100% of full scale down to 0.033% of full scale. Figure 26 and Figure 28 were obtained using a frequency of 50 Hz; Figure 27 and Figure 29
were obtained using a variable frequency between 45 Hz and 65 Hz.
1.5
1.5
TA = –40°C
TA = +25°C
TA = +85°C
1.0
1.0
0
0
–0.5
–0.5
–1.0
–1.0
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
–1.5
0.1
Figure 26. Current RMS Error as a Percentage of Reading
over Temperature
0.10
0.08
0.06
0.06
0.04
0.04
0.02
0.02
ERROR (%)
0.10
0
–0.02
0
–0.02
–0.04
–0.06
–0.06
–0.08
–0.08
–0.10
50
55
60
65
LINE FREQUENCY (Hz)
70
11116-129
–0.04
45
100
Figure 28. Voltage RMS Error as a Percentage of Reading
over Temperature
0.08
40
10
1
PERCENTAGE OF FULL-SCALE VOLTAGE (%)
Figure 27. Current RMS Error as a Percentage of Reading
over Frequency
–0.10
40
45
50
55
60
65
LINE FREQUENCY (Hz)
Figure 29. Voltage RMS Error as a Percentage of Reading
over Frequency
Rev. 0 | Page 24 of 120
70
11116-130
–1.5
0.1
11116-126
ERROR (%)
0.5
11116-125
ERROR (%)
0.5
ERROR (%)
TA = –40°C
TA = +25°C
TA = +85°C
Data Sheet
ADE7978/ADE7933/ADE7932
1.5
1.0
1.0
0.5
0.5
–0.5
–0.5
–1.0
–1.0
–1.5
0.01
0.1
1
10
100
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 30. Total Active Energy Error as a Percentage of Reading, PF = 1
(Standard Deviation σ = 0.06% at 0.2% of Full-Scale Current
and σ = 0.12% at 0.05% of Full-Scale Current)
–1.5
0.01
1.0
1.0
0.5
0.5
ERROR (%)
1.5
–0.5
–1.0
–1.0
0.1
1
10
PERCENTAGE OF FULL-SCALE CURRENT (%)
100
Figure 31. Fundamental Active Energy Error as a Percentage of Reading, PF = 1
(Standard Deviation σ = 0.06% at 0.2% of Full-Scale Current
and σ = 0.11% at 0.05% of Full-Scale Current)
10
100
0
–0.5
–1.5
0.01
1
Figure 32. Total Reactive Energy Error as a Percentage of Reading, PF = 0
(Standard Deviation σ = 0.09% at 0.2% of Full-Scale Current
and σ = 0.13% at 0.05% of Full-Scale Current)
1.5
0
0.1
PERCENTAGE OF FULL-SCALE CURRENT (%)
–1.5
0.01
11116-132
ERROR (%)
0
0.1
1
10
PERCENTAGE OF FULL-SCALE CURRENT (%)
100
11116-134
0
11116-133
ERROR (%)
1.5
11116-131
ERROR (%)
Figure 30 through Figure 33 were generated using the following conditions: sinusoidal voltage with an amplitude of 50% of full scale and a
frequency of 50 Hz; sinusoidal current with variable amplitudes from 100% of full scale down to 0.033% of full scale and with a frequency
of 50 Hz; offset compensation executed. For Figure 31 and Figure 33, besides the fundamental component, the voltage contained a 5th harmonic
with a constant amplitude of 5% of full scale, and the current contained a 5th harmonic with a constant amplitude of 17% of full scale. Measurements at 25°C were repeated 30 times, and the standard deviation values were extracted for current levels of 0.2% and 0.05% of full scale.
Figure 33. Fundamental Reactive Energy Error as a Percentage of Reading, PF = 0
(Standard Deviation σ = 0.06% at 0.2% of Full-Scale Current
and σ = 0.13% at 0.05% of Full-Scale Current)
Rev. 0 | Page 25 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
TEST CIRCUIT
100nF
1kΩ
IPIN_A
150Ω
FERRITE
7
33nF
330kΩ
330kΩ
1kΩ
1kΩ
150Ω
FERRITE
6
IMIN_A
330kΩ
GNDISO
IP
VDD
GND
TS4148
150Ω
FERRITE
V1PIN_A
VDDISO
33nF
GND_A
150Ω
FERRITE
2
4
EMI_CTRL
IM
1kΩ
V1P
ADE7933A
DATA
TS4148
33nF
TS4148
5
33nF
V2/TEMP
VM
SYNC
TS4148
330kΩ 330kΩ
TS4148
3
330kΩ
V2PIN_A
RESET_EN
V2P
XTAL1
LDO
XTAL2
8
1kΩ
33nF
4.7µF
4.7µF
100nF
100nF
10
9
1
2
3
4
SAME AS IN
ADE7933 A
5
6
7
8
9
10
GNDISO
GND
19
3.3V
20
100nF
10kΩ
ADE7978
18
15
28
17
27
12
5
16
3
13
4
14
25
11
24
EMI_CTRL
SYNC
GNDISO
V2P
XTAL2
V1P
RESET_EN
V2/TEMP
VM
ADE7933B
IP
VDD
XTAL1
GNDISO
GND
2
3
4
SAME AS IN
ADE7933 A
5
6
7
8
9
10
1
2
3
4
5
SAME AS IN
ADE7933 A
6
7
8
9
10
VDDISO
EMI_CTRL
GNDISO
SYNC
V2P
DATA
RESET_EN
V1P
V2/TEMP
VM
IM
ADE7933C
VDD
IP
XTAL1
LDO
XTAL2
REF
GND
GNDISO
GND
VDDISO
EMI_CTRL
GNDISO
SYNC
V2P
XTAL2
V1P
RESET_EN
VM
IM
V2/TEMP
ADE7933N
IP
LDO
VDD
XTAL1
DATA
REF
GND
GNDISO
GND
11
TO MCU
3.3V
RESET_EN
1µF
CLKOUT
10kΩ
3.3V
12
XTALIN
RESET
XTALOUT
CF1
13
12
10kΩ
14
10kΩ
16
1
17
CF2
VT_B
SAME AS IN
ADE7933 A
19
13
CF3/HSCLK
2
SS/HSA
DATA_B
3.3V
20
SCLK/SCL
MISO/HSD
10kΩ
1
IRQ1
SYNC
18
DATA
11
GND
REF
TO MCU
20pF
15
LDO
VT_A
80.6Ω
20pF
VDDISO
IRQ0 10
DATA_A
16.384MHz
REF
IM
3.3V
10µF
3.3V
10µF
18
100nF
21
20
VDD
MOSI/SDA
GND
ZX/DREADY
14
15
16
17
18
19
26
SAME AS
CF1
TO MCU
TO MCU
TO MCU
TO MCU
TO MCU
TO MCU
12
7
15
DATA_C
16
6
17
19
VT_C
SAME AS IN
ADE7933 A
13
14
11
3.3V
4.7µF
100nF
22
23
20
LDO
DGND
18
12
14
10kΩ
16
8
17
19
13
15
VT_N
SAME AS IN
ADE7933 A
9
DATA_N
11
20
Figure 34. Test Circuit
Rev. 0 | Page 26 of 120
11116-014
1
10µF
Data Sheet
ADE7978/ADE7933/ADE7932
TERMINOLOGY
Energy Measurement Error
The accuracy of the energy measurement is assessed as follows:
1.
2.
3.
The voltage channel is supplied with a sinusoidal signal that
has peak values equal to ±250 mV. This value represents
half of the full scale.
The current channel is supplied with sinusoidal signals that
have peak values equal to ±31.25 mV (full scale), ±3.125 mV
(1/10 of full scale), ±312.5 µV (1/100 of full scale), ±31.25 µV
(1/1000 of full scale), and ±15.625 µV (1/2000 of full scale).
The energy is accumulated in line cycle accumulation mode,
and the accumulation time varies with the current channel
signal level.
The energy calculated for current peaks equal to ±3.125 mV
(1/10 of full scale) is considered the reference. The energy
measurement error is computed relative to a straight line that
passes through this point, as follows:
AccTime(I 1/10 ) I 1/10


×

 Energy (I x ) ×
Ix
AccTime(I x )


− 1 × 100% (1)
ε=
Energy (I 1/10 )






where:
Energy(Ix) is the energy measurement when the current is Ix.
Energy(I1/10) is the energy measurement when the current
is I1/10. This is the reference measurement.
AccTime(I1/10) is the accumulation time used to measure
Energy(I1/10).
AccTime(Ix) is the accumulation time used to measure
Energy(Ix).
2.
The voltage and current channels are supplied with sinusoidal signals of various peaks, starting with the full-scale
signals (±500 mV for the voltage channel and ±31.25 mV
for the current channel) and ending with ±1 mV and
±62.5 µV, respectively.
The rms registers are read at least once per line cycle over
1 sec and averaged.
The measurement performed when the input signal has peaks
equal to 1/10 of full scale is considered the reference. The rms
measurement error is computed relative to a straight line that
passes through this point, as follows:
I 1/10


 I rms(I x ) ×

Ix
εI = 
− 1 × 100%
 I rms(I 1/10 )





(3)
where:
I rms(Ix) is the current rms measurement when the current is Ix.
I rms(I1/10) is the current rms measurement when the current is
I1/10. This is the reference measurement.
V rms(Vx) is the voltage rms measurement when the voltage
is Vx.
V rms(V1/10) is the voltage rms measurement when the voltage is
V1/10. This is the reference measurement.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The spectral components are calculated over a 2 sec window. The value for SNR is
expressed in decibels.
Signal-to-Noise-and-Distortion (SINAD) Ratio
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The spectral
components are calculated over a 2 sec window. The value for
SINAD is expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of all harmonics (excluding
the noise components) to the rms value of the fundamental.
The spectral components are calculated over a 2 sec window.
The value for THD is expressed in decibels.
I rms and V rms Measurement Error
The accuracy of the rms measurement is assessed as follows:
1.
V1/10


 V rms(Vx ) ×

V
x
εV = 
− 1 × 100%
 V rms(V1/10 )





Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the rms value of the actual input signal to the
rms value of the peak spurious component over the measurement
bandwidth of the waveform samples. The spectral components are
calculated over a 2 sec window. The value of SFDR is expressed
in decibels relative to full scale, dBFS.
CF Jitter
The period of pulses at one of the CF1, CF2, or CF3 pins is
continuously measured. The maximum, minimum, and average
values of four consecutive pulses are computed as follows:
Maximum = max(Period0, Period1, Period2, Period3)
Minimum = min(Period0, Period1, Period2, Period3)
Average =
(2)
Period 0 + Period1 + Period 2 + Period 3
4
The CF jitter is then computed as follows:
CFJITTER =
Rev. 0 | Page 27 of 120
Maximum − Minimum
Average
× 100%
(4)
ADE7978/ADE7933/ADE7932
Data Sheet
Pseudo Differential Signal Voltage Range Between the IP
and IM Pins, V1P and VM Pins, and V2P and VM Pins
This range represents the peak-to-peak pseudo differential voltage that must be applied to the ADCs to generate a full-scale
response when the IM and VM pins are connected to the GNDISO
pin (Pin 2). The IM and VM pins are connected to the GNDISO
pin using antialiasing filters (see Figure 34).
Figure 35 shows the input voltage range between the IP and IM
pins. Figure 36 shows the input voltage range between the V1P
and VM pins and between the V2P and VM pins.
+31.25mV
IP
–31.25mV
0V
IP – IM
+31.25mV
Crosstalk is equal to the ratio between the grounded ADC
output value and the ADC full-scale output value. The ADC
outputs are acquired for 2 sec. Crosstalk is expressed in decibels.
–31.25mV
11116-015
0V
Figure 35. Pseudo Differential Input Voltage Range
Between the IP and IM Pins
V1P, V2P
0V
ADC Offset Error
ADC offset error is the difference between the average measured
ADC output code with both inputs connected to GNDISO and the
ideal ADC output code. The magnitude of the offset depends
on the input range of each channel.
–500mV
0V
V1P – VM,
V2P – VM
Input Impedance to Ground, DC
The input impedance to ground represents the impedance
measured at each ADC input pin (IP, IM, V1P, V2P, and VM)
with respect to GNDISO (Pin 10).
Differential Input Impedance, DC
The differential input impedance represents the impedance
measured between the ADC inputs: IP and IM, V1P and VM,
and V2P and VM (ADE7933 only).
+500mV
VM
Crosstalk
Crosstalk represents the leakage of signals, usually via capacitance
between circuits. Crosstalk in the current channel is measured by
setting the IP and IM pins to the GNDISO pin (Pin 10), supplying
a full-scale alternate differential voltage between the V1P, V2P,
and VM pins of the voltage channel, and measuring the output
of the current channel.
Crosstalk in the V1P voltage channel is measured by setting the
V1P and VM pins to the GNDISO pin (Pin 10), supplying a fullscale alternate differential voltage at the IP and V2P pins, and
measuring the output of the V1P channel. Crosstalk in the V2P
voltage channel is measured by setting the V2P and VM pins to
the GNDISO pin (Pin 10), supplying a full-scale alternate differential voltage at the IP and V1P pins, and measuring the output
of the V2P channel.
0V
IM
Maximum VM and IM Voltage Range
The maximum VM and IM voltage range represents the maximum allowed voltage at the VM and IM pins relative to the
GNDISO pin (Pin 10).
ADC Offset Drift over Temperature
ADC offset drift is the change in offset over temperature.
ADC offset drift is determined by measuring the ADC offset
at −40°C, +25°C, and +85°C. The offset drift over temperature
is computed as follows:
+500mV
–500mV
11116-016
0V
Figure 36. Pseudo Differential Input Voltage Range
Between the V1P and VM Pins and Between the V2P and VM Pins
Drift =
 Offset (− 40° C ) − Offset (25° C ) Offset (85° C ) − Offset (25° C ) 
max 
)
),
(
) (
(
) (
 Offset 25° C × − 40° C − 25° C Offset 25° C × 85° C − 25° C 
Offset drift is expressed in nV/°C.
Rev. 0 | Page 28 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Gain Error
Gain error in the ADE7933/ADE7932 represents the difference
between the measured ADC output code (minus the offset) and
the ideal output code (see the Current Channel ADC and Voltage
Channel ADCs sections). The difference is expressed as a percentage of the ideal code and represents the overall gain error of one
current or voltage channel.
Gain Drift over Temperature
Gain drift is the change in gain over temperature. The gain
temperature coefficient includes the temperature variation of the
ADC gain and of the internal voltage reference. Gain drift over
temperature represents the overall temperature coefficient of one
current or voltage channel. With the internal voltage reference
in use, the ADC gain is measured at −40°C, +25°C, and +85°C.
The temperature coefficient is computed as follows:
Drift =
 Gain(− 40° C ) − Gain(25° C ) Gain(85° C ) − Gain(25° C ) 
max 
,

 Gain(25° C ) × (− 40° C − 25° C ) Gain(25° C ) × (85° C − 25° C ) 
Power Supply Rejection (PSR)
PSR quantifies the ADE7978 and ADE7933/ADE7932 chipset
measurement error as a percentage of reading when the power
supplies are varied. For the ac PSR measurement, a reading at
nominal supplies (3.3 V) is taken when the voltage at the input
pins is 0 V. A second reading is obtained with the same input
signal levels when an ac signal (120 mV rms at 50 Hz or
100 Hz) is introduced onto the supplies. Any error introduced
by this ac signal is expressed as a percentage of reading (power
supply rejection ratio, PSRR). PSR = 20 log10 (PSRR).
For the dc PSR measurement, a reading at nominal supplies
(3.3 V) is taken when the voltage between the IP and IM pins is
6.25 mV rms, and the voltages between the V1P, V2P, and VM
pins are 100 mV rms. A second reading is obtained with the
same input signal levels when the power supplies are varied by
±10%. Any error introduced is expressed as a percentage of the
reading (PSRR). PSR = 20 log10 (PSRR).
Gain drift is measured in ppm of FS/°C.
Rev. 0 | Page 29 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
THEORY OF OPERATION
ADE7933/ADE7932 ANALOG INPUTS
V1
The ADE7933 has three analog input channels: one current
channel and two voltage channels. The ADE7932 does not
include the second voltage channel. The current channel has
two fully differential voltage input pins, IP and IM, that accept
a maximum differential signal of ±31.25 mV.
+500mV
VIP
IM
11116-031
VIM
Figure 37. Maximum Input Level, Current Channel
The current channel is used to sense the voltage across a shunt.
In this case, one pole of the shunt becomes the ground of the
meter (see Figure 101) and, therefore, the current channel is
used in a pseudo differential configuration, similar to the
voltage channel configuration (see Figure 38).
The voltage channels have two pseudo differential, single-ended
voltage input pins: V1P and V2P. These single-ended voltage
inputs have a maximum input voltage of ±500 mV with respect
to VM. The maximum signal allowed at the VM input is ±25 mV.
Figure 38 shows a schematic of the voltage channel inputs and
their relation to the maximum VM pin voltage.
ANALOG-TO-DIGITAL CONVERSION
The ADE7933/ADE7932 have three second-order Σ-Δ ADCs.
For simplicity, the block diagram in Figure 39 shows a first-order
Σ-Δ ADC. The converter is composed of the Σ-Δ modulator and
the digital low-pass filter, separated by the digital isolation block.
For any given input value in a single sampling interval, the data
from the 1-bit ADC is virtually meaningless. A meaningful result
is obtained only when a large number of samples is averaged. This
averaging is carried out in the second part of the ADC, the digital
low-pass filter, after the data is passed through the digital isolators.
By averaging a large number of bits from the modulator, the lowpass filter can produce 24-bit data-words that are proportional
to the input signal level.
ISOLATION
BARRIER
CLKIN/16
ANALOG
LOW-PASS
FILTER
+
C
+
–
DIGITAL
LOW-PASS
FILTER
LATCHED
COMPARATOR
–
DIGITAL
ISOLATION
VREF
24
ADE7978
.....10100101.....
1-BIT DAC
11116-033
R
INTEGRATOR
11116-032
Figure 38. Maximum Input Level, Voltage Channels
A Σ-Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7933/ADE7932, the sampling clock is equal to
1.024 MHz (CLKIN/16). The 1-bit DAC in the feedback loop is
driven by the serial data stream. The DAC output is subtracted
from the input signal. If the loop gain is high enough, the average
value of the DAC output (and, therefore, the bit stream) can
approach that of the input signal level.
IP
0V
–31.25mV
VM
VM
–500mV
VIP = ±31.25mV MAX PEAK
VIM = ±25mV MAX
+31.25mV
V1P OR
V2P
V1
0V
The maximum differential signal level on the IP and IM pins
with respect to GNDISO is also ±31.25 mV. However, the maximum signal allowed at the IM input is ±25 mV. Figure 37 shows
a schematic of the current channel input and its relation to the
maximum IM pin voltage.
VIP
V1 = ±500mV MAX PEAK
VM = ±25mV MAX
ADE7932/ADE7933
Figure 39. First-Order Σ-∆ ADC
Rev. 0 | Page 30 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Oversampling
Oversampling is the first technique used to achieve high resolution. Oversampling means that the signal is sampled at a rate
(frequency) that is many times higher than the bandwidth of
interest. For example, when CLKIN = 4.096 MHz, the sampling
rate in the ADE7933/ADE7932 is 1.024 MHz, whereas the bandwidth of interest is 40 Hz to 3.3 kHz. Oversampling has the effect
of spreading the quantization noise (noise due to sampling) over
a wider bandwidth. With the noise spread more thinly over a
wider bandwidth, the quantization noise in the band of interest
is lowered (see Figure 40).
Antialiasing Filter
As shown in Figure 39, an external low-pass analog RC filter is
required on the input to the ADE7933/ADE7932 ADC. The role
of this filter is to prevent aliasing. Aliasing is an artifact of all
sampled systems, as shown in Figure 41. Aliasing refers to the
frequency components in the input signal to the ADC that are
imaged or folded back and appear in the sampled signal at a
frequency below half the sampling rate. This effect occurs with
signals that are higher than half the sampling rate of the ADC
(also known as the Nyquist frequency, that is, 512 kHz).
ALIASING EFFECTS
ANTIALIASING FILTER
ADE7978
(RC)
DIGITAL FILTER
SHAPED NOISE
SAMPLING
FREQUENCY
SIGNAL
0
3.3
4
512
FREQUENCY (kHz)
IMAGE
FREQUENCIES
NOISE
SAMPLING
FREQUENCY
1024
11116-035
The Σ-∆ converter uses two techniques—oversampling and noise
shaping—to achieve high resolution from what is essentially a
1-bit conversion technique.
Figure 41. Aliasing Effects
0
3.3 4
512
FREQUENCY (kHz)
1024
HIGH RESOLUTION
OUTPUT FROM
ADE7978 DIGITAL LPF
SIGNAL
0
3.3 4
512
FREQUENCY (kHz)
1024
11116-034
NOISE
Figure 40. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
However, oversampling alone is not sufficient to improve the
signal-to-noise ratio (SNR) in the bandwidth of interest. For
example, an oversampling ratio of 4 is required to increase the
SNR by only 6 dB (1 bit). To keep the oversampling ratio at a
reasonable level, it is possible to shape the quantization noise so
that the majority of the noise lies at the higher frequencies (see
the Noise Shaping section).
Noise Shaping
Noise shaping is the second technique used to achieve high
resolution. In the Σ-∆ modulator, the noise is shaped by the
integrator, which has a high-pass type response for the quantization noise. The result is that most of the noise is at the higher
frequencies where it can be removed by the digital low-pass
filter in the ADE7978. This noise shaping is shown in Figure 40.
In Figure 41, only frequencies near the sampling frequency of
1.024 MHz move into the band of interest for metering, that is,
40 Hz to 3.3 kHz. To attenuate high frequency (near 1.024 MHz)
noise and prevent the distortion of the band of interest, a low-pass
filter (LPF) must be introduced. It is recommended that one RC
filter with a corner frequency of 5 kHz be used for the attenuation
to be sufficiently high at the sampling frequency of 1.024 MHz.
The 20 dB per decade attenuation of this filter is usually sufficient
to eliminate the effects of aliasing for conventional current sensors.
ADC Transfer Function
The ADE7933/ADE7932 provide a stream of bits at the DATA
pin based on the SYNC clock signal provided by the ADE7978
(see the Bit Stream Communication Between the ADE7978 and
the ADE7933/ADE7932 section). The ADE7978 digital filter
processes the bit streams coming from all ADE7933/ADE7932
devices in the system and produces the 24-bit signed output
codes of the ADCs.
With a full-scale input signal of ±31.25 mV on the current
channel and ±0.5 V on the voltage channels and with an internal
reference of 1.2 V, the ADC output code is nominally 5,320,000
and usually varies for each ADE7933/ADE7932 around this value.
The code obtained by the ADE7978 from the ADE7933/ADE7932
ADCs can vary from 0x800000 (−8,388,608) to 0x7FFFFF
(+8,388,607); this code is equivalent to an input signal level of
±49.27 mV on the current channel and ±0.788 V on the voltage
channels. However, for specified performance, do not exceed the
nominal range of ±31.25 mV for the current channel and ±0.5 V
for the voltage channels; ADC performance is guaranteed only
for input signals within these limits.
Rev. 0 | Page 31 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
CURRENT CHANNEL ADC
With the specified full-scale analog input signal of ±31.25 mV, the
ADC produces its maximum output code value. Figure 42 shows
a full-scale voltage signal applied to the differential inputs (IP and
IM). The ADC output swings from −5,320,000 to +5,320,000.
Note that these are nominal values, and every ADE7978/
ADE7933/ADE7932 chipset varies around these values.
In this data sheet, the measurements obtained on the current
channel of the ADE7933/ADE7932 devices that monitor Phase A,
Phase B, and Phase C are called IA, IB, and IC, respectively (see
Figure 101). The measurement obtained on the current channel
of the ADE7933/ADE7932 device that monitors the neutral
current is called IN (see Figure 102).
Input IN corresponds to the neutral current of a 3-phase system.
If the neutral line is not monitored, connect the DATA_N pin
of the ADE7978 to VDD. The datapath of the neutral current is
similar to the path of the phase currents, as shown in Figure 43.
Figure 42 shows the signal processing path for Input IA in the
current channel (the path is the same for IB and IC). The ADC
outputs are signed twos complement 24-bit data-words and are
available at a rate 8000 samples per second (8 kSPS).
ADE7978
LPF1
TEMPCO[23:0]
0x512D40 =
+5,320,000
FUNDAMENTAL CURRENT
RMS (AFIRMS) CALCULATION
PHASE A
ATEMP0[23:0]
ADE7933
REFERENCE
AIGAIN[23:0]
DIGITAL
LPF
0V
CURRENT RMS (AIRMS)
CALCULATIONS
1
IP
Σ-Δ
MODULATOR
ZX SIGNAL DATA RANGE
CURRENT PEAK,
OVERCURRENT DETECTION
ATEMP[23:0]
VIN
ZX DETECTION
HPFEN BIT
CONFIG[4]
IAWV WAVEFORM
SAMPLE REGISTER
0xFFAED2C0 =
–5,320,000
TOTAL/FUNDAMENTAL
ACTIVE AND REACTIVE
POWER CALCULATION
HPF
IM
CURRENT CHANNEL DATA RANGE
CURRENT CHANNEL DATA RANGE
AFTER HPF
+31.25mV
0x512D40 =
+5,320,000
0x512D40 =
+5,320,000
0V
0V
0V
ANALOG INPUT RANGE
0xFFAED2C0 =
–5,320,000
0xFFAED2C0 =
–5,320,000
ADC OUTPUT RANGE
Figure 42. Phase A Current Channel Signal Path
ADE7978
TEMPCO[23:0]
NTEMP[23:0]
NEUTRAL LINE
NTEMP0[23:0]
ADE7933
1
REFERENCE
NIGAIN[23:0]
IP
Σ-Δ
MODULATOR
VIN
DIGITAL
LPF
HPFEN BIT
CONFIG[4]
HPF
IM
Figure 43. Neutral Current Signal Path
Rev. 0 | Page 32 of 120
INWV WAVEFORM
SAMPLE REGISTER
CURRENT RMS (NIRMS)
CALCULATION
11116-037
–31.25mV
11116-036
VIN
Data Sheet
ADE7978/ADE7933/ADE7932
Current Waveform Gain Registers
There is a multiplier in the signal path of each phase and neutral
current. The current waveform can be changed by ±100% by
writing a corresponding twos complement number to the 24-bit
signed current waveform gain registers (AIGAIN, BIGAIN,
CIGAIN, and NIGAIN). For example, if 0x400000 is written to
these registers, the ADC output is scaled up by 50%. To scale
the output by −50%, write 0xC00000 to the registers. Equation 5
describes mathematically the function of the current waveform
gain registers.
Current Waveform =
(5)
Contents of Current Gain Register 


ADC Output × 1 +
2 23


Changing the contents of the AIGAIN, BIGAIN, CIGAIN, or
NIGAIN register affects all calculations based on the current
of the corresponding phase, including the active, reactive, and
apparent energy and the current rms calculations. In addition,
waveform samples scale accordingly.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. The 24-bit
AIGAIN, BIGAIN, CIGAIN, and NIGAIN registers are sign
extended to 28 bits and padded with four 0s for transmission
as 32-bit registers (see Figure 44).
28 27
24 23
0000
BIT 23 IS A SIGN BIT
Figure 44. 24-Bit xIGAIN Register Transmitted as a 32-Bit Signed Word
The ADE7933/ADE7932 contain a temperature sensor that is
internally multiplexed with the second voltage measurement,
V2P (see the Second Voltage Channel and Temperature
Measurement section). The ADE7978 assumes that all shunts
used in the system have the same temperature coefficient. The
24-bit signed register TEMPCO contains the value of the
temperature coefficient.
Assume that the shunt resistance, R, varies linearly according
to the following formula:
R = R0 × [1 + ε × (T − T0)]
Equation 8 describes mathematically the function of the current
waveform temperature compensation.
Current Waveform =
ADC Output ×
A simple approach to implement temperature compensation is
to use the temperature measurements without any gain correction
(see the Second Voltage Channel and Temperature Measurement
section). The xTEMP and xTEMP0 registers contain the temperature sensor measurements. Set the 24-bit signed register
TEMPCO to the following value:
TEMPCO = ε × k × 246
(9)
where:
ε is the temperature coefficient of the shunt.
k = 8.72101 × 10−5 is the gain correction of the temperature
measurement.
For example, if ε = 50 ppm/°C,
TEMPCO = round(50 × 10−6 × 8.72101 × 10−5 × 246) =
306,843 = 0x4AE9B
(6)
where:
R0 is the shunt resistance at the nominal temperature, T0.
ε is the temperature coefficient of the shunt.
T is the temperature of the shunt.
The maximum value that can be written to the TEMPCO
register is 0x7FFFFF. This value translates into a maximum
temperature coefficient that can be compensated equal to
To compensate for the increase in resistance, the current waveform must be divided by 1 + ε × (T − T0). Because ε is a very
small number, this expression is equivalent to a multiplication
by 1 − ε × (T − T0). This multiplication is introduced in the
datapath signal of each phase and neutral current.
Current Waveform =
ADC Output × [1 − ε × (T − T0)]
(8)
where TEMPCO, TEMP, and TEMP0 represent the contents
of the registers with the same name.
0
24-BIT NUMBER
BITS[27:24] ARE
EQUAL TO BIT 23
The temperature sensor measurement starts when the VT_A,
VT_B, VT_C, and VT_N pins of the ADE7978 are set low; the
results are first stored in the ATEMP, BTEMP, CTEMP, and
NTEMP registers after 1.024 sec (see the Second Voltage Channel
and Temperature Measurement section). At this point, the temperature compensation scheme becomes active and works at an
8 kHz update rate. Therefore, ATEMP, BTEMP, CTEMP, and
NTEMP represent the temperature (T) in Equation 7.

IGAIN  
TEMPCO  TEMP
TEMP0 
 × 1 −

× 
−
1 +
23
23
23
2
2
2 23 

 
 2
11116-038
31
The 24-bit signed ATEMP0, BTEMP0, CTEMP0, and NTEMP0
registers represent the ambient temperature (T0) at which the
meter temperature sensor gain calibration was executed on
every phase (see the Second Voltage Channel and Temperature
Measurement section). The 24-bit signed ATEMP, BTEMP,
CTEMP, and NTEMP registers represent the shunt temperatures (T) measured by the temperature sensor of every ADE7933/
ADE7932 in the system.
(7)
Rev. 0 | Page 33 of 120
ε MAX =
1
2 × 8.72101 × 10 −5
23
= 1367 ppm/ ° C
ADE7978/ADE7933/ADE7932
Data Sheet
The ADC outputs may contain a dc offset that can create errors in
power and rms calculations. High-pass filters (HPFs) are placed
in the signal path of the phase and neutral currents and in the
signal path of the phase voltages. When the HPF is enabled, the
filter eliminates any dc offset on the current channel. All filters
in both current and voltage channels are implemented in the DSP
and are enabled by default: Bit 4 (HPFEN) of the CONFIG register
(Address 0xE618) is set to 1. All filters are disabled by setting
Bit 4 (HPFEN) to 0.
Current Channel Sampling
The waveform samples of the current channel are taken at the
output of the HPF and stored in the 24-bit signed IAWV, IBWV,
ICWV, and INWV registers at a rate of 8 kSPS. All power and
rms calculations remain uninterrupted during this process.
Bit 17 (DREADY) in the STATUS0 register (Address 0xE502) is
set when the IAWV, IBWV, ICWV, and INWV registers are available to be read using the I2C or SPI serial port. Setting Bit 17
(DREADY) in the MASK0 register (Address 0xE50A) enables
an interrupt to be set when the DREADY flag is set. For more
information about the DREADY bit, see the Digital Signal
Processor section.
The low to high transition of the ZX/DREADY pin can be used
to initiate a burst read of the waveform sample registers. For more
information, see the I2C Burst Read Operation and the SPI Burst
Read Operation sections.
For information about using the ZX functionality at the
ZX/DREADY pin (ZX_DREADY bits in the CONFIG register
are set to 01, 10, or 11), see the Zero-Crossing Detection section.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. When the
24-bit signed IAWV, IBWV, ICWV, and INWV registers are
read from the ADE7978, they are transmitted as sign extended
32-bit registers (see Figure 45).
31
24 23 22
0
24-BIT SIGNED NUMBER
BITS[31:24] ARE
EQUAL TO BIT 23
BIT 23 IS A SIGN BIT
11116-039
Current Channel HPF
Figure 45. 24-Bit IxWV Register Transmitted as a 32-Bit Signed Word
The ADE7978 contains a high speed data capture (HSDC) port
that is specially designed to provide fast access to the waveform
sample registers. For more information, see the HSDC Interface
section.
In addition, if Bits[1:0] (ZX_DREADY) in the CONFIG register
are set to 00, the DREADY functionality is selected at the
ZX/DREADY pin. In this case, the pin goes low approximately
70 ns after the DREADY bit is set to 1 in the STATUS0 register.
The ZX/DREADY pin stays low for 10 µs and then returns high.
Rev. 0 | Page 34 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
VOLTAGE CHANNEL ADCs
The ADC outputs are signed twos complement 24-bit words
and are available at a rate of 8 kSPS.
In this data sheet, the measurements obtained on the voltage
channel of the ADE7933/ADE7932 devices that monitor Phase A,
Phase B, and Phase C are called VA, VB, and VC, respectively. The
measurement obtained on the voltage channel of the ADE7933/
ADE7932 device that monitors the neutral current is called VN
(see Figure 102). VA, VB, VC, and VN represent the signals measured between the V1P and VM pins of the ADE7933/ADE7932
devices in the system. The signals measured between the V2P and
VM pins of the ADE7933/ADE7932 devices are called VA2, VB2,
VC2, and VN2 (see the Second Voltage Channel and Temperature
Measurement section).
With the specified full-scale analog input signal of ±0.5 V, the
ADC produces its maximum output code value. Figure 46 shows
a full-scale voltage signal applied to the differential inputs (V1P
and VM). The ADC output swings from −5,320,000 to +5,320,000.
Note these are nominal values, and every ADE7978/ADE7933/
ADE7932 chipset varies around these values.
Input VN between the V1P and VM pins of the neutral line
ADE7933/ADE7932 corresponds to the earth to neutral voltage
of a 3-phase system. If no voltage is monitored at the V1P pin,
connect the V1P pin to the VM pin. The datapath of the earth
to neutral voltage is similar to the path of the phase voltages, as
shown in Figure 47.
Figure 46 shows the ADC and signal processing chain for Input VA
in the voltage channel (the path is the same for VB and VC).
VOLTAGE PEAK,
OVERVOLTAGE, SAG DETECTION
ADE7978
FUNDAMENTAL VOLTAGE RMS
(AFVRMS) CALCULATION
VOLTAGE RMS (AVRMS)
CALCULATION
PHASE A
ADE7933
AVGAIN[23:0]
V1P
Σ-Δ
MODULATOR
VIN
VAWV WAVEFORM
SAMPLE REGISTER
HPFEN BIT
CONFIG[4]
REFERENCE
DIGITAL
LPF
TOTAL/FUNDAMENTAL
ACTIVE AND REACTIVE
POWER CALCULATION
HPF
LPF1
ZX DETECTION
VM
ZX SIGNAL DATA RANGE
VOLTAGE CHANNEL
DATA RANGE
+0.5V
0x512D40 =
+5,320,000
0x512D40 =
+5,320,000
0V
0V
0V
0xFFAED2C0 =
–5,320,000
ANALOG INPUT RANGE
ADC OUTPUT RANGE
0xFFAED2C0 =
–5,320,000
Figure 46. Phase A to Neutral Voltage Channel Datapath
ADE7978
NEUTRAL LINE
ADE7933
REFERENCE
NVGAIN[23:0]
V1P
Σ-Δ
MODULATOR
VIN
DIGITAL
LPF
HPFEN BIT
CONFIG[4]
HPF
VNWV WAVEFORM
SAMPLE REGISTER
VOLTAGE RMS (NVRMS)
CALCULATION
VM
VIN
VOLTAGE CHANNEL
DATA RANGE
+0.5V
0x512D40 =
+5,320,000
0V
0V
–0.5V
ANALOG INPUT RANGE
0xFFAED2C0 =
–5,320,000
ADC OUTPUT RANGE
Figure 47. Earth to Neutral Voltage Channel Datapath
Rev. 0 | Page 35 of 120
11116-041
–0.5V
11116-040
VIN
ADE7978/ADE7933/ADE7932
Data Sheet
Second Voltage Channel and Temperature Measurement
Although the Vx2 channel is not available on the ADE7932,
the V2/TEMP pin must still be connected to the corresponding
VT_A, VT_B, VT_C, or VT_N pin of the ADE7978.
Figure 48 shows the ADC and signal processing chain for the
Input VA2 in the voltage channel (ADE7933 only). The VB2,
VC2, and VN2 channels have similar processing chains. The
V2P input pin of the ADE7933/ADE7932 is multiplexed with a
temperature sensor. On the ADE7932, the Vx2 channel is not
available, and the V2P pin must be connected to the VM pin.
On the ADE7933, if no voltage is monitored at the V2P pin,
connect the V2P pin to the VM pin.
The V2/TEMP pin is also used during the reset procedure
of the ADE7933/ADE7932 (see the Hardware Reset section).
On the ADE7978, the selection of the second voltage channel
or the temperature sensor is based on Bits[3:0] (VN2_EN,
VC2_EN, VB2_EN, and VA2_EN) in the CONFIG3 register
(Address 0xE708). When these bits are set to 1 (the default value),
the VT_A, VT_B, VT_C, and VT_N pins are set high, and VA2,
VB2, VC2, and VN2 are measured. When the bits are cleared to
0, the VT_A, VT_B, VT_C, and VT_N pins are set low, and the
temperature sensors of each ADE7933/ADE7932 are measured.
This is true even on the ADE7932 where the temperature sensor
is always measured.
On the ADE7933/ADE7932, the selection of the second voltage
channel or the temperature sensor is based on the state of the
V2/TEMP pin. Connect the V2/TEMP pin of the ADE7933/
ADE7932 to the appropriate pin of the ADE7978 (see Figure 1
and Table 15).
Table 15. Connecting the ADE7933/ADE7932 V2/TEMP Pin
to the ADE7978
ADE7933/ADE7932
Monitors This Phase
Phase A
Phase B
Phase C
Phase N
V2/TEMP Pin of the ADE7933/ADE7932
Connected to This Pin on the ADE7978
VT_A
VT_B
VT_C
VT_N
PHASE A
ADE7978
ADE7933
TEMPERATURE
SENSOR
HPFEN BIT
CONFIG[4]
REFERENCE
AV2GAIN[23:0]
V2P
Σ-Δ
MODULATOR
VIN
VM
DIGITAL
LPF
VT_A
VIN
+0.5V
HPF
VOLTAGE RMS (AV2RMS)
CALCULATION
BIT 0 (VA2_EN) IN
CONFIG3 REGISTER
SET TO 1
VOLTAGE CHANNEL DATA RANGE
WHEN V2P IS SELECTED
0x512D40 =
+5,320,000
0V
ANALOG INPUT RANGE
0xFFAED2C0 =
–5,320,000
ADC OUTPUT RANGE
Figure 48. Phase A V2P Channel Datapath (ADE7933 Only)
Rev. 0 | Page 36 of 120
11116-042
0V
–0.5V
VA2WV WAVEFORM
SAMPLE REGISTER
Data Sheet
ADE7978/ADE7933/ADE7932
The temperature measurements are also used in the current
channel datapath for the temperature compensation of the current
gain (see the Current Waveform Gain Registers section). A simple
approach to implement the temperature measurement is to leave
the temperature gain registers at their default values so that the
temperature compensation path uses the temperature measurements without any gain correction.
Figure 49 shows the ADC and signal processing chain for the
temperature sensor when the ADE7933/ADE7932 monitor
Phase A. The temperature measurement is characterized by
offset and gain errors. The offset information is calculated
during the manufacturing process and is stored with a sign
opposite of the calculated sign into the ADE7933/ADE7932.
The ADE7978 reads the offset information using the bit stream
communication (see the Bit Stream Communication Between
the ADE7978 and the ADE7933/ADE7932 section for more
information). The ADE7978 then stores this information in the
8-bit signed ATEMPOS, BTEMPOS, CTEMPOS, and NTEMPOS
registers. The offset information is shifted left by 11 bits before
it is added to the temperature datapath.
The temperature measurement results are stored in the 24-bit
signed ATEMP, BTEMP, CTEMP, and NTEMP registers 1.024 sec
after the temperature sensor measurement is started by setting
the VT_A, VT_B, VT_C, and VT_N pins low. These registers
are updated at an 8 kSPS rate. The VT_A, VT_B, VT_C, and
VT_N pins must be kept low for at least 1.024 sec for the
temperature measurement results to be stored in the ATEMP,
BTEMP, CTEMP, and NTEMP registers.
The 24-bit signed temperature gain registers (ATGAIN, BTGAIN,
CTGAIN, and NTGAIN) can be used for gain compensation to
change the temperature waveform by ±100%. For example, if
0x400000 is written to these registers, the ADC output is scaled
up by 50%. To scale the output by −50%, write 0xC00000 to the
registers. Equation 10 describes mathematically the function of
the temperature waveform gain registers.
Temperature Waveform =
The microcontroller can obtain the temperature measurements
expressed in °C units by applying the following formula:
Temperature(°C) = 8.72101 × 10−5 × TEMP − 306.47
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. Like the
SAGLVL register shown in Figure 61, the 24-bit signed ATEMP,
BTEMP, CTEMP, and NTEMP registers are transmitted as 32-bit
registers with the eight MSBs padded with 0s.
(10)
Contents of Temp Gain Register 


ADC Output × 1 +
2 23


PHASE A
ADE7978
ADE7933
ATEMPOS[7:0]
TEMPERATURE
SENSOR
211
REFERENCE
ATEMP TEMPERATURE
RANGE
ATGAIN[23:0]
V2P
Σ-Δ
MODULATOR
VIN
VM
DIGITAL LPF
WITH 10Hz
CORNER
DIGITAL
LPF
VT_A
AIGAIN TEMPERATURE
COMPENSATION
BIT 0 (VA2_EN) IN
CONFIG3 REGISTER
CLEARED TO 0
+0.3672V
4,488,800
+0.3098V
3,800,800
+0.2472V
3,055,500
+25°C
+85°C
TEMPERATURE SENSOR CHARACTERISTIC
0V
–40°C
+25°C
+85°C
VOLTAGE CHANNEL DATA RANGE
WHEN TEMPERATURE SENSOR IS SELECTED
Figure 49. Temperature Measurement Datapath
Rev. 0 | Page 37 of 120
11116-043
VIN
0V
–40°C
(11)
ADE7978/ADE7933/ADE7932
Data Sheet
Voltage Waveform Gain Registers
Voltage Channel Sampling
There is a multiplier in the signal path of each phase voltage.
The voltage waveform can be changed by ±100% by writing
a corresponding twos complement number to the 24-bit signed
voltage waveform gain registers (AVGAIN, AV2GAIN, BVGAIN,
BV2GAIN, CVGAIN, CV2GAIN, NVGAIN, and NV2GAIN).
For example, if 0x400000 is written to these registers, the ADC
output is scaled up by 50%. To scale the output by −50%, write
0xC00000 to the registers. Equation 12 describes mathematically the function of the voltage waveform gain registers.
The waveform samples of the voltage channels are taken at
the output of the HPF and are stored in the 24-bit signed
VAWV, VA2WV, VBWV, VB2WV, VCWV, VC2WV, VNWV,
and VN2WV registers at a rate of 8 kSPS. All power and rms
calculations remain uninterrupted during this process.
Voltage Waveform =
(12)
Contents of Voltage Gain Register 


ADC Output × 1 +
2 23


Changing the contents of the AVGAIN, AV2GAIN, BVGAIN,
BV2GAIN, CVGAIN, CV2GAIN, NVGAIN, or NV2GAIN
register affects all calculations based on the voltage of the
corresponding phase, including the active, reactive, and apparent
energy and the voltage rms calculations. In addition, waveform
samples scale accordingly.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. Like the
xIGAIN registers shown in Figure 44, the AVGAIN, AV2GAIN,
BVGAIN, BV2GAIN, CVGAIN, CV2GAIN, NVGAIN, and
NV2GAIN registers are sign extended to 28 bits and padded
with four 0s for transmission as 32-bit registers.
Voltage Channel HPF
The ADC outputs may contain a dc offset that can create errors
in power and rms calculations. High-pass filters (HPFs) are placed
in the signal path of the phase voltages and the phase and neutral
currents. When the HPF is enabled, the filter eliminates any dc
offset on the voltage channel. All filters in both voltage and current
channels are implemented in the DSP and are enabled by default:
Bit 4 (HPFEN) of the CONFIG register (Address 0xE618) is set
to 1. All filters are disabled by setting Bit 4 (HPFEN) to 0.
Bit 17 (DREADY) in the STATUS0 register (Address 0xE502) is
set when the VAWV, VA2WV, VBWV, VB2WV, VCWV, VC2WV,
VNWV, and VN2WV registers are available to be read using the
I2C or SPI serial port. Setting Bit 17 (DREADY) in the MASK0
register (Address 0xE50A) enables an interrupt to be set when the
DREADY flag is set. For more information about the DREADY
bit, see the Digital Signal Processor section.
In addition, if Bits[1:0] (ZX_DREADY) in the CONFIG register
are set to 00, the DREADY functionality is selected at the
ZX/DREADY pin. In this case, the pin goes low approximately
70 ns after the DREADY bit is set to 1 in the STATUS0 register.
The ZX/DREADY pin stays low for 10 µs and then returns high.
The low to high transition of the ZX/DREADY pin can be used
to initiate a burst read of the waveform sample registers. For more
information, see the I2C Burst Read Operation and the SPI Burst
Read Operation sections.
For information about using the ZX functionality at the
ZX/DREADY pin (ZX_DREADY bits in the CONFIG register
are set to 01, 10, or 11), see the Zero-Crossing Detection section.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. Like the IxWV
registers shown in Figure 45, the 24-bit signed VAWV, VA2WV,
VBWV, VB2WV, VCWV, VC2WV, VNWV, and VN2WV registers
are transmitted as sign extended 32-bit registers.
The ADE7978 contains a high speed data capture (HSDC) port
that is specially designed to provide fast access to the waveform
sample registers. For more information, see the HSDC Interface
section.
Rev. 0 | Page 38 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
CHANGING THE PHASE VOLTAGE DATAPATH
The ADE7978 can direct one phase voltage input to the computational datapath of another phase. For example, the Phase A
voltage can be introduced into the Phase B computational datapath, which means that all powers computed by the ADE7978
in Phase B are based on the Phase A voltage and the Phase B
current. Table 16 lists the settings of the VTOIA[1:0] bits and
the configured phase voltage directed to the Phase A computational datapath.
Figure 50 shows the Phase A voltage used in the Phase B datapath, the Phase B voltage used in the Phase C datapath, and the
Phase C voltage used in the Phase A datapath.
IA
Voltage Directed to the Phase A
Computational Datapath
Phase A voltage
Phase B voltage
Phase C voltage
Phase A voltage
VTOIC[1:0] = 10,
PHASE B VOLTAGE
DIRECTED
TO PHASE C
11116-044
Figure 50. Phase Voltages Used in Different Datapaths
Voltage Directed to the Phase B
Computational Datapath
Phase B voltage
Phase C voltage
Phase A voltage
Phase B voltage
Voltage Directed to the Phase C
Computational Datapath
Phase C voltage
Phase A voltage
Phase B voltage
Phase C voltage
CPHCAL
PHASE C
COMPUTATIONAL
DATAPATH
VC
Table 18 lists the settings of the VTOIC[1:0] bits and the configured phase voltage directed to the Phase C computational
datapath.
VTOIC[1:0] Bits
00 (default)
01
10
11
VTOIB[1:0] = 10,
PHASE A VOLTAGE
DIRECTED
TO PHASE B
IC
Table 17. VTOIB[1:0] Bit Settings (CONFIG Register,
Bits[11:10])
Table 18. VTOIC[1:0] Bit Settings (CONFIG Register,
Bits[13:12])
BPHCAL
PHASE B
COMPUTATIONAL
DATAPATH
IB
VTOIA[1:0] = 10,
PHASE C VOLTAGE
DIRECTED
TO PHASE A
VB
Table 17 lists the settings of the VTOIB[1:0] bits and the configured
phase voltage directed to the Phase B computational datapath.
VTOIB[1:0] Bits
00 (default)
01
10
11
PHASE A
COMPUTATIONAL
DATAPATH
VA
Table 16. VTOIA[1:0] Bit Settings (CONFIG Register,
Bits[9:8])
VTOIA[1:0] Bits
00 (default)
01
10
11
APHCAL
REFERENCE CIRCUITS
The nominal reference voltage at the REF pin of the ADE7933/
ADE7932 is 1.2 V. This reference voltage is used for the ADCs.
Because the on chip dc-to-dc converter cannot supply external
loads, the REF pin cannot be overdriven by a standalone external
voltage reference.
The voltage of the ADE7933/ADE7932 reference drifts slightly
with temperature. Table 6 specifies the gain drift over temperature
for each ADC channel. The gain drift includes the temperature
variation of the ADC gain, together with the temperature variation of the internal voltage reference. The value of the gain
temperature drift varies from device to device.
Because the energy calculation uses two ADC channels, one for
the current and one for the voltage, any x% drift in the gain results
in a 2x% deviation of the meter accuracy. The reference drift
resulting from temperature changes is usually very small and is
typically much smaller than the drift of other components on a
meter. As an alternative, the meter can be calibrated at multiple
temperatures.
The VA2, VB2, VC2, and VN2 voltages and the temperature
sensor use the third ADC of the ADE7933/ADE7932, so any x%
drift in the gain results in an x% deviation of these measurements.
Rev. 0 | Page 39 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
PHASE COMPENSATION
If the current leads the voltage, the result is negative, and the
absolute value is written to the xPHCAL registers. If the current
lags the voltage, the result is positive and 512 is added to the
result before it is written to the xPHCAL registers.
Typically, phase compensation is not needed in the
ADE7978/ADE7933/ADE7932 chipset. As described in the
Current Channel ADC and Voltage Channel ADC sections, the
same datapath is used for the phase current and phase voltages;
therefore, no phase error exists between the phase current and
voltage signals introduced by the ADE7978. In addition, shunts
are used with the ADE7933/ADE7932 devices to sense the phase
currents, eliminating the need for phase compensation.
APHCAL, BPHCAL, or CHPCAL =
The ADE7978 provides a means of digitally calibrating eventual
phase mismatch errors. The ADE7978 allows a small time delay
or time advance to be introduced into the signal processing chain
to compensate for the small phase errors.
Figure 52 illustrates the use of phase compensation to remove an
x = −1° phase lead in IA of the current channel from the external
current transducer (equivalent of 55.5 µs for 50 Hz systems). To
cancel the lead (1°) in the current channel of Phase A, a phase
lead must be introduced into the corresponding voltage channel.
Using Equation 13, APHCAL is 57 LSBs, rounded up from 56.8.
The phase lead is achieved by introducing a time delay of 55.73 µs
into the Phase A current.
The 10-bit phase calibration registers (APHCAL, BPHCAL, and
CPHCAL) can vary the time advance in the voltage channel signal
path from −374.0 µs to +374.0 μs. Negative values written to the
xPHCAL registers represent a time advance, whereas positive
values represent a time delay. One LSB is equivalent to 0.976 µs of
time delay or time advance (assuming a clock rate of 1.024 MHz).
With a line frequency of 60 Hz, this calibration gives a phase resolution of 0.0211° (360° × 60 Hz/1.024 MHz) at the fundamental
and corresponds to a total correction range of −8.079° to +8.079°
at 60 Hz. With a line frequency of 50 Hz, the correction range
is −6.732° to +6.732°, and the resolution is 0.0176° (360° ×
50 Hz/1.024 MHz).
15
10 9
0000 00
0
xPHCAL
Figure 51. 10-Bit xPHCAL Register Transmitted as a 16-Bit Word
PHASE A
ADE7978
IP
Σ-Δ
MODULATOR
IA
PHASE
CALIBRATION
APHCAL = 57
IM
V1P
Σ-Δ
MODULATOR
VA
VM
1°
IA
IA
11116-058
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. As shown
in Figure 51, the 10-bit APHCAL, BPHCAL, and CPHCAL
registers are accessed as 16-bit registers with the six MSBs
padded with 0s.
Given a phase error of x degrees, measured using the phase
voltage as the reference, the corresponding LSBs are computed
by dividing x by the phase resolution (0.0211°/LSB for 60 Hz
and 0.0176°/LSB for 50 Hz). Only results from −383 to +383 are
allowed; values outside this range are not allowed.
ADE7933
(13)


x


,x≤0
 phase _ resolution



x


x
+
512
,
>
0


phase
resolution
_


VA
11116-059
VA
PHASE COMPENSATION
ACHIEVED DELAYING
IA BY 56µs
50Hz
Figure 52. Phase Calibration Process
Rev. 0 | Page 40 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
DIGITAL SIGNAL PROCESSOR
The ADE7978 contains a fixed function digital signal processor
(DSP) that computes all powers and rms values. The DSP contains program memory ROM and data memory RAM.
Program memory ROM stores the program used for the power
and rms computations; the processor executes the program every
8 kHz. The end of the computations is signaled by setting Bit 17
(DREADY) to 1 in the STATUS0 register (Address 0xE502). An
interrupt attached to this flag can be enabled by setting Bit 17
(DREADY) in the MASK0 register (Address 0xE50A).
When the interrupt is enabled, the IRQ0 pin is set low and the
DREADY status bit is set to 1 at the end of the computations.
The status bit is cleared and the IRQ0 pin returns high when
a 1 is written to Bit 17 (DREADY) in the STATUS0 register.
In addition, when Bits[1:0] (ZX_DREADY) in the CONFIG
register (Address 0xE618) are set to 00, the DREADY functionality
is selected at the ZX/DREADY pin. In this case, the ZX/DREADY
pin goes low approximately 70 ns after the DREADY bit is set to
1 in the STATUS0 register. The ZX/DREADY pin stays low for
10 µs and then returns high.
The low to high transition of the ZX/DREADY pin can be used
to initiate a burst read of the waveform sample registers. For more
information, see the I2C Burst Read Operation and the SPI Burst
Read Operation sections. For information about using the ZX
functionality at the ZX/DREADY pin (ZX_DREADY bits in the
CONFIG register are set to 01, 10, or 11), see the Zero-Crossing
Detection section.
The registers used as inputs by the DSP are located in the data
memory RAM at addresses from 0x4380 to 0x43BF. The width
of this memory is 28 bits. Within the DSP core, the DSP contains
a two-stage pipeline. This means that when a single register must
be initialized, two more writes are required to ensure that the
value is written into RAM, and if two or more registers must be
initialized, the last register must be written two more times to
ensure that the values are written into RAM.
At power-up or after a hardware or software reset, the DSP is in
idle mode. No instruction is executed. All registers located in
the data memory RAM are initialized to 0, their default values,
and they can be read or written without any restriction. The run
register (Address 0xE228), which is used to start and stop the
DSP, is cleared to 0x0000.
To protect the integrity of the data stored in the data memory RAM
of the DSP (addresses from 0x4380 to 0x43BF), a write protection
mechanism is available. By default, the protection is disabled and
registers located from Address 0x4380 to Address 0x43BF can be
written without restriction. When the protection is enabled, no
writes to these registers are allowed. Registers can always be read
without restriction, independent of the write protection state.
To enable the protection, write 0xAD to the internal 8-bit register
located at Address 0xE7FE, followed by a write of 0x80 to the
internal 8-bit register located at Address 0xE7E3.
It is recommended that the write protection be enabled after the
registers are initialized. If any data memory RAM-based register
must be changed, disable the protection, change the value, and
then reenable the protection. There is no need to stop the DSP
to change these registers.
To disable the protection, write 0xAD to the internal 8-bit
register located at Address 0xE7FE, followed by a write of 0x00
to the internal 8-bit register located at Address 0xE7E3.
The recommended procedure for initializing the registers
located in the data memory RAM at power-up is described in
the Initializing the Chipset section.
In the unlikely event that one or more registers are not initialized
correctly, disable the protection by writing 0xAD to the internal
8-bit register located at Address 0xE7FE, followed by a write of
0x00 to the internal 8-bit register located at Address 0xE7E3.
Reinitialize the registers, writing the last register in the queue three
times. Enable the write protection by writing 0xAD to the internal
8-bit register located at Address 0xE7FE, followed by a write of
0x80 to the internal 8-bit register located at Address 0xE7E3.
There is no obvious reason to stop the DSP. All ADE7978
registers, including the registers located in the data memory RAM,
can be modified without stopping the DSP. However, to stop the
DSP, 0x0000 must be written to the run register. To restart the DSP,
one of the following procedures must be followed:
•
•
The run register must be written with 0x0001 for the DSP to start
code execution. Before writing 0x0001 to the run register, it is
recommended that all ADE7978 registers located in the data
memory RAM be initialized to their desired values. Next, write
the last register in the queue two additional times to flush the
pipeline, and then write 0x0001 to the run register. In this way,
the DSP starts the computations from a desired configuration.
Rev. 0 | Page 41 of 120
If the ADE7978 registers located in the data memory RAM
have not been modified, write 0x0001 to the run register to
start the DSP.
If the ADE7978 registers located in the data memory RAM
must be modified, execute a software or a hardware reset,
initialize all ADE7978 registers at the desired values, enable
the write protection, and then write 0x0001 into the run
register to start the DSP.
ADE7978/ADE7933/ADE7932
Data Sheet
POWER QUALITY MEASUREMENTS
ZERO-CROSSING DETECTION
Table 19. Zero-Crossing Status Bits in the STATUS1 Register
The ADE7978 has a zero-crossing (ZX) detection circuit on the
phase current and phase voltage channels. The neutral current
datapath and the second voltage channels do not have zerocrossing detection circuits. Zero-crossing events are used as a
time base for various power quality measurements and in the
calibration process.
Bit No.
9
10
11
12
13
14
The output of the digital filter LPF1 is used to generate zerocrossing events. The low-pass filter is intended to eliminate all
harmonics of 50 Hz and 60 Hz systems and to help identify
zero-crossing events on the fundamental components of both
current and voltage channels.
LPF1 has a pole at 80 Hz and is clocked at 256 kHz. As a result,
there is a phase lag between the analog input signal (one of IA,
IB, IC, VA, VB, or VC) and the output of LPF1. The error in ZX
detection is 0.0703° for 50 Hz systems and 0.0843° for 60 Hz
systems. The phase lag response of LPF1 results in a time delay
of approximately 31.4° (1.74 ms) at 50 Hz between the input
and output. The overall delay between the zero crossing on the
analog inputs and the ZX detection obtained after LPF1 is
approximately 39.6° (2.2 ms) at 50 Hz. The ADC and HPF
introduce the additional delay. To assure a good resolution of
the ZX detection, LPF1 cannot be disabled. Figure 53 shows
how the zero-crossing signal is detected.
IA, IB, IC AFTER
TEMPERATURE
COMPENSATION
OR
VA, VB, VC AFTER
HPF
LPF1
39.6° OR 2.2ms @ 50Hz
1
0.855
IA, IB, IC,
OR VA, VB, VC
ZX/
DREADY PIN
Zero-Crossing Event Detected on
Phase A voltage
Phase B voltage
Phase C voltage
Phase A current
Phase B current
Phase C current
If a ZX detection bit (any of Bits[14:9]) is set in the MASK1 register
(Address 0xE50B), the IRQ1 interrupt pin is driven low and the
corresponding status flag is set to 1 when the configured zerocrossing event occurs. The status bit is cleared and the IRQ1 pin
returns high when a 1 is written to the appropriate bit in the
STATUS1 register.
By default, the ZX/DREADY pin is configured for the DREADY
functionality. Zero-crossing functionality can be configured for
the ZX/DREADY pin by setting Bits[1:0] (ZX_DREADY) in the
CONFIG register (Address 0xE618). When the ZX/DREADY pin
is configured for the ZX function, the pin stays high when the
phase voltage is positive and goes low when the phase voltage is
negative (see Figure 53).
When the ZX_DREADY bits are set to 01, zero-crossing events
detected on the Phase A voltage trigger the ZX/DREADY pin to
toggle simultaneously with Bit 9 (ZXVA) in the STATUS1 register
being set to 1. When the ZX_DREADY bits are set to 10 or 11,
zero-crossing events detected on the Phase B or Phase C voltage
trigger the ZX/DREADY pin to toggle simultaneously with Bit 10
(ZXVB) or Bit 11 (ZXVC) in the STATUS1 register being set to 1.
Zero-Crossing Timeout
ZX
ZX
ZX
ZX
LPF1
OUTPUT
11116-045
0V
ZX
DETECTION
Bit Name
ZXVA
ZXVB
ZXVC
ZXIA
ZXIB
ZXIC
Figure 53. Zero-Crossing Detection on Voltage and Current Channels
To provide additional protection from noise, input signals to
the voltage channel with amplitudes 1000 times lower than full
scale never generate zero-crossing events. The current channel
ZX detection circuit is active for all input signals, regardless of
their amplitudes.
The ADE7978 contains six zero-crossing detection circuits, one
for each phase voltage and current channel. Each circuit drives a
flag in the STATUS1 register (Address 0xE503). The status bits set
in the STATUS1 register when a zero-crossing detection circuit
detects a zero-crossing event are listed in Table 19.
Each zero-crossing detection circuit has an associated internal
timeout register that starts to decrement 1 ms (sixteen cycles of
a 16 kHz clock) after a zero-crossing event is triggered. This
register is loaded with the value written to the 16-bit ZXTOUT
register (Address 0xE60D) and is decremented by 1 LSB every
62.5 μs (16 kHz clock). The register is reset to the ZXTOUT value
every time a zero crossing is detected. The default value of this
register is 0xFFFF. If the timeout register decrements to 0 before
a zero crossing is detected, one of Bits[8:3] of the STATUS1
register is set to 1.


Rev. 0 | Page 42 of 120
Bit 3 (ZXTOVA), Bit 4 (ZXTOVB), and Bit 5 (ZXTOVC)
in the STATUS1 register refer to the Phase A, Phase B, and
Phase C voltage channels.
Bit 6 (ZXTOIA), Bit 7 (ZXTOIB), and Bit 8 (ZXTOIC) in
the STATUS1 register refer to the Phase A, Phase B, and
Phase C current channels.
Data Sheet
ADE7978/ADE7933/ADE7932
If a ZXTOIx or ZXTOVx bit (any of Bits[8:3]) is set in the
MASK1 register, the IRQ1 interrupt pin is driven low when the
corresponding status bit is set to 1. The status bit is cleared and
the IRQ1 pin returns high when a 1 is written to the appropriate
bit in the STATUS1 register.
The resolution of the ZXTOUT register is 62.5 μs (16 kHz clock)
per LSB. Thus, the maximum timeout period for an interrupt is
4.096 sec, that is, 216/16 kHz. Note that because the timer starts
to decrement 1 ms after a zero-crossing event is triggered, the
value of the ZXTOUT register is
ZXTOUT = Desired ZX Timeout × 16 kHz − 16
(14)
Figure 54 shows the mechanism of zero-crossing timeout
detection when the voltage or current signal stays at a fixed
dc level for more than 62.5 μs × ZXTOUT μs.
16-BIT INTERNAL
REGISTER VALUE
ZXTOUT
If the sequence of zero-crossing events is, instead, Phase A
followed by Phase C followed by Phase B, then Bit 19 (SEQERR)
in the STATUS1 register is set. If Bit 19 (SEQERR) in the MASK1
register is set to 1 and a phase sequence error event is triggered,
the IRQ1 interrupt pin is driven low. The status bit is cleared and
the IRQ1 pin returns high when a 1 is written to Bit 19 (SEQERR)
in the STATUS1 register.
The phase sequence error detection circuit is functional only
when the ADE7978/ADE7933/ADE7932 chipset is connected
in a 3-phase, 4-wire, three voltage sensor configuration (Bits[5:4],
CONSEL[1:0], in the ACCMODE register at Address 0xE701 are
set to 00). In all other configurations, only two voltage sensors
are used; therefore, it is not recommended to use the detection
circuit. In these configura-tions, use the time intervals between
phase voltages to analyze the phase sequence (see the Time
Interval Between Phases section).
Figure 56 shows an example of the Phase A voltage followed by
the Phase C voltage instead of the Phase B voltage. After this error
occurs, Bit 19 (SEQERR) in the STATUS1 register is set to 1
every time a negative to positive zero crossing occurs.
PHASE A
VOLTAGE
OR
CURRENT
SIGNAL
PHASE C
PHASE B
0V
A, B, C PHASE
VOLTAGES AFTER
LPF1
ZXTOxy FLAG IN
STATUS1[31:0], x = V, I,
y = A, B, C
11116-046
ZX A
IRQ1 INTERRUPT PIN
ZX C
ZX B
BIT 19 (SEQERR) IN
STATUS1 REGISTER
Figure 54. Zero-Crossing Timeout Detection
Phase Sequence Detection
The ADE7978 has on-chip phase sequence error detection circuits.
This detection works on phase voltages and considers only the
zero crossings determined by their negative to positive transitions.
The regular succession of these zero-crossing events is Phase A
followed by Phase B followed by Phase C (see Figure 55).
ZX A
PHASE B
ZX B
PHASE C
ZX C
STATUS1[19] SET TO 1
STATUS1[19] CANCELLED
BY A WRITE TO
STATUS1 REGISTER WITH
SEQERR BIT SET
Figure 56. SEQERR Bit Set to 1 When Phase A Voltage Is Followed by
Phase C Voltage
After a phase sequence error is detected, the time measurement
between various phase voltages can help to identify which phase
voltage should be combined with another phase current in the
computational datapath (see the Time Interval Between Phases
section). Bits[9:8] (VTOIA[1:0]), Bits[11:10] (VTOIB[1:0]), and
Bits[13:12] (VTOIC[1:0]) in the CONFIG register (Address 0xE618)
can be used to direct one phase voltage to the datapath of another
phase (see the Changing the Phase Voltage Datapath section for
more information).
11116-048
PHASE A
IRQ1
11116-047
When the phase voltage is 0, noise in the voltage measurement
can trigger spurious zero-crossing events that may nullify the
action of the ZX timeout. A threshold 1000 times lower than full
scale is implemented in conjunction with this circuit. If the peak
of the phase voltage is below this threshold, the ZX timeout
counter begins to decrement automatically.
Figure 55. Regular Succession of Zero-Crossing Events:
Phase A, Phase B, and Phase C
Rev. 0 | Page 43 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
Time Interval Between Phases
The ADE7978 can measure the time delay between phase
voltages, between phase currents, or between the voltages and
currents of the same phase. The negative to positive transitions
identified by the zero-crossing detection circuit are used as the
start and stop measuring points. Because the zero-crossing events
are identified based on the fundamental components of the phase
currents and voltages, the time interval measurements relate to
the fundamental components. Only one set of time delay measurements is available at one time; these measurements are based on
Bits[10:9] (ANGLESEL[1:0]) in the COMPMODE register
(Address 0xE60E).
When the ANGLESEL[1:0] bits are set to 00 (the default value),
the delays between voltages and currents on the same phase are
measured (see Figure 57). The delay between the Phase A voltage
and Phase A current is stored in the 16-bit unsigned ANGLE0
register (Address 0xE601). The delays between the voltages and
currents of Phase B and Phase C are stored in the ANGLE1 and
ANGLE2 registers, respectively.
The ANGLE0, ANGLE1, and ANGLE2 registers are 16-bit
unsigned registers with 1 LSB corresponding to 3.90625 μs
(256 kHz clock), which means a resolution of 0.0703° (360° ×
50 Hz/256 kHz) for 50 Hz systems and 0.0843° (360° × 60 Hz/
256 kHz) for 60 Hz systems. The delays between phase voltages
or between phase currents are used to characterize how balanced
the load is. The delays between phase voltages and currents are
used to compute the fundamental power factor on each phase,
as shown in Equation 15.

360  × f LINE 

cosφx = cos  ANGLEx ×

256 kHz 

(15)
where fLINE is the line frequency.
PHASE A
VOLTAGE
PHASE A
CURRENT
11116-049
PERIOD MEASUREMENT
ANGLE0
Figure 57. Delay Between Phase A Voltage and Phase A Current Is
Stored in the ANGLE0 Register
When the ANGLESEL[1:0] bits are set to 01, the delays between
phase voltages are measured. The delay between the Phase A voltage and the Phase C voltage is stored in the ANGLE0 register. The
delay between the Phase B voltage and the Phase C voltage is
stored in the ANGLE1 register, and the delay between the Phase A
voltage and the Phase B voltage is stored in the ANGLE2 register
(see Figure 58).
PHASE A
PHASE B
PHASE C
The period measurement has a resolution of 3.90625 μs/LSB
(256 kHz clock), which represents 0.0195% (50 Hz/256 kHz)
when the line frequency is 50 Hz and 0.0234% (60 Hz/256 kHz)
when the line frequency is 60 Hz. The value of the period registers
for 50 Hz networks is approximately 5120 (256 kHz/50 Hz); the
value of the period registers for 60 Hz networks is approximately
4267 (256 kHz/60 Hz). The length of the registers enables the
measurement of line frequencies as low as 3.9 Hz (256 kHz/216).
The period registers are stable at ±1 LSB when the line is established and the measurement does not change.
Use the following equations to compute the line period and
frequency using the period registers:
ANGLE1
ANGLE0
The ADE7978 provides the period measurement of the line in the
voltage channel. The period of each phase voltage is measured and
stored in three registers: APERIOD, BPERIOD, and CPERIOD
(Address 0xE905 to Address 0xE907). The 16-bit unsigned period
registers are updated every line period. Because of the LPF1 filter
(see Figure 53), the period measurement becomes stable after a
settling time of 30 ms to 40 ms.
11116-050
ANGLE2
When the ANGLESEL[1:0] bits are set to 10, the delays between
phase currents are measured. The delay between the Phase A
current and the Phase C current is stored in the ANGLE0 register,
the delay between the Phase B current and the Phase C current is
stored in the ANGLE1 register, and the delay between the Phase A
current and the Phase B current is stored in the ANGLE2 register
(see Figure 58).
Figure 58. Delays Between Phase Voltages or Phase Currents
Rev. 0 | Page 44 of 120
TL = xPERIOD[15:0]/256E3 (sec)
(16)
fL = 256E3/xPERIOD[15:0] (Hz)
(17)
Data Sheet
ADE7978/ADE7933/ADE7932
The ADE7978 can be programmed to detect when the absolute
value of any phase voltage falls below or rises above a specified
peak value for a number of half line cycles. The phase in which
this event takes place and the state of the phase voltage relative
to the threshold is identified in Bits[14:12] (VSPHASE[x]) of the
PHSTATUS register (Address 0xE600). An associated interrupt is
triggered when any phase falls below or rises above a threshold.
Bit 6 (SAGCFG) in the ACCMODE register (Address 0xE701)
selects the way that Bit 16 (sag) in the STATUS1 register is
generated. If the SAGCFG bit is cleared to 0 (the default value),
the sag status bit is set to 1 when any phase voltage is below the
SAGLVL threshold. If the SAGCFG bit is set to 1, the sag status
bit is set to 1 only when a phase voltage goes below and then
above the SAGLVL threshold.
2.
3.
4.
5.
6.
5.
6.
IRQ1 PIN
STATUS1[16]
CANCELLED
BY A WRITE TO
STATUS1[31:0]
WITH SAG BIT SET
PHSTATUS[12]
REMAINS HIGH UNTIL
PHASE A VOLTAGE
GOES ABOVE SAGLVL
DURING ONE SAGCYC
IRQ1 PIN LOW
EVERY TIME
PHASE A VOLTAGE
STAYS BELOW
SAGLVL FOR
SAGCYC PERIOD
PHASE A VOLTAGE
FULL SCALE
SAGLVL[23:0]
SAGCYC[7:0] = 0x4
BIT 16 (SAG) IN
STATUS1[31:0]
VSPHASE[0] =
PHSTATUS[12]
IRQ1 PIN
STATUS1[16]
CANCELLED
BY A WRITE TO
STATUS1[31:0]
WITH SAG BIT SET
PHSTATUS[12]
REMAINS HIGH UNTIL
PHASE A VOLTAGE
GOES ABOVE SAGLVL
DURING ONE SAGCYC
IRQ1 PIN LOW
WHEN PHASE A
VOLTAGE GOES
BELOW AND THEN
ABOVE SAGLVL
FOR SAGCYC
PERIOD
Figure 60. Sag Detection: SAGCFG Bit in ACCMODE Register Set to 1
The SAGCYC register (Address 0xE704) represents the number
of half line cycles during which the phase voltage must remain
below or above the level configured in the SAGLVL register
(Address 0xE509) to trigger a sag interrupt; 0 is not a valid value for
SAGCYC. For example, when the sag cycle bits (SAGCYC[7:0])
contain a value of 0x07, the sag flag in the STATUS1 register is
set at the end of the seventh half line cycle during which the line
voltage falls below the threshold.
11116-051
VSPHASE[0] =
PHSTATUS[12]
7.
The VSPHASE[1] and VSPHASE[2] bits configure the sag events
on Phase B and Phase C in the same way: when the Phase B or
Phase C voltage stays below SAGLVL during a SAGCYC period,
these bits are set to 1. When the phase voltages are above SAGLVL
during a SAGCYC period, the bits are set to 0.
PHASE A VOLTAGE
FULL SCALE
SAGLVL[23:0]
BIT 16 (SAG) IN
STATUS1[31:0]
2.
4.
The Phase A voltage falls below the threshold set in
the sag level register (SAGLVL) for four half line cycles
(SAGCYC = 4).
When Bit 16 (sag) in the STATUS1 register is set to 1 to
indicate the condition, the VSPHASE[0] bit in the PHSTATUS
register is also set to 1 because the Phase A voltage is below
SAGLVL. The IRQ1 interrupt pin goes low.
The microcontroller writes a 1 to Bit 16 (sag) in the STATUS1
register to clear the bit and bring the IRQ1 interrupt pin
back high. The VSPHASE[0] bit in the PHSTATUS register
remains set.
The Phase A voltage continues to stay below the SAGLVL
threshold for four more half line cycles (SAGCYC = 4).
Bit 16 (sag) in the STATUS1 register is again set to 1. The
IRQ1 interrupt pin is again set low. The VSPHASE[0] bit
in the PHSTATUS register remains set.
During the next four half line cycles (SAGCYC = 4), the
Phase A voltage is above the SAGLVL threshold. The
VSPHASE[0] bit in the PHSTATUS register is cleared to 0
at the end of the SAGCYC period.
SAGCYC[7:0] = 0x4
The Phase A voltage falls below the threshold set in
the sag level register (SAGLVL) for four half line cycles
(SAGCYC = 4).
When Bit 16 (sag) in the STATUS1 register is set to 1 to
indicate the condition, the VSPHASE[0] bit in the PHSTATUS
register is also set to 1 because the Phase A voltage is below
SAGLVL. The IRQ1 interrupt pin goes low.
The microcontroller writes a 1 to Bit 16 (sag) in the
STATUS1 register to clear the bit and bring the IRQ1
interrupt pin back high. The VSPHASE[0] bit in the
PHSTATUS register remains set.
The Phase A voltage continues to stay below the SAGLVL
threshold for four more half line cycles (SAGCYC = 4).
Bit 16 (sag) in the STATUS1 register remains cleared to 0.
After four more half line cycles, the Phase A voltage rises
above the SAGLVL threshold.
Bit 16 (sag) in the STATUS1 register is set to 1. The IRQ1
interrupt pin is set low. The VSPHASE[0] bit in the
PHSTATUS register is cleared to 0.
1.
3.
Figure 59 shows the behavior of the ADE7978 when the
SAGCFG bit is cleared to 0.
1.
Figure 60 shows the behavior of the ADE7978 when the
SAGCFG bit is set to 1.
11116-052
PHASE VOLTAGE SAG DETECTION
Figure 59. Sag Detection: SAGCFG Bit in ACCMODE Register Cleared to 0
Rev. 0 | Page 45 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
Note that the internal zero-crossing counter is always active. When
the SAGLVL register is set, the first sag detection result is, therefore,
not executed across a full SAGCYC period. Writing to the SAGCYC
register when the SAGLVL register is already initialized resets the
zero-crossing counter, thus ensuring that the first sag detection
result is obtained across a full SAGCYC period.
The recommended procedure to manage sag events is as follows:
1.
2.
3.
4.
5.
Configure Bit 6 (SAGCFG) in the ACCMODE register to
select the desired behavior of the sag status bit (Bit 16) in
the STATUS1 register.
Enable sag interrupts in the MASK1 register by setting Bit 16
(sag) to 1. When a sag event occurs, the IRQ1 interrupt pin
goes low, and Bit 16 (sag) in the STATUS1 register is set to 1.
Read the STATUS1 register to verify that Bit 16 is set to 1.
Read the PHSTATUS register (Bits[14:12]) to identify the
phase or phases on which the sag event occurred.
Write to the STATUS1 register with Bit 16 (sag) set to 1.
The sag bit is erased immediately.
Sag Detection Level Setting
31
24 23
0000 0000
0
24-BIT NUMBER
For example, if a peak value is identified on the Phase A current,
Bit 24 (IPPHASE[0]) in the IPEAK register is set to 1. If a new
peak value is then measured on Phase B, Bit 24 (IPPHASE[0])
of the IPEAK register is cleared to 0, and Bit 25 (IPPHASE[1])
is set to 1. Figure 62 shows the composition of the IPEAK and
VPEAK registers.
IPPHASE/VPPHASE BITS
31
27 26 25 24 23
00000
Figure 61. 24-Bit SAGLVL Register Transmitted as a 32-Bit Word
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words. The SAGLVL register is transmitted as a 32-bit register
with the eight MSBs padded with 0s (see Figure 61).
0
24-BIT UNSIGNED NUMBER
PEAK DETECTED
ON PHASE C
PEAK DETECTED
ON PHASE A
PEAK DETECTED
ON PHASE B
Figure 62. Composition of IPEAK[31:0] and VPEAK[31:0] Registers
Figure 63 shows how the ADE7978 records the peak value on
the current channel when measurements on Phase A and Phase B
are enabled (PEAKSEL[2:0] bits in the MMODE register are set
to 011).
PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF FIRST
PEAKCYC PERIOD
END OF FIRST
PEAKCYC = 16 PERIOD
END OF SECOND
PEAKCYC = 16 PERIOD
PHASE A
CURRENT
11116-053
The contents of the sag level register (SAGLVL[23:0]) are
compared to the absolute value of the output from the HPF.
Writing 5,320,000 to the SAGLVL register sets the sag detection
level to full scale (see the Voltage Channel ADC section); therefore, the sag event is triggered continuously. Writing 0x00 or
0x01 to the SAGLVL register sets the sag detection level to 0;
therefore, the sag event is never triggered.
Selecting more than one phase to monitor the peak values
decreases proportionally the measurement period specified in
the PEAKCYC register because zero crossings from more than
one phase are involved in the process. When a new peak value is
determined, Bits[26:24] (IPPHASE[2:0]) in the IPEAK register
or Bits[26:24] (VPPHASE[2:0]) in the VPEAK register identify
the phase that triggered the peak detection event.
11116-054
If Bit 16 (sag) in the MASK1 register is set and a sag event
occurs, the IRQ1 interrupt pin is driven low at the same time
that Bit 16 (sag) in the STATUS1 register is set to 1. The sag bit
in the STATUS1 register and the IRQ1 pin are returned high by
writing a 1 to Bit 16 in the STATUS1 register.
BIT 24 OF IPEAK
CLEARED TO 0 AT
THE END OF SECOND
PEAKCYC PERIOD
BIT 24
OF IPEAK
PHASE B
CURRENT
The ADE7978 records the maximum absolute values reached by
the phase current and voltage channels over a specified number
of half line cycles and stores them in the least significant 24 bits
of the 32-bit IPEAK and VPEAK registers (Address 0xE500 and
Address 0xE501).
The PEAKCYC register (Address 0xE703) contains the number
of half line cycles used as a time base for the measurement. The
circuit uses the zero-crossing points identified by the zero-crossing
detection circuit. Bits[4:2] (PEAKSEL[2:0]) in the MMODE
register (Address 0xE700) select the phases on which the peak
measurement is performed. Bit 2 selects Phase A, Bit 3 selects
Phase B, and Bit 4 selects Phase C.
BIT 25
OF IPEAK
PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF
SECOND PEAKCYC PERIOD
BIT 25 OF IPEAK
SET TO 1 AT THE
END OF SECOND
PEAKCYC PERIOD
Figure 63. Peak Level Detection
In this example, PEAKCYC is set to 16, meaning that the peak
measurement cycle is four line periods. The maximum absolute
value of Phase A is greatest during the first four line periods
(PEAKCYC = 16); therefore, the maximum absolute value is
written to the least significant 24 bits of the IPEAK register, and
Bit 24 (IPPHASE[0]) of the IPEAK register is set to 1 at the end
of the period. This bit remains set to 1 for the duration of the
second PEAKCYC period of four line cycles.
Rev. 0 | Page 46 of 120
11116-055
PEAK DETECTION
Data Sheet
ADE7978/ADE7933/ADE7932
The maximum absolute value of Phase B is greatest during the
second PEAKCYC period; therefore, the maximum absolute value
is written to the least significant 24 bits of the IPEAK register,
and Bit 25 (IPPHASE[1]) in the IPEAK register is set to 1 at the
end of the period.
Note that the internal zero-crossing counter is always active.
When Bits[4:2] (PEAKSEL[2:0]) are set in the MMODE register,
the first peak detection result is, therefore, not executed across a
full PEAKCYC period. Writing to the PEAKCYC register when
the PEAKSEL[2:0] bits are already initialized resets the zerocrossing counter, thereby ensuring that the first peak detection
result is obtained across a full PEAKCYC period.
OVERVOLTAGE AND OVERCURRENT DETECTION
The ADE7978 detects when the instantaneous absolute value
measured on the phase voltage and current channels becomes
greater than the thresholds set in the 24-bit unsigned OVLVL
and OILVL registers (Address 0xE508 and Address 0xE507).
OVLVL[23:0]
BIT 18 (OV) OF
STATUS1
STATUS1[18] AND
PHSTATUS[9]
CANCELLED BY A
WRITE OF STATUS1
WITH OV BIT SET.
BIT 9 (OVPHASE)
OF PHSTATUS
Figure 64. Overvoltage Detection
The recommended procedure to manage overvoltage events is
as follows:
1.
2.
3.
4.
5.
Overvoltage Detection
If Bit 18 (OV) in the MASK1 register is set, the IRQ1 interrupt
pin is driven low if an overvoltage event occurs. Two status flags
are set when an overvoltage event occurs: Bit 18 (OV) in the
STATUS1 register and one of Bits[11:9] (OVPHASE[2:0]) in the
PHSTATUS register (Address 0xE600). The OVPHASE[2:0] bits
identify the phase that generated the overvoltage. Bit 18 (OV) in
the STATUS1 register and Bits[11:9] (OVPHASE[2:0]) in the
PHSTATUS register are cleared and the IRQ1 pin is set high by
writing a 1 to Bit 18 (OV) in the STATUS1 register.
Figure 64 shows overvoltage detection in the Phase A voltage.
When the absolute instantaneous value of the voltage goes above
the threshold set in the OVLVL register, Bit 18 (OV) in the
STATUS1 register and Bit 9 (OVPHASE[0]) in the PHSTATUS
register are set to 1. Bit 18 (OV) of the STATUS1 register and
Bit 9 (OVPHASE[0]) in the PHSTATUS register are cleared
when a 1 is written to Bit 18 (OV) in the STATUS1 register.
OVERVOLTAGE
DETECTED
11116-056
At the end of the peak detection period in the current channel,
Bit 23 (PKI) in the STATUS1 register is set to 1; if Bit 23 (PKI)
in the MASK1 register is set, the IRQ1 interrupt pin is driven
low at the end of the PEAKCYC period. In a similar way, at the
end of the peak detection period in the voltage channel, Bit 24
(PKV) in the STATUS1 register is set to 1; if Bit 24 (PKV) in the
MASK1 register is set, the IRQ1 interrupt pin is driven low at the
end of the PEAKCYC period. To identify the phase that triggered
the interrupt, the IPEAK or VPEAK register is read immediately
after reading the STATUS1 register. After identifying the phase
that triggered the interrupt, the status bits are cleared and the
IRQ1 pin is returned high by writing a 1 to Bit 23 (PKI) or Bit 24
(PKV) in the STATUS1 register.
PHASE A
VOLTAGE CHANNEL
Enable overvoltage interrupts in the MASK1 register by
setting Bit 18 (OV) to 1.
When an overvoltage event occurs, the IRQ1 interrupt pin
goes low and Bit 18 (OV) in the STATUS1 register is set to 1.
Read the STATUS1 register to verify that Bit 18 is set to 1.
Read the PHSTATUS register (Bits[11:9]) to identify the
phase or phases on which the overvoltage event occurred.
Write a 1 to Bit 18 (OV) in the STATUS1 register to clear
Bit 18 and Bits[11:9] (OVPHASE[2:0]) of the PHSTATUS
register. The IRQ1 interrupt pin returns high.
Overcurrent Detection
If Bit 17 (OI) in the MASK1 register is set, the IRQ1 interrupt
pin is driven low when an overcurrent event occurs. Two status
flags are set when an overcurrent event occurs: Bit 17 (OI) in the
STATUS1 register and one of Bits[5:3] (OIPHASE[2:0]) in the
PHSTATUS register. The OIPHASE[2:0] bits identify the phase
that generated the overcurrent. The recommended procedure to
manage overcurrent events is as follows:
1.
2.
3.
4.
5.
Rev. 0 | Page 47 of 120
Enable overcurrent interrupts in the MASK1 register by
setting Bit 17 (OI) to 1.
When an overcurrent event occurs, the IRQ1 interrupt pin
goes low and Bit 17 (OI) in the STATUS1 register is set to 1.
Read the STATUS1 register to verify that Bit 17 is set to 1.
Read the PHSTATUS register (Bits[5:3]) to identify the
phase or phases on which the overcurrent event occurred.
Write a 1 to Bit 17 (OI) in the STATUS1 register to clear
Bit 17 and Bits[5:3] (OIPHASE[2:0]) of the PHSTATUS
register. The IRQ1 interrupt pin returns high.
ADE7978/ADE7933/ADE7932
Data Sheet
Overvoltage and Overcurrent Level Setting
The contents of the 24-bit unsigned overvoltage (OVLVL) and
overcurrent (OILVL) registers are compared to the absolute value
of the voltage and current channels. The maximum value of these
registers is the maximum value of the HPF outputs: 5,320,000.
When the OVLVL or OILVL register is equal to this value, the
overvoltage or overcurrent conditions are never detected. Writing
0x0 to these registers signifies that the overvoltage or overcurrent
condition is continuously detected, and the corresponding
interrupt is permanently triggered.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words. Like the SAGLVL register, the OILVL and OVLVL registers
are transmitted as 32-bit registers with the eight MSBs padded
with 0s (see Figure 61).
NEUTRAL CURRENT MISMATCH
In 3-phase systems, the neutral current is equal to the algebraic
sum of the phase currents.
IN(t) = IA(t) + IB(t) + IC(t)
If there is a mismatch between these two quantities, a tamper
situation may have occurred in the system.
The ADE7978 computes the sum of the phase currents by
adding the contents of the IAWV, IBWV, and ICWV registers
(Address 0xE50C to Address 0xE50E) and storing the result in
the 28-bit signed ISUM register (Address 0x43CA).
ISUM(t) = IA(t) + IB(t) + IC(t)
The ISUM value is computed every 125 µs (8 kHz frequency), the
rate at which the current samples are available. Bit 17 (DREADY)
in the STATUS0 register is used to signal when the ISUM register
can be read. For more information about the DREADY bit, see
the Digital Signal Processor section.
To recover the ISUM(t) value from the ISUM register, use the
following equation:
ISUM[27:0]
ADC MAX
× I FS
The ADE7978 computes the difference between the absolute values
of ISUM and the neutral current from the INWV register, takes the
absolute value, and compares it against the threshold configured
in the ISUMLVL register (Address 0x4398).
If ||ISUM| − |INWV|| ≤ |ISUMLVL|, it is assumed that the
neutral current is equal to the sum of the phase currents and
that the system is functioning properly.
If ||ISUM| − |INWV|| > |ISUMLVL|, a tamper situation may have
occurred, and Bit 20 (MISMTCH) in the STATUS1 register is set
to 1. An interrupt attached to the flag can be enabled by setting
Bit 20 (MISMTCH) in the MASK1 register. If the interrupt is
enabled, the IRQ1 pin is set low when the MISMTCH status bit
is set to 1. The status bit is cleared and the IRQ1 pin returns high
by writing a 1 to Bit 20 (MISMTCH) in the STATUS1 register.
If ||ISUM| − |INWV|| ≤ |ISUMLVL|, the MISMTCH bit = 0.
If ||ISUM| − |INWV|| > |ISUMLVL|, the MISMTCH bit = 1.
ISUMLVL, the positive threshold used in the process, is a 24-bit
signed register. Because it is used in a comparison with an absolute
value, always set ISUMLVL to a positive value from 0x00000 to
0x7FFFFF. ISUMLVL uses the same scale as the outputs of the
current ADCs; therefore, writing 5,320,000 to the ISUMLVL
register sets the mismatch detection level to full scale (see the
Current Channel ADC section for more information). Writing
0x000000 (the default value) or a negative value to the ISUMLVL
register signifies that the MISMTCH event is always triggered.
Write the correct value for the application to the ISUMLVL
register after power-up or after a hardware or software reset to
avoid continuously triggering MISMTCH events.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. The 28-bit
signed ISUM register is transmitted as a 32-bit register with the
four MSBs padded with 0s (see Figure 65).
where:
ADCMAX = 5,320,000, the ADC output when the input is
at full scale.
IFS is the full-scale ADC phase current.
31
Note that the ADE7978 also computes the rms of ISUM and
stores it in the NIRMS register (Address 0x43C9) when Bit 14
(INSEL) in the CONFIG register is set to 1. For more information, see the Current RMS Calculation section.
28 27
0000
BIT 27 IS A SIGN BIT
0
28-BIT SIGNED NUMBER
11116-057
I SUM (t ) =
When Bits[5:4] (CONSEL[1:0]) in the ACCMODE register are
set to 01 (meter functions in a 3-wire delta configuration), the
Phase B ADE7933/ADE7932 is not connected, and the IBWV
value output by the HPF is 0. In this case, ISUM represents a
negative estimate of the Phase B current (−IBWV). The NIRMS
register contains the rms value of the Phase B current if Bit 14
(INSEL) in the CONFIG register is set to 1.
Figure 65. 28-Bit ISUM Register Transmitted as a 32-Bit Word
Like the xIGAIN registers shown in Figure 44, the ISUMLVL
register is sign extended to 28 bits and padded with four 0s for
transmission as a 32-bit register.
Rev. 0 | Page 48 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
ROOT MEAN SQUARE MEASUREMENT
Root mean square (rms) is a measurement of the magnitude of
an ac signal. Its definition can be both practical and mathematical.
Defined practically, the rms value assigned to an ac signal is the
amount of dc required to produce an equivalent amount of power
in the load. Mathematically, the rms value of a continuous signal
f(t) is defined as
f 2 t  dt
(18)
For time sampled signals, rms calculation involves squaring the
signal, taking the average, and obtaining the square root.
1
f rms 
N
27
CURRENT
SIGNAL
FROM HPF
x2
N
 f 2 n
0x512D40 =
+5,320,000
(19)
N 1
Equation 19 implies that for signals containing harmonics, the
rms calculation contains the contribution of all harmonics, not
only the fundamental.
The method used by the ADE7978 to compute the rms values is
to low-pass filter (LPF) the square of the input signal and take
the square root of the result (see Figure 66). If the input signal
f(t) is written as a sum of harmonic components, then

f (t )   Fk 2 sinkωt  γ k 
k 1
(20)
The square of f(t) is


k 1
k 1
f 2 (t )   Fk2   Fk2 cos(2kt  2  k ) 

2
 2  Fk  Fm sinkt   k   sinmt   m 
(21)
k ,m 1
k m
After the LPF and the execution of the square root, the rms
value of f(t) is obtained by
f 
xIRMS[23:0]
LPF

 Fk2
(22)
k 1
The rms calculation based on this method is simultaneously
processed on all current and voltage input channels. The results
are available in the following 24-bit registers: AIRMS, AVRMS,
AV2RMS, BIRMS, BVRMS, BV2RMS, CIRMS, CVRMS, CV2RMS,
and NIRMS (Address 0x43C0 to Address 0x43C9) and NVRMS
and NV2RMS (Address 0xE530 and Address 0xE531).
In addition, the ADE7978 computes the fundamental rms value of
the phase currents and voltages and makes them available in the
following 24-bit registers: AFIRMS, BFIRMS, CFIRMS, AFVRMS,
BFVRMS, and CFVRMS (Address 0xE537 to Address 0xE53C).
CURRENT RMS CALCULATION
This section describes how the rms values of all phase and neutral
currents are computed. Figure 66 shows the signal processing chain
for the rms calculation on one phase of the current channel. The
current channel rms value is processed from the samples used
in the current channel.
0V
11116-060
t
t
0
xIRMSOS[23:0]
0xAED2C0 =
–5,320,000
Figure 66. Current RMS Signal Processing
When Bit 14 (INSEL) of the CONFIG register is cleared to 0 (the
default value), the NIRMS register contains the rms value of the
neutral current. When the INSEL bit is set to 1, the NIRMS register contains the rms value of the sum of the instantaneous values
of the phase currents. Note that in 3-phase, 3-wire delta configuration, the Phase B current is not measured, and its estimated rms
value is equal to NIRMS when the INSEL bit is set to 1. See the
Neutral Current Mismatch section for more information.
With the specified full-scale analog input signal of 31.25 mV, the
ADC produces an output code that is approximately 5,320,000.
The equivalent rms value of a full-scale sinusoidal signal is
3,761,808, independent of the line frequency.
The accuracy of the current rms is typically 0.1% error from
the full-scale input down to 1/1000 of the full-scale input. This
measurement has a bandwidth of 3.3 kHz.
To ensure rms measurement stability, follow these steps:
1.
2.
Read the rms registers at least once per line cycle over 1 sec.
Average the readings to obtain the rms value.
The settling time for the current rms measurement is 580 ms for
both 50 Hz and 60 Hz input signals. The current rms measurement
settling time is the time it takes for the rms register to reflect the
value at the input to the current channel when starting from 0.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. The 24-bit
signed xIRMS and xFIRMS registers are transmitted as 32-bit
registers with the eight MSBs padded with 0s (see Figure 67).
31
24 23
0000
0000
0
24-BIT NUMBER
11116-061
1
f rms 
The current rms values are signed 24-bit values and are stored
in the AIRMS, BIRMS, CIRMS, and NIRMS registers. The rms
values of the fundamental components are stored in the AFIRMS,
BFIRMS, and CFIRMS registers. The update rate of the current
rms measurement is 8 kHz.
Figure 67. 24-Bit xIRMS and xFIRMS Registers Transmitted as 32-Bit Words
Rev. 0 | Page 49 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
Current RMS Offset Compensation
The ADE7978 incorporates current rms offset compensation
registers for each phase: AIRMSOS, AFIRMSOS, BIRMSOS,
BFIRMSOS, CIRMSOS, CFIRMSOS, and NIRMSOS. These
24-bit signed registers are used to remove offsets in the current
rms calculations. An offset can exist in the rms calculation due
to input noises that are integrated in the dc component of I2(t).
The current rms offset compensation register is shifted left by
seven bits and then added to the squared current rms before the
square root is executed. Assuming that the maximum value from
the current rms calculation is 3,761,808 with full-scale ac inputs
(50 Hz or 60 Hz), one LSB of the current rms offset represents
the following value of the rms measurement at 60 dB down
from full scale:
 37612 + 128



0.00045% = 
− 1 × 100


3761


Conduct offset calibration at low current; avoid using currents
equal to zero for calibration purpose.
I rms =
I rms 02 + 128 × IRMSOS
(23)
where I rms0 is the rms measurement without offset correction.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. Like the
xIGAIN registers shown in Figure 44, the 24-bit xIRMSOS and
xFIRMSOS registers are sign extended to 28 bits and padded
with four 0s for transmission as 32-bit registers.
VOLTAGE RMS CALCULATION
Figure 68 shows the signal processing chain for the rms calculation on one phase of the voltage channels. The voltage channel
rms value is processed from the samples used in the voltage
channel. The voltage rms values are signed 24-bit values and are
stored in the AVRMS, AV2RMS, BVRMS, BV2RMS, CVRMS,
CV2RMS, NVRMS, and NV2RMS registers. The rms values of
the fundamental components are stored in the AFVRMS, BFVRMS,
and CFVRMS registers. The update rate of the voltage rms
measurement is 8 kHz.
xVRMSOS[23:0]
The accuracy of the voltage rms is typically 0.1% error from
the full-scale input down to 1/1000 of the full-scale input. This
measurement has a bandwidth of 3.3 kHz.
To ensure rms measurement stability, follow these steps:
1.
2.
Read the rms registers at least once per line cycle over 1 sec.
Average the readings to obtain the rms value.
The settling time for the voltage rms measurement is 580 ms for
both 50 Hz and 60 Hz input signals. The voltage rms measurement
settling time is the time it takes for the rms register to reflect the
value at the input to the voltage channel when starting from 0.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit words,
whereas the DSP works with 28-bit words. The 24-bit signed
AVRMS, AFVRMS, AV2RMS, BVRMS, BFVRMS, BV2RMS,
CVRMS, CFVRMS, CV2RMS, NVRMS, and NV2RMS registers
are transmitted as 32-bit registers with the eight MSBs padded
with 0s (see Figure 67).
Voltage RMS Offset Compensation
The ADE7978 incorporates voltage rms offset compensation
registers for each phase: AVRMSOS, AFVRMSOS, AV2RMSOS,
BVRMSOS, BFVRMSOS, BV2RMSOS, CVRMSOS, CFVRMSOS,
CV2RMSOS, NVRMSOS, and NV2RMSOS. These 24-bit signed
registers are used to remove offsets in the voltage rms calculations.
An offset can exist in the rms calculation due to input noises that
are integrated in the dc component of V2(t). The voltage rms
offset compensation register is shifted left by seven bits and then
added to the squared voltage rms before the square root is executed. Assuming that the maximum value from the voltage rms
calculation is 3,761,808 with full-scale ac inputs (50 Hz or 60 Hz),
one LSB of the voltage rms offset represents the following value
of the rms measurement at 60 dB down from full scale:
 37612 + 128



0.00045% = 
− 1 × 100


3761


Conduct offset calibration at low current; avoid using voltages
equal to zero for calibration purposes.
27
V rms =
x2
xVRMS[23:0]
(24)
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. Like the
xIGAIN registers shown in Figure 44, the 24-bit xVRMSOS,
xV2RMSOS, and xFVRMSOS registers are sign extended to 28
bits and padded with four 0s for transmission as 32-bit registers.
0x512D40 =
+5,320,000
0V
0xAED2C0 =
–5,320,000
V rms 02 + 128 × VRMSOS
where V rms0 is the rms measurement without offset correction.
LPF
11116-062
VOLTAGE
SIGNAL
FROM HPF
With the specified full-scale analog input signal of 0.5 V, the ADC
produces an output code that is approximately 5,320,000. The
equivalent rms value of a full-scale sinusoidal signal is 3,761,808,
independent of the line frequency.
Figure 68. Voltage RMS Signal Processing
Rev. 0 | Page 50 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
VOLTAGE RMS IN DELTA CONFIGURATIONS
The BVGAIN, BPHCAL, BVRMSOS, and BFVRMSOS registers
can be used to calibrate the BVRMS and BFVRMS registers
computed in this configuration.
In 3-phase, 3-wire delta configurations, Phase B is considered
the ground of the system, and the Phase A and Phase C voltages
are measured relative to it (see Figure 105). This configuration
is selected by setting Bits[5:4] (CONSEL[1:0]) equal to 01 in the
ACCMODE register (Address 0xE701). Table 22 lists all configurations where the ADE7978 can be used.
In 3-phase, 4-wire delta configurations, the Phase B voltage is
not sensed, and the Phase A and Phase C voltages are measured
relative to the neutral line (see Figure 106). This configuration
is selected by setting Bits[5:4] (CONSEL[1:0]) equal to 11 in the
ACCMODE register.
In the 3-phase, 3-wire delta configuration (see Figure 69), all
Phase B active, reactive, and apparent powers are 0. The ADE7978
subtracts the uncompensated and unfiltered instantaneous values
of the Phase A and Phase C voltages and sends them to the
regular Phase B datapath: VB = VA − VC. The rms value of the
result—that is, the line voltage between Phase A and Phase C—
is computed and stored in the BVRMS register. The BFVRMS
register contains the rms of the fundamental component of the
BVRMS line voltage.
AVGAIN[23:0]
PHASE A
ADE7933
DIGITAL
LPF
In the 3-phase, 4-wire delta configuration (see Figure 70), the
ADE7978 calculates the opposite of the uncompensated and
unfiltered instantaneous value of the Phase A voltage and sends
the value to the regular Phase B datapath: VB = −VA.
HPFEN BIT
CONFIG[4]
ADE7978
HPF
BVGAIN[23:0]
HPFEN BIT
CONFIG[4]
FUNDAMENTAL VOLTAGE
RMS (BFVRMS) CALCULATION
HPF
PHASE C
ADE7933
DIGITAL
LPF
VOLTAGE RMS (BVRMS)
CALCULATION
11116-063
CVGAIN[23:0]
HPFEN BIT
CONFIG[4]
HPF
Figure 69. Phase B Voltage Calculation in 3P3W Delta Configuration (CONSEL = 01 in the ACCMODE Register)
AVGAIN[23:0]
DIGITAL
LPF
HPF
BVGAIN[23:0]
–1
ADE7978
HPFEN BIT
CONFIG[4]
FUNDAMENTAL VOLTAGE
RMS (BFVRMS) CALCULATION
HPF
VOLTAGE RMS (BVRMS)
CALCULATION
11116-064
PHASE A
ADE7933
HPFEN BIT
CONFIG[4]
Figure 70. Phase B Voltage Calculation in 3P4W Delta Configuration (CONSEL = 11 in the ACCMODE Register)
Rev. 0 | Page 51 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
ACTIVE POWER CALCULATION
The ADE7978 computes the total active power on every phase.
The calculation of total active power includes all fundamental
and harmonic components of the voltages and currents. The
ADE7978 also computes the fundamental active power, that is,
the power determined only by the fundamental components of
the voltages and currents.
If the phase currents and voltages contain only the fundamental
component, are in phase (that is, φ1 = γ1 = 0), and correspond to
full-scale ADC inputs, then multiplying them results in an instantaneous power signal that has a dc component, V1 × I1, and a
sinusoidal component, V1 × I1 × cos(2ωt). Figure 72 shows the
corresponding waveforms.
TOTAL ACTIVE POWER CALCULATION
INSTANTANEOUS
POWER SIGNAL
Electrical power is defined as the rate of energy flow from source
to load and is given by the product of the voltage and current
waveforms. The resulting waveform is called the instantaneous
power signal, and it is equal to the rate of energy flow at every
instant of time. The unit of power is the watt or joules/sec. If an
ac system is supplied by a voltage, v(t), and consumes the current,
i(t), and the voltage and current contain harmonics, then
∞
v(t ) = ∑ Vk 2 sin(kωt + ϕ k )
INSTANTANEOUS
ACTIVE POWER
SIGNAL: V rms × I rms
V rms × I rms =
26,991,271
0
(25)
k =1
i(t ) = ∑ I k 2 sin(kωt + γ k )
Figure 72. Active Power Calculation
k =1
Because LPF2 does not have an ideal brick wall frequency response,
the active power signal has some ripple due to the instantaneous
power signal. This ripple is sinusoidal and has a frequency equal
to twice the line frequency. Because the ripple is sinusoidal in
nature, it is removed when the active power signal is integrated
over time to calculate the energy.
The total active power is equal to the dc component of the
instantaneous power signal, that is,
∞
∑Vk I k cos(φk − γk)
k =1
This equation represents the total active power calculated in the
ADE7978 for each phase.
The equation for fundamental active power is
FP = V1I1 cos(φ1 − y1)
(26)
Figure 71 shows how the ADE7978 computes the total active
power on each phase. The ADE7978 first multiplies the current
and voltage signals in each phase. It then extracts the dc component of the instantaneous power signal in each phase (A, B, and
C) using the LPF2 low-pass filter.
0
–5
INSTANTANEOUS
PHASE A
ACTIVE POWER
24
Figure 71. Total Active Power Datapath
–15
AWATT
–25
0.1
1
FREQUENCY (Hz)
10
11116-068
:
–10
–20
11116-065
LPF2
VOLTAGE SIGNAL
FROM HPF
AWATTOS
LPFSEL BIT
CONFIG[5]
Bit 5 (LPFSEL) of the CONFIG register (Address 0xE618) selects
the LPF2 strength. When LPFSEL is cleared to 0 (the default value),
the settling time is 650 ms, and the ripple attenuation is 65 dB.
When LPFSEL is set to 1, the settling time is 1300 ms, and the
ripple attenuation is 128 dB. Figure 73 shows the frequency
response of LPF2 when LPFSEL is cleared to 0. Figure 74 shows
the frequency response of LPF2 when LPFSEL is set to 1.
MAGNITUDE (dB)
where:
Vk, Ik are the rms voltage and current, respectively, of each
harmonic.
φk, γk are the phase delays of each harmonic.
APGAIN
11116-066
i(t) = √2 × I rms × sin(ωt)
v(t) = √2 × V rms × sin(ωt)
∞
CURRENT SIGNAL
FROM HPF
p(t) = V rms × I rms – V rms × I rms × cos(2ωt)
53,982,544
Figure 73. Frequency Response of the LPF Used to Filter Instantaneous Power
in Each Phase: LPFSEL Bit of CONFIG Register Set to 0 (Default)
Rev. 0 | Page 52 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Table 20 provides the settling time for the fundamental active
power measurement. The settling time is the time required for
the power to reflect the value at the input of the ADE7978.
Table 20. Settling Time for Fundamental Active Power
–10
Input Signal
63% PMAX
100% PMAX
–20
–40
0.1
1
FREQUENCY (Hz)
10
11116-069
–30
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. The 28-bit
signed VLEVEL register is transmitted as a 32-bit register with
the four most significant bits padded with 0s (see Figure 75).
31
∞
xWATT = ∑
Vk
k =1 V
×
FS
Ik
I FS
× cos(φk − γk) × PMAX ×
1
24
(27)
where:
VFS and IFS are the rms values of the phase voltage and current
when the ADC inputs are at full scale.
PMAX = 26,991,271, the instantaneous power computed when
the ADC inputs are at full scale and in phase.
The xWATT[23:0] waveform registers can be accessed using
any of the serial port interfaces. For more information, see the
Waveform Sampling Mode section.
FUNDAMENTAL ACTIVE POWER CALCULATION
The ADE7978 computes the fundamental active power using a
proprietary algorithm that requires initialization of the network
frequency and of the nominal voltage measured in the voltage
channel. Bit 14 (SELFREQ) in the COMPMODE register
(Address 0xE60E) must be set according to the frequency of the
network in which the ADE7978 is connected. If the network
frequency is 50 Hz, clear this bit to 0 (the default value). If the
network frequency is 60 Hz, set this bit to 1.
To initialize the nominal voltage measured in the voltage channel,
configure the 28-bit signed VLEVEL register (Address 0x43A2)
with a positive value based on the following equation:
VLEVEL =
VFS
Vn
× 4 × 10 6
(28)
28 27
0000
Figure 74. Frequency Response of the LPF Used to Filter Instantaneous Power
in Each Phase: LPFSEL Bit of CONFIG Register Set to 1
The ADE7978 stores the instantaneous total phase active
powers in the 24-bit AWATT, BWATT, and CWATT registers
(Address 0xE518 to Address 0xE51A). To calculate the value
of these registers, use the following equation:
Settling Time (ms)
375
875
0
28-BIT NUMBER
11116-067
MAGNITUDE (dB)
0
Figure 75. 28-Bit VLEVEL Register Transmitted as a 32-Bit Word
ACTIVE POWER GAIN CALIBRATION
The average active power result from the LPF2 output in each
phase can be scaled by ±100% by writing to the 24-bit watt
gain register for each phase: APGAIN, BPGAIN, or CPGAIN
(Address 0x4399 to Address 0x439B). Because all power datapaths
have identical overall gains, the xPGAIN registers are used with
the datapaths of all powers computed by the ADE7978: total
active and reactive powers, fundamental active and reactive
powers, and apparent powers. Therefore, to compensate the
gain errors in the datapaths of various powers, it is sufficient to
analyze only one power datapath (for example, the total active
power) and calculate the corresponding APGAIN, BPGAIN,
and CPGAIN register values.
The power gain registers are twos complement signed registers
with a resolution of 2−23/LSB. Equation 29 describes mathematically the function of the power gain registers.
Average Power Data =
(29)

Power Gain Register 

LPF2 Output × 1 +
2 23


The output is decreased by 50% by writing 0xC00000 to the
watt gain registers; the output is increased by 50% by writing
0x400000 to the watt gain registers. These registers are used to
calibrate the active, reactive, and apparent power (or energy)
calculation for each phase.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. Like the
xIGAIN registers shown in Figure 44, the 24-bit APGAIN,
BPGAIN, and CPGAIN registers are sign extended to 28 bits
and padded with four 0s for transmission as 32-bit registers.
where:
VFS is the rms value of the phase voltages when the ADC inputs
are at full scale.
Vn is the rms nominal value of the phase voltage.
Rev. 0 | Page 53 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
ACTIVE POWER OFFSET CALIBRATION
Bit 0 (REVAPSEL) in the MMODE register (Address 0xE700)
specifies the type of active power that is monitored. When
REVAPSEL is cleared to 0 (the default value), the total active
power is monitored. When REVAPSEL is set to 1, the fundamental active power is monitored.
The ADE7978 includes a 24-bit watt offset register for each
phase and each active power. The AWATTOS, BWATTOS, and
CWATTOS registers (Address 0x439C to Address 0x439E) compensate offsets in the total active power calculations. The AFWATTOS,
BFWATTOS, and CFWATTOS registers (Address 0x43A3 to
Address 0x43A5) compensate offsets in the fundamental active
power calculations. These signed twos complement registers are
used to remove offsets in the active power calculations.
Bits[8:6] (REVAPC, REVAPB, and REVAPA) in the STATUS0
register (Address 0xE502) are set when a sign change occurs in
the power selected by Bit 0 (REVAPSEL) in the MMODE register.
Bits[2:0] (CWSIGN, BWSIGN, and AWSIGN) in the PHSIGN
register are set simultaneously with the REVAPC, REVAPB,
and REVAPA bits in the STATUS0 register. The xWSIGN bits
indicate the sign of the power. When these bits are set to 0, the
corresponding power is positive. When the bits are set to 1, the
corresponding power is negative.
An offset can exist in the power calculation due to crosstalk
between channels on the PCB or in the chip itself. One LSB in
the active power offset register is equivalent to 1 LSB in the
active power multiplier output. With full-scale current and
voltage inputs, the LPF2 output is PMAX = 26,991,271. At
−80 dB down from full scale (active power scaled down 104
times), one LSB of the active power offset register represents
0.037% of PMAX.
The REVAPx bits in the STATUS0 register and the xWSIGN
bits in the PHSIGN register refer to the total active power of
Phase x and the power type selected by Bit 0 (REVAPSEL) in
the MMODE register.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. Like the
xIGAIN registers shown in Figure 44, the 24-bit xWATTOS
and xFWATTOS registers are sign extended to 28 bits and
padded with four 0s for transmission as 32-bit registers.
Interrupts attached to Bits[8:6] (REVAPC, REVAPB, and
REVAPA) in the STATUS0 register can be enabled by setting
Bits[8:6] in the MASK0 register. When enabled, the IRQ0 pin
goes low and the status bit is set to 1 when a change of sign occurs.
To identify the phase that triggered the interrupt, read the PHSIGN
register immediately after reading the STATUS0 register. The
status bit is cleared and the IRQ0 pin is returned high by writing
a 1 to the appropriate bits in the STATUS0 register.
SIGN OF ACTIVE POWER CALCULATION
The average active power is a signed calculation. If the phase
difference between the current and voltage waveforms is more
than 90°, the average power becomes negative. Negative power
indicates that energy is being injected back onto the grid. The
ADE7978 has sign detection circuitry for active power calculations; this circuitry can monitor the total active powers or the
fundamental active powers.
ACTIVE ENERGY CALCULATION
Active energy is defined as the integral of active power.
Energy =
As described in the Active Energy Calculation section, the
active energy accumulation is performed in two stages. Each
time a sign change is detected in the energy accumulation at the
end of the first stage—that is, after the energy accumulated in the
internal accumulator reaches the WTHR register threshold—a
dedicated interrupt is triggered. The sign of each phase active
power can be read in the PHSIGN register (Address 0xE617).
∫ p(t) dt
(30)
The ADE7978 achieves the integration of the active power
signal in two stages (see Figure 76). The process is identical for
total active power and fundamental active power.
The first stage accumulates the instantaneous phase total or
fundamental active power at 1.024 MHz (the DSP computes
these values at an 8 kHz rate). Each time a threshold is reached,
a pulse is generated, and the threshold is subtracted from the
internal register. The sign of the energy at this moment is
considered the sign of the active power (see the Sign of Active
Power Calculation section for more information).
WATTACC BITS IN
ACCMODE[7:0]
REVAPA BIT IN
STATUS0[31:0]
AWATTHR[31:0]
INSTANTANEOUS
PHASE A ACTIVE POWER
COMPUTED IN DIGITAL
SIGNAL PROCESSOR
INTERNAL
ACCUMULATOR
32-BIT REGISTER
34
0
27 26
WTHR
0
Figure 76. Total Active Energy Accumulation
Rev. 0 | Page 54 of 120
11116-070
THRESHOLD
Data Sheet
ADE7978/ADE7933/ADE7932
The fundamental phase active powers are accumulated in the
32-bit signed AFWATTHR, BFWATTHR, and CFWATTHR
registers (Address 0xE403 to Address 0xE405). The active energy
register contents can roll over to full-scale negative (0x80000000)
and continue to increase in value when the active power is positive.
Conversely, if the active power is negative, the energy register
underflows to full-scale positive (0x7FFFFFFF) and continues
decreasing in value.
The second stage consists of accumulating the pulses generated
at the first stage into internal 32-bit accumulation registers. The
contents of these registers are transferred to the watthour registers,
xWATTHR and xFWATTHR, when these registers are accessed.
Figure 77 shows this process.
THRESHOLD
FIRST STAGE OF
ACTIVE POWER
ACCUMULATION
The ADE7978 provides a status flag to indicate that one of the
xWATTHR registers is half full. Bit 0 (AEHF) in the STATUS0
register (Address 0xE502) is set when Bit 30 of one of the
xWATTHR registers changes, signifying that one of these
registers is half full.
11116-071
PULSES
GENERATED
AFTER FIRST
STAGE
1 PULSE = 1LSB OF WATTHR[31:0]
•
Figure 77. Active Power Accumulation Inside the DSP
The threshold is formed by concatenating the 8-bit unsigned
WTHR register (Address 0xEA02) to 27 bits equal to 0. The
WTHR register is configured by the user and is the same for
total active and fundamental powers on all phases. Its value
depends on how much energy is assigned to one LSB of the
watthour registers. For example, if a derivative of Wh (10n Wh,
where n is an integer) is desired as one LSB of the xWATTHR
register, WTHR is calculated using the following equation:
WTHR =
PMAX × f S × 3600 × 10 n
(31)
VFS × I FS × 2 27
where:
PMAX = 26,991,271 = 0x19BDAA7, the instantaneous power
computed when the ADC inputs are at full scale.
fS = 1.024 MHz, the frequency at which every instantaneous
power computed by the DSP at 8 kHz is accumulated.
VFS and IFS are the rms values of the phase voltages and currents
when the ADC inputs are at full scale.
The WTHR register is an 8-bit unsigned number, so its maximum value is 28 − 1. Its default value is 0x3. Avoid using values
lower than 3, that is, 2 or 1; never use the value 0 because the
threshold must be a non-zero value.
This discrete time accumulation or summation is equivalent
to integration in continuous time, as shown in Equation 32.
∞

Energy = ∫ p (t ) dt = Lim  ∑ p (nT ) × T 
T→0 n=0

(32)
•
If the active power is positive, the watthour register
becomes half full when it increments from 0x3FFFFFFF
to 0x40000000.
If the active power is negative, the watthour register
becomes half full when it decrements from 0xC0000000
to 0xBFFFFFFF.
Similarly, Bit 1 (FAEHF) in the STATUS0 register is set when
Bit 30 of one of the xFWATTHR registers changes, signifying
that one of these registers is half full.
Setting Bits[1:0] in the MASK0 register enables the FAEHF and
AEHF interrupts. When enabled, the IRQ0 pin goes low and the
status bit is set to 1 when one of the energy registers (xWATTHR
for the AEHF interrupt, or xFWATTHR for the FAEHF interrupt),
becomes half full. The status bit is cleared and the IRQ0 pin is
returned high by writing a 1 to the appropriate bit in the STATUS0
register.
Setting Bit 6 (RSTREAD) in the LCYCMODE register
(Address 0xE702) enables a read with reset for all watthour
accumulation registers, that is, the registers are reset to 0 after
a read operation.
INTEGRATION TIME UNDER STEADY LOAD
The discrete time sample period (T) for the accumulation
registers is 976.5625 ns (1.024 MHz frequency). With full-scale
sinusoidal signals on the analog inputs and the watt gain registers
set to 0x00000, the average word value from each LPF2 is PMAX =
26,991,271. If the WTHR register threshold is set to 3 (its minimum recommended value), the first stage accumulator generates
a pulse that is added to the watthour registers at intervals of
3 × 2 27
where:
n is the discrete time sample number.
T is the sample period.
PMAX × 1.024 × 10 6
In the ADE7978, the total phase active powers are accumulated
in the 32-bit signed AWATTHR, BWATTHR, and CWATTHR
registers (Address 0xE400 to Address 0xE402).
= 14.5683 µs
The maximum value that can be stored in the watthour accumulation register before it overflows is 231 − 1 or 0x7FFFFFFF.
The integration time is calculated as
Time = 0x7FFFFFFF × 14.5683 μs = 8 hr, 41 min, 25 sec
Rev. 0 | Page 55 of 120
(33)
ADE7978/ADE7933/ADE7932
Data Sheet
The active power is accumulated in each 32-bit watthour
accumulation register (AWATTHR, BWATTHR, CWATTHR,
AFWATTHR, BFWATTHR, and CFWATTHR) according to
the configuration of Bits[5:4] (CONSEL[1:0] bits) in the
ACCMODE register (see Table 21).
Table 21. Inputs to Watthour Accumulation Registers
CONSEL[1:0]
00
01
AWATTHR
AFWATTHR
VA × IA
VA × IA
10
11
Reserved
VA × IA
1
BWATTHR
BFWATTHR
VB × IB
VB × IB
VB = VA − VC1
CWATTHR
CFWATTHR
VC × IC
VC × IC
VB × IB
VB = −VA
VC × IC
See the BWATTHR and BFWATTHR Accumulation Register in 3-Phase, 3-Wire
Configurations section.
LINE CYCLE ACTIVE ENERGY ACCUMULATION
MODE
In line cycle energy accumulation mode, the energy accumulation
is synchronized to the voltage channel zero crossings such that
active energy is accumulated over an integral number of half line
cycles. The advantage of summing the active energy over an integer
number of line cycles is that the sinusoidal component in the active
energy is reduced to 0. This eliminates any ripple in the energy
calculation and allows the energy to be accumulated accurately
over a shorter time. The line cycle energy accumulation mode
greatly simplifies the energy calibration and significantly reduces
the time required to calibrate the meter.
In line cycle energy accumulation mode, the ADE7978 transfers
the active energy accumulated in the 32-bit internal accumulation
registers to the xWATTHR or xFWATTHR registers after an
integral number of line cycles (see Figure 78). The number of half
line cycles is specified in the LINECYC register (Address 0xE60C).
ZXSEL[0] IN
LCYCMODE[7:0]
Depending on the polyphase meter service, choose the appropriate formula to calculate the active energy. The ANSI C12.10
standard defines the different configurations of the meter.
Table 22 describes which mode to choose in these various
configurations.
ZEROCROSSING
DETECTION
(PHASE A)
ZXSEL[1] IN
LCYCMODE[7:0]
Table 22. Meter Form Configuration
ANSI Meter
Form
5S/13S
8S/15S
9S/16S
Configuration
3-wire delta
4-wire delta
4-wire wye
CONSEL[1:0]
Bits
01
11
00
LINECYC[15:0]
ZEROCROSSING
DETECTION
(PHASE B)
Figure
Figure 105
Figure 106
Figure 103
Bits[1:0] (WATTACC[1:0]) in the ACCMODE register
determine how the active power is accumulated in the watthour
registers and how the CF frequency output can be generated as
a function of the total and fundamental active powers. For more
information, see the Energy-to-Frequency Conversion section.
CALIBRATION
CONTROL
ZXSEL[2] IN
LCYCMODE[7:0]
ZEROCROSSING
DETECTION
(PHASE C)
APGAIN
AWATTOS
AWATTHR[31:0]
OUTPUT
FROM
LPF2
INTERNAL
ACCUMULATOR
BWATTHR and BFWATTHR Accumulation Register in
3-Phase, 3-Wire Configurations
34
27 26
WTHR
In a 3-phase, 3-wire configuration (CONSEL[1:0] = 01), the
ADE7978 computes the rms value of the line voltage between
Phase A and Phase C and stores the result in the BVRMS register
(see the Voltage RMS in Delta Configurations section). The
Phase B current value provided after the HPF is 0; therefore,
the powers associated with Phase B are 0.
To avoid any errors in the frequency output pins (CF1, CF2, or
CF3) related to the powers associated with Phase B, disable the
contribution of Phase B to the energy-to-frequency converters
by setting the TERMSEL1[1], TERMSEL2[1], or TERMSEL3[1]
bit to 0 in the COMPMODE register (Address 0xE60E). For more
information, see the Energy-to-Frequency Conversion section.
32-BIT
REGISTER
THRESHOLD
0
0
Figure 78. Line Cycle Active Energy Accumulation Mode
The line cycle active energy accumulation mode is activated by setting Bit 0 (LWATT) in the LCYCMODE register (Address 0xE702).
The total active energy accumulated over an integer number of half
line cycles (or zero crossings) is written to the watthour accumulation registers after the number of half line cycles specified by the
LINECYC register is detected. When using the line cycle accumulation mode, set Bit 6 (RSTREAD) of the LCYCMODE register
to Logic 0 because a read with reset of the watthour registers
outside the LINECYC period resets the energy accumulation.
Rev. 0 | Page 56 of 120
11116-072
ENERGY ACCUMULATION MODES
Data Sheet
ADE7978/ADE7933/ADE7932
Phase A, Phase B, and Phase C zero crossings are included
when counting the number of half line cycles by setting
Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combination of zero crossings from all three phases can be used to
count the zero crossings. Select only one phase at a time for
inclusion in the count of zero crossings during calibration.
The number of zero crossings is specified by the 16-bit
unsigned LINECYC register. The ADE7978 can accumulate
active power for up to 65,535 combined zero crossings. Note
that the internal zero-crossing counter is always active. By
setting Bit 0 (LWATT) in the LCYCMODE register, the first
energy accumulation result is, therefore, incorrect. Writing to
the LINECYC register when the LWATT bit is set resets the
zero-crossing counter, thus ensuring that the first energy
accumulation result is accurate.
At the end of an energy calibration cycle, Bit 5 (LENERGY) in
the STATUS0 register is set. When the corresponding mask bit
in the MASK0 register is enabled, the IRQ0 pin is set low. The
status bit is cleared and the IRQ0 pin is returned high by writing
a 1 to Bit 5 (LENERGY) in the STATUS0 register.
Because the active power is integrated on an integer number of
half line cycles in line cycle accumulation mode, the sinusoidal
components are reduced to 0, eliminating any ripple in the
energy calculation. Therefore, total energy accumulated using
the line cycle accumulation mode is
e =
t +nT
∫ p (t )dt
t
∞
= nT ∑ Vk I k cos(φk − γk)
k =1
(34)
where nT is the accumulation time.
Note that line cycle active energy accumulation uses the same
signal path as active energy accumulation. The LSB size of these
two methods is equivalent.
Rev. 0 | Page 57 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
REACTIVE POWER CALCULATION
The ADE7978 can compute the total reactive power on every
phase. The calculation of total reactive power includes all fundamental and harmonic components of the voltages and currents.
The ADE7978 also computes the fundamental reactive power,
that is, the power determined only by the fundamental components
of the voltages and currents.
TOTAL REACTIVE POWER CALCULATION
A load that contains a reactive element (inductor or capacitor)
produces a phase difference between the applied ac voltage and
the resulting current. The power associated with reactive elements
is called reactive power, and its unit is VAR. Reactive power is
defined as the product of the voltage and current waveforms
when all harmonic components of one of these signals are phase
shifted by 90°.
∞
Q = ∑ Vk I k sin(φk − γk)
(35)
k =1
where:
Vk, Ik are the rms voltage and current, respectively, of each
harmonic.
φk, γk are the phase delays of each harmonic.
The ADE7978 stores the instantaneous total phase reactive powers
in the AVAR, BVAR, and CVAR registers (Address 0xE51B to
Address 0xE51D). The instantaneous total phase reactive powers
are expressed by
Vk
k =1 V
FS
×
Ik
I FS
× sin(φk − γk) × PMAX ×
FQ = V1I1 sin(φ1 − γ1)
The ADE7978 computes the fundamental reactive power using a
proprietary algorithm that requires initialization of the network
frequency and of the nominal voltage measured in the voltage
channel. The required initialization is the same as for the fundamental active powers and is described in the Fundamental Active
Power Calculation section.
Table 23 provides the settling time for the fundamental reactive
power measurement. The settling time is the time required for
the power to reflect the value at the input of the ADE7978.
1
24
(36)
where:
VFS and IFS are the rms values of the phase voltage and current
when the ADC inputs are at full scale.
PMAX = 26,991,271, the instantaneous power computed when
the ADC inputs are at full scale and in phase.
The xVAR[23:0] waveform registers can be accessed using
any of the serial port interfaces. For more information, see
the Waveform Sampling Mode section.
Input Signal
63% PMAX
100% PMAX
Settling Time (ms)
375
875
REACTIVE POWER GAIN CALIBRATION
This relationship is used to calculate the total reactive power in
the ADE7978 for each phase. The instantaneous reactive power
signal is generated by multiplying each harmonic of the voltage
signals by the corresponding 90° phase-shifted harmonic of the
current in each phase.
∞
The expression of fundamental reactive power is obtained from
Equation 35 with k = 1, as follows:
Table 23. Settling Time for Fundamental Reactive Power
The total reactive power is equal to
xVAR = ∑
FUNDAMENTAL REACTIVE POWER CALCULATION
The average reactive power in each phase can be scaled by ±100%
by writing to the 24-bit VAR gain register for each phase: APGAIN,
BPGAIN, or CPGAIN (Address 0x4399 to Address 0x439B). The
same registers are used to compensate the other powers computed
by the ADE7978. For more information about these registers,
see the Active Power Gain Calibration section.
REACTIVE POWER OFFSET CALIBRATION
The ADE7978 includes a 24-bit reactive power offset register for
each phase and each reactive power. The AVAROS, BVAROS,
and CVAROS registers (Address 0x439F to Address 0x43A1)
compensate offsets in the total reactive power calculations. The
AFVAROS, BFVAROS, and CFVAROS registers (Address 0x43A6
to Address 0x43A8) compensate offsets in the fundamental reactive
power calculations. These signed twos complement registers are
used to remove offsets in the reactive power calculations.
An offset can exist in the power calculation due to crosstalk
between channels on the PCB or in the chip itself. One LSB in
the reactive power offset register is equivalent to 1 LSB in the
reactive power multiplier output. With full-scale current and
voltage inputs, the LPF2 output is PMAX = 26,991,271. At
−80 dB down from full scale (active power scaled down 104
times), one LSB of the reactive power offset register represents
0.037% of PMAX.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. Like the
xIGAIN registers shown in Figure 44, the 24-bit xVAROS and
xFVAROS registers are sign extended to 28 bits and padded
with four 0s for transmission as 32-bit registers.
Rev. 0 | Page 58 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
SIGN OF REACTIVE POWER CALCULATION
The REVRPx bits in the STATUS0 register and the xVARSIGN
bits in the PHSIGN register refer to the reactive power of
Phase x and the power type selected by Bit 1 (REVRPSEL) in
the MMODE register.
The reactive power is a signed calculation. Table 24 summarizes
the relationship between the phase difference between the voltage
and the current and the sign of the resulting reactive power
calculation.
Interrupts attached to Bits[12:10] (REVRPC, REVRPB, and
REVRPA) in the STATUS0 register can be enabled by setting
Bits[12:10] in the MASK0 register. When enabled, the IRQ0 pin
goes low and the status bit is set to 1 when a change of sign occurs.
To identify the phase that triggered the interrupt, read the PHSIGN
register immediately after reading the STATUS0 register. The status
bit is cleared and the IRQ0 pin is returned high by writing a 1 to
the appropriate bits in the STATUS0 register.
Table 24. Sign of Reactive Power Calculation
1
Sign of Reactive Power
Positive
Negative
Φ is defined as the phase angle of the voltage signal minus the current
signal; that is, Φ is positive if the load is inductive and negative if the load
is capacitive.
REACTIVE ENERGY CALCULATION
The ADE7978 has sign detection circuitry for reactive power
calculations; this circuitry can monitor the total reactive powers
or the fundamental reactive powers. As described in the Reactive
Energy Calculation section, the reactive energy accumulation is
performed in two stages. Each time a sign change is detected in
the energy accumulation at the end of the first stage—that is, after
the energy accumulated in the internal accumulator reaches the
VARTHR register threshold—a dedicated interrupt is triggered.
The sign of each phase reactive power can be read in the PHSIGN
register (Address 0xE617).
Reactive energy is defined as the integral of reactive power.
Reactive Energy = ∫ q(t) dt
Similar to active power, the ADE7978 achieves the integration
of the reactive power signal in two stages (see Figure 79). The
process is identical for total reactive power and fundamental
reactive power.
The first stage accumulates the instantaneous phase total or
fundamental reactive power at 1.024 MHz (the DSP computes
these values at an 8 kHz rate). Each time a threshold is reached,
a pulse is generated, and the threshold is subtracted from the
internal register. The sign of the energy at this moment is considered the sign of the reactive power (see the Sign of Reactive
Power Calculation section for more information).
Bit 1 (REVRPSEL) in the MMODE register (Address 0xE700)
specifies the type of reactive power that is monitored. When
REVRPSEL is cleared to 0 (the default value), the total reactive
power is monitored. When REVRPSEL is set to 1, the fundamental reactive power is monitored.
Bits[12:10] (REVRPC, REVRPB, and REVRPA) in the STATUS0
register are set when a sign change occurs in the power selected
by Bit 1 (REVRPSEL) in the MMODE register.
The second stage consists of accumulating the pulses generated
at the first stage into internal 32-bit accumulation registers. The
contents of these registers are transferred to the var-hour registers
(xVARHR and xFVARHR) when these registers are accessed.
AVARHR, BVARHR, CVARHR, AFVARHR, BFVARHR, and
CFVARHR represent phase total and fundamental reactive
powers. Figure 79 shows this process.
Bits[6:4] (CVARSIGN, BVARSIGN, and AVARSIGN) in the
PHSIGN register are set simultaneously with the REVRPC,
REVRPB, and REVRPA bits in the STATUS0 register. The
xVARSIGN bits indicate the sign of the reactive power. When
these bits are set to 0, the reactive power is positive. When the
bits are set to 1, the reactive power is negative.
CURRENT SIGNAL
FROM HPF
APGAIN
AVAROS
VARACC BITS IN
ACCMODE[7:0]
TOTAL
REACTIVE
POWER
ALGORITHM
VOLTAGE SIGNAL
FROM HPF
DIGITAL SIGNAL PROCESSOR
(37)
REVRPA BIT IN
STATUS0[31:0]
AVARHR[31:0]
INTERNAL
ACCUMULATOR
:
32-BIT REGISTER
AVAR
THRESHOLD
24
34
27 26
VARTHR
Figure 79. Total Reactive Energy Accumulation
Rev. 0 | Page 59 of 120
0
0
11116-073
Φ1
From 0 to +180
From −180 to 0
ADE7978/ADE7933/ADE7932
Data Sheet
The threshold is formed by concatenating the 8-bit unsigned
VARTHR register (Address 0xEA03) to 27 bits equal to 0. The
VARTHR register is configured by the user and is the same for
the total reactive and fundamental powers on all phases. Its value
depends on how much energy is assigned to one LSB of the
var-hour registers. For example, if a derivative of a volt ampere
reactive hour, varh (10n varh, where n is an integer) is desired
as one LSB of the xVARHR register, the VARTHR register is
calculated using the following equation:
VARTHR =
PMAX × f s × 3600 × 10 n
VFS × I FS × 2 27
•
•
(38)
where:
PMAX = 26,991,271 = 0x19BDAA7, the instantaneous power
computed when the ADC inputs are at full scale.
fS = 1.024 MHz, the frequency at which every instantaneous
power computed by the DSP at 8 kHz is accumulated.
VFS and IFS are the rms values of the phase voltages and currents
when the ADC inputs are at full scale.
The VARTHR register is an 8-bit unsigned number, so its maximum value is 28 − 1. Its default value is 0x3. Avoid using values
lower than 3, that is, 2 or 1; never use the value 0 because the
threshold must be a non-zero value.
This discrete time accumulation or summation is equivalent to
integration in continuous time, as shown in Equation 39:
 ∞

Reactive Energy = ∫ q(t)dt = Lim  ∑ q(nT) × T 
T →0 n = 0


The ADE7978 provides a status flag to indicate that one of the
xVARHR registers is half full. Bit 2 (REHF) in the STATUS0
register (Address 0xE502) is set when Bit 30 of one of the
xVARHR registers changes, signifying that one of these registers
is half full.
(39)
where:
n is the discrete time sample number.
T is the sample period.
In the ADE7978, the total phase reactive powers are accumulated
in the 32-bit signed registers AVARHR, BVARHR, and CVARHR
(Address 0xE406 to Address 0xE408). The fundamental phase
reactive powers are accumulated in the 32-bit signed registers
AFVARHR, BFVARHR, and CFVARHR (Address 0xE409 to
Address 0xE40B). The reactive energy register contents can roll
over to full-scale negative (0x80000000) and continue to increase
in value when the reactive power is positive. Conversely, if the
reactive power is negative, the energy register underflows to fullscale positive (0x7FFFFFFF) and continues to decrease in value.
If the reactive power is positive, the var-hour register
becomes half full when it increments from 0x3FFFFFFF
to 0x40000000.
If the reactive power is negative, the var-hour register
becomes half full when it decrements from 0xC0000000
to 0xBFFFFFFF.
Similarly, Bit 3 (FREHF) in the STATUS0 register is set when
Bit 30 of one of the xFVARHR registers changes, signifying that
one of these registers is half full.
Setting Bits[3:2] in the MASK0 register enables the FREHF and
REHF interrupts. When enabled, the IRQ0 pin goes low and the
status bit is set to 1 when one of the energy registers (xVARHR
for the REHF interrupt or xFVARHR for the FREHF interrupt),
becomes half full. The status bit is cleared and the IRQ0 pin is
returned high by writing a 1 to the appropriate bit in the STATUS0
register.
Setting Bit 6 (RSTREAD) in the LCYCMODE register
(Address 0xE702) enables a read with reset for all var-hour
accumulation registers, that is, the registers are reset to 0 after
a read operation.
INTEGRATION TIME UNDER STEADY LOAD
The discrete time sample period (T) for the accumulation
registers is 976.5625 ns (1.024 MHz frequency). With full-scale
sinusoidal signals on the analog inputs and a 90° phase difference
between the voltage and current signals (the largest possible
reactive power), the average word value representing the reactive
power is PMAX = 26,991,271. If the VARTHR register threshold
is set to 3 (its minimum recommended value), the first stage
accumulator generates a pulse that is added to the var-hour
registers at intervals of
3 × 2 27
PMAX × 1.024 × 10 6
= 14.5683 µs
The maximum value that can be stored in the var-hour accumulation register before it overflows is 231 − 1 or 0x7FFFFFFF. The
integration time is calculated as
Time = 0x7FFFFFFF × 14.5683 μs = 8 hr, 41 min, 25 sec
Rev. 0 | Page 60 of 120
(40)
Data Sheet
ADE7978/ADE7933/ADE7932
ENERGY ACCUMULATION MODES
The reactive power is accumulated in each 32-bit var-hour accumulation register (AVARHR, BVARHR, CVARHR, AFVARHR,
BFVARHR, and CFVARHR) according to the configuration of
Bits[5:4] (CONSEL[1:0] bits) in the ACCMODE register (see
Table 25). Note that IA’, IB’, and IC’ are the phase-shifted current
waveforms.
Table 25. Inputs to Var-Hour Accumulation Registers
AVARHR,
AFVARHR
VA × IA’
VA × IA’
10
11
Reserved
VA × IA’
1
BVARHR,
BFVARHR
VB × IB’
VB × IB’
VB = VA − VC1
CVARHR,
CFVARHR
VC × IC’
VC × IC’
VB × IB’
VB = −VA
VC × IC’
ZXSEL[0] IN
LCYCMODE[7:0]
ZEROCROSSING
DETECTION
(PHASE A)
ZXSEL[1] IN
LCYCMODE[7:0]
LINECYC[15:0]
ZEROCROSSING
DETECTION
(PHASE B)
CALIBRATION
CONTROL
ZXSEL[2] IN
LCYCMODE[7:0]
ZEROCROSSING
DETECTION
(PHASE C)
See the BWATTHR and BFWATTHR Accumulation Register in 3-Phase, 3-Wire
Configurations section.
Bits[3:2] (VARACC[1:0]) in the ACCMODE register determine
how the reactive power is accumulated in the var-hour registers
and how the CF frequency output can be generated as a function
of total and fundamental active and reactive powers. For more
information, see the Energy-to-Frequency Conversion section.
APGAIN
AVAROS
AVARHR[31:0]
INTERNAL
ACCUMULATOR
OUTPUT FROM
TOTAL REACTIVE
POWER ALGORITHM
34
0
27 26
VARTHR
BWATTHR and BFWATTHR Accumulation Register in
3-Phase, 3-Wire Configurations
32-BIT
REGISTER
THRESHOLD
0
11116-074
CONSEL[1:0]
00
01
In line cycle energy accumulation mode, the ADE7978 transfers
the reactive energy accumulated in the 32-bit internal accumulation registers to the xVARHR or xFVARHR registers after an
integral number of line cycles (see Figure 80). The number of half
line cycles is specified in the LINECYC register (Address 0xE60C).
Figure 80. Line Cycle Total Reactive Energy Accumulation Mode
In a 3-phase, 3-wire configuration (CONSEL[1:0] = 01), the
ADE7978 computes the rms value of the line voltage between
Phase A and Phase C and stores the result in the BVRMS register
(see the Voltage RMS in Delta Configurations section). The
Phase B current value provided after the HPF is 0; therefore, the
powers associated with Phase B are 0.
To avoid any errors in the frequency output pins (CF1, CF2, or
CF3) related to the powers associated with Phase B, disable the
contribution of Phase B to the energy-to-frequency converters
by setting the TERMSEL1[1], TERMSEL2[1], or TERMSEL3[1]
bit to 0 in the COMPMODE register (Address 0xE60E). For more
information, see the Energy-to-Frequency Conversion section.
LINE CYCLE REACTIVE ENERGY ACCUMULATION
MODE
In line cycle energy accumulation mode, the energy accumulation
is synchronized to the voltage channel zero crossings such that
reactive energy is accumulated over an integral number of half
line cycles. The advantage of summing the reactive energy over
an integer number of line cycles is that the sinusoidal component
in the reactive energy is reduced to 0. This eliminates any ripple
in the energy calculation and allows the energy to be accumulated
accurately over a shorter time. The line cycle energy accumulation
mode greatly simplifies the energy calibration and significantly
reduces the time required to calibrate the meter.
The line cycle reactive energy accumulation mode is activated by
setting Bit 1 (LVAR) in the LCYCMODE register (Address 0xE702).
The total reactive energy accumulated over an integer number
of half line cycles (or zero crossings) is written to the var-hour
accumulation registers after the number of half line cycles specified by the LINECYC register is detected. When using the line
cycle accumulation mode, set Bit 6 (RSTREAD) of the LCYCMODE
register to Logic 0 because a read with reset of the var-hour registers
outside the LINECYC period resets the energy accumulation.
Phase A, Phase B, and Phase C zero crossings are included
when counting the number of half line cycles by setting
Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combination of zero crossings from all three phases can be used to
count the zero crossings. Select only one phase at a time for
inclusion in the count of zero crossings during calibration.
For more information about setting the LINECYC register and
Bit 5 (LENERGY) in the MASK0 register associated with the
line cycle accumulation mode, see the Line Cycle Active Energy
Accumulation Mode section.
Rev. 0 | Page 61 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
APPARENT POWER CALCULATION
Apparent power is defined as the maximum active power that can
be delivered to a load. One way to obtain the apparent power is by
multiplying the voltage rms value by the current rms value (also
called the arithmetic apparent power).
S = V rms × I rms
(41)
where:
S is the apparent power.
V rms and I rms are the rms voltage and current, respectively.
The ADE7978 computes the arithmetic apparent power on each
phase. Figure 81 illustrates the signal processing in each phase for
the calculation of the apparent power in the ADE7978. Because
V rms and I rms contain all harmonic information, the apparent
power computed by the ADE7978 is total apparent power. The
ADE7978 does not compute fundamental apparent power.
The ADE7978 stores the instantaneous phase apparent powers
in the AVA, BVA, and CVA registers (Address 0xE51E to
Address 0xE520). The equation for apparent power is
xVA =
V
VFS
×
I
I FS
× PMAX ×
1
2
4
(42)
where:
V and I are the rms values of the phase voltage and current.
VFS and IFS are the rms values of the phase voltage and current
when the ADC inputs are at full scale.
PMAX = 26,991,271, the instantaneous power computed when
the ADC inputs are at full scale and in phase.
The xVA[23:0] waveform registers can be accessed using
any of the serial port interfaces. For more information, see
the Waveform Sampling Mode section.
APPARENT POWER GAIN CALIBRATION
The average apparent power in each phase can be scaled by ±100%
by writing to the appropriate 24-bit phase gain registers: APGAIN,
BPGAIN, or CPGAIN (Address 0x4399 to Address 0x439B). The
same registers are used to compensate the other powers computed
by the ADE7978. For more information about these registers, see
the Active Power Gain Calibration section.
APPARENT POWER OFFSET CALIBRATION
Each rms measurement includes an offset compensation register
to calibrate and eliminate the dc component in the rms value (see
the Root Mean Square Measurement section). The voltage and
current rms values are multiplied together in the apparent power
signal processing. Because no additional offsets are created in the
multiplication of the rms values, there is no specific offset
compensation for the apparent power signal processing. The offset
compensation of the apparent power measurement in each phase
is accomplished by calibrating each individual rms measurement.
APPARENT POWER CALCULATION USING VNOM
The ADE7978 can compute the apparent power by multiplying
the phase rms current by an rms voltage introduced externally
in the 24-bit signed VNOM register (Address 0xE533).
When one of Bits[13:11] (VNOMCEN, VNOMBEN, or
VNOMAEN) in the COMPMODE register (Address 0xE60E) is
set to 1, the apparent power in the specified phase (Phase x for
VNOMxEN) is computed in this way. When the VNOMxEN
bits are cleared to 0 (the default value), the arithmetic apparent
power is computed.
The VNOM register value can be calculated as follows:
The ADE7978 can also compute the apparent power by multiplying the phase rms current by an rms voltage that is introduced
externally. For more information, see the Apparent Power
Calculation Using VNOM section.
VNOM = V/VFS × 3,761,808
(43)
where:
V is the nominal phase rms voltage.
VFS is the rms value of the phase voltage when the ADC inputs
are at full scale.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. Like the
SAGLVL register, the VNOM register is transmitted as a 32-bit
register with the eight MSBs padded with 0s (see Figure 61).
Rev. 0 | Page 62 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
APPARENT ENERGY CALCULATION
The VATHR register is an 8-bit unsigned number, so its maximum value is 28 − 1. Its default value is 0x3. Avoid using values
lower than 3, that is, 2 or 1; never use the value 0 because the
threshold must be a non-zero value.
Apparent energy is defined as the integral of apparent power.
Apparent Energy = ∫ s(t) dt
(44)
This discrete time accumulation or summation is equivalent
to integration in continuous time, as shown in Equation 46.
The ADE7978 achieves the integration of the apparent power
signal in two stages (see Figure 81). The first stage accumulates
the instantaneous apparent power at 1.024 MHz (the DSP
computes these values at an 8 kHz rate). Each time a threshold
is reached, a pulse is generated, and the threshold is subtracted
from the internal register. The second stage consists of accumulating the pulses generated at the first stage into internal 32-bit
accumulation registers. The contents of these registers are transferred to the VA-hour registers, xVAHR, when these registers
are accessed. Figure 81 illustrates this process.
 ∞

Apparent Energy = ∫ s(t)dt = Lim  ∑ s(nT) × T 
T →0 n = 0


where:
n is the discrete time sample number.
T is the sample period.
In the ADE7978, the phase apparent powers are accumulated
in the 32-bit signed registers AVAHR, BVAHR, and CVAHR
(Address 0xE40C to Address 0xE40E). The apparent energy
register contents can roll over to full-scale negative (0x80000000)
and continue to increase in value when the apparent power is
positive.
The threshold is formed by concatenating the 8-bit unsigned
VATHR register (Address 0xEA04) to 27 bits equal to 0. The
VATHR register is configured by the user. Its value depends on
how much energy is assigned to one LSB of the VA-hour registers.
For example, if a derivative of the apparent energy, VAh (10n VAh,
where n is an integer) is desired as one LSB of the xVAHR
register, VATHR is calculated using the following equation:
PMAX × f s × 3600 × 10 n
The ADE7978 provides a status flag to indicate that one of the
xVAHR registers is half full. Bit 4 (VAEHF) in the STATUS0
register (Address 0xE502) is set when Bit 30 of one of the xVAHR
registers changes, signifying that one of these registers is half full.
Because the apparent power is always positive and the xVAHR
registers are signed, the VA-hour registers become half full when
they increment from 0x3FFFFFFF to 0x40000000.
(45)
VFS × I FS × 2 27
where:
PMAX = 26,991,271 = 0x19BDAA7, the instantaneous power
computed when the ADC inputs are at full scale.
fS = 1.024 MHz, the frequency at which every instantaneous
power computed by the DSP at 8 kHz is accumulated.
VFS and IFS are the rms values of the phase voltages and currents
when the ADC inputs are at full scale.
Setting Bit 4 (VAEHF) in the MASK0 register enables the VAEHF
interrupt. When enabled, the IRQ0 pin goes low and the status bit
is set to 1 when one of the apparent energy registers (xVAHR)
becomes half full. The status bit is cleared and the IRQ0 pin is
returned high by writing a 1 to Bit 4 (VAEHF) in the STATUS0
register.
Setting Bit 6 (RSTREAD) in the LCYCMODE register
(Address 0xE702) enables a read with reset for all xVAHR accumulation registers, that is, the registers are reset to 0 after a read
operation.
APGAIN
AIRMS
AVAHR[31:0]
INTERNAL
ACCUMULATOR
:
AVRMS
DIGITAL SIGNAL
PROCESSOR
32-BIT REGISTER
AVA
THRESHOLD
24
34
27 26
VATHR
0
0
Figure 81. Apparent Power Data Flow and Apparent Energy Accumulation
Rev. 0 | Page 63 of 120
11116-075
VATHR =
(46)
ADE7978/ADE7933/ADE7932
Data Sheet
INTEGRATION TIME UNDER STEADY LOAD
The discrete time sample period (T) for the accumulation
registers is 976.5625 ns (1.024 MHz frequency). With full-scale
pure sinusoidal signals on the analog inputs, the average word
value representing the apparent power is PMAX. If the VATHR
threshold register is set to 3 (its minimum recommended value),
the first stage accumulator generates a pulse that is added to the
xVAHR registers at intervals of
PMAX × 1.024 × 10 6
= 14.5683 µs
In line cycle energy accumulation mode, the energy accumulation
is synchronized to the voltage channel zero crossings, allowing
apparent energy to be accumulated over an integral number of
half line cycles. In line cycle energy accumulation mode, the
ADE7978 transfers the apparent energy accumulated in the 32-bit
internal accumulation registers to the xVAHR registers after an
integral number of line cycles (see Figure 82). The number of half
line cycles is specified in the LINECYC register (Address 0xE60C).
The maximum value that can be stored in the xVAHR accumulation register before it overflows is 231 − 1 or 0x7FFFFFFF. The
integration time is calculated as follows:
Time = 0x7FFFFFFF × 14.5683 μs = 8 hr, 41 min, 25 sec
ZXSEL[0] IN
LCYCMODE[7:0]
ZEROCROSSING
DETECTION
(PHASE A)
(47)
ENERGY ACCUMULATION MODE
ZEROCROSSING
DETECTION
(PHASE B)
The apparent power is accumulated in each 32-bit VA-hour
accumulation register (AVAHR, BVAHR, and CVAHR) according to the configuration of Bits[5:4] (CONSEL[1:0] bits) in the
ACCMODE register (see Table 26).
1
CVAHR
CVRMS × CIRMS
CVRMS × CIRMS
CALIBRATION
CONTROL
ZXSEL[2] IN
LCYCMODE[7:0]
ZEROCROSSING
DETECTION
(PHASE C)
Table 26. Inputs to VA-Hour Accumulation Registers
CONSEL[1:0] AVAHR
BVAHR
00
AVRMS × AIRMS BVRMS × BIRMS
01
AVRMS × AIRMS BVRMS × BIRMS
VB = VA − VC1
10
Reserved
11
AVRMS × AIRMS BVRMS × BIRMS
VB = −VA
LINECYC[15:0]
ZXSEL[1] IN
LCYCMODE[7:0]
AIRMS
APGAIN
AVAHR[31:0]
INTERNAL
ACCUMULATOR
32-BIT REGISTER
AVRMS
THRESHOLD
CVRMS × CIRMS
34
BWATTHR and BFWATTHR Accumulation Register in
3-Phase, 3-Wire Configurations
In a 3-phase, 3-wire configuration (CONSEL[1:0] = 01), the
ADE7978 computes the rms value of the line voltage between
Phase A and Phase C and stores the result in the BVRMS register
(see the Voltage RMS in Delta Configurations section). The
Phase B current value provided after the HPF is 0; therefore,
the powers associated with Phase B are 0.
To avoid any errors in the frequency output pins (CF1, CF2, or
CF3) related to the powers associated with Phase B, disable the
contribution of Phase B to the energy-to-frequency converters
by setting the TERMSEL1[1], TERMSEL2[1], or TERMSEL3[1]
bit to 0 in the COMPMODE register (Address 0xE60E). For more
information, see the Energy-to-Frequency Conversion section.
27 26
VATHR
See the BWATTHR and BFWATTHR Accumulation Register in 3-Phase, 3-Wire
Configurations section.
0
0
Figure 82. Line Cycle Apparent Energy Accumulation Mode
The line cycle apparent energy accumulation mode is activated by
setting Bit 2 (LVA) in the LCYCMODE register (Address 0xE702).
The apparent energy accumulated over an integer number of half
line cycles (or zero crossings) is written to the xVAHR accumulation registers after the number of half line cycles specified in the
LINECYC register is detected. When using the line cycle accumulation mode, set Bit 6 (RSTREAD) of the LCYCMODE register
to Logic 0 because a read with reset of the xVAHR registers
outside the LINECYC period resets the energy accumulation.
Phase A, Phase B, and Phase C zero crossings are included
when counting the number of half line cycles by setting
Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combination of zero crossings from all three phases can be used to
count the zero crossings. Select only one phase at a time for
inclusion in the count of zero crossings during calibration.
For more information about setting the LINECYC register and
Bit 5 (LENERGY) in the MASK0 register associated with the
line cycle accumulation mode, see the Line Cycle Active Energy
Accumulation Mode section.
Rev. 0 | Page 64 of 120
11116-076
3 × 2 27
LINE CYCLE APPARENT ENERGY ACCUMULATION
MODE
Data Sheet
ADE7978/ADE7933/ADE7932
POWER FACTOR CALCULATION AND TOTAL HARMONIC DISTORTION CALCULATION
POWER FACTOR CALCULATION
The ADE7978 provides a direct power factor measurement
simultaneously on all phases. Power factor in an ac circuit is
defined as the ratio of the total active power flowing to the load
to the apparent power. The absolute power factor measurement
is defined in terms of leading or lagging, referring to whether
the current waveform is leading or lagging the voltage waveform.
When the current waveform is leading the voltage waveform, the
load is capacitive and is defined as a negative power factor. When
the current waveform is lagging the voltage waveform, the load
is inductive and is defined as a positive power factor. Figure 83
illustrates the relationship of the current waveform to the
voltage waveform.
ACTIVE (+)
REACTIVE (–)
PF (–)
ACTIVE (–)
REACTIVE (–)
PF (+)
CAPACITIVE:
CURRENT LEADS
VOLTAGE
θ = +60°
PF = –0.5
θ = –60°
PF = +0.5
To use the line cycle accumulation mode to determine the power
factor, the ADE7978 must be configured as follows:
•
11116-077
INDUCTIVE:
CURRENT LAGS
VOLTAGE
ACTIVE (+)
REACTIVE (+)
PF (+)
ACTIVE (–)
REACTIVE (+)
PF (–)
By default, the instantaneous total phase active and apparent
powers are used to calculate the power factor; the registers are
updated at a rate of 8 kHz. The sign bit is taken from the instantaneous total phase reactive energy measurement on each phase.
If a power factor measurement with more averaging is required,
the ADE7978 can use the line cycle accumulation measurement
on the active and apparent energies to determine the power
factor. This option provides a more stable power factor reading.
V
I
The ADE7978 provides a power factor measurement on all phases
simultaneously. These readings are stored in three 16-bit signed
twos complement registers: APF (Address 0xE902) for Phase A,
BPF (Address 0xE903) for Phase B, and CPF (Address 0xE904)
for Phase C. The MSB of these registers indicates the polarity of
the power factor. Each LSB of the APF, BPF, and CPF registers
equates to a weight of 2−15. Therefore, the maximum register value
of 0x7FFF equates to a power factor value of 1, and the minimum
register value of 0x8000 corresponds to a power factor of −1. If
the power factor is outside the −1 to +1 range (because of offset
and gain calibrations), the result is set to −1 or +1, depending
on the sign of the fundamental reactive power.
•
Figure 83. Capacitive and Inductive Loads
As shown in Figure 83, the reactive power measurement is
negative when the load is capacitive and positive when the load
is inductive. The sign of the reactive power can therefore be
used to reflect the sign of the power factor. The ADE7978 uses
the sign of the total reactive power as the sign of the absolute
power factor. If the total reactive power is in a no load state, the
sign of the power factor is the sign of the total active power.
Equation 48 shows the mathematical definition of power factor.
Power Factor = (Sign Total Reactive Power) ×
Total Active Power
Apparent Power
(48)
Set the PFMODE bit (Bit 7) to 1 in the LCYCMODE
register (Address 0xE702).
Enable line cycle accumulation mode on both the active
and apparent energies by setting the LWATT and LVA bits
to 1 in the LCYCMODE register. The update rate of the
power factor measurement is now an integral number of
half line cycles that can be programmed in the LINECYC
register (Address 0xE60C).
For complete information about configuring line cycle accumulation mode, see the Line Cycle Active Energy Accumulation Mode
and Line Cycle Apparent Energy Accumulation Mode sections.
Note that the power factor measurement is affected by the no
load condition if no load detection is enabled (see the No Load
Condition section). If the apparent energy no load condition is
true, the power factor measurement is set to 1. If the no load
condition based on total active and reactive energies is true, the
power factor measurement is set to 0.
Rev. 0 | Page 65 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
TOTAL HARMONIC DISTORTION CALCULATION
The ADE7978 computes the total harmonic distortion (THD)
on all phase currents and voltages. The THD expressions are
shown in the following equations:
THD I =
THDV =
I 2 − I 12
I1
(49)
V 2 − V12
The THD calculations are stored in the AVTHD, AITHD,
BVTHD, BITHD, CVTHD, and CITHD registers (Address 0xE521
to Address 0xE526). These registers are 24-bit registers in 3.21
signed format. This means the ratios are limited to +3.9999 and
all greater results are clamped to it.
Like the xIRMS and xFIRMS registers, the 24-bit signed xITHD
and xVTHD registers are transmitted as 32-bit registers with
the eight MSBs padded with 0s (see Figure 67).
V1
where:
I and V are the rms values of the phase currents and voltages
stored in the AIRMS, AVRMS, BIRMS, BVRMS, CIRMS, and
CVRMS registers.
I1 and V1 are the fundamental rms values stored in the AFIRMS,
AFVRMS, BFIRMS, BFVRMS, CFIRMS, and CFVRMS
registers.
Rev. 0 | Page 66 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
WAVEFORM SAMPLING MODE
The current and voltage waveform samples, as well as the active,
reactive, and apparent power outputs and the total harmonic
distortion values, are stored every 125 µs (8 kHz rate) in 24-bit
signed registers that can be accessed using any of the serial port
interfaces of the ADE7978. Table 27 lists these registers.
Bit 17 (DREADY) in the STATUS0 register (Address 0xE502)
can be used to signal when the registers listed in Table 27 can
be read using the I2C or SPI serial port. An interrupt attached
to the flag can be enabled by setting Bit 17 (DREADY) in the
MASK0 register (Address 0xE50A). For more information about
the DREADY bit, see the Digital Signal Processor section.
In addition, if Bits[1:0] (ZX_DREADY) in the CONFIG register
(Address 0xE618) are set to 00, the DREADY functionality is
selected at the ZX/DREADY pin. In this case, the ZX/DREADY
pin goes low approximately 70 ns after the DREADY bit is set to
1 in the STATUS0 register. The ZX/DREADY pin stays low for
10 µs and then returns high. The low to high transition of the
ZX/DREADY pin can be used to initiate a burst read of the waveform sample registers. For more information, see the I2C Burst
Read Operation and the SPI Burst Read Operation sections.
The ADE7978 includes a high speed data capture (HSDC) port
that is specially designed to provide fast access to the following
waveform sample registers: IAWV, IBWV, ICWV, INWV,
VAWV, VBWV, VCWV, AWATT, BWATT, CWATT, AVAR,
BVAR, CVAR, AVA, BVA, and CVA. For more information
about the HSDC interface, see the HSDC Interface section.
The serial ports of the ADE7978 work with 32-, 16-, or 8-bit
words, whereas the DSP works with 28-bit words. Like the
xIGAIN registers shown in Figure 44, the registers listed in
Table 27 are sign extended to 28 bits and padded with four 0s
for transmission as 32-bit registers.
Table 27. Waveform Sample Registers
Register
IAWV
IBWV
ICWV
INWV
VAWV
VBWV
VCWV
VA2WV
VB2WV
VC2WV
VNWV
VN2WV
AVA
BVA
CVA
AWATT
BWATT
CWATT
AVAR
BVAR
CVAR
AVTHD
AITHD
BVTHD
BITHD
CVTHD
CITHD
Rev. 0 | Page 67 of 120
Description
Phase A current
Phase B current
Phase C current
Neutral current
Phase A voltage
Phase B voltage
Phase C voltage
Phase A auxiliary voltage
Phase B auxiliary voltage
Phase C auxiliary voltage
Neutral line voltage
Neutral line auxiliary voltage
Phase A apparent power
Phase B apparent power
Phase C apparent power
Phase A total active power
Phase B total active power
Phase C total active power
Phase A total reactive power
Phase B total reactive power
Phase C total reactive power
Phase A voltage total harmonic distortion
Phase A current total harmonic distortion
Phase B voltage total harmonic distortion
Phase B current total harmonic distortion
Phase C voltage total harmonic distortion
Phase C current total harmonic distortion
ADE7978/ADE7933/ADE7932
Data Sheet
ENERGY-TO-FREQUENCY CONVERSION
Two sets of bits specify the powers that are converted on the
CFx pins: the TERMSELx[2:0] bits and the CFxSEL[2:0] bits.
The ADE7978 provides three frequency output pins: CF1, CF2,
and CF3. The CF3 pin is multiplexed with the HSCLK pin of the
HSDC interface. When HSDC is enabled, the CF3 functionality
is disabled at the pin. The CF1 and CF2 pins are always available.
TERMSELx[2:0] BITS
Bits[2:0] (TERMSEL1[2:0]), Bits[5:3] (TERMSEL2[2:0]),
and Bits[8:6] (TERMSEL3[2:0]) of the COMPMODE register
(Address 0xE60E) specify which phases are summed in the
energy-to-frequency conversion.
After initial calibration at manufacturing, the manufacturer or
end customer verifies the energy meter calibration. One convenient way to verify the meter calibration is to provide an output
frequency proportional to the active, reactive, or apparent power
under steady load conditions. This output frequency can provide
a simple, single-wire, optically isolated interface to external calibration equipment. Figure 84 illustrates the energy-to-frequency
conversion in the ADE7978.
•
•
•
The TERMSEL1[2:0] bits configure the CF1 pin.
The TERMSEL2[2:0] bits configure the CF2 pin.
The TERMSEL3[2:0] bits configure the CF3 pin.
The TERMSELx[0] bits manage Phase A. When these bits are
set to 1, Phase A power is included in the sum of powers at the
CFx converter; when these bits are cleared to 0, Phase A power
is not included in the sum of powers. The TERMSELx[1] bits
manage Phase B, and the TERMSELx[2] bits manage Phase C.
The DSP computes the instantaneous values of all phase
powers: total active, fundamental active, total reactive, fundamental reactive, and apparent. For information about how the
energy is sign accumulated in the xWATTHR, xFWATTHR,
xVARHR, xFVARHR, and xVAHR registers, see the Active
Energy Calculation, Reactive Energy Calculation, and Apparent
Energy Calculation sections.
Setting all TERMSELx[2:0] bits to 1 means that the powers
from all three phases are added at the CFx converter. Clearing
all TERMSELx[2:0] bits to 0 means that no phase power is
added at the CFx converter and no CF pulse is generated.
In the energy-to-frequency conversion process, the instantaneous powers generate signals at the frequency output pins
(CF1, CF2, and CF3). One energy-to-frequency converter is
used for every CFx pin. Each converter sums certain phase
powers and generates a signal proportional to the sum.
CFxSEL[2:0] BITS
Bits[2:0] (CF1SEL[2:0]), Bits[5:3] (CF2SEL[2:0]), and Bits[8:6]
(CF3SEL[2:0]) in the CFMODE register (Address 0xE610)
specify what type of power is used at the inputs of the CF1, CF2,
and CF3 converters, respectively (see Table 28).
TERMSELx BITS IN
COMPMODE
INSTANTANEOUS
PHASE B
ACTIVE POWER
INSTANTANEOUS
PHASE C
ACTIVE POWER
CFxSEL BITS IN
CFMODE
VA
27
WATT
REVPSUMx BIT OF
STATUS0[31:0]
VAR
INTERNAL
ACCUMULATOR
FWATT
FVAR
FREQUENCY
DIVIDER
CFx PULSE
OUTPUT
THRESHOLD
CFxDEN
DIGITAL SIGNAL
PROCESSOR
27
34
27 26
WTHR
0
0
Figure 84. Energy-to-Frequency Conversion
Table 28. Description of the CFxSEL[2:0] Bits in the CFMODE Register
CFxSEL[2:0]
000
001
010
011
100
101 to 111
CFx Signal Proportional to the Sum of
Total phase active powers
Total phase reactive powers
Phase apparent powers
Fundamental phase active powers
Fundamental phase reactive powers
Reserved
Registers Latched When CFxLATCH = 1
AWATTHR, BWATTHR, CWATTHR
AVARHR, BVARHR, CVARHR
AVAHR, BVAHR, CVAHR
AFWATTHR, BFWATTHR, CFWATTHR
AFVARHR, BFVARHR, CFVARHR
Rev. 0 | Page 68 of 120
11116-078
INSTANTANEOUS
PHASE A
ACTIVE POWER
Data Sheet
ADE7978/ADE7933/ADE7932


The CF1 converter produces signals proportional to the
sum of the total active powers on all three phases.
The CF2 converter produces signals proportional to the
sum of the total reactive powers on all three phases.
The CF3 converter produces signals proportional to the
sum of the apparent powers on all three phases.
ENERGY-TO-FREQUENCY CONVERSION PROCESS
The energy-to-frequency conversion is accomplished in two
stages. The first stage is the same as for the energy accumulation
processes described in the Active Energy Calculation, Reactive
Energy Calculation, and Apparent Energy Calculation sections.
The second stage uses the frequency divider implemented by
the 16-bit unsigned registers CF1DEN, CF2DEN, and CF3DEN
(Address 0xE611 to Address 0xE613). The values of the CFxDEN
registers depend on the meter constant (MC), measured in
impulses/kWh, and how much energy is assigned to one LSB of
the various energy registers (xWATTHR, xVARHR, and so on).
For example, if a derivative of Wh (10n Wh, where n is an integer)
is desired as one LSB of the xWATTHR register, CFxDEN is
calculated using the following equation:
CFxDEN 
103
MC [impulses/kW h]  10n
(50)
The derivative of Wh must be selected to obtain a CFxDEN
register value greater than 1. If CFxDEN = 1, the CFx pin stays
active low for only 1 μs. For this reason, do not set the CFxDEN
register to 1. The frequency converter cannot accommodate
fractional results; the result of the division must be rounded to
the nearest integer. If CFxDEN is set equal to 0, the ADE7978
considers it to be equal to 1.
The CFx pulse output stays low for 80 ms if the pulse period is
greater than 160 ms (6.25 Hz). If the pulse period is less than
160 ms and CFxDEN is an even number, the duty cycle of the pulse
output is exactly 50%. If the pulse period is less than 160 ms and
CFxDEN is an odd number, the duty cycle of the pulse output is
(1 + 1/CFxDEN) × 50%
The maximum pulse frequency at the CF1, CF2 or CF3 pins
is 68.8 kHz and is obtained on one phase under the following
conditions:



WTHR, VARTHR, and VATHR registers are set to 3.
CF1DEN, CF2DEN, and CF3DEN registers are set to 1.
Phase is supplied with in-phase full-scale currents and
voltages.
The CFx pulse output is active low. It is recommended that the
pin be connected to an LED, as shown in Figure 85. No transistor
is required to supplement the drive strength of the CFx pin.
CFx PIN
Figure 85. CFx Pin Recommended Connection
Bits[11:9] (CF3DIS, CF2DIS, and CF1DIS) of the CFMODE
register (Address 0xE610) specify whether the frequency
converter output is generated at the CF3, CF2, or CF1 pin. When
Bit CFxDIS is set to 1 (the default value), the CFx pin is disabled
and the pin stays high. When Bit CFxDIS is cleared to 0, the
corresponding CFx pin output generates an active low signal.
Bits[16:14] (CF3, CF2, and CF1) in the MASK0 register
(Address 0xE50A) manage the CF3, CF2, and CF1 interrupts.
If the CFx bits are set and a high to low transition at the corresponding frequency converter output occurs, the IRQ0 interrupt
is triggered and the appropriate bit in the STATUS0 register is
set to 1. The interrupts are available even if the CFx outputs are
not enabled by the CFxDIS bits in the CFMODE register.
SYNCHRONIZING ENERGY REGISTERS WITH THE
CFx OUTPUTS
The ADE7978 allows the contents of the phase energy accumulation registers to be synchronized with the generation of a CFx
pulse. When a high to low transition at one frequency converter
output occurs, the contents of all internal phase energy registers
that relate to the power being output at the CFx pin are latched into
the hour registers and then reset to 0. See Table 28 for the list of
registers that are latched based on the CFxSEL[2:0] bits in the
CFMODE register. All three phase registers are latched independent of the setting of the TERMSELx[2:0] bits of the COMPMODE
register. Figure 86 shows this process for CF1SEL[2:0] = 010
(apparent powers contribute at the CF1 pin) and CFCYC = 2.
CF1 PULSE
BASED ON
PHASE A AND
PHASE B
APPARENT
POWERS
CFCYC = 2
AVAHR, BVAHR,
CVAHR LATCHED
ENERGY REGISTERS
RESET
AVAHR, BVAHR,
CVAHR LATCHED
ENERGY REGISTERS
RESET
11116-080

11116-079
VDD
By default, the TERMSELx[2:0] bits are set to 1, the CF1SEL[2:0]
bits are set to 000, the CF2SEL[2:0] bits are set to 001, and the
CF3SEL[2:0] bits are set to 010. Therefore, the default configuration for the energy-to-frequency converters is as follows:
Figure 86. Synchronizing AVAHR and BVAHR with CF1
The 8-bit unsigned CFCYC register (Address 0xE705) contains
the number of high to low transitions at the frequency converter
output between two consecutive latches. Avoid writing a new
value to the CFCYC register during a high to low transition at
any CFx pin.
Bits[14:12] (CF3LATCH, CF2LATCH, and CF1LATCH) of the
CFMODE register enable the latching of the phase energy accumulation registers when the bits are set to 1. When these bits are
cleared to 0 (the default state), no latching occurs. The latching
process can be used even if the CFx outputs are not enabled by
the CFxDIS bits in the CFMODE register.
Rev. 0 | Page 69 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
ENERGY REGISTERS AND CFx OUTPUTS FOR
VARIOUS ACCUMULATION MODES
ACTIVE ENERGY
NO LOAD
THRESHOLD
ACTIVE POWER
NO LOAD
THRESHOLD
When WATTACC[1:0] = 00 (the default value), the active powers
are sign accumulated in the watthour energy registers before entering the energy-to-frequency converter. Figure 87 shows how signed
active power accumulation works. In this mode, the CFx pulses
synchronize perfectly with the active energy accumulated in the
xWATTHR and xFWATTHR registers because the powers are
sign accumulated in both datapaths.
REVAPx BIT
IN STATUS0
xWSIGN BIT
IN PHSIGN
APNOLOAD
SIGN = POSITIVE
POS
NEG POS NEG
11116-082
Bits[1:0] (WATTACC[1:0]) in the ACCMODE register
(Address 0xE701) specify the accumulation mode of the total
and fundamental active powers when signals proportional to
the active powers are selected at the CFx pins (the CFxSEL[2:0]
bits in the CFMODE register are set to 000 or 011). These bits
also specify the accumulation mode of the watthour energy
registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR).
Figure 88. Active Power Positive Only Accumulation Mode
The WATTACC[1:0] = 10 setting is reserved, and the ADE7978
behaves identically to the case when WATTACC[1:0] = 00.
ACTIVE ENERGY
When WATTACC[1:0] = 11, the active powers are accumulated
in absolute mode. When the powers are negative, they change
sign and are accumulated together with the positive power in
the watthour registers before entering the energy-to-frequency
converter.
NO LOAD
THRESHOLD
ACTIVE POWER
In this mode, the CFx pulses synchronize perfectly with the
active energy accumulated in the xWATTHR and xFWATTHR
registers because the powers are accumulated in the same way
in both datapaths. Figure 89 shows how absolute active power
accumulation works.
NO LOAD
THRESHOLD
REVAPx BIT
IN STATUS0
APNOLOAD
SIGN = POSITIVE
POS
NEG POS
NEG
11116-081
xWSIGN BIT
IN PHSIGN
Figure 87. Active Power Signed Accumulation Mode
When WATTACC[1:0] = 01, the active powers are accumulated
in positive only mode. When the powers are negative, the watthour energy registers do not accumulate them. The CFx pulses
are generated based on signed accumulation mode. When
WATTACC[1:0] = 01, the CFx pulses do not synchronize
perfectly with the active energy accumulated in the xWATTHR
and xFWATTHR registers because the powers are accumulated
differently in each datapath. Figure 88 shows how positive only
active power accumulation works.
ACTIVE ENERGY
NO LOAD
THRESHOLD
ACTIVE POWER
NO LOAD
THRESHOLD
REVAPx BIT
IN STATUS0
APNOLOAD
SIGN = POSITIVE
POS
NEG POS
NEG
Figure 89. Active Power Absolute Accumulation Mode
Rev. 0 | Page 70 of 120
11116-083
xWSIGN BIT
IN PHSIGN
Data Sheet
ADE7978/ADE7933/ADE7932
Bits[3:2] (VARACC[1:0]) in the ACCMODE register specify the
accumulation mode of the total and fundamental reactive powers
when signals proportional to the reactive powers are selected at
the CFx pins (the CFxSEL[2:0] bits in the CFMODE register are
set to 001 or 100). These bits also specify the accumulation mode
of the var-hour energy registers (AVARHR, BVARHR, CVARHR,
AFVARHR, BFVARHR, and CFVARHR).
NO LOAD
THRESHOLD
REACTIVE
POWER
NO LOAD
THRESHOLD
NO LOAD
THRESHOLD
ACTIVE
POWER
REVRPx BIT
IN STATUS0
xVARSIGN BIT
IN PHSIGN
VARNOLOAD
SIGN = POSITIVE
POS
NEG POS
11116-085
When VARACC[1:0] = 00 (the default value), the reactive powers
are sign accumulated in the var-hour energy registers before
entering the energy-to-frequency converter. Figure 90 shows
how signed reactive power accumulation works. In this mode,
the CFx pulses synchronize perfectly with the reactive energy
accumulated in the xVARHR and xFVARHR registers because
the powers are sign accumulated in both datapaths.
REACTIVE
ENERGY
Figure 91. Reactive Power Sign Adjusted Mode
REACTIVE
ENERGY
When VARACC[1:0] = 11, the reactive powers are accumulated
in absolute mode. When the powers are negative, they change
sign and are accumulated together with the positive power in
the var-hour registers before entering the energy-to-frequency
converter. In this mode, the CFx pulses synchronize perfectly
with the reactive energy accumulated in the xVARHR and
xFVARHR registers. Figure 92 shows how absolute reactive
power accumulation works.
NO LOAD
THRESHOLD
REACTIVE
POWER
NO LOAD
THRESHOLD
REVRPx BIT
IN STATUS0
POS
NEG POS
NEG
REACTIVE ENERGY
Figure 90. Reactive Power Signed Accumulation Mode
The VARACC[1:0] = 01 setting is reserved, and the ADE7978
behaves identically to the case when VARACC[1:0] = 00.
When VARACC[1:0] = 10, the reactive powers are accumulated
depending on the sign of the corresponding active power in the
var-hour energy registers before entering the energy-to-frequency
converter. If the active power is positive or considered 0 when
lower than the no load threshold APNOLOAD, the reactive
power is accumulated as is. If the active power is negative, the
sign of the reactive power is changed for accumulation.
NO LOAD
THRESHOLD
REACTIVE POWER
Figure 91 shows how the sign adjusted reactive power accumulation mode works. In this mode, the CFx pulses synchronize
perfectly with the reactive energy accumulated in the xVARHR
and xFVARHR registers because the powers are accumulated in
the same way in both datapaths.
Rev. 0 | Page 71 of 120
NO LOAD
THRESHOLD
REVRPx BIT
IN STATUS0
xVARSIGN BIT
IN PHSIGN
VARNOLOAD
SIGN = POSITIVE
POS
NEG POS NEG
Figure 92. Reactive Power Absolute Accumulation Mode
11116-086
VARNOLOAD
SIGN = POSITIVE
11116-084
xVARSIGN BIT
IN PHSIGN
ADE7978/ADE7933/ADE7932
Data Sheet
SIGN OF SUM OF PHASE POWERS IN THE CFx
DATAPATH
The ADE7978 has sign detection circuitry for the sum of phase
powers that are used in the CFx datapath. As described in the
Energy-to-Frequency Conversion Process section, the energy
accumulation in the CFx datapath is executed in two stages. Each
time a sign change is detected in the energy accumulation at the
end of the first stage—that is, after the energy accumulated in the
accumulator reaches one of the WTHR, VARTHR, or VATHR
thresholds—a dedicated interrupt can be triggered synchronously
with the corresponding CFx pulse. The sign of each sum can be
read in the PHSIGN register (Address 0xE617).
Bit 18, Bit 13, and Bit 9 (REVPSUM3, REVPSUM2, and
REVPSUM1, respectively) of the STATUS0 register are set to 1
when a sign change of the sum of powers in the CF3, CF2, or CF1
datapaths occurs. To correlate these events with the pulses generated at the CFx pins after a sign change occurs, the REVPSUM3,
REVPSUM2, or REVPSUM1 bit is set when a high to low transition occurs at the CF3, CF2, or CF1 pin, respectively.
Bit 8, Bit 7, and Bit 3 (SUM3SIGN, SUM2SIGN, and
SUM1SIGN, respectively) of the PHSIGN register are set to 1 when
the REVPSUM3, REVPSUM2, and REVPSUM1 bits are set to 1.
The SUMxSIGN bits indicate the sign of the sum of phase powers.
When these bits are cleared to 0, the sum is positive. When the
bits are set to 1, the sum is negative.
Interrupts attached to Bit 18, Bit 13, and Bit 9 (REVPSUM3,
REVPSUM2, and REVPSUM1, respectively) in the STATUS0
register are enabled by setting Bit 18, Bit 13, and Bit 9 in the
MASK0 register. If enabled, the IRQ0 pin is set low and the
status bit is set to 1 when a change of sign occurs. To identify
the phase that triggered the interrupt, read the PHSIGN register
immediately after reading the STATUS0 register. Then clear the
status bit by writing a 1 to the appropriate bit in the STATUS0
register; the IRQ0 pin is set high again.
Rev. 0 | Page 72 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
NO LOAD CONDITION
The no load condition is defined in metering equipment
standards as a condition where voltage is applied to the meter
but no current flows in the current circuit. To eliminate any
creep effects in the meter, the ADE7978 contains three separate
no load detection circuits: one related to the total active and
reactive powers, one related to the fundamental active and
reactive powers, and one related to the apparent power.
NO LOAD DETECTION BASED ON TOTAL ACTIVE
AND REACTIVE POWERS
The no load condition based on the total active and reactive
powers is triggered when no LSBs are accumulated in the total
active and reactive energy registers on one phase (xWATTHR and
xVARHR, x = A, B, or C) for the time specified in the APNOLOAD
and VARNOLOAD registers. In the no load condition, the total
active and reactive energies of the phase are not accumulated,
and no CFx pulses are generated based on these energies.
The equations used to compute the values of the 16-bit unsigned
registers APNOLOAD and VARNOLOAD are as follows:
APNOLOAD = 216 − 1 −
Y × WTHR × 217
VARNOLOAD = 216 − 1 −
PMAX
(51)
Y × VARTHR × 217
PMAX
where:
Y is the required no load current threshold computed relative
to full scale. For example, if the no load threshold current is set
10,000 times lower than the full-scale value, Y = 10,000.
WTHR and VARTHR are the values stored in the WTHR and
VARTHR registers. These values are used as the thresholds in
the first stage energy accumulators for active and reactive energy,
respectively (see the Active Energy Calculation and Reactive
Energy Calculation sections).
PMAX = 26,991,271, the instantaneous active power computed
when the ADC inputs are at full scale.
The VARNOLOAD register (Address 0xE909) usually contains
the same value as the APNOLOAD register (Address 0xE908).
When both the APNOLOAD and VARNOLOAD registers are set
to 0x0, the no load detection circuit is disabled. If the APNOLOAD
or VARNOLOAD threshold is set to 0 and the other threshold is
set to a non-zero value, the no load circuit is disabled, and the
total active and reactive powers are accumulated without any
restriction.
Bit 0 (NLOAD) in the STATUS1 register (Address 0xE503) is
set when a no load condition based on the total active or reactive
power is detected on one of the three phases. Bits[2:0]
(NLPHASE[2:0]) in the PHNOLOAD register (Address 0xE608)
indicate the state of all phases relative to a no load condition and
are set simultaneously with the NLOAD bit in the STATUS1
register.
NLPHASE[0] indicates the state of Phase A, NLPHASE[1]
indicates the state of Phase B, and NLPHASE[2] indicates the
state of Phase C. When the NLPHASE[x] bit is cleared to 0,
Phase x is not in a no load condition. When the bit is set to 1,
Phase x is in a no load condition.
An interrupt attached to Bit 0 (NLOAD) in the STATUS1
register can be enabled by setting Bit 0 in the MASK1 register
(Address 0xE50B). When enabled, the IRQ1 pin goes low and the
status bit is set to 1 when any of the three phases enters or exits the
no load condition. To identify the phase that triggered the interrupt, read the PHNOLOAD register immediately after reading
the STATUS1 register. The status bit is cleared and the IRQ1 pin
is returned high by writing a 1 to Bit 0 in the STATUS1 register.
NO LOAD DETECTION BASED ON FUNDAMENTAL
ACTIVE AND REACTIVE POWERS
The no load condition based on the fundamental active and
reactive powers is triggered when no LSBs are accumulated in
the fundamental active and reactive energy registers on one phase
(xFWATTHR and xFVARHR, x = A, B, or C) for the time specified
in the 16-bit unsigned APNOLOAD and VARNOLOAD registers.
In the no load condition, the fundamental active and reactive
energies of the phase are not accumulated, and no CFx pulses
are generated based on these energies.
APNOLOAD and VARNOLOAD are the same no load
thresholds set for the total active and reactive energies. When
both the APNOLOAD and VARNOLOAD registers are set to
0x0, the no load detection circuit is disabled. If the APNOLOAD
or VARNOLOAD threshold is set to 0 and the other threshold
is set to a non-zero value, the no load circuit is disabled, and the
fundamental active and reactive powers are accumulated without
any restriction.
Bit 1 (FNLOAD) in the STATUS1 register is set when a no load
condition based on the fundamental active or reactive power is
detected on one of the three phases. Bits[5:3] (FNLPHASE[2:0])
in the PHNOLOAD register indicate the state of all phases
relative to a no load condition and are set simultaneously with
the FNLOAD bit in the STATUS1 register.
FNLPHASE[0] indicates the state of Phase A, FNLPHASE[1]
indicates the state of Phase B, and FNLPHASE[2] indicates the
state of Phase C. When the FNLPHASE[x] bit is cleared to 0,
Phase x is not in a no load condition. When the bit is set to 1,
Phase x is in a no load condition.
An interrupt attached to Bit 1 (FNLOAD) in the STATUS1
register can be enabled by setting Bit 1 in the MASK1 register.
When enabled, the IRQ1 pin goes low and the status bit is set to 1
when any of the three phases enters or exits the no load condition. To identify the phase that triggered the interrupt, read the
PHNOLOAD register immediately after reading the STATUS1
register. The status bit is cleared and the IRQ1 pin is returned
high by writing a 1 to Bit 1 in the STATUS1 register.
Rev. 0 | Page 73 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
NO LOAD DETECTION BASED ON APPARENT
POWER
When the VANOLOAD register (Address 0xE90A) is set to 0x0,
the no load detection circuit is disabled.
The no load condition based on the apparent power is triggered
when no LSBs are accumulated in the apparent energy register
on one phase (xVAHR, x = A, B, or C) for the time specified in
the VANOLOAD register. In the no load condition, the apparent
energy of the phase is not accumulated, and no CFx pulses are
generated based on this energy.
Bit 2 (VANLOAD) in the STATUS1 register is set when a no load
condition based on apparent power is detected on one of the
three phases. Bits[8:6] (VANLPHASE[2:0]) in the PHNOLOAD
register indicate the state of all phases relative to a no load condition and are set simultaneously with the VANLOAD bit in the
STATUS1 register.
The equation used to compute the value of the 16-bit unsigned
VANOLOAD register is as follows:
VANLPHASE[0] indicates the state of Phase A, VANLPHASE[1]
indicates the state of Phase B, and VANLPHASE[2] indicates the
state of Phase C. When the VANLPHASE[x] bit is cleared to 0,
Phase x is not in a no load condition. When the bit is set to 1,
Phase x is in a no load condition.
VANOLOAD = 216 − 1 −
Y × VATHR × 217
PMAX
(52)
where:
Y is the required no load current threshold computed relative
to full scale. For example, if the no load threshold current is set
10,000 times lower than the full-scale value, Y = 10,000.
VATHR is the value stored in the VATHR register. This value is
used as the threshold in the first stage energy accumulator for
apparent energy (see the Apparent Energy Calculation section).
PMAX = 26,991,271, the instantaneous active power computed
when the ADC inputs are at full scale.
An interrupt attached to Bit 2 (VANLOAD) in the STATUS1
register can be enabled by setting Bit 2 in the MASK1 register.
When enabled, the IRQ1 pin goes low and the status bit is set to
1 when any of the three phases enters or exits the no load condition. To identify the phase that triggered the interrupt, read the
PHNOLOAD register immediately after reading the STATUS1
register. The status bit is cleared and the IRQ1 pin is returned
high by writing a 1 to Bit 2 in the STATUS1 register.
Rev. 0 | Page 74 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
INTERRUPTS
The ADE7978 has two interrupt pins, IRQ0 and IRQ1. Each
pin is managed by a 32-bit interrupt mask register, MASK0
(Address 0xE50A) and MASK1 (Address 0xE50B), respectively.
To enable an interrupt, the appropriate bit in the MASKx register
must be set to 1. To disable an interrupt, the bit must be cleared
to 0. Two 32-bit status registers, STATUS0 (Address 0xE502) and
STATUS1 (Address 0xE503), are associated with the interrupts.
When an interrupt event occurs in the ADE7978, the corresponding flag in the status register is set to Logic 1 (see Table 43 and
Table 44). If the mask bit for the interrupt in the interrupt mask
register is Logic 1, the IRQx output goes active low. The flag bits in
the status registers are set regardless of the state of the mask bits.
To determine the source of the interrupt, the microcontroller
(MCU) reads the corresponding STATUSx register to identify
which bit is set to 1. To clear the flag in the status register, the
MCU writes back to the STATUSx register with the flag set to 1.
After an interrupt pin goes low, the status register is read and
the source of the interrupt is identified. A 1 is written back to
the status register to clear the status flag to 0. The IRQx pin
remains low until the status flag is cleared.
By default, all interrupts are disabled with the exception of the
RSTDONE interrupt. This interrupt cannot be disabled (masked)
and, therefore, Bit 15 (RSTDONE) in the MASK1 register has no
function. The IRQ1 pin always goes low and Bit 15 (RSTDONE)
in the STATUS1 register is always set to 1 when a power-up
or a hardware/software reset ends. To cancel the status flag, the
STATUS1 register must be written with Bit 15 (RSTDONE)
set to 1.
Certain interrupts are used in conjunction with other status
registers. When the STATUSx register is read and one of the bits
listed in Table 29 to Table 33 is set to 1, the status register associated with the bit is immediately read to identify the phase that
triggered the interrupt. Only after reading the associated status
register can the STATUSx register be written back with the bit
set to 1.
Table 30 lists the bits in the MASK1 register that work with bits
in the PHNOLOAD register (Address 0xE608).
Table 30. MASK1 Register Bits and PHNOLOAD Register Bits
MASK1 Register
(Address 0xE50B)
Bits
Bit Name
0
NLOAD
1
FNLOAD
2
VANLOAD
Table 31 lists the bits in the MASK1 register that work with bits
in the PHSTATUS register (Address 0xE600).
Table 31. MASK1 Register Bits and PHSTATUS Register Bits
MASK1 Register
(Address 0xE50B)
Bits
Bit Name
16
Sag
17
OI
18
OV
PHSTATUS Register
(Address 0xE600)
Bits
Bit Name
[14:12]
VSPHASE[2:0]
[5:3]
OIPHASE[2:0]
[11:9]
OVPHASE[2:0]
Table 32 and Table 33 list the bits in the MASK1 register that
work with bits in the IPEAK register (Address 0xE500) and the
VPEAK register (Address 0xE501).
Table 32. MASK1 Register Bits and IPEAK Register Bits
MASK1 Register
(Address 0xE50B)
Bits
Bit Name
23
PKI
IPEAK Register Register
(Address 0xE500)
Bits
Bit Name
[26:24]
IPPHASE[2:0]
Table 33. MASK1 Register Bits and VPEAK Register Bits
MASK1 Register
(Address 0xE50B)
Bits
Bit Name
24
PKV
Table 29 lists the bits in the MASK0 register that work with bits
in the PHSIGN register (Address 0xE617).
Table 29. MASK0 Register Bits and PHSIGN Register Bits
MASK0 Register
(Address 0xE50A)
Bits
Bit Name
[8:6]
REVAPx
[12:10]
REVRPx
9
REVPSUM1
13
REVPSUM2
18
REVPSUM3
PHNOLOAD Register
(Address 0xE608)
Bits
Bit Name
[2:0]
NLPHASE[2:0]
[5:3]
FNLPHASE[2:0]
[8:6]
VANLPHASE[2:0]
PHSIGN Register
(Address 0xE617)
Bits
Bit Name
[2:0]
xWSIGN[2:0]
[6:4]
xVARSIGN[2:0]
3
SUM1SIGN
7
SUM2SIGN
8
SUM3SIGN
Rev. 0 | Page 75 of 120
VPEAK Register
(Address 0xE501)
Bits
Bit Name
[26:24]
VPPHASE[2:0]
ADE7978/ADE7933/ADE7932
Data Sheet
If a subsequent interrupt event occurs during the ISR (t3), that event
is indicated by the MCU external interrupt flag being set again.
USING THE INTERRUPTS WITH AN MCU
Figure 93 shows a timing diagram for a suggested implementation of ADE7978 interrupt management using an MCU. At
Time t1, the IRQx pin goes low, indicating that one or more
interrupt events have occurred in the ADE7978. After the
IRQx pin goes low, the following steps take place:
3.
4.
5.
t1
t2
t3
MCU
INTERRUPT
FLAG SET
IRQx
PROGRAM
SEQUENCE
JUMP
TO ISR
GLOBAL
INTERRUPT
MASK
CLEAR MCU
INTERRUPT
FLAG
READ
STATUSx
WRITE
BACK
STATUSx
ISR ACTION
(BASED ON STATUSx CONTENTS)
ISR RETURN
GLOBAL INTERRUPT
MASK RESET
JUMP
TO ISR
11116-089
2.
Figure 94 shows a recommended timing diagram when the
status bits in the STATUSx registers work in conjunction with
bits in other registers. When the IRQx pin goes low, the STATUSx
register is read, and if one of these bits is set to 1, a second status
register is read immediately to identify the phase that triggered
the interrupt. In Figure 94, PHx denotes the PHNOLOAD,
PHSTATUS, IPEAK, VPEAK, or PHSIGN register. After reading
the PHx register, the STATUSx register is written back to clear
the status flags.
Tie the IRQx pin to a negative edge triggered external
interrupt on the MCU.
Configure the MCU to start executing its interrupt service
routine (ISR) when it detects the negative edge.
When the MCU starts executing the ISR, disable all
interrupts using the global interrupt mask bit. The MCU
external interrupt flag can now be cleared to capture
interrupt events that occur during the current ISR.
When the MCU interrupt flag is cleared, read STATUSx,
the interrupt status register. The interrupt status register
contents are used to determine the source of the interrupts
and, therefore, the appropriate action to take.
Write back the same STATUSx contents to the ADE7978 to
clear the status flags and reset the IRQx line to logic high (t2).
Figure 93. Interrupt Management
t1
t2
t3
MCU
INTERRUPT
FLAG SET
IRQx
PROGRAM
SEQUENCE
JUMP
TO ISR
GLOBAL
INTERRUPT
MASK
CLEAR MCU
INTERRUPT
FLAG
READ
STATUSx
READ
PHx
WRITE
BACK
STATUSx
ISR RETURN
ISR ACTION
JUMP
(BASED ON STATUSx CONTENTS) GLOBAL INTERRUPT TO ISR
MASK RESET
Figure 94. Interrupt Management When PHSTATUS, IPEAK, VPEAK, or PHSIGN Register Is Involved
Rev. 0 | Page 76 of 120
11116-090
1.
On returning from the ISR, the global interrupt mask bit is
cleared in the same instruction cycle, and the external interrupt
flag uses the MCU to jump to its ISR again. This action ensures
that the MCU does not miss any external interrupts.
Data Sheet
ADE7978/ADE7933/ADE7932
POWER MANAGEMENT
The dc-to-dc converter section of the ADE7933/ADE7932 works
on principles that are common to most modern power supply
designs. VDD power is supplied to an oscillating circuit that
switches current into a chip scale air core transformer. Power is
transferred to the secondary side, where it is rectified to a 3.3 V
dc voltage. This voltage is then supplied to the ADC section of
the ADE7933/ADE7932 through a 2.5 V LDO regulator.
The PWM control block operates at a frequency of 1.024 MHz
(CLKIN/4). Every other half period, the control block generates a
PWM pulse to the ac source based on the state of the EMI_CTRL
pin (see Figure 96).
PWM CONTROL PULSE
WHEN EMI_CTRL = VDD
PWM CONTROL PULSE
WHEN EMI_CTRL = GND
The state of the internal dc-to-dc converter in the ADE7933/
ADE7932 is controlled by the VDD input. In normal operational mode, maintain VDD at a voltage from 2.97 V to 3.63 V.
Figure 95 is a block diagram of the ADE7933/ADE7932 isolated
dc-to-dc converter. The primary supply voltage input (VDD)
supplies an ac source. The ac signal passes through a chip scale
air core transformer and is transferred to the secondary side. A
rectifier then produces the isolated power supply, VDDISO. Using
another chip scale air core transformer, a feedback circuit measures
VDDISO and passes the information back to the VDD domain,
where a PWM control block controls the ac source to maintain
VDDISO at 3.3 V.
ISOLATION
BARRIER
VDDISO
RECTIFIER
AC SOURCE
FEEDBACK
CIRCUIT
PWM
CONTROL
VDD = 3.3V
Figure 95. Isolated DC-to-DC Converter Block Diagram
11116-025
TO ADC
BLOCK
1.024MHz CLOCK
0
1
2
3
4
5
6
7
0
1
11116-026
DC-TO-DC CONVERTER
Figure 96. PWM Control Block Generates Pulses Based on 1.024 MHz Clock
Each time a PWM pulse is generated, the ac source transmits
very high frequency signals across the isolation barrier to allow
efficient power transfer through the small chip scale transformers.
This transfer creates high frequency currents that can propagate
in circuit board ground and power planes, causing edge and
dipole radiation.
To manage electromagnetic interference (EMI) issues, attention
must be paid to proper PCB layout. The Layout Guidelines
section describes the best approach to PCB layout. In addition
to creating a well-designed PCB layout, the designer can use the
EMI_CTRL pin to help reduce the emissions generated by the
dc-to-dc converter of the ADE7933/ADE7932.
Every four periods of the clock that manages the PWM control
block are divided into eight slots, Slot 0 to Slot 7 (see Figure 96).
When the EMI_CTRL pin is connected to GND, the PWM
control block generates pulses during Slot 0, Slot 2, Slot 4, and
Slot 6. When the EMI_CTRL pin is connected to VDD, the PWM
control block generates pulses during Slot 1, Slot 3, Slot 5, and
Slot 7. Table 34 describes the recommended connections for the
EMI_CTRL pin in all configurations of a 3-phase energy meter.
Table 34. Connection of EMI_CTRL Pins
No. of ADE7933/
ADE7932 Devices
1
2
3
4
Rev. 0 | Page 77 of 120
EMI_CTRL Pin Connections
Connect the pin to GND
Connect the pin to GND on one device;
connect the pin to VDD on the other device
Connect the pin to GND on two devices;
connect the pin to VDD on the third device
Connect the pin to GND on two devices;
connect the pin to VDD on the other devices
ADE7978/ADE7933/ADE7932
Data Sheet
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately
0.5 V, thus establishing a 0.5 V margin within which induced voltages can be tolerated. The voltage induced across the receiving
coil is given by
 dβ 
 ∑ πrn2
V =  −
 dt n = 1
N
(53)
where:
β is the ac magnetic field: β(t) = B × sin(ωt).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil.
Given the geometry of the receiving coil in the ADE7933/
ADE7932 and an imposed requirement that the induced voltage
(VTHR) be, at most, 50% of the 0.5 V margin at the decoder, a
maximum allowable magnetic field (B) is calculated, as shown
in Figure 97 and Equation 54.
B =
VTHR
(54)
N
2πf × ∑ πrn2
n =1
where f is the frequency of the magnetic field.
10
I=
B
µ0
× 2πd =
V ×d
(55)
N
µ 0 × f × ∑ πrn2
n =1
where µ0 is 4π × 10 H/m, the magnetic permeability of air.
−7
Figure 98 shows the allowable current magnitudes as a function
of frequency for selected distances. As shown in Figure 98, the
ADE7933/ADE7932 are extremely immune and can be affected
only by extremely large currents operated at high frequency very
close to the component. For the 10 kHz example, a current with
a magnitude of 69 kA must be placed 5 mm away from the
ADE7933/ADE7932 to affect the operation of the component.
1000
100
0.005m
0.1m
1m
10
1
0.1
0.01
1k
1
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 98. Maximum Allowable Current for Various Current-toADE7933/ADE7932 Spacings
0.1
0.01
0.001
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
11116-027
MAGNETIC FIELD MAXIMUM AMPLITUDE (T)
100
The preceding magnetic field values correspond to specific current
magnitudes at given distances from the ADE7933/ADE7932
transformers.
11116-028
Because the ADE7933/ADE7932 use air core transformers, the
devices are immune to dc magnetic fields. The limitation on the
ac magnetic field immunity of the ADE7933/ADE7932 is set by
the condition in which the induced voltage in the receiving coil
of the transformer is sufficiently large to either falsely set or reset
the decoder. The following analysis defines the conditions under
which this can occur. The 3.3 V operating condition is examined
because it is the nominal supply of the ADE7933/ADE7932.
For example, at a magnetic field frequency of 10 kHz, the maximum allowable magnetic field of 2.8 T induces a voltage of 0.25 V
at the receiving coil. This voltage is approximately 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse (and
is of the worst-case polarity), the received pulse is reduced from
more than 1.0 V to 0.75 V, still well above the 0.5 V sensing
threshold of the decoder.
MAXIMUM ALLOWABLE CURRENT (kA)
MAGNETIC FIELD IMMUNITY
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large to trigger the thresholds of succeeding
circuitry. Exercise care in the layout of such traces to avoid this
possibility (see the Layout Guidelines section).
Figure 97. Maximum Allowable External Magnetic Field
Rev. 0 | Page 78 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
7.
POWER-UP PROCEDURE
The ADE7978/ADE7933/ADE7932 chipset contains on-chip
power supply monitors that supervise the power supply (VDD).
The ADE7933/ADE7932 have a monitor with a threshold at
2.0 V ± 10% and a timeout timer of 23 ms. The ADE7978 has
a monitor with a threshold between 2.5 V and 2.6 V and a timeout timer of 32 ms. Because the ADE7933/ADE7932 are fully
managed by the ADE7978, the power supply monitor of the
ADE7978 determines the power-up of the chipset.
After a successful power-up of the chipset, follow the instructions
in the Initializing the Chipset section.
If the supply voltage, VDD, falls below 2 V ± 10%, the ADE7978
and the ADE7933/ADE7932 devices enter an inactive state, which
means that no measurements or computations are executed.
The ADE7978 is in an inactive state until VDD reaches the
threshold of 2.5 V to 2.6 V. The ADE7933/ADE7932 are also in
an inactive state. Before the chipset is powered up, make sure
that the power supply for the ADE7978 ensures a transition from
around 2.5 V or 2.6 V to 3.3 V − 10% in less than 32 ms. Figure 99
shows the power-up procedure, which follows these steps:
2.
3.
4.
5.
6.
INITIALIZING THE CHIPSET
After the ADE7978/ADE7933/ADE7932 are powered up,
initialize the chipset as follows.
1.
When VDD crosses the 2.5 V to 2.6 V threshold, the
ADE7978 power supply monitor keeps the chip in the
inactive state for an additional 32 ms, allowing VDD to reach
3.3 V − 10%, the minimum recommended supply voltage.
The ADE7978 starts to function and generates a 4.096 MHz
clock signal for the ADE7933/ADE7932 at the CLKOUT pin.
The ADE7933/ADE7932 devices begin to function.
After 20 μs, the ADE7978 resets the ADE7933/ADE7932
devices by setting the RESET_EN pin low. The ADE7978
toggles the following pins eight times from high to low at a
4.096 MHz frequency (CLKIN/4): VT_A, VT_B, VT_C,
and VT_N.
The ADE7933/ADE7932 devices begin to function at
default conditions.
When the ADE7978 and the ADE7933/ADE7932 devices
become fully functional, the IRQ1 interrupt pin is set low, and
Bit 15 (RSTDONE) in the STATUS1 register (Address 0xE503)
is set to 1. This bit is cleared to 0 during power-up and is set
to 1 when the power-up is completed.
2.
3.
Monitor the IRQ1 pin until it goes low, indicating that the
RSTDONE interrupt is triggered.
When the ADE7978 starts functioning after power-up, the
I2C port is the active serial port. If SPI communication is
to be used, toggle the SS/HSA pin three times from high to
low to select the SPI interface. For more information about
changing the communication port to SPI, see the Serial
Interface Selection section.
Read the STATUS1 register (Address 0xE503) to verify that
Bit 15 (RSTDONE) is set to 1, and then write a 1 to the bit
to clear it. The IRQ1 pin returns high. Because RSTDONE
is an unmaskable interrupt, Bit 15 (RSTDONE) must be
reset to 0 for the IRQ1 pin to return high.
It is recommended that all other flags in the STATUS1 and
STATUS0 registers also be reset by writing a 1 to all bits in
the registers.
3.3V – 10%
2.5V TO 2.6V
ADE7978 AND
ADE7933/ADE7932s
READY.
0V
32ms
ADE7978 AND
ADE7933/ADE7932s
POWERED UP.
ADE7978 POR
TIMER TURNED ON.
20µs
50ms
ADE7978 STARTS
FUNCTIONING. ADE7978
CLOCKS ADE7933/ADE7932s.
RSTDONE
INTERRUPT
TRIGGERED.
ADE7978 RESETS ADE7933/ADE7932s.
ADE7933/ADE7932s START
FUNCTIONING.
Figure 99. Power-Up Procedure
Rev. 0 | Page 79 of 120
MICROPROCESSOR
MAKES THE CHOICE
BETWEEN I2C AND SPI.
11116-029
1.
After a power-up of the ADE7978, the I2C serial port is
active. For information about changing the serial port to SPI
and about locking in the selected serial port (I2C or SPI), see
the Serial Interface Selection section. Immediately after
power-up, the ADE7978 resets all registers to their default
values.
ADE7978/ADE7933/ADE7932
Data Sheet
4.
If I2C communication is used, lock the port by writing a 1 to
Bit 0 (I2C_LOCK) of the CONFIG2 register (Address 0xEA00).
If SPI communication is used, lock the port by writing any
value to the CONFIG2 register. After the serial port is locked
to I2C or SPI, the communication protocol can be changed
only after a power-down or hardware reset operation.
5. Initialize the AIGAIN, BIGAIN, CIGAIN, and NIGAIN registers (Address 0x4380, Address 0x4383, Address 0x4386,
and Address 0x4389, respectively).
6. Start the DSP by writing 0x0001 to the run register
(Address 0xE228). For more information, see the Digital
Signal Processor section.
7. Initialize the DSP RAM-based registers located at
Address 0x4380 to Address 0x43BF. Write the last register
in the queue three times.
8. Initialize the hardware-based configuration registers
located at Address 0xE507 to Address 0xEA04 with the
exception of the CFMODE register (see Step 11).
9. Enable the DSP RAM write protection by writing 0xAD to the
internal 8-bit register located at Address 0xE7FE. Then write
0x80 to the internal 8-bit register located at Address 0xE7E3.
For more information, see the Digital Signal Processor section.
10. Read the energy registers xWATTHR, xVARHR,
xFWATTHR, xFVARHR, and xVAHR to erase their contents
and start energy accumulation from a known state.
11. Clear Bit 9 (CF1DIS), Bit 10 (CF2DIS), and Bit 11 (CF3DIS)
in the CFMODE register (Address 0xE610) to enable pulses
at the CF1, CF2, and CF3 pins.
12. Read back all ADE7978 registers to ensure that they are
initialized with the desired values.
•
•
During a hardware reset, the ADE7978 generates signals to reset
the ADE7933/ADE7932 devices. When the ADE7978 RESET pin
is toggled high again after at least 10 µs, the ADE7978 RESET_EN
pin goes low, and the VT_A, VT_B, VT_C, and VT_N pins
toggle eight times from high to low at a frequency of 4.096 MHz
(CLKIN/4). These actions reset the ADE7933/ADE7932 devices.
When the RESET_EN pin is taken high, the ADE7978 starts
generating 4.096 MHz (CLKIN/4) at the CLKOUT pin. This
signal clocks the ADE7933/ADE7932 devices and they become
operational.
The ADE7978 signals the end of a reset by pulling the IRQ1
interrupt pin low and by setting Bit 15 (RSTDONE) in the
STATUS1 register (Address 0xE503) to 1. This bit is set to 0
during the reset and is set to 1 when the reset ends. Write a 1 to
the RSTDONE status bit to clear the bit. The IRQ1 pin returns
high, and the ADE7978 and ADE7933/ADE7932 devices are
operational.
Because the I2C port is the default serial port of the ADE7978, it
becomes active after a reset. If SPI is the port used by the external
microprocessor, the procedure to enable SPI must be repeated
immediately after the RESET pin is toggled back to high (for
more information, see the Serial Interface Selection section).
After a hardware reset, all registers in the ADE7978 are reset
to their default values, and the DSP is in idle mode. Reinitialize
all ADE7978 registers, enable the DSP RAM write protection,
and start the DSP, as described in the Initializing the Chipset
section (Step 5 to Step 12). For more information about data
memory RAM protection and the run register, see the Digital
Signal Processor section.
HARDWARE RESET
When the RESET pin of the ADE7978 is set low, the ADE7978
enters the hardware reset state (see Figure 100). In the hardware
reset state, the following events take place:
The CLKOUT pin of the ADE7978 stops generating the
clock and is set high. The SYNC, RESET_EN, VT_A,
VT_B, VT_C, and VT_N pins are set high.
AT LEAST 10µs
50ms
ADE7978 RESET PIN
10ms
•ADE7978 ENTERS RESET
•ADE7978 CLKOUT, SYNC, RESET_EN, VT_A,
VT_B, VT_C, VT_N PINS SET HIGH
•ADE7933/ADE7932s DC-TO-DC CONVERTERS,
Σ-Δ MODULATORS STOP WORKING
•RSTDONE INTERRUPT TRIGGERED
•ADE7978, ADE7933/ADE7932s READY
ADE7933/ADE7932s START
WORKING
•ADE7978 RESET_EN PIN SET LOW
•ADE7978 VT_A, VT_B, VT_C, VT_N PINS
TOGGLE HIGH TO LOW 8 TIMES AT 4.096MHz
•ADE7933/ADE7932s ARE RESET
•ADE7978 RESET_EN PIN SET HIGH
•ADE7978 GENERATES 4.096MHz CLOCK AT CLKOUT PIN
Figure 100. ADE7978/ADE7933/ADE7932 Chipset During Hardware Reset
Rev. 0 | Page 80 of 120
11116-030
•
The dc-to-dc converter of the ADE7933/ADE7932 stops
working because the clock signal at the ADE7933/
ADE7932 XTAL1 pin is high.
The Σ-Δ modulators on the isolated side of the ADE7933/
ADE7932 are not powered and stop working.
Data Sheet
ADE7978/ADE7933/ADE7932
ADE7978/ADE7933/ADE7932 CHIPSET
SOFTWARE RESET
ADE7933/ADE7932 SOFTWARE RESET
Bit 7 (SWRST) in the CONFIG register (Address 0xE618)
manages the software reset functionality of the ADE7978 and
ADE7933/ADE7932 devices. The default value of this bit is 0. If
this bit is set to 1, the ADE7978 and ADE7933/ADE7932 devices
enter the software reset state. In this state, all internal registers are
reset to their default values. However, the serial port selection,
I2C or SPI, remains unchanged if the lock-in procedure was
executed before the reset (see the Serial Interface Selection
section for more information).
The ADE7978 signals the end of the reset by pulling the IRQ1
interrupt pin low and setting Bit 15 (RSTDONE) in the STATUS1
register (Address 0xE503) to 1. This bit is set to 0 during the reset
and is set to 1 when the reset ends. Write a 1 to the RSTDONE
status bit to clear the bit; the IRQ1 pin returns high.
After a software reset, all registers in the ADE7978 are reset to
their default values, the DSP is in idle mode, and Bit 7 (SWRST)
is cleared to 0. Reinitialize all ADE7978 registers, enable the
DSP RAM write protection, and start the DSP, as described in
the Initializing the Chipset section (Step 5 to Step 12). For more
information about data memory RAM protection and the run
register, see the Digital Signal Processor section.
During a software reset of the ADE7978, the ADE7978 resets
the ADE7933/ADE7932 devices while continuing to generate
the clock at the CLKOUT pin. The ADE7978 RESET_EN pin
goes low, and the VT_A, VT_B, VT_C, and VT_N pins toggle
eight times from high to low at a frequency of 4.096 MHz
(CLKIN/4). The RESET_EN, VT_A, VT_B, VT_C, and VT_N
pins are then taken high, and the reset ends.
To reset only the ADE7933/ADE7932 devices without resetting
the ADE7978, use Bit 7 (ADE7933_SWRST) in the CONFIG3
register (Address 0xE708). This bit resets the ADE7933/
ADE7932 devices by setting the RESET_EN pin low and
toggling the VT_A, VT_B, VT_C, and VT_N pins from high to
low eight times at 4.096 MHz (CLKIN/4). When the reset ends,
the ADE7933_SWRST bit is cleared to 0.
The recommended procedure to perform a software reset of the
ADE7933/ADE7932 devices only is as follows:
1.
2.
Write to the CONFIG3 register with Bit 7 (ADE7933_
SWRST) set to 1.
Read back the CONFIG3 register until Bit 7 reads as 0,
indicating that the reset has ended.
LOW POWER MODE
Under certain conditions, it may be desirable to lower the
current consumption of the chipset; in this case, the ADE7978
and ADE7933/ADE7932 can be set to a low power mode.
To enter low power mode, set Bit 6 (CLKOUT_DIS) and Bit 7
(ADE7933_SWRST) in the CONFIG3 register (Address 0xE708)
to 1. The ADE7978 stops generating the clock to the ADE7933/
ADE7932 devices and places them in the reset state.
To exit the low power mode, clear Bit 6 (CLKOUT_DIS) and
Bit 7 (ADE7933_SWRST) in the CONFIG3 register to 0. During
low power mode, the ADE7978 registers maintain their configurations, so they do not need to be reinitialized.
Rev. 0 | Page 81 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
APPLICATIONS INFORMATION
The ADE7978 is not the only chip capable of managing
multiple ADE7933/ADE7932 devices. Any microcontroller
that conforms to the ADE7933/ADE7932 serial interface can
manage the devices correctly. (For more information, see the Bit
Stream Communication Between the ADE7978 and the
ADE7933/ADE7932 section). However, similar devices, such as
the ADE7913/ADE7912 3-channel, isolated, Σ-Δ ADCs with an
SPI interface, may be more suitable for direct interfacing with a
microcontroller. For more information about the ADE7913/
ADE7912 ADCs, see the product pages for these devices.
Figure 101 shows Phase A of a 3-phase energy meter. The Phase A
current, IA, is sensed with a shunt. A pole of the shunt is connected
to the IM pin of the ADE7933/ADE7932 and becomes the ground
of the isolated side of the ADE7933/ADE7932, GNDISO. The
Phase A to neutral voltage, VAN, is sensed with a resistor divider,
and the VM pin is also connected to the IM and GNDISO pins.
Note that the voltages measured by the ADCs of the ADE7933/
ADE7932 are opposite to VAN and IA, a classic approach in singlephase metering. The other ADE7933/ADE7932 devices, which
monitor Phase B and Phase C, are connected in a similar way.
NEUTRAL PHASE A
PHASE A
VAN
ADE7932/
ADE7933
Figure 102 shows how to connect the ADE7933/ADE7932
inputs when the neutral line of a 3-phase system is monitored.
The neutral current is sensed using a shunt, and the voltage
across the shunt is measured at the fully differential inputs IP
and IM. The neutral to earth voltage is sensed with a voltage
divider at the single-ended inputs V1P and VM.
NEUTRAL LINE
VN
V1P
VM
IM
GNDISO
IP
IN
EARTH
Figure 102. Neutral Line and Neutral to Earth Voltage Monitoring
with the ADE7933/ADE7932
ADE7978 AND ADE7933/ADE7932 IN POLYPHASE
ENERGY METERS
A polyphase energy meter must manage three phases and an
optional neutral line. Figure 103 shows an example of a 3-phase
meter built for a 4-wire wye configuration. Three ADE7933/
ADE7932 devices read the phase currents and voltages. The
fourth ADE7933/ADE7932 manages the neutral line measurements. If the neutral line measurements are not required, only
three ADE7933/ADE7932 devices are used (see Figure 104); in
this configuration, the DATA_N pin of the ADE7978 is
connected to VDD.
V1P
IP
11116-017
VM
GNDISO
IM
IA
ADE7932/
ADE7933
NEUTRAL
11116-018
The ADE7978 and ADE7933/ADE7932 chipset was designed
for use in 3-phase energy metering systems in which one master
device, usually a microcontroller, manages the ADE7978
through an I2C or SPI interface. The ADE7978 then manages
two, three, or four ADE7933/ADE7932 devices.
Figure 101. Phase A ADE7933/ADE7932 Current and Voltage Sensing
Rev. 0 | Page 82 of 120
PHASE C
PHASE A
PHASE B
ADE7978/ADE7933/ADE7932
NEUTRAL
Data Sheet
ISOLATION
BARRIER
V1P
VM
DATA
V2/TEMP
3.3V
DATA_A
VT_A
3.3V
IM PHASE A
ADE7932/
ADE7933
V2P
GNDISO_A
SYNC
RESET_EN
XTAL1
ADE7978
GNDMCU
V1P
VM
DATA
V2/TEMP
3.3V
IM PHASE B
IP
3.3V
DATA_B
VT_B
ADE7932/
ADE7933
V2P
GNDISO_B
SYNC
RESET_EN
XTAL1
I2C/HSDC OR SPI
IRQ0, IRQ1
GNDMCU
V1P
VM
DATA
V2/TEMP
3.3V
DATA_C
VT_C
SYSTEM
MICROCONTROLLER
IP
IM PHASE C
IP
ADE7932/
ADE7933
V2P
GNDISO_C
SYNC
RESET_EN
XTAL1
SYNC
RESET_EN
CLKOUT
GNDMCU
V1P
VM
DATA
V2/TEMP
3.3V
DATA_N
VT_N
IM
NEUTRAL LINE
ADE7932/
ADE7933
V2P
LOAD
EARTH
GNDMCU
SYNC
RESET_EN
XTAL1
11116-019
IP
GNDMCU
GNDISO_N
PHASE C
PHASE B
PHASE A
NEUTRAL
Figure 103. 3-Phase, 4-Wire Wye Meter with One ADE7978 and Four ADE7933 Devices
ISOLATION
BARRIER
V1P
VM
DATA
V2/TEMP
3.3V
DATA_A
VT_A
3.3V
IM PHASE A
ADE7932/
ADE7933
V2P
SYNC
RESET_EN
XTAL1
ADE7978
GNDMCU
GNDISO_A
V1P
VM
DATA
V2/TEMP
3.3V
IP
3.3V
DATA_B
VT_B
IM PHASE B
ADE7932/
ADE7933
V2P
SYNC
RESET_EN
XTAL1
I2C/HSDC OR SPI
IRQ0, IRQ1
GNDMCU
GNDISO_B
V1P
VM
DATA
V2/TEMP
3.3V
DATA_C
VT_C
SYSTEM
MICROCONTROLLER
IP
IM PHASE C
LOAD
ADE7932/
ADE7933
V2P
GNDISO_C
SYNC
RESET_EN
XTAL1
GNDMCU
SYNC
RESET_EN
CLKOUT
3.3V
DATA_N
GNDMCU
Figure 104. 3-Phase, 4-Wire Wye Meter with One ADE7978 and Three ADE7933/ADE7932 Devices
Rev. 0 | Page 83 of 120
11116-020
IP
ADE7978/ADE7933/ADE7932
Data Sheet
If the meter is built for a 4-wire delta configuration, three
ADE7933/ADE7932 devices are required (see Figure 106). The
voltage dividers measure the Phase A and Phase C to neutral
voltages. The shunts measure the Phase A, Phase B, and
Phase C currents. In this configuration, the DATA_N pin of the
ADE7978 is connected to VDD.
PHASE C
ISOLATION
BARRIER
3.3V
V1P
DATA_A
VT_A
DATA
V2/TEMP
VM
IM PHASE A
IP
3.3V
ADE7932/
ADE7933
SYNC
RESET_EN
XTAL1
V2P
GNDISO_A
ADE7978
GNDMCU
3.3V
V1P
3.3V
DATA_C
VT_C
DATA
V2/TEMP
VM
IM PHASE C
IP
ADE7932/
ADE7933
SYNC
RESET_EN
CLKOUT
SYNC
RESET_EN
XTAL1
V2P
GNDISO_C
I2C/HSDC OR SPI
3.3V
GNDMCU
IRQ0, IRQ1
11116-021
DATA_B
DATA_N
SYSTEM
MICROCONTROLLER
PHASE A
PHASE B
A meter built for a 3-wire delta configuration requires only two
ADE7933/ADE7932 devices (see Figure 105): one for Phase A
and one for Phase C. The voltage dividers measure the Phase A
to Phase B and the Phase C to Phase B voltages. The shunts measure the Phase A and Phase C currents. In this configuration,
the DATA_N and DATA_B pins of the ADE7978 are connected
to VDD.
GNDMCU
PHASE C
PHASE B
PHASE A
NEUTRAL
Figure 105. 3-Phase, 3-Wire Delta Meter with One ADE7978 and Two ADE7933/ADE7932 Devices
ISOLATION
BARRIER
V1P
VM
3.3V
DATA_A
VT_A
DATA
V2/TEMP
3.3V
IM PHASE A
ADE7932/
ADE7933
V2P
GNDISO_A
SYNC
RESET_EN
XTAL1
ADE7978
GNDMCU
V1P
VM
3.3V
3.3V
DATA_B
VT_B
DATA
V2/TEMP
IM PHASE B
IP
ADE7932/
ADE7933
V2P
GNDISO_B
SYNC
RESET_EN
XTAL1
I2C/HSDC OR SPI
IRQ0, IRQ1
GNDMCU
V1P
VM
3.3V
DATA_C
VT_C
DATA
V2/TEMP
SYSTEM
MICROCONTROLLER
IP
IM PHASE C
IP
LOAD
ADE7932/
ADE7933
V2P
GNDISO_C
SYNC
RESET_EN
CLKOUT
SYNC
RESET_EN
XTAL1
GNDMCU
3.3V
GNDMCU
Figure 106. 3-Phase, 4-Wire Delta Meter with One ADE7978 and Three ADE7933/ADE7932 Devices
Rev. 0 | Page 84 of 120
11116-022
DATA_N
Data Sheet
ADE7978/ADE7933/ADE7932
If only two or three ADE7933/ADE7932 devices are used, the
DATA_B and/or DATA_N pins are connected to VDD. The
waveform samples computed by the ADE7978 that correspond
to these unconnected ADE7933/ADE7932 devices are set to full
scale. After passing through the high-pass filter, the waveform
samples are set to 0, and all quantities computed by the
ADE7978 using these samples are 0.
Bits[5:4] (CONSEL[1:0]) in the ACCMODE register (Address
0xE701) determine the way that the phase powers are computed
in the ADE7978, based on the meter configuration. For more
information, see the Energy Accumulation Modes section.
The ADE7933/ADE7932 receive a 4.096 MHz clock at the XTAL1
pin from the ADE7978 CLKOUT pin; the XTAL2 pin of the
ADE7933/ADE7932 is left open. Do not clock the ADE7933/
ADE7932 using a crystal connected between the XTAL1 and
XTAL2 pins because the ADE7933/ADE7932 devices must
function synchronously with the ADE7978; using the CLKOUT
clock of the ADE7978 ensures this synchronization.
The ADE7978 RESET_EN pin is connected to the RESET_EN
pins of all ADE7933/ADE7932 devices in the system. The
ADE7978 VT_A, VT_B, VT_C, and VT_N pins are connected
to the corresponding V2/TEMP pin of each ADE7933/ADE7932
in the system. For example, the VT_A pin of the ADE7978 is
connected to the V2/TEMP pin of the ADE7933/ADE7932 that
monitors Phase A. If the schematic does not monitor certain
phases, leave the corresponding VT_x pin of the ADE7978
unconnected. For example, the meter in the configuration
shown in Figure 105 does not monitor Phase B or the neutral
current. Therefore, the VT_B and VT_N pins are left open.
When the RESET pin of the ADE7978 is set low for at least
10 µs and then brought high again, the RESET_EN pin is set
low, and the VT_A, VT_B, VT_C, and VT_N pins toggle eight
times from high to low at a frequency of 4.096 MHz, resetting
the ADE7933/ADE7932 devices. When the RESET_EN, VT_A,
VT_B, VT_C, and VT_N pins are set high again, the reset of the
ADE7933/ADE7932 devices ends (see the Hardware Reset
section for more information).
The VT_A, VT_B, VT_C, and VT_N pins of the ADE7978 select
the signal measured by the V2 voltage ADC of the ADE7933:
either the second voltage input or the internal temperature sensor.
(The ADE7932 always measures the internal temperature sensor.)
If the VT_x signal is low, the ADC measures the input signal at
the V2P pin. If the VT_x signal is high, the ADC measures the
internal temperature sensor.
The ADE7978 reads the outputs of the ADE7933/ADE7932
using a bit stream communication composed of two signals,
SYNC and DATA. The SYNC pin of the ADE7978 is connected
to the SYNC pin of each ADE7933/ADE7932 device. The DATA
pin of each ADE7933/ADE7932 is connected to the corresponding
DATA_x pin of the ADE7978 (x = A, B, C, or N). For example,
the DATA pin of the Phase A ADE7933/ADE7932 is connected
to the DATA_A pin of the ADE7978.
If the schematic does not monitor certain phases, connect the
corresponding DATA_x pin of the ADE7978 to VDD. For
example, the meter in the configuration shown in Figure 105
does not monitor Phase B or the neutral current. Therefore, the
DATA_B and DATA_N pins of the ADE7978 are tied to VDD.
The SYNC pin of the ADE7978 generates a 1.024 MHz serial clock
to the ADE7933/ADE7932 slaves. Each ADE7933/ADE7932
responds with a bit stream generated by the first stage of the
ADE7933/ADE7932 ADCs (see the Bit Stream Communication
Between the ADE7978 and the ADE7933/ADE7932 section).
ADE7978 QUICK SETUP AS AN ENERGY METER
An energy meter is usually characterized by the nominal current
(In), nominal voltage (Vn), nominal frequency (fn), and the meter
constant (MC). To quickly set up the ADE7978, follow these steps:
1.
2.
If fn = 60 Hz, set Bit 14 (SELFREQ) to 1 in the COMPMODE
register (Address 0xE60E). If fn = 50 Hz, leave the SELFREQ
bit at 0, the default value.
Initialize the CF1DEN, CF2DEN, and CF3DEN registers
(Address 0xE611 to Address 0xE613) based on the following
equation:
CFxDEN =
10 3
MC [imp/kwh] × 10 n
For more information, see the Energy-to-Frequency
Conversion section.
3.
Initialize the WTHR, VARTHR, and VATHR registers
(Address 0xEA02 to Address 0xEA04) based on the
following equation:
WTHR, VARTHR, and VATHR =
PMAX × f s × 3600 × 10 n
VFS × I FS × 2 27
For more information, see the Active Energy Calculation
section, the Reactive Energy Calculation, and the Apparent
Energy Calculation section.
4.
Initialize the VLEVEL register (Address 0x43A2) based on
the following equation:
VLEVEL = VFS/Vn × 4 × 106
For more information, see the Fundamental Active Power
Calculation section.
5.
6.
7.
Rev. 0 | Page 85 of 120
Initialize the VNOM register based on the following equation:
VNOM = V/VFS × 3,761,808
For more information, see the Apparent Power Calculation
Using VNOM section.
Enable the data memory RAM protection by writing 0xAD
to the internal 8-bit register located at Address 0xE7FE, followed by a write of 0x80 to the internal 8-bit register located
at Address 0xE7E3.
Start the DSP by writing 0x0001 to the run register
(Address 0xE228).
ADE7978/ADE7933/ADE7932
Data Sheet
BIT STREAM COMMUNICATION BETWEEN THE
ADE7978 AND THE ADE7933/ADE7932
The ADE7978 extracts information from the ADE7933/
ADE7932 devices of the system using the bit stream communication shown in Figure 107. The ADE7978 generates a 1.024 MHz
clock signal at the SYNC pin. This clock signal is equal to 1/16
of the ADE7978 internal clock, CLKIN (CLKIN/16 = 1.024 MHz
for XTALIN = 16.384 MHz) and one-fourth of the ADE7933/
ADE7932 XTAL1 clock (CLKIN/4). The duty cycle of this clock
is 25%.
The low to high transition of SYNC is generated one-fourth of
a cycle before a high to low transition of the CLKIN/4 clock.
SYNC stays high for one CLKIN/4 cycle and stays low for the
rest of the period.
After the first high to low transition of SYNC, the ADE7978
CLKIN/4 transitions from high to low four times. At each high
to low transition of CLKIN/4, the ADE7933/ADE7932 devices
place these bits on the DATA pin: the bits coming from the first
stage of the ADCs and the bits of the temperature offset stored
in the ADE7933/ADE7932 devices. The order of the bits on the
Phase A ADE7933/ADE7932 is VA bit, VA2 bit, temperature
offset bit, and IA bit. The other ADE7933/ADE7932 devices
follow the same pattern. The ADE7978 receives these bits at its
DATA_A, DATA_B, DATA_C, and DATA_N pins. The process is
repeated when a new high to low transition takes place on SYNC.
The delimiters identifying the 8-bit signed number representing
the temperature offset are shown in Figure 108.
Any master device that can generate a 1.024 MHz SYNC signal
like the one shown in Figure 107 and can filter the bit streams
coming from the DATA pins of the ADE7933/ADE7932 devices
can replace the ADE7978.
ADE7978
CLKIN/4
DATA_A
IA BIT
VA BIT
VA2 BIT
TEMP OFFSET
IA BIT
DATA_B
IB BIT
VB BIT
VB2 BIT
TEMP OFFSET
IB BIT
DATA_C
IC BIT
VC BIT
VC2 BIT
TEMP OFFSET
IC BIT
DATA_N
IN BIT
VN1 BIT
VN2 BIT
TEMP OFFSET
IN BIT
11116-023
SYNC
Figure 107. Bit Stream Communication Between the ADE7978 and the ADE7933/ADE7932 Devices
0
0
0
0
0
1
BIT 7 BIT 6 BIT 5 BIT 4
4 LEAST SIGNIFICANT
BITS OF TEMPERATURE
OFFSET
1
BIT 3 BIT 2 BIT 1 BIT 0
Figure 108. Temperature Offset Bit Stream Communication
Rev. 0 | Page 86 of 120
1
11116-220
4 MOST SIGNIFICANT
BITS OF TEMPERATURE
OFFSET
Data Sheet
ADE7978/ADE7933/ADE7932
ADE7978 AND ADE7933/ADE7932 CLOCKS
Provide a digital clock signal at the XTALIN pin to clock the
ADE7978. The ADE7978 is clocked at the frequency provided
at this pin; this frequency is referred to as CLKIN throughout
this data sheet. The ADE7978 is specified for a CLKIN value of
16.384 MHz, but frequencies of 16.384 MHz ± 1% are acceptable.
Alternatively, a 16.384 MHz crystal with a typical drive level of
0.5 mW and equivalent series resistance (ESR) of 20 Ω can be
connected across the XTALIN and XTALOUT pins to provide
a clock source for the ADE7978 (see Figure 109).
CP1
ADE7978
C1
C2
XTALOUT
CP2
11116-024
TC
Figure 109. ADE7978 Crystal Circuitry
The total capacitance (TC) at the XTALIN and XTALOUT pins
is as follows:
TC = C1 + CP1 = C2 + CP2
where:
C1 and C2 are the ceramic capacitors between the XTALIN and
GND pins and between the XTALOUT and GND pins (C1 = C2).
CP1 and CP2 are the parasitic capacitors of the wires connecting the crystal to the ADE7978 (CP1 = CP2).
The load capacitance (LC) of the crystal is equal to half the total
capacitance TC because it is the capacitance of the series circuit
composed by C1 + CP1 and C2 + CP2.
LC =
C1 + CP1
2
=
C2 + CP2
2
=
TC
2
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage
waveform applied across the insulation. In addition to the testing
performed by the regulatory agencies, Analog Devices carries
out an extensive set of evaluations to determine the lifetime of
the insulation structure within the ADE7933/ADE7932 devices.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage.
The values shown in Table 12 summarize the peak voltage for
50 years of service life for a bipolar ac operating condition and
the maximum CSA/VDE approved working voltages. In many
cases, the approved working voltage is higher than the 50-year
service life voltage. Operation at these high working voltages
can lead to shortened insulation life in some cases.
The insulation lifetime of the ADE7933/ADE7932 devices
depends on the voltage waveform type imposed across the
isolation barrier. The iCoupler insulation structure degrades
at different rates depending on whether the waveform is bipolar
ac, unipolar ac, or dc. Figure 110, Figure 111, and Figure 112
illustrate these different isolation voltage waveforms.
RATED PEAK VOLTAGE
Therefore, the value of Capacitors C1 and C2 as a function
of the load capacitance of the crystal is
0V
11116-102
TC
XTALIN
The ADE7933/ADE7932 clock circuit does not need a crystal
when it is used in conjunction with the ADE7978 because the
ADE7978 generates the 4.096 MHz clock used by the ADE7933/
ADE7932. However, if the ADE7933/ADE7932 are used as standalone chips, a 4.096 MHz crystal with a typical drive level of
0.5 mW and ESR of 20 Ω can be connected across the ADE7933/
ADE7932 XTAL1 and XTAL2 pins to provide a clock source.
The values of the ceramic capacitors (C1 and C2) are calculated
in the same way as for the clock circuitry of the ADE7978.
C1 = C2 = 2 × LC − CP1 = 2 × LC − CP2
Figure 110. Bipolar AC Waveform
For the ADE7978, the typical total capacitance TC of the
XTALIN and XTALOUT pins is 40 pF (see Table 2).
RATED PEAK VOLTAGE
Select a crystal with a load capacitance of
For example, if the parasitic capacitances of CP1 and CP2 are
equal to 20 pF, select Capacitors C1 and C2 equal to 20 pF.
11116-103
LC = TC/2 = 20 pF
0V
Figure 111. Unipolar AC Waveform
11116-104
RATED PEAK VOLTAGE
0V
Figure 112. DC Waveform
Rev. 0 | Page 87 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the bipolar ac condition
determines the maximum working voltage recommended by
Analog Devices. In the case of unipolar ac or dc voltage, the stress
on the insulation is significantly lower. This allows operation at
higher working voltages while still achieving a 50-year service life.
The working voltages listed in Table 12 can be applied while
maintaining the 50-year minimum lifetime, provided that the
voltage conforms to either the unipolar ac or dc voltage cases.
Treat any cross-insulation voltage waveform that does not conform to Figure 111 or Figure 112 as a bipolar ac waveform, and
limit its peak voltage to the 50-year lifetime voltage value listed
in Table 12.
The voltage presented in Figure 111 is shown as sinusoidal for
illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
LAYOUT GUIDELINES
Figure 34 shows the test circuit of the ADE7978/ADE7933/
ADE7932 chipset. The test circuit contains four ADE7933
devices and one ADE7978, together with the circuitry required
to sense the phase currents and voltages in a 3-phase system.
The chipset is managed by a microcontroller using the SPI
interface. (The microcontroller is not shown in the schematic.)
Figure 34 replicates the schematic of the ADE7978/ADE7933
evaluation board (see the ADE7978 and ADE7933/ADE7932
Evaluation Board section).
Figure 113 and Figure 114 show a recommended layout for a
printed circuit board (PCB) with two layers; in this layout, the
components are placed only on the top side of the board.
Following these layout guidelines helps to create a low noise
design with higher immunity to EMC influences. Note that
Figure 113 and Figure 114 show layout images that were
cropped from images of a board containing other circuitry
besides the ADE7978 and ADE7933 devices.
The layout of a meter using the ADE7932 is very similar to
the one designed for the ADE7933. The only difference is the
absence of the voltage channel V2P and its related circuitry: the
resistor divider and the protection diodes.
The primary supply voltage is supplied at VDD (Pin 19) of the
ADE7933. Two decoupling capacitors are placed between VDD
and GND (Pin 20): a 10 µF capacitor and a 100 nF ceramic
capacitor. The ceramic capacitor must be placed closest to the
ADE7933/ADE7932 because it decouples the high frequency
noise; the 10 µF capacitor must be placed in close proximity to
the ADE7933/ADE7932.
The ADE7933 VDDISO pin (Pin 1) is decoupled from GNDISO
(Pin 2) using two capacitors: a 10 µF capacitor and a 100 nF
ceramic capacitor. Place the ceramic capacitor closest to the
ADE7933/ADE7932; place the 10 µF capacitor in close proximity to the ADE7933/ADE7932.
The ADE7933 LDO and REF pins (Pin 8 and Pin 9) are each
decoupled from GNDISO (Pin 10) using two capacitors: a 4.7 µF
capacitor and a 100 nF ceramic capacitor. Place the ceramic
capacitor closest to the ADE7933/ADE7932; place the 4.7 µF
capacitor in close proximity to the ADE7933/ADE7932.
Note that the ADE7933/ADE7932 isolated ground point is one
of the shunt poles. This point is directly connected to Pin 10
(GNDISO). It is not necessary to connect the shunt ground pole
to Pin 2; the two GNDISO pins (Pin 2 and Pin 10) are internally
connected to each other.
Note that the top layer components placed on the isolated
secondary side of the ADE7933 are surrounded by a ground plane
connected to GNDISO. The bottom layer extends the ground of
the primary side below the ADE7933 and the related circuitry,
creating a stitching capacitor. This capacitance has an important
role in reducing the emissions generated by the dc-to-dc converter
of the ADE7933/ADE7932. Note that a distance of at least 8 mm
is maintained on both sides between the input pins on the board
and the ground planes.
Rev. 0 | Page 88 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
11116-215
8mm
11116-216
Figure 113. ADE7978 and ADE7933 Circuit Board, Top Layer
Figure 114. ADE7978 and ADE7933 Circuit Board, Bottom Layer
Rev. 0 | Page 89 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
If 4-layer PCBs are used, additional stitching capacitors can
be created. The top and bottom layers remain unchanged (see
Figure 113 and Figure 114). Layer 2 of the 4-layer PCB replicates
the bottom layer, extending the ground of the primary side below
the ADE7933 and the related circuitry. Layer 3 replicates the
ground plane of the top layer.
Figure 115 shows the structure of the stitching capacitors
created by a 4-layer PCB. The isolated ground plane of the top
layer creates the 10 pF capacitor (C12) with the primary side
ground plane placed on Layer 2. In a similar manner, the 400 pF
capacitor (C23) is created between Layer 2 and Layer 3.
These capacitances play an important role in reducing the
emissions generated by the ADE7933/ADE7932 dc-to-dc
converter.
28MILS = 0.7112mm
ADE7978 DIE VERSION
The version register identifies the version of the ADE7978 die.
This 8-bit, read-only register is located at Address 0xE707.
PRIMARY SIDE GROUND
PLANE ON TOP LAYER
C12
C23
4MILS = 0.1016mm
PRIMARY SIDE GROUND
PLANE ON LAYER 2
1mm
8mm
Figure 115. Stitching Capacitors Created by 4-Layer PCB
Rev. 0 | Page 90 of 120
PRIMARY SIDE GROUND
PLANE ON BOTTOM LAYER
11116-217
28MILS = 0.7112mm
An evaluation board built upon the ADE7978 and ADE7933
chipset configuration is available (see the Ordering Guide). This
board is used in conjunction with the system demonstration
platform (EVAL-SDP-CB1Z). Order both the ADE7978/
ADE7933 evaluation board and the system demonstration
platform to evaluate the ADE7978 and ADE7933. For more
information, see the ADE7978 product page.
ADE7932/ADE7933
ISOLATED SIDE GROUND
PLANE ON TOP LAYER
ISOLATED SIDE GROUND
PLANE ON LAYER 3
ADE7978 AND ADE7933/ADE7932 EVALUATION
BOARD
Data Sheet
ADE7978/ADE7933/ADE7932
SERIAL INTERFACES
The ADE7978 has three serial port interfaces: one fully licensed
I2C interface, one serial peripheral interface (SPI), and one high
speed data capture (HSDC) port. The SPI pins are multiplexed
with pins for the I2C and HSDC ports; therefore, the ADE7978
accepts two configurations: one using the SPI port only and one
using the I2C port in conjunction with the HSDC port.
SERIAL INTERFACE SELECTION
After a reset of the ADE7978, the HSDC port is always disabled.
After power-up or after a hardware reset, select the I2C or SPI
port by manipulating the SS/HSA pin (Pin 16).
•
•
If the SS/HSA pin is pulled high, the ADE7978 uses the I2C
port until another hardware reset is executed.
If the SS/HSA pin is toggled high to low three times, the
ADE7978 uses the SPI port until another hardware reset is
executed.
The manipulation of the SS/HSA pin can be accomplished in
two ways.
•
•
Use the SS pin of the master device (that is, the microcontroller) as a regular I/O pin and toggle it three times.
Execute three SPI write operations to a location in the
address space that is not allocated to a specific ADE7978
register (for example, Address 0xEBFF, where writes to 8-bit
registers can be executed). These writes cause the SS/HSA
pin to toggle three times. For more information about the
write protocol involved, see the SPI Write Operation section.
After the serial port selection is completed, the selection must
be locked. In this way, the active port remains enabled until a
hardware reset or a power-down operation is performed. If the
active serial port is I2C, Bit 0 (I2C_LOCK) of the CONFIG2
register (Address 0xEA00) must be set to 1 to lock it in. After
the write to this bit is done, the ADE7978 ignores spurious
toggling of the SS/HSA pin, and a switch to the SPI port is no
longer possible. If the active serial port is SPI, any write to the
CONFIG2 register locks the port. After this write, a switch to
the I2C port is no longer possible.
The functionality of the ADE7978 is configurable via several
on-chip registers. The contents of these registers can be updated
or read using the I2C or SPI interface. The HSDC port provides
the state of up to 16 registers that contain the instantaneous
values of phase voltages and neutral currents, as well as active,
reactive, and apparent powers.
COMMUNICATION VERIFICATION
The ADE7978 includes a set of three registers that allow any
communication via I2C or SPI to be verified. The LAST_OP
(Address 0xEA01), LAST_ADD (Address 0xE9FE), and LAST_
RWDATA registers record the nature, address, and data of the
last successful communication, respectively. The LAST_RWDATA
register has three separate addresses depending on the length of
the successful communication (see Table 35).
Table 35. LAST_RWDATA Register Locations
Communication Type
8-Bit Read/Write
16-Bit Read/Write
32-Bit Read/Write
Address
0xE7FD
0xE9FF
0xE5FF
After each successful communication with the ADE7978, the
address of the register that was last accessed is stored in the
16-bit LAST_ADD register (Address 0xE9FE). This read-only
register stores the value until the next successful read or write
operation is completed.
The LAST_OP register (Address 0xEA01) stores the nature of
the operation; that is, it indicates whether a read or a write was
performed. If the last operation was a write, the LAST_OP
register stores the value 0xCA. If the last operation was a read,
the LAST_OP register stores the value 0x35. The LAST_RWDATA
register stores the data that was written to or read from the register.
An unsuccessful read or write operation is not stored in these
registers.
When the LAST_OP, LAST_ADD, and LAST_RWDATA
registers are read, their values remain unchanged.
I2C-COMPATIBLE INTERFACE
The ADE7978 supports a fully licensed I2C interface. The I2C
interface is implemented as a full hardware slave. The maximum
serial clock frequency supported by the I2C interface is 400 kHz.
SDA is the data I/O pin, and SCL is the serial clock. These two
pins are shared with the MOSI and SCLK pins of the on-chip SPI
interface. The SDA and SCL pins are configured in a wire-AND
format that allows arbitration in a multimaster system.
The transfer sequence of an I2C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the address of the slave
device and the direction of the data transfer in the initial
address transfer. If the slave acknowledges the master, the data
transfer is initiated. Data transfer continues until the master
issues a stop condition, and the bus becomes idle.
Rev. 0 | Page 91 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
I2C Write Operation
As shown in Figure 117, the first stage begins when the master
generates a start condition, which consists of one byte representing
the slave address of the ADE7978 followed by the 16-bit address
of the target register. The ADE7978 acknowledges each byte
received. The address byte is similar to the address byte for a
write operation and is equal to 0x70 (see the I2C Write Operation
section).
2
A write operation using the I C interface of the ADE7978 is
initiated when the master generates a start condition, which
consists of one byte representing the slave address of the
ADE7978 followed by the 16-bit address of the target register
and by the value of the register (see Figure 116). The addresses
and the register contents are sent with the most significant bit
first.
I2C Read Operation
START
A read operation using the I2C interface of the ADE7978 is
accomplished in two stages. The first stage sets the pointer to
the address of the register. The second stage reads the contents
of the register.
15
8
7
0
31
24
23
16
15
8
7
STOP
After the last byte of the register address is sent and acknowledged
by the ADE7978, the second stage begins with the master generating a new start condition followed by the address byte. The most
significant seven bits of this address byte contain the address of
the ADE7978, which is equal to 0111000. Bit 0 of the address byte
is the read/write bit. For a read operation, Bit 0 must be set to 1;
therefore, the first byte of the read operation is 0x71. After this
byte is received, the ADE7978 generates an acknowledge. The
ADE7978 then sends the value of the register, and, after each byte
is received, the master generates an acknowledge. All bytes are
sent with the most significant bit first. Registers can have 8, 16,
or 32 bits; after the last bit of the register is received, the master
does not acknowledge the transfer but generates a stop condition.
The most significant seven bits of the address byte contain the
address of the ADE7978, which is equal to 0111000. Bit 0 of the
address byte is the read/write bit. For a write operation, Bit 0 must
be cleared to 0; therefore, the first byte of the write operation is
0x70. The ADE7978 acknowledges each byte received. Registers
can have 8, 16, or 32 bits; after the last bit of the register is transmitted and the ADE7978 acknowledges the transfer, the master
generates a stop condition.
0
BYTE 1 OF REGISTER
BYTE 0 (LEAST
SIGNIFICANT) OF
REGISTER
11116-091
ACK
BYTE 2 OF REGISTER
ACK
BYTE 3 (MOST
SIGNIFICANT)
OF REGISTER
ACK
LEAST SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK
ACK
MOST SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK
S
SLAVE ADDRESS
ACK
S 0 1 1 1 0 0 0 0
ACK GENERATED
BY ADE7978
START
Figure 116. I2C Write Operation of a 32-Bit Register
8
15
7
0
MOST SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
LEAST SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK
ACK
SLAVE ADDRESS
ACK
S 0 1 1 1 0 0 0 0
1
0
0
0 1
SLAVE ADDRESS
BYTE 3
(MOST SIGNIFICANT)
OF REGISTER
BYTE 2 OF
REGISTER
7
8
0
BYTE 1 OF
REGISTER
STOP
15
16
S
BYTE 0
(LEAST SIGNIFICANT)
OF REGISTER
11116-092
1
23
ACK
1
24
ACK
0
ACK
S
31
ACK
START
ACK
GENERATED BY
MASTER
NO ACK
ACK GENERATED
BY ADE7978
ACK GENERATED
BY ADE7978
Figure 117. I2C Read Operation of a 32-Bit Register
Rev. 0 | Page 92 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
I2C Burst Read Operation
The registers from Address 0xE50C to Address 0xE526
represent quantities computed by the ADE7978 every 8 kHz.
These registers contain the following information:



After the address byte is received, the ADE7978 acknowledges
the byte and sends the value of the first register located at the
pointer. The register is sent with the most significant byte
first, and all bytes are sent with the most significant bit first.
After every eight bits are received, the master generates an
acknowledge.
After the bytes of the first register are sent, if the master
acknowledges the last byte, the ADE7978 increments the
pointer by one location to position it at the next register and
begins to send it out byte by byte, most significant byte first.
If the master acknowledges the last byte of the second
register, the ADE7978 increments the pointer again and
begins to send data from the next register.
The process continues until the master does not acknowledge the last byte of a register and then generates a stop
condition.
2.
3.
Waveform samples (IAWV, IBWV, ICWV, INWV, VAWV,
VBWV, VCWV, VA2WV, VB2WV, VC2WV, VNWV, and
VN2WV)
Instantaneous values of various powers (AWATT, BWATT,
CWATT, AVAR, BVAR, CVAR, AVA, BVA, and CVA)
Total harmonic distortion (AVTHD, AITHD, BVTHD,
BITHD, CVTHD, and CITHD)
4.
5.
These registers can be read in two ways: one register at a time
(see the I2C Read Operation section) or multiple consecutive
registers at a time in a burst mode.
6.
Burst mode is accomplished in two stages (see Figure 118).
The first stage sets the pointer to the address of the first register
in the burst and is identical to the first stage executed when only
one register is read. Any register from Address 0xE50C to
Address 0xE526 can be the first register in the burst.
Address 0xE526 is the last location of the memory range allocated
to the burst read operation. Do not perform a burst read operation
on register locations with addresses greater than 0xE526.
The high to low transition of the ZX/DREADY pin can be used
to initiate a burst read operation. The pin must be configured for
the DREADY functionality (set Bits[1:0], ZX_DREADY, to 00
in the CONFIG register, Address 0xE618). The ZX/DREADY
pin goes low approximately 70 ns after Bit 17 (DREADY) in the
STATUS0 register (Address 0xE502) is set to 1. The pin stays
low for 10 μs and then goes high again.
The second stage reads the contents of the registers. The second
stage proceeds as follows (see Figure 118):
START
The master generates a new start condition followed by an
address byte equal to the address byte used when a single
register is read, 0x71.
15
8
7
0
LEAST SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK
MOST SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK
SLAVE ADDRESS
ACK
S 0 1 1 1 0 0 0 0
BYTE 3
(MOST SIGNIFICANT)
OF REGISTER 0
BYTE 0
(LEAST SIGNIFICANT)
OF REGISTER 0
7
0
ACK
ACK
24
BYTE 3
(MOST SIGNIFICANT)
OF REGISTER 1
S
BYTE 0
(LEAST SIGNIFICANT)
OF REGISTER n
11116-093
SLAVE ADDRESS
31
0
ACK
S 0 1 1 1 0 0 0 1
7
24
ACK
31
STOP
ACK
GENERATED BY
MASTER
NO ACK
ACK GENERATED
BY ADE7978
START
1.
ACK GENERATED
BY ADE7978
Figure 118. I2C Burst Read of Consecutive Registers Located Between Address 0xE50C and Address 0xE526
Rev. 0 | Page 93 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
SPI-COMPATIBLE INTERFACE
The SPI interface of the ADE7978 is always a slave in the communication and consists of four pins (with dual functions): SCLK/SCL,
MOSI/SDA, MISO/HSD, and SS/HSA. The functions used in the
SPI-compatible interface are SCLK, MOSI, MISO, and SS.
The serial clock for a data transfer is applied at the SCLK logic
input. All data transfer operations are synchronized to the serial
clock. The maximum serial clock frequency supported by the
SPI interface is 2.5 MHz.
Data shifts into the ADE7978 at the MOSI logic input on the
falling edge of SCLK, and the ADE7978 samples it on the rising
edge of SCLK. Data shifts out of the ADE7978 at the MISO
logic output on the falling edge of SCLK and is sampled by the
master device on the rising edge of SCLK. The most significant
bit of the word is shifted in and out first. MISO stays in high
impedance when no data is transmitted from the ADE7978.
Figure 119 shows the connection between the ADE7978 SPI
interface and a master device that contains an SPI interface.
MOSI
MOSI
MISO
MISO
SCLK
SCK
SS
A write operation using the SPI interface of the ADE7978 is
initiated when the master sets the SS pin low and begins sending
one byte, representing the slave address of the ADE7978, on the
MOSI line (see Figure 120). The master sends data on the MOSI
line starting with the first high to low transition of SCLK. The
SPI interface of the ADE7978 samples the data on the low to high
transitions of SCLK.
Figure 119. Connecting the ADE7978 SPI Interface to an SPI Device
SS
SCLK
15 14
MOSI
0 0 0 0 0 0 0 0
1 0 31 30
REGISTER ADDRESS
REGISTER VALUE
Figure 120. SPI Write Operation of a 32-Bit Register
Rev. 0 | Page 94 of 120
1 0
11116-097
SS
SPI Write Operation
The most significant seven bits of the address byte can have any
value, but as a good programming practice, these bits should have
a value other than 0111000, which is the 7-bit address used in the
I2C protocol. Bit 0 of the address byte is the read/write bit. For a
write operation, Bit 0 must be cleared to 0. The master then sends
the 16-bit address of the register that is to be written followed
by the 32-, 16-, or 8-bit value of that register without losing an
SCLK cycle. After the last bit is transmitted, the master sets the
SS and SCLK lines high at the end of the SCLK cycle, and the
communication ends. The data lines, MOSI and MISO, enter a
high impedance state.
SPI DEVICE
11116-094
ADE7978
The SS logic input is the chip select input. This input is used when
multiple devices share the serial bus. Drive the SS input low for
the entire data transfer operation. Bringing SS high during a data
transfer operation aborts the transfer and places the serial bus in a
high impedance state. A new transfer can be initiated by returning
the SS logic input low. However, aborting a data transfer before
completion leaves the accessed register in a state that cannot be
guaranteed. Every time a register is written, its value should be
verified by reading it back. The protocol is similar to the protocol
used in the I2C interface.
Data Sheet
ADE7978/ADE7933/ADE7932
SPI Read Operation
Burst mode is initiated when the master sets the SS pin low and
begins sending one byte, representing the address of the ADE7978,
on the MOSI line (see Figure 122). The address is the same address
byte used for reading a single register. The master sends data on
the MOSI line starting with the first high to low transition of
SCLK. The SPI interface of the ADE7978 samples data on the
low to high transitions of SCLK.
A read operation using the SPI interface of the ADE7978 is
initiated when the master sets the SS pin low and begins sending
one byte, representing the address of the ADE7978, on the MOSI
line (see Figure 121). The master sends data on the MOSI line
starting with the first high to low transition of SCLK. The SPI
interface of the ADE7978 samples the data on the low to high
transitions of SCLK.
The most significant seven bits of the address byte can have any
value, but as a good programming practice, these bits should have
a value other than 0111000, which is the 7-bit address used in the
I2C protocol. Bit 0 of the address byte is the read/write bit. For a
read operation, Bit 0 must be set to 1. The master then sends the
16-bit address of the register that is to be read. After the ADE7978
receives the last bit of the register address on a low to high transition of SCLK, it begins to transmit the register contents on the
MISO line when the next SCLK high to low transition occurs;
the master samples the data on a low to high SCLK transition.
After the master receives the last bit, it sets the SS and SCLK
lines high, and the communication ends. The data lines, MOSI
and MISO, enter a high impedance state.
The master sends the 16-bit address of the first register in the burst
to be read. Any register from Address 0xE50C to Address 0xE526
can be the first register in the burst. After the ADE7978 receives
the last bit of the register address on a low to high transition of
SCLK, it begins to transmit the register contents on the MISO line
when the next SCLK high to low transition occurs; the master
samples the data on a low to high SCLK transition.
After the master receives the last bit of the first register, the
ADE7978 sends the contents of the register placed at the next
location. This process is repeated until the master sets the SS
and SCLK lines high and the communication ends. The data
lines, MOSI and MISO, enter a high impedance state.
Address 0xE526 is the last location of the memory range allocated
to the burst read operation. Do not perform a burst read operation
on register locations with addresses greater than 0xE526.
SPI Burst Read Operation
The registers from Address 0xE50C to Address 0xE526 represent
quantities computed by the ADE7978 every 8 kHz (see the I2C
Burst Read Operation section for the list of registers).
These registers can be read in two ways: one register at a time (see
the SPI Read Operation section) or multiple consecutive registers
at a time in a burst mode.
The high to low transition of the ZX/DREADY pin can be used
to initiate a burst read operation. The pin must be configured for
the DREADY functionality (set Bits[1:0], ZX_DREADY, to 00
in the CONFIG register, Address 0xE618). The ZX/DREADY
pin goes low approximately 70 ns after Bit 17 (DREADY) in the
STATUS0 register (Address 0xE502) is set to 1. The pin stays
low for 10 µs and then goes high again.
SS
SCLK
15 14
0 0 0 0 0 0 0 1
1 0
REGISTER ADDRESS
31 30
MISO
1 0
11116-095
MOSI
REGISTER VALUE
Figure 121. SPI Read Operation of a 32-Bit Register
SS
SCLK
0 0 0 0 0 0 0 1
REGISTER
ADDRESS
31
MISO
0
REGISTER 0
VALUE
31
0
REGISTER n
VALUE
11116-096
MOSI
Figure 122. SPI Burst Read of Consecutive Registers Located Between Address 0xE50C and Address 0xE526
Rev. 0 | Page 95 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
HSDC INTERFACE
The high speed data capture (HSDC) interface is disabled by
default. It can be used only when the ADE7978 is configured for
the I2C interface. The SPI interface of the ADE7978 cannot be
used at the same time as the HSDC interface.
When Bit 6 (HSDCEN) is set to 1 in the CONFIG register, the
HSDC interface is enabled. If the HSDCEN bit is cleared to 0
(the default value), the HSDC interface is disabled. Setting this
bit to 1 when the SPI interface is in use has no effect on the part.
The HSDC interface is used to send data to an external device
(usually a microprocessor or a DSP); this data can consist of up
to sixteen 32-bit words. The words represent the instantaneous
values of the phase currents and voltages, neutral current, and
active, reactive, and apparent powers. The registers transmitted
are IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, INWV, AVA,
BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and
CVAR. These 24-bit registers are sign extended to 32 bits
(see Figure 45).
HSDC can interface with SPI or similar interfaces; HSDC is
always the master of the communication. The HSDC interface
consists of three pins: HSA, HSD, and HSCLK. HSA represents
the select signal. It stays active low or high when a word is transmitted and is usually connected to the select pin of the slave. HSD
sends data to the slave and is usually connected to the data input
pin of the slave. HSCLK is the serial clock line that is generated
by the ADE7978; HSCLK is usually connected to the serial clock
input of the slave. Figure 123 shows the connections between
the ADE7978 HSDC interface and a slave device containing an
SPI interface.
HSD
HSCLK
HSA
SPI DEVICE
MOSI
SCK
SS
11116-098
ADE7978
Figure 123. Connecting the ADE7978 HSDC Interface to an SPI Slave
HSDC communication is managed by the HSDC_CFG register
(see Table 58). It is recommended that the HSDC_CFG register
be set to the desired value before the HSDC port is enabled using
Bit 6 (HSDCEN) in the CONFIG register. In this way, the state
of various pins belonging to the HSDC port do not accept levels
inconsistent with the desired HSDC behavior. After a hardware
reset or after power-up, the HSD and HSA pins are set high.
Bit 0 (HCLK) in the HSDC_CFG register determines the serial
clock frequency of the HSDC communication. When the HCLK
bit is set to 0 (the default value), the clock frequency is 8 MHz.
When the HCLK bit is set to 1, the clock frequency is 4 MHz. A
bit of data is transmitted at every HSCLK high to low transition.
The slave device that receives data from the HSDC interface
samples the HSD line on the low to high transition of HSCLK.
The words can be transmitted as 32-bit packages or as 8-bit
packages. When Bit 1 (HSIZE) in the HSDC_CFG register is
set to 0 (the default value), the words are transmitted as 32-bit
packages. When the HSIZE bit is set to 1, the registers are
transmitted as 8-bit packages. The HSDC interface transmits
the words MSB first.
When set to 1, Bit 2 (HGAP) introduces a gap of seven HSCLK
cycles between packages. When the HGAP bit is cleared to 0 (the
default value), no gap is introduced between packages, yielding
the shortest communication time. When HGAP is set to 0, the
HSIZE bit has no effect on the communication, and a data bit is
placed on the HSD line at every HSCLK high to low transition.
Bits[4:3] (HXFER[1:0]) specify how many words are transmitted.
When HXFER[1:0] is set to 00 (the default value), all 16 words
are transmitted. When HXFER[1:0] is set to 01, only the words
representing the instantaneous values of phase and neutral
currents and phase voltages are transmitted in the following
order: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, and
INWV. When HXFER[1:0] is set to 10, only the instantaneous
values of phase powers are transmitted in the following order:
AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and
CVAR. The value 11 for HXFER[1:0] is reserved, and writing it
is equivalent to writing 00, the default value.
Bit 5 (HSAPOL) specifies the polarity of the HSA function on
the HSA pin during communication. When the HSAPOL bit is
set to 0 (the default value), the HSA pin is active low during the
communication; that is, HSA stays high when no communication
is in progress. When a communication is executed, HSA is low
when the 32-bit or 8-bit packages are transferred and high during
the gaps. When the HSAPOL bit is set to 1, the HSA pin is active
high during the communication; that is, HSA stays low when no
communication is in progress. When a communication is executed,
HSA is high when the 32-bit or 8-bit packages are transferred and
is low during the gaps.
Bits[7:6] of the HSDC_CFG register are reserved. Any value
written into these bits has no effect on HSDC behavior.
Figure 124 shows the HSDC transfer protocol for HGAP = 0,
HXFER[1:0] = 00, and HSAPOL = 0. Note that the HSDC
interface sets a data bit on the HSD line at every HSCLK high to
low transition; the value of the HSIZE bit is irrelevant.
Figure 125 shows the HSDC transfer protocol for HSIZE = 0,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-cycle HSCLK gap between
every 32-bit word.
Figure 126 shows the HSDC transfer protocol for HSIZE = 1,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-cycle HSCLK gap between
every 8-bit word.
Rev. 0 | Page 96 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Table 58 describes the HCLK, HSIZE, HGAP, HXFER[1:0], and
HSAPOL bits in the HSDC_CFG register. Table 36 lists the time
it takes to execute an HSDC data transfer for all HSDC_CFG
register settings. For some settings, the transfer time is less than
125 μs (8 kHz), which is the update rate of the waveform sample
registers. When the transfer time is less than 125 μs, the HSDC
port transmits data every sampling cycle. When the transfer
time is greater than 125 μs, the HSDC port transmits data only
in the first of two consecutive 8 kHz sampling cycles; that is, the
port transmits registers at an effective rate of 4 kHz.
Table 36. Communication Times for Various HSDC Settings
HXFER[1:0]
00
00
00
00
00
00
01
01
01
01
01
01
10
10
10
10
10
10
HCLK
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Communication Time (μs)
64
128
77.125
154.25
119.25
238.25
28
56
33.25
66.5
51.625
103.25
36
72
43
86
66.625
133.25
N/A means not applicable.
HSCLK
31
HSD
0 31
VAWV (32 BITS)
0
31
IBWV (32 BITS)
0
CFVAR (32 BITS)
11116-099
IAVW (32 BITS)
0 31
HSA
Figure 124. HSDC Communication for HGAP = 0, HXFER[1:0] = 00, and HSAPOL = 0; HSIZE Is Irrelevant
HSCLK
31
0
IAVW (32 BITS)
31
7 HCLK
CYCLES
0
VAWV (32 BITS)
31
7 HCLK
CYCLES
0
IBWV (32 BITS)
31
0
CVAR (32 BITS)
11116-100
HSD
HSA
Figure 125. HSDC Communication for HSIZE = 0, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0
HSCLK
31
HSD
24
IAVW (BYTE 3)
23
7 HCLK
CYCLES
16
IAVW (BYTE 2)
15
7 HCLK
CYCLES
IAVW (BYTE 1)
8
7
0
CVAR (BYTE 0)
11116-101
1
HSIZE1
N/A
N/A
0
0
1
1
N/A
N/A
0
0
1
1
N/A
N/A
0
0
1
1
HGAP
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
HSA
Figure 126. HSDC Communication for HSIZE = 1, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0
Rev. 0 | Page 97 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
All other gi coefficients are equal to 0.
CHECKSUM REGISTER
The ADE7978 has a 32-bit checksum register (Address 0xE532)
to ensure that the configuration registers maintain their desired
values. The checksum register verifies all configuration registers
of the ADE7978, as well as the reserved internal registers, which
always maintain their default values.
0
Figure 127. Checksum Register Calculation
The formulas that govern the LFSR generator are as follows:
bi(j) = FB(j) AND gi XOR bi − 1(j − 1), i = 1, 2, 3, ..., 31
(60)
For more information, see the Hardware Reset and
ADE7978/ADE7933/ADE7932 Chipset Software Reset sections.
bi(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that
form the CRC. Bit b0 is the least significant bit, and Bit b31
is the most significant bit.
gi, i = 0, 1, 2, …, 31 are the coefficients of the generating
polynomial defined by the IEEE 802.3 standard as follows:
G(x) =
(56)
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 +
x4 + x2 + x + 1
g0 = g1 = g2 = g4 = g5 = g7 = 1
g8 = g10 = g11 = g12 = g16 = g22 = g23 = g26 = 1
g0
(57)
g1
g2
g3
g31
FB
b0
b1
b2
b31
LFSR
a2399, a2398, ..., a2, a1, a0
Figure 128. LFSR Generator Used in Checksum Register Calculation
Rev. 0 | Page 98 of 120
11116-088

(59)
If the CRC bit in the STATUS1 register is set to 1 when no register
was written to, it can be assumed that one of the registers has
changed value and, therefore, the configuration of the ADE7978
has changed. The recommended response is to initiate a hardware or software reset to reset all registers, including reserved
registers, to their default values, and then to reinitialize the
configuration registers.
Figure 128 shows how the LFSR generator is used in the CRC
calculation. The configuration registers and the reserved
internal registers form the bits (a2399, a2398,…, a0) used by the
LFSR generator. Bit a0 is the least significant bit of the first
register to enter the LFSR generator; Bit a2399 is the most
significant bit of the last register to enter the LFSR generator.

b0(j) = FB(j) AND g0
Every time a configuration register of the ADE7978 is written
to or changes value inadvertently, Bit 25 (CRC) in the STATUS1
register (Address 0xE503) is set to 1 to indicate that the checksum
value has changed. If Bit 25 (CRC) in the MASK1 register is set
to 1, the IRQ1 interrupt pin is driven low, and the status flag
CRC in the STATUS1 register is set to 1. The status bit is cleared
and the IRQ1 pin returns high after a 1 is written to the CRC
status bit in the STATUS1 register.
11116-087
LFSR
GENERATOR
ARRAY OF 2400 BITS
(58)
Equation 58, Equation 59, and Equation 60 must be repeated
for j = 1, 2, …, 2400. The value written to the checksum register
contains the Bits bi(2400), i = 0, 1, …, 31.
The ADE7978 computes the cyclic redundancy check (CRC)
based on the IEEE 802.3 standard. The registers are introduced
one by one into a linear feedback shift register (LFSR) generator
starting with the least significant bit (see Figure 127). The 32-bit
result is written to the checksum register. After power-up or after
a hardware or software reset, the CRC is computed on the default
values of the registers, giving a result equal to 0x6BF87803.
2399
FB(j) = aj − 1 XOR b31(j − 1)
Data Sheet
ADE7978/ADE7933/ADE7932
REGISTER LIST
Table 37. Registers Located in DSP Data Memory RAM
Address
0x4380
0x4381
0x4382
0x4383
0x4384
0x4385
0x4386
0x4387
0x4388
0x4389
0x438A
0x438B
0x438C
0x438D
0x438E
0x438F
0x4390
0x4391
0x4392
0x4393
0x4394
0x4395
0x4396
0x4397
0x4398
Register
Name
AIGAIN
AVGAIN
AV2GAIN
BIGAIN
BVGAIN
BV2GAIN
CIGAIN
CVGAIN
CV2GAIN
NIGAIN
NVGAIN
NV2GAIN
AIRMSOS
AVRMSOS
AV2RMSOS
BIRMSOS
BVRMSOS
BV2RMSOS
CIRMSOS
CVRMSOS
CV2RMSOS
NIRMSOS
NVRMSOS
NV2RMSOS
ISUMLVL
R/W 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Length
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
Bit Length During
Communication 2
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
Type 3
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
Default
Value
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x4399
0x439A
0x439B
0x439C
0x439D
0x439E
0x439F
0x43A0
0x43A1
0x43A2
APGAIN
BPGAIN
CPGAIN
AWATTOS
BWATTOS
CWATTOS
AVAROS
BVAROS
CVAROS
VLEVEL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
24
24
24
24
24
24
24
24
24
24
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
S
S
S
S
S
S
S
S
S
S
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x43A3
AFWATTOS
R/W
24
32 ZPSE
S
0x000000
0x43A4
BFWATTOS
R/W
24
32 ZPSE
S
0x000000
0x43A5
CFWATTOS
R/W
24
32 ZPSE
S
0x000000
0x43A6
AFVAROS
R/W
24
32 ZPSE
S
0x000000
0x43A7
BFVAROS
R/W
24
32 ZPSE
S
0x000000
0x43A8
CFVAROS
R/W
24
32 ZPSE
S
0x000000
Rev. 0 | Page 99 of 120
Description
Phase A current gain adjust.
Phase A voltage gain adjust.
Phase A V2P channel gain adjust.
Phase B current gain adjust.
Phase B voltage gain adjust.
Phase B V2P channel gain adjust.
Phase C current gain adjust.
Phase C voltage gain adjust.
Phase C V2P channel gain adjust.
Neutral current gain adjust.
Neutral line V1P channel gain adjust.
Neutral line V2P channel gain adjust.
Phase A current rms offset.
Phase A voltage rms offset.
Phase A V2P voltage rms offset.
Phase B current rms offset.
Phase B voltage rms offset.
Phase B V2P voltage rms offset.
Phase C current rms offset.
Phase C voltage rms offset.
Phase C V2P voltage rms offset.
Neutral current rms offset.
Neutral line V1P voltage rms offset.
Neutral line V2P voltage rms offset.
Threshold used to compare the absolute sum
of phase currents and the neutral current.
Phase A power gain adjust.
Phase B power gain adjust.
Phase C power gain adjust.
Phase A total active power offset adjust.
Phase B total active power offset adjust.
Phase C total active power offset adjust.
Phase A total reactive power offset adjust.
Phase B total reactive power offset adjust.
Phase C total reactive power offset adjust.
Register used in the algorithm that
computes the fundamental active and
reactive powers. See Equation 28.
Phase A fundamental active power offset
adjust.
Phase B fundamental active power offset
adjust.
Phase C fundamental active power offset
adjust.
Phase A fundamental reactive power offset
adjust.
Phase B fundamental reactive power offset
adjust.
Phase C fundamental reactive power offset
adjust.
ADE7978/ADE7933/ADE7932
Data Sheet
Address
0x43A9
0x43AA
0x43AB
0x43AC
0x43AD
0x43AE
0x43AF
0x43B0
Register
Name
AFIRMSOS
BFIRMSOS
CFIRMSOS
AFVRMSOS
BFVRMSOS
CFVRMSOS
TEMPCO
ATEMP0
R/W 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Length
24
24
24
24
24
24
24
24
Bit Length During
Communication 2
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
Type 3
S
S
S
S
S
S
S
S
Default
Value
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x43B1
BTEMP0
R/W
24
32 ZPSE
S
0x000000
0x43B2
CTEMP0
R/W
24
32 ZPSE
S
0x000000
0x43B3
NTEMP0
R/W
24
32 ZPSE
S
0x000000
0x43B4
0x43B5
0x43B6
0x43B7
0x43B8
to
0x43BF
0x43C0
0x43C1
0x43C2
0x43C3
0x43C4
0x43C5
0x43C6
0x43C7
0x43C8
0x43C9
0x43CA
0x43CB
0x43CC
0x43CD
0x43CE
ATGAIN
BTGAIN
CTGAIN
NTGAIN
Reserved
R/W
R/W
R/W
R/W
N/A
24
24
24
24
N/A
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
N/A
S
S
S
S
N/A
0x000000
0x000000
0x000000
0x000000
0x000000
AIRMS
AVRMS
AV2RMS
BIRMS
BVRMS
BV2RMS
CIRMS
CVRMS
CV2RMS
NIRMS
ISUM
ATEMP
BTEMP
CTEMP
NTEMP
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
24
24
24
24
24
24
24
24
24
24
28
24
24
24
24
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x43CF
to
0x43FF
Reserved
N/A
N/A
N/A
N/A
0x000000
Description
Phase A fundamental current rms offset.
Phase B fundamental current rms offset.
Phase C fundamental current rms offset.
Phase A fundamental voltage rms offset.
Phase B fundamental voltage rms offset.
Phase C fundamental voltage rms offset.
Temperature coefficient of the shunt.
Phase A ADE7933/ADE7932 ambient
temperature at calibration.
Phase B ADE7933/ADE7932 ambient
temperature at calibration.
Phase C ADE7933/ADE7932 ambient
temperature at calibration.
Neutral line ADE7933/ADE7932 ambient
temperature at calibration.
Phase A temperature gain adjust.
Phase B temperature gain adjust.
Phase C temperature gain adjust.
Neutral line temperature gain adjust.
These memory locations should be kept at
0x000000 for proper operation.
Phase A current rms value.
Phase A voltage rms value.
Phase A V2P voltage rms value.
Phase B current rms value.
Phase B voltage rms value.
Phase B V2P voltage rms value.
Phase C current rms value.
Phase C voltage rms value.
Phase C V2P voltage rms value.
Neutral current rms value.
Sum of IAWV, IBWV, and ICWV registers.
Phase A ADE7933/ADE7932 temperature.
Phase B ADE7933/ADE7932 temperature.
Phase C ADE7933/ADE7932 temperature.
Neutral line ADE7933/ADE7932
temperature.
These memory locations should be kept at
0x000000 for proper operation.
R = read only; R/W = read and write; N/A = not applicable.
32 ZPSE = 24-bit signed register that is transmitted as a 32-bit word with four MSBs padded with 0s and sign extended to 28 bits. 32 ZP = 28- or 24-bit signed or
unsigned register that is transmitted as a 32-bit word with four MSBs or eight MSBs, respectively, padded with 0s.
3
S = signed register in twos complement format.
1
2
Rev. 0 | Page 100 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Table 38. Internal DSP Memory RAM Registers
Address
0xE203
Register Name
Reserved
R/W 1
R/W
Bit Length
16
Type 2
U
Default Value
0x0000
0xE228
Run
R/W
16
U
0x0000
R/W 1
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Length
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Type 2
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
1
2
Description
This address should not be written for proper
operation.
The run register starts and stops the DSP (see the
Digital Signal Processor section).
R/W = read and write.
U = unsigned register.
Table 39. Billable Registers
Address
0xE400
0xE401
0xE402
0xE403
0xE404
0xE405
0xE406
0xE407
0xE408
0xE409
0xE40A
0xE40B
0xE40C
0xE40D
0xE40E
1
2
Register Name
AWATTHR
BWATTHR
CWATTHR
AFWATTHR
BFWATTHR
CFWATTHR
AVARHR
BVARHR
CVARHR
AFVARHR
BFVARHR
CFVARHR
AVAHR
BVAHR
CVAHR
R = read only.
S = signed register in twos complement format.
Rev. 0 | Page 101 of 120
Description
Phase A total active energy accumulation.
Phase B total active energy accumulation.
Phase C total active energy accumulation.
Phase A fundamental active energy accumulation.
Phase B fundamental active energy accumulation.
Phase C fundamental active energy accumulation.
Phase A total reactive energy accumulation.
Phase B total reactive energy accumulation.
Phase C total reactive energy accumulation.
Phase A fundamental reactive energy accumulation.
Phase B fundamental reactive energy accumulation.
Phase C fundamental reactive energy accumulation.
Phase A apparent energy accumulation.
Phase B apparent energy accumulation.
Phase C apparent energy accumulation.
ADE7978/ADE7933/ADE7932
Data Sheet
Table 40. Configuration and Power Quality Registers
Address
0xE500
Register
Name
IPEAK
R/W 1
R
Bit
Length
32
Bit Length During
Communication 2
32
Type 3
U
Default
Value 4
N/A
0xE501
VPEAK
R
32
32
U
N/A
0xE502
0xE503
0xE504
to
0xE506
0xE507
0xE508
0xE509
0xE50A
0xE50B
0xE50C
0xE50D
0xE50E
0xE50F
0xE510
0xE511
0xE512
0xE513
0xE514
0xE515
0xE516
STATUS0
STATUS1
Reserved
R/W
R/W
32
32
32
32
U
U
N/A
N/A
OILVL
OVLVL
SAGLVL
MASK0
MASK1
IAWV
IBWV
ICWV
INWV
VAWV
VBWV
VCWV
VA2WV
VB2WV
VC2WV
VNWV
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
24
24
24
32
32
24
24
24
24
24
24
24
24
24
24
24
32 ZP
32 ZP
32 ZP
32
32
32 SE
32 SE
32 SE
32 SE
32 SE
32 SE
32 SE
32 SE
32 SE
32 SE
32 SE
U
U
U
U
U
S
S
S
S
S
S
S
S
S
S
S
0xFFFFFF
0xFFFFFF
0x000000
0x00000000
0x00000000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0xE517
VN2WV
R
24
32 SE
S
N/A
0xE518
AWATT
R
24
32 SE
S
N/A
0xE519
BWATT
R
24
32 SE
S
N/A
0xE51A
CWATT
R
24
32 SE
S
N/A
0xE51B
AVAR
R
24
32 SE
S
N/A
0xE51C
BVAR
R
24
32 SE
S
N/A
0xE51D
CVAR
R
24
32 SE
S
N/A
0xE51E
AVA
R
24
32 SE
S
N/A
0xE51F
BVA
R
24
32 SE
S
N/A
0xE520
CVA
R
24
32 SE
S
N/A
0xE521
0xE522
0xE523
0xE524
0xE525
0xE526
AVTHD
AITHD
BVTHD
BITHD
CVTHD
CITHD
R
R
R
R
R
R
24
24
24
24
24
24
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
S
S
S
S
S
S
N/A
N/A
N/A
N/A
N/A
N/A
Rev. 0 | Page 102 of 120
Description
Current peak register (see Figure 62 and
Table 41 for more information).
Voltage peak register (see Figure 62 and
Table 42 for more information).
Interrupt Status Register 0 (see Table 43).
Interrupt Status Register 1 (see Table 44).
These addresses should not be written for
proper operation.
Overcurrent threshold.
Overvoltage threshold.
Voltage sag level threshold.
Interrupt Enable Register 0 (see Table 45).
Interrupt Enable Register 1 (see Table 46).
Instantaneous value of Phase A current.
Instantaneous value of Phase B current.
Instantaneous value of Phase C current.
Instantaneous value of neutral current.
Instantaneous value of Phase A voltage.
Instantaneous value of Phase B voltage.
Instantaneous value of Phase C voltage.
Instantaneous value of Phase A V2P voltage.
Instantaneous value of Phase B V2P voltage.
Instantaneous value of Phase C V2P voltage.
Instantaneous value of neutral line V1P
voltage.
Instantaneous value of neutral line V2P
voltage.
Instantaneous value of Phase A total active
power.
Instantaneous value of Phase B total active
power.
Instantaneous value of Phase C total active
power.
Instantaneous value of Phase A total
reactive power.
Instantaneous value of Phase B total
reactive power.
Instantaneous value of Phase C total
reactive power.
Instantaneous value of Phase A apparent
power.
Instantaneous value of Phase B apparent
power.
Instantaneous value of Phase C apparent
power.
Total harmonic distortion of Phase A voltage.
Total harmonic distortion of Phase A current.
Total harmonic distortion of Phase B voltage.
Total harmonic distortion of Phase B current.
Total harmonic distortion of Phase C voltage.
Total harmonic distortion of Phase C current.
Data Sheet
ADE7978/ADE7933/ADE7932
Register
Name
Reserved
R/W 1
Bit
Length
Bit Length During
Communication 2
Type 3
Default
Value 4
NVRMS
NV2RMS
CHECKSUM
R
R
R
24
24
32
32 ZP
32 ZP
32
S
S
U
N/A
N/A
0x6BF87803
0xE533
VNOM
R/W
24
32 ZP
S
0x000000
0xE534
to
0xE536
0xE537
0xE538
0xE539
0xE53A
0xE53B
0xE53C
0xE53D
to
0xE5FE
0xE5FF
Reserved
AFIRMS
AFVRMS
BFIRMS
BFVRMS
CFIRMS
CFVRMS
Reserved
R
R
R
R
R
R
24
24
24
24
24
24
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
S
S
S
S
S
S
N/A
N/A
N/A
N/A
N/A
N/A
Phase A fundamental current rms value.
Phase A fundamental voltage rms value.
Phase B fundamental current rms value.
Phase B fundamental voltage rms value.
Phase C fundamental current rms value.
Phase C fundamental voltage rms value.
These addresses should not be written for
proper operation.
R
32
32
U
N/A
0xE600
0xE601
LAST_
RWDATA32
PHSTATUS
ANGLE0
R
R
16
16
16
16
U
U
N/A
N/A
0xE602
ANGLE1
R
16
16
U
N/A
0xE603
ANGLE2
R
16
16
U
N/A
0xE604
to
0xE607
0xE608
0xE609
to
0xE60B
0xE60C
0xE60D
0xE60E
0xE60F
Reserved
Contains the data from the last successful
32-bit register communication.
Phase peak register (see Table 47).
Time Delay 0 (see the Time Interval Between
Phases section for more information).
Time Delay 1 (see the Time Interval Between
Phases section for more information).
Time Delay 2 (see the Time Interval Between
Phases section for more information).
These addresses should not be written for
proper operation.
PHNOLOAD
Reserved
R
16
16
U
N/A
Phase no load register (see Table 48).
These addresses should not be written for
proper operation.
LINECYC
ZXTOUT
COMPMODE
Reserved
R/W
R/W
R/W
16
16
16
16
16
16
U
U
U
0xFFFF
0xFFFF
0x01FF
0xE610
0xE611
0xE612
0xE613
0xE614
0xE615
0xE616
0xE617
0xE618
0xE619
to
0xE6FF
CFMODE
CF1DEN
CF2DEN
CF3DEN
APHCAL
BPHCAL
CPHCAL
PHSIGN
CONFIG
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
16
16
16
16
10
10
10
16
16
16
16
16
16
16 ZP
16 ZP
16 ZP
16
16
U
U
U
U
U
U
U
U
U
0x0E88
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
N/A
0x0010
Line cycle accumulation mode count.
Zero-crossing timeout count.
Computation mode register (see Table 49).
This address should not be written for
proper operation.
CFx configuration register (see Table 50).
CF1 denominator.
CF2 denominator.
CF3 denominator.
Phase calibration of Phase A (see Table 51).
Phase calibration of Phase B (see Table 51).
Phase calibration of Phase C (see Table 51).
Power sign register (see Table 52).
ADE7978 configuration register (see Table 53).
These addresses should not be written for
proper operation.
Address
0xE527
to
0xE52F
0xE530
0xE531
0xE532
Rev. 0 | Page 103 of 120
Description
These addresses should not be written for
proper operation.
Neutral line V1P voltage rms value.
Neutral line V2P voltage rms value.
Checksum verification (see the Checksum
Register section for more information).
Nominal phase voltage rms used in the
alternative computation of the apparent
power.
These addresses should not be written for
proper operation.
ADE7978/ADE7933/ADE7932
Data Sheet
Address
0xE700
0xE701
0xE702
Register
Name
MMODE
ACCMODE
LCYCMODE
R/W 1
R/W
R/W
R/W
Bit
Length
8
8
8
Bit Length During
Communication 2
8
8
8
Type 3
U
U
U
Default
Value 4
0x1C
0x00
0x78
0xE703
0xE704
0xE705
PEAKCYC
SAGCYC
CFCYC
R/W
R/W
R/W
8
8
8
8
8
8
U
U
U
0x00
0x00
0x01
0xE706
0xE707
0xE708
HSDC_CFG
Version
CONFIG3
R/W
R
R/W
8
8
8
8
8
8
U
U
U
0x00
0xE709
ATEMPOS
R
8
8
S
0x00
0xE70A
BTEMPOS
R
8
8
S
0x00
0xE70B
CTEMPOS
R
8
8
S
0x00
0xE70C
NTEMPOS
R
8
8
S
0x00
0xE70D
to
0xE7E2
0xE7E3
Reserved
R/W
8
8
U
N/A
0xE7E4
to
0xE7FC
0xE7FD
Reserved
Internal register used in conjunction with
the internal register at Address 0xE7FE to
enable/disable the protection of the DSP
RAM-based registers (see the Digital Signal
Processor section for more information).
These addresses should not be written for
proper operation.
R
8
8
U
N/A
R/W
8
8
U
N/A
Contains the data from the last successful
8-bit register communication.
Internal register used in conjunction with
the internal register at Address 0xE7E3 to
enable/disable the protection of the DSP
RAM-based registers (see the Digital Signal
Processor section for more information).
These addresses should not be written for
proper operation.
0xE7FE
Reserved
LAST_
RWDATA8
Reserved
0x0F
0xE7FF
to
0xE901
0xE902
0xE903
0xE904
0xE905
0xE906
0xE907
0xE908
Reserved
APF
BPF
CPF
APERIOD
BPERIOD
CPERIOD
APNOLOAD
R
R
R
R
R
R
R/W
16
16
16
16
16
16
16
16
16
16
16
16
16
16
U
U
U
U
U
U
U
N/A
N/A
N/A
N/A
N/A
N/A
0x0000
0xE909
VARNOLOAD
R/W
16
16
U
0x0000
0xE90A
VANOLOAD
R/W
16
16
U
0x0000
Rev. 0 | Page 104 of 120
Description
Measurement mode register (see Table 54).
Accumulation mode register (see Table 55).
Line accumulation mode behavior (see
Table 57).
Peak detection half line cycles.
Sag detection half line cycles.
Number of CF pulses between two
consecutive energy latches (see the
Synchronizing Energy Registers with the
CFx Outputs section).
HSDC configuration register (see Table 58).
Version of die.
ADE7933/ADE7932 configuration register
(see Table 59).
Phase A ADE7933/ADE7932 temperature
sensor offset.
Phase B ADE7933/ADE7932 temperature
sensor offset.
Phase C ADE7933/ADE7932 temperature
sensor offset.
Neutral line ADE7933/ADE7932 temperature
sensor offset.
These addresses should not be written for
proper operation.
Phase A power factor.
Phase B power factor.
Phase C power factor.
Line period on Phase A voltage.
Line period on Phase B voltage.
Line period on Phase C voltage.
No load threshold in the total/fundamental
active power datapath.
No load threshold in the total/fundamental
reactive power datapath.
No load threshold in the apparent power
datapath.
Data Sheet
ADE7978/ADE7933/ADE7932
Register
Name
Reserved
R/W 1
Bit
Length
Bit Length During
Communication 2
Type 3
Default
Value 4
LAST_ADD
R
16
16
U
N/A
R
16
16
U
N/A
0xEA00
0xEA01
LAST_
RWDATA16
CONFIG2
LAST_OP
R/W
R
8
8
8
8
U
U
0x00
N/A
0xEA02
WTHR
R/W
8
8
U
0x03
0xEA03
VARTHR
R/W
8
8
U
0x03
0xEA04
VATHR
R/W
8
8
U
0x03
0xEA05
to
0xEBFE
0xEBFF
Reserved
8
8
Reserved
8
8
Address
0xE90B
to
0xE9FD
0xE9FE
0xE9FF
Description
These addresses should not be written for
proper operation.
Contains the address of the register accessed
during the last successful read or write
operation.
Contains the data from the last successful
16-bit register communication.
Configuration register (see Table 60).
Indicates the type (read or write) of the last
successful read or write operation.
Threshold used in phase total/fundamental
active energy datapath.
Threshold used in phase total/fundamental
reactive energy datapath.
Threshold used in phase apparent energy
datapath.
These addresses should not be written for
proper operation.
This address can be used to manipulate the
SS/HSA pin when SPI is chosen as the active
port. See the Serial Interfaces section for
more information.
R = read only; R/W = read and write.
32 ZP = 24-bit signed or unsigned register that is transmitted as a 32-bit word with eight MSBs padded with 0s. 32 SE = 24-bit signed register that is transmitted as a
32-bit word sign extended to 32 bits. 16 ZP = 10-bit unsigned register that is transmitted as a 16-bit word with six MSBs padded with 0s.
3
U = unsigned register; S = signed register in twos complement format.
4
N/A = not applicable.
1
2
Table 41. IPEAK Register (Address 0xE500)
Bits
[23:0]
24
25
26
[31:27]
Bit Name
IPEAKVAL[23:0]
IPPHASE[0]
IPPHASE[1]
IPPHASE[2]
Default Value
0
0
0
0
00000
Description
These bits contain the peak value determined in the current channel.
When this bit is set to 1, the Phase A current generated the IPEAKVAL[23:0] value.
When this bit is set to 1, the Phase B current generated the IPEAKVAL[23:0] value.
When this bit is set to 1, the Phase C current generated the IPEAKVAL[23:0] value.
These bits are always set to 0.
Table 42. VPEAK Register (Address 0xE501)
Bits
[23:0]
24
25
26
[31:27]
Bit Name
VPEAKVAL[23:0]
VPPHASE[0]
VPPHASE[1]
VPPHASE[2]
Default Value
0
0
0
0
00000
Description
These bits contain the peak value determined in the voltage channel.
When this bit is set to 1, the Phase A voltage generated the VPEAKVAL[23:0] value.
When this bit is set to 1, the Phase B voltage generated the VPEAKVAL[23:0] value.
When this bit is set to 1, the Phase C voltage generated the VPEAKVAL[23:0] value.
These bits are always set to 0.
Rev. 0 | Page 105 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
Table 43. STATUS0 Register (Address 0xE502)
Bits
0
Bit Name
AEHF
Default Value
0
1
FAEHF
0
2
REHF
0
3
FREHF
0
4
VAEHF
0
5
LENERGY
0
6
REVAPA
0
7
REVAPB
0
8
REVAPC
0
9
REVPSUM1
0
10
REVRPA
0
11
REVRPB
0
12
REVRPC
0
13
REVPSUM2
0
14
CF1
0
15
CF2
0
16
CF3
0
17
DREADY
0
18
REVPSUM3
0
[31:19]
Reserved
0 0000 0000
0000
Description
When this bit is set to 1, it indicates that Bit 30 in one of the total active energy registers
(AWATTHR, BWATTHR, or CWATTHR) has changed.
When this bit is set to 1, it indicates that Bit 30 in one of the fundamental active energy
registers (FWATTHR, BFWATTHR, or CFWATTHR) has changed.
When this bit is set to 1, it indicates that Bit 30 in one of the total reactive energy registers
(AVARHR, BVARHR, or CVARHR) has changed.
When this bit is set to 1, it indicates that Bit 30 in one of the fundamental reactive energy
registers (AFVARHR, BFVARHR, or CFVARHR) has changed.
When this bit is set to 1, it indicates that Bit 30 in one of the apparent energy registers
(AVAHR, BVAHR, or CVAHR) has changed.
When this bit is set to 1, it indicates the end of an integration over the integer number of
half line cycles set in the LINECYC register (line cycle energy accumulation mode).
When this bit is set to 1, it indicates that the Phase A active power (total or fundamental)
identified by Bit 0 (REVAPSEL) in the MMODE register has changed sign. The sign itself is
indicated in Bit 0 (AWSIGN) of the PHSIGN register (see Table 52).
When this bit is set to 1, it indicates that the Phase B active power (total or fundamental)
identified by Bit 0 (REVAPSEL) in the MMODE register has changed sign. The sign itself is
indicated in Bit 1 (BWSIGN) of the PHSIGN register (see Table 52).
When this bit is set to 1, it indicates that the Phase C active power (total or fundamental)
identified by Bit 0 (REVAPSEL) in the MMODE register has changed sign. The sign itself is
indicated in Bit 2 (CWSIGN) of the PHSIGN register (see Table 52).
When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 datapath
has changed sign. The sign itself is indicated in Bit 3 (SUM1SIGN) of the PHSIGN register
(see Table 52).
When this bit is set to 1, it indicates that the Phase A reactive power (total or fundamental)
identified by Bit 1 (REVRPSEL) in the MMODE register has changed sign. The sign itself is
indicated in Bit 4 (AVARSIGN) of the PHSIGN register (see Table 52).
When this bit is set to 1, it indicates that the Phase B reactive power (total or fundamental)
identified by Bit 1 (REVRPSEL) in the MMODE register has changed sign. The sign itself is
indicated in Bit 5 (BVARSIGN) of the PHSIGN register (see Table 52).
When this bit is set to 1, it indicates that the Phase C reactive power (total or fundamental)
identified by Bit 1 (REVRPSEL) in the MMODE register has changed sign. The sign itself is
indicated in Bit 6 (CVARSIGN) of the PHSIGN register (see Table 52).
When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 datapath
has changed sign. The sign itself is indicated in Bit 7 (SUM2SIGN) of the PHSIGN register
(see Table 52).
When this bit is set to 1, it indicates that a high to low transition has occurred at the CF1
pin; that is, an active low pulse has been generated. This bit is set even if the CF1 output is
disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of power used at
the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register (see Table 50).
When this bit is set to 1, it indicates that a high to low transition has occurred at the CF2
pin; that is, an active low pulse has been generated. This bit is set even if the CF2 output is
disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of power used at
the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register (see Table 50).
When this bit is set to 1, it indicates that a high to low transition has occurred at the CF3
pin; that is, an active low pulse has been generated. This bit is set even if the CF3 output is
disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power used at
the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see Table 50).
When this bit is set to 1, it indicates that all periodical (8 kHz rate) DSP computations have
finished.
When this bit is set to 1, it indicates that the sum of all phase powers in the CF3 datapath
has changed sign. The sign itself is indicated in Bit 8 (SUM3SIGN) of the PHSIGN register
(see Table 52).
Reserved. These bits are always set to 0.
Rev. 0 | Page 106 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Table 44. STATUS1 Register (Address 0xE503)
Bits
0
Bit Name
NLOAD
Default Value
0
1
FNLOAD
0
2
VANLOAD
0
3
4
5
6
7
8
9
10
11
12
13
14
15
ZXTOVA
ZXTOVB
ZXTOVC
ZXTOIA
ZXTOIB
ZXTOIC
ZXVA
ZXVB
ZXVC
ZXIA
ZXIB
ZXIC
RSTDONE
0
0
0
0
0
0
0
0
0
0
0
0
1
16
Sag
0
17
OI
0
18
OV
0
19
SEQERR
0
20
MISMTCH
0
21
22
23
Reserved
Reserved
PKI
1
0
0
24
PKV
0
25
CRC
0
[31:26]
Reserved
00 0000
Description
When this bit is set to 1, it indicates that at least one phase entered or exited the no load
condition based on the total active and reactive powers. The phase is indicated in Bits[2:0]
(NLPHASE[x]) in the PHNOLOAD register (see Table 48).
When this bit is set to 1, it indicates that at least one phase entered or exited the no load
condition based on the fundamental active and reactive powers. The phase is indicated in
Bits[5:3] (FNLPHASE[x]) in the PHNOLOAD register (see Table 48).
When this bit is set to 1, it indicates that at least one phase entered or exited the no load
condition based on the apparent power. The phase is indicated in Bits[8:6] (VANLPHASE[x])
in the PHNOLOAD register (see Table 48).
When this bit is set to 1, it indicates that a zero crossing on the Phase A voltage is missing.
When this bit is set to 1, it indicates that a zero crossing on the Phase B voltage is missing.
When this bit is set to 1, it indicates that a zero crossing on the Phase C voltage is missing.
When this bit is set to 1, it indicates that a zero crossing on the Phase A current is missing.
When this bit is set to 1, it indicates that a zero crossing on the Phase B current is missing.
When this bit is set to 1, it indicates that a zero crossing on the Phase C current is missing.
When this bit is set to 1, it indicates that a zero crossing was detected on the Phase A voltage.
When this bit is set to 1, it indicates that a zero crossing was detected on the Phase B voltage.
When this bit is set to 1, it indicates that a zero crossing was detected on the Phase C voltage.
When this bit is set to 1, it indicates that a zero crossing was detected on the Phase A current.
When this bit is set to 1, it indicates that a zero crossing was detected on the Phase B current.
When this bit is set to 1, it indicates that a zero crossing was detected on the Phase C current.
At the end of a hardware or software reset, this bit is set to 1, and the IRQ1 pin goes low.
To clear this interrupt and return the IRQ1 pin high, write a 1 to this bit. The RSTDONE
interrupt cannot be masked; therefore, this bit must always be reset to 0 for the IRQ1 pin
to return high.
When this bit is set to 1, it indicates that a sag event occurred on the phase indicated by
Bits[14:12] (VSPHASE[x]) in the PHSTATUS register (see Table 47).
When this bit is set to 1, it indicates that an overcurrent event occurred on the phase
indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 47).
When this bit is set to 1, it indicates that an overvoltage event occurred on the phase
indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 47).
When this bit is set to 1, it indicates that a negative to positive zero crossing on the
Phase A voltage was followed by a negative to positive zero crossing on the Phase C
voltage instead of on the Phase B voltage.
When this bit is set to 1, it indicates that ||ISUM| − |INWV|| > |ISUMLVL|, where ISUMLVL is
the value of the ISUMLVL register (Address 0x4398). For more information, see the Neutral
Current Mismatch section.
Reserved. This bit is always set to 1.
Reserved. This bit is always set to 0.
When this bit is set to 1, it indicates that the period used to detect the peak value in the
current channel has ended. The IPEAK register contains the peak value and the phase
where the peak was detected (see Table 41).
When this bit is set to 1, it indicates that the period used to detect the peak value in the
voltage channel has ended. The VPEAK register contains the peak value and the phase
where the peak was detected (see Table 42).
When this bit is set to 1, it indicates that the ADE7978 has computed a checksum value
that is different from the checksum value computed when the run register was set to 1.
Reserved. These bits are always set to 0.
Rev. 0 | Page 107 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
Table 45. MASK0 Register (Address 0xE50A)
Bits
0
Bit Name
AEHF
Default Value
0
1
FAEHF
0
2
REHF
0
3
FREHF
0
4
VAEHF
0
5
LENERGY
0
6
REVAPA
0
7
REVAPB
0
8
REVAPC
0
9
REVPSUM1
0
10
REVRPA
0
11
REVRPB
0
12
REVRPC
0
13
REVPSUM2
0
14
CF1
0
15
CF2
0
16
CF3
0
17
DREADY
0
18
REVPSUM3
0
[31:19]
Reserved
0 0000 0000
0000
Description
When this bit is set to 1, it enables an interrupt when Bit 30 changes in any of the total
active energy registers (AWATTHR, BWATTHR, or CWATTHR).
When this bit is set to 1, it enables an interrupt when Bit 30 changes in any of the
fundamental active energy registers (AFWATTHR, BFWATTHR, or CFWATTHR).
When this bit is set to 1, it enables an interrupt when Bit 30 changes in any of the total
reactive energy registers (AVARHR, BVARHR, or CVARHR).
When this bit is set to 1, it enables an interrupt when Bit 30 changes in any of the
fundamental reactive energy registers (AFVARHR, BFVARHR, or CFVARHR).
When this bit is set to 1, it enables an interrupt when Bit 30 changes in any of the apparent
energy registers (AVAHR, BVAHR, or CVAHR).
When this bit is set to 1, it enables an interrupt at the end of an integration over the integer
number of half line cycles set in the LINECYC register (line cycle energy accumulation mode).
When this bit is set to 1, it enables an interrupt when the Phase A active power (total or
fundamental) identified by Bit 0 (REVAPSEL) in the MMODE register changes sign.
When this bit is set to 1, it enables an interrupt when the Phase B active power (total or
fundamental) identified by Bit 0 (REVAPSEL) in the MMODE register changes sign.
When this bit is set to 1, it enables an interrupt when the Phase C active power (total or
fundamental) identified by Bit 0 (REVAPSEL) in the MMODE register changes sign.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the
CF1 datapath changes sign.
When this bit is set to 1, it enables an interrupt when the Phase A reactive power (total or
fundamental) identified by Bit 1 (REVRPSEL) in the MMODE register changes sign.
When this bit is set to 1, it enables an interrupt when the Phase B reactive power (total or
fundamental) identified by Bit 1 (REVRPSEL) in the MMODE register changes sign.
When this bit is set to 1, it enables an interrupt when the Phase C reactive power (total or
fundamental) identified by Bit 1 (REVRPSEL) in the MMODE register changes sign.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the
CF2 datapath changes sign.
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at the
CF1 pin; that is, an active low pulse is generated. The interrupt can be enabled even if the
CF1 output is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of
power used at the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register
(see Table 50).
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at the
CF2 pin; that is, an active low pulse is generated. The interrupt can be enabled even if the
CF2 output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of
power used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register
(see Table 50).
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at the
CF3 pin; that is, an active low pulse is generated. The interrupt can be enabled even if the
CF3 output is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of
power used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register
(see Table 50).
When this bit is set to 1, it enables an interrupt when all periodical (8 kHz rate) DSP
computations finish.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the
CF3 datapath changes sign.
Reserved. These bits do not manage any functionality.
Rev. 0 | Page 108 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Table 46. MASK1 Register (Address 0xE50B)
Bits
0
Bit Name
NLOAD
Default Value
0
1
FNLOAD
0
2
VANLOAD
0
3
ZXTOVA
0
4
ZXTOVB
0
5
ZXTOVC
0
6
ZXTOIA
0
7
ZXTOIB
0
8
ZXTOIC
0
9
ZXVA
0
10
ZXVB
0
11
ZXVC
0
12
ZXIA
0
13
ZXIB
0
14
ZXIC
0
15
RSTDONE
0
16
Sag
0
17
OI
0
18
OV
0
19
SEQERR
0
20
MISMTCH
0
[22:21]
23
Reserved
PKI
00
0
24
PKV
0
25
CRC
0
[31:26]
Reserved
00 0000
Description
When this bit is set to 1, it enables an interrupt when at least one phase enters the no load
condition based on the total active and reactive powers.
When this bit is set to 1, it enables an interrupt when at least one phase enters the no load
condition based on the fundamental active and reactive powers.
When this bit is set to 1, it enables an interrupt when at least one phase enters the no load
condition based on the apparent power.
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase A
voltage is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase B
voltage is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase C
voltage is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase A
current is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase B
current is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase C
current is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the
Phase A voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the
Phase B voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the
Phase C voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the
Phase A current.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the
Phase B current.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the
Phase C current.
Because the RSTDONE interrupt cannot be disabled, this bit has no function. It can be set
to 1 or cleared to 0 with no effect on the device.
When this bit is set to 1, it enables an interrupt when a sag event occurs on the phase
indicated by Bits[14:12] (VSPHASE[x]) in the PHSTATUS register (see Table 47).
When this bit is set to 1, it enables an interrupt when an overcurrent event occurs on the
phase indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 47).
When this bit is set to 1, it enables an interrupt when an overvoltage event occurs on the
phase indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 47).
When this bit is set to 1, it enables an interrupt when a negative to positive zero crossing
on the Phase A voltage is followed by a negative to positive zero crossing on the Phase C
voltage instead of on the Phase B voltage.
When this bit is set to 1, it enables an interrupt when ||ISUM| − |INWV|| > |ISUMLVL|, where
ISUMLVL is the value of the ISUMLVL register (Address 0x4398). For more information, see
the Neutral Current Mismatch section.
Reserved. These bits do not manage any functionality.
When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the current channel has ended.
When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the voltage channel has ended.
When this bit is set to 1, it enables an interrupt when the latest checksum value is different
from the checksum value computed when the run register was set to 1.
Reserved. These bits do not manage any functionality.
Rev. 0 | Page 109 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
Table 47. PHSTATUS Register (Address 0xE600)
Bits
[2:0]
3
4
5
[8:6]
9
10
11
12
13
14
15
Bit Name
Reserved
OIPHASE[0]
OIPHASE[1]
OIPHASE[2]
Reserved
OVPHASE[0]
OVPHASE[1]
OVPHASE[2]
VSPHASE[0]
VSPHASE[1]
VSPHASE[2]
Reserved
Default Value
000
0
0
0
000
0
0
0
0
0
0
0
Description
Reserved. These bits are always set to 0.
When this bit is set to 1, the Phase A current generates Bit 17 (OI) in the STATUS1 register.
When this bit is set to 1, the Phase B current generates Bit 17 (OI) in the STATUS1 register.
When this bit is set to 1, the Phase C current generates Bit 17 (OI) in the STATUS1 register.
Reserved. These bits are always set to 0.
When this bit is set to 1, the Phase A voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, the Phase B voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, the Phase C voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, the Phase A voltage generates Bit 16 (sag) in the STATUS1 register.
When this bit is set to 1, the Phase B voltage generates Bit 16 (sag) in the STATUS1 register.
When this bit is set to 1, the Phase C voltage generates Bit 16 (sag) in the STATUS1 register.
Reserved. This bit is always set to 0.
Table 48. PHNOLOAD Register (Address 0xE608)
Bits
0
Bit Name
NLPHASE[0]
Default Value
0
1
NLPHASE[1]
0
2
NLPHASE[2]
0
3
FNLPHASE[0]
0
4
FNLPHASE[1]
0
5
FNLPHASE[2]
0
6
VANLPHASE[0]
0
7
VANLPHASE[1]
0
8
VANLPHASE[2]
0
[15:9]
Reserved
000 0000
Description
0: Phase A is out of the no load condition based on the total active and reactive powers.
1: Phase A is in the no load condition based on the total active and reactive powers. This
bit is set together with Bit 0 (NLOAD) in the STATUS1 register.
0: Phase B is out of the no load condition based on the total active and reactive powers.
1: Phase B is in the no load condition based on the total active and reactive powers. This
bit is set together with Bit 0 (NLOAD) in the STATUS1 register.
0: Phase C is out of the no load condition based on the total active and reactive powers.
1: Phase C is in the no load condition based on the total active and reactive powers. This
bit is set together with Bit 0 (NLOAD) in the STATUS1 register.
0: Phase A is out of the no load condition based on the fundamental active and reactive
powers.
1: Phase A is in the no load condition based on the fundamental active and reactive
powers. This bit is set together with Bit 1 (FNLOAD) in the STATUS1 register.
0: Phase B is out of the no load condition based on the fundamental active and reactive
powers.
1: Phase B is in the no load condition based on the fundamental active and reactive
powers. This bit is set together with Bit 1 (FNLOAD) in the STATUS1 register.
0: Phase C is out of the no load condition based on the fundamental active and reactive
powers.
1: Phase C is in the no load condition based on the fundamental active and reactive
powers. This bit is set together with Bit 1 (FNLOAD) in the STATUS1 register.
0: Phase A is out of the no load condition based on the apparent power.
1: Phase A is in the no load condition based on the apparent power. This bit is set together
with Bit 2 (VANLOAD) in the STATUS1 register.
0: Phase B is out of the no load condition based on the apparent power.
1: Phase B is in the no load condition based on the apparent power. This bit is set together
with Bit 2 (VANLOAD) in the STATUS1 register.
0: Phase C is out of the no load condition based on the apparent power.
1: Phase C is in the no load condition based on the apparent power. This bit is set together
with Bit 2 (VANLOAD) in the STATUS1 register.
Reserved. These bits are always set to 0.
Rev. 0 | Page 110 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Table 49. COMPMODE Register (Address 0xE60E)
Bits
0
Bit Name
TERMSEL1[0]
Default Value
1
1
TERMSEL1[1]
1
2
TERMSEL1[2]
1
3
TERMSEL2[0]
1
4
TERMSEL2[1]
1
5
TERMSEL2[2]
1
6
TERMSEL3[0]
1
7
TERMSEL3[1]
1
8
TERMSEL3[2]
1
[10:9]
ANGLESEL[1:0]
00
11
VNOMAEN
0
12
VNOMBEN
0
13
VNOMCEN
0
14
SELFREQ
0
15
Reserved
0
Description
0: Phase A is not included in the CF1 output calculations.
1: Phase A is included in the CF1 output calculations. Setting the TERMSEL1[2:0] bits to 111
specifies that the sum of all three phases is included in the CF1 output.
0: Phase B is not included in the CF1 output calculations.
1: Phase B is included in the CF1 output calculations. Setting the TERMSEL1[2:0] bits to 111
specifies that the sum of all three phases is included in the CF1 output.
0: Phase C is not included in the CF1 output calculations.
1: Phase C is included in the CF1 output calculations. Setting the TERMSEL1[2:0] bits to 111
specifies that the sum of all three phases is included in the CF1 output.
0: Phase A is not included in the CF2 output calculations.
1: Phase A is included in the CF2 output calculations. Setting the TERMSEL2[2:0] bits to 111
specifies that the sum of all three phases is included in the CF2 output.
0: Phase B is not included in the CF2 output calculations.
1: Phase B is included in the CF2 output calculations. Setting the TERMSEL2[2:0] bits to 111
specifies that the sum of all three phases is included in the CF2 output.
0: Phase C is not included in the CF2 output calculations.
1: Phase C is included in the CF2 output calculations. Setting the TERMSEL2[2:0] bits to 111
specifies that the sum of all three phases is included in the CF2 output.
0: Phase A is not included in the CF3 output calculations.
1: Phase A is included in the CF3 output calculations. Setting the TERMSEL3[2:0] bits to 111
specifies that the sum of all three phases is included in the CF3 output.
0: Phase B is not included in the CF3 output calculations.
1: Phase B is included in the CF3 output calculations. Setting the TERMSEL3[2:0] bits to 111
specifies that the sum of all three phases is included in the CF3 output.
0: Phase C is not included in the CF3 output calculations.
1: Phase C is included in the CF3 output calculations. Setting the TERMSEL3[2:0] bits to 111
specifies that the sum of all three phases is included in the CF3 output.
00: delays between the voltages and currents of the same phase are measured.
01: delays between the phase voltages are measured.
10: delays between the phase currents are measured.
11: no delays are measured.
0: the apparent power on Phase A is computed normally by multiplying the voltage rms
value by the current rms value.
1: the apparent power on Phase A is computed by multiplying the phase rms current by an
rms voltage written to the VNOM register (Address 0xE533).
0: the apparent power on Phase B is computed normally by multiplying the voltage rms
value by the current rms value.
1: the apparent power on Phase B is computed by multiplying the phase rms current by an
rms voltage written to the VNOM register (Address 0xE533).
0: the apparent power on Phase C is computed normally by multiplying the voltage rms
value by the current rms value.
1: the apparent power on Phase C is computed by multiplying the phase rms current by an
rms voltage written to the VNOM register (Address 0xE533).
0: ADE7978 is connected to a 50 Hz network.
1: ADE7978 is connected to a 60 Hz network.
This bit is set to 0 by default and does not manage any functionality.
Rev. 0 | Page 111 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
Table 50. CFMODE Register (Address 0xE610)
Bits
[2:0]
Bit Name
CF1SEL[2:0]
Default Value
000
[5:3]
CF2SEL[2:0]
001
[8:6]
CF3SEL[2:0]
010
9
CF1DIS
1
10
CF2DIS
1
11
CF3DIS
1
12
CF1LATCH
0
13
CF2LATCH
0
14
CF3LATCH
0
15
Reserved
0
Description
000: CF1 frequency is proportional to the sum of the total active powers on each phase
identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.
001: CF1 frequency is proportional to the sum of the total reactive powers on each phase
identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.
010: CF1 frequency is proportional to the sum of the apparent powers on each phase
identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.
011: CF1 frequency is proportional to the sum of the fundamental active powers on each
phase identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.
100: CF1 frequency is proportional to the sum of the fundamental reactive powers on each
phase identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.
101, 110, 111: reserved. The CF1 signal is not generated.
000: CF2 frequency is proportional to the sum of the total active powers on each phase
identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.
001: CF2 frequency is proportional to the sum of the total reactive powers on each phase
identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.
010: CF2 frequency is proportional to the sum of the apparent powers on each phase
identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.
011: CF2 frequency is proportional to the sum of the fundamental active powers on each
phase identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.
100: CF2 frequency is proportional to the sum of the fundamental reactive powers on each
phase identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.
101, 110, 111: reserved. The CF2 signal is not generated.
000: CF3 frequency is proportional to the sum of the total active powers on each phase
identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
001: CF3 frequency is proportional to the sum of the total reactive powers on each phase
identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
010: CF3 frequency is proportional to the sum of the apparent powers on each phase
identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
011: CF3 frequency is proportional to the sum of the fundamental active powers on each
phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
100: CF3 frequency is proportional to the sum of the fundamental reactive powers on each
phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
101, 110, 111: reserved. The CF3 signal is not generated.
0: CF1 output is enabled.
1: CF1 output is disabled. The energy-to-frequency converter remains enabled.
0: CF2 output is enabled.
1: CF2 output is disabled. The energy-to-frequency converter remains enabled.
0: CF3 output is enabled.
1: CF3 output is disabled. The energy-to-frequency converter remains enabled.
0: no latching of energy registers occurs when a CF1 pulse is generated.
1: the contents of the corresponding energy registers are latched when a CF1 pulse
is generated. See the Synchronizing Energy Registers with the CFx Outputs section.
0: no latching of energy registers occurs when a CF2 pulse is generated.
1: the contents of the corresponding energy registers are latched when a CF2 pulse is
generated. See the Synchronizing Energy Registers with the CFx Outputs section.
0: no latching of energy registers occurs when a CF3 pulse is generated.
1: the contents of the corresponding energy registers are latched when a CF3 pulse is
generated. See the Synchronizing Energy Registers with the CFx Outputs section.
Reserved. This bit does not manage any functionality.
Rev. 0 | Page 112 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Table 51. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616)
Bits
[9:0]
Bit Name
PHCALVAL
Default Value
0000000000
[15:10]
Reserved
000000
Description
If current channel compensation is necessary, these bits can be set to a value from 0 to 383.
If voltage channel compensation is necessary, these bits can be set to a value from 512 to
895. If the PHCALVAL bits are set to values from 384 to 511, the compensation behaves in
the same way as when the PHCALVAL bits are set to values from 0 to 127. If the PHCALVAL
bits are set to values from 896 to 1023, the compensation behaves in the same way as
when the PHCALVAL bits are set to values from 512 and 639.
Reserved. These bits do not manage any functionality.
Table 52. PHSIGN Register (Address 0xE617)
Bits
0
Bit Name
AWSIGN
Default Value
0
1
BWSIGN
0
2
CWSIGN
0
3
SUM1SIGN
0
4
AVARSIGN
0
5
BVARSIGN
0
6
CVARSIGN
0
7
SUM2SIGN
0
8
SUM3SIGN
0
[15:9]
Reserved
000 0000
Description
0: the Phase A active power (total or fundamental, as specified by Bit 0 (REVAPSEL) in the
MMODE register) is positive.
1: the Phase A active power (total or fundamental, as specified by Bit 0 (REVAPSEL) in the
MMODE register) is negative.
0: the Phase B active power (total or fundamental, as specified by Bit 0 (REVAPSEL) in the
MMODE register) is positive.
1: the Phase B active power (total or fundamental, as specified by Bit 0 (REVAPSEL) in the
MMODE register) is negative.
0: the Phase C active power (total or fundamental, as specified by Bit 0 (REVAPSEL) in the
MMODE register) is positive.
1: the Phase C active power (total or fundamental, as specified by Bit 0 (REVAPSEL) in the
MMODE register) is negative.
0: the sum of all phase powers in the CF1 datapath is positive.
1: the sum of all phase powers in the CF1 datapath is negative. Phase powers in the CF1
datapath are identified by Bits[2:0] (TERMSEL1[x]) of the COMPMODE register and by
Bits[2:0] (CF1SEL[2:0]) of the CFMODE register.
0: the Phase A reactive power (total or fundamental, as specified by Bit 1 (REVRPSEL) in the
MMODE register) is positive.
1: the Phase A reactive power (total or fundamental, as specified by Bit 1 (REVRPSEL) in the
MMODE register) is negative.
0: the Phase B reactive power (total or fundamental, as specified by Bit 1 (REVRPSEL) in the
MMODE register) is positive.
1: the Phase B reactive power (total or fundamental, as specified by Bit 1 (REVRPSEL) in the
MMODE register) is negative.
0: the Phase C reactive power (total or fundamental, as specified by Bit 1 (REVRPSEL) in the
MMODE register) is positive.
1: the Phase C reactive power (total or fundamental, as specified by Bit 1 (REVRPSEL) in the
MMODE register) is negative.
0: the sum of all phase powers in the CF2 datapath is positive.
1: the sum of all phase powers in the CF2 datapath is negative. Phase powers in the CF2
datapath are identified by Bits[5:3] (TERMSEL2[x]) of the COMPMODE register and by
Bits[5:3] (CF2SEL[2:0]) of the CFMODE register.
0: the sum of all phase powers in the CF3 datapath is positive.
1: the sum of all phase powers in the CF3 datapath is negative. Phase powers in the CF3
datapath are identified by Bits[8:6] (TERMSEL3[x]) of the COMPMODE register and by
Bits[8:6] (CF3SEL[2:0]) of the CFMODE register.
Reserved. These bits are always set to 0.
Rev. 0 | Page 113 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
Table 53. CONFIG Register (Address 0xE618)
Bits
[1:0]
Bit Name
ZX_DREADY
Default Value
00
2
3
Reserved
Swap
0
0
4
HPFEN
1
5
LPFSEL
0
6
HSDCEN
0
7
[9:8]
SWRST
VTOIA[1:0]
0
00
[11:10]
VTOIB[1:0]
00
[13:12]
VTOIC[1:0]
00
14
INSEL
0
15
Reserved
0
Description
This bit manages the output signal at the ZX/DREADY pin. For more information about the
zero-crossing function, see the Zero-Crossing Detection section.
00: DREADY functionality is enabled (see the Digital Signal Processor section).
01: ZX functionality is generated by the Phase A voltage.
10: ZX functionality is generated by the Phase B voltage.
11: ZX functionality is generated by the Phase C voltage.
Reserved. This bit is always set to 0.
1: the voltage channel outputs VA, VB, VC, and VN are swapped with the current channel
outputs IA, IB, IC, and IN, respectively. Thus, the current channel information is present in
the phase voltage channel registers and vice versa.
0: all high-pass filters in the voltage and current channels are disabled.
1: all high-pass filters in the voltage and current channels are enabled.
This bit specifies the settling time introduced by the low-pass filter in the total active
power datapath.
0: settling time = 650 ms.
1: settling time = 1300 ms.
0: HSDC serial port is disabled and CF3 functionality is configured on the CF3/HSCLK pin.
1: HSDC serial port is enabled and HSCLK functionality is configured on the CF3/HSCLK pin.
When this bit is set to 1, a software reset is initiated.
These bits select the phase voltage that is considered together with the Phase A current in
the power path.
00: Phase A voltage.
01: Phase B voltage.
10: Phase C voltage.
11: reserved (same as VTOIA[1:0] = 00).
These bits select the phase voltage that is considered together with the Phase B current in
the power path.
00: Phase B voltage.
01: Phase C voltage.
10: Phase A voltage.
11: reserved (same as VTOIB[1:0] = 00).
These bits select the phase voltage that is considered together with the Phase C current in
the power path.
00: Phase C voltage.
01: Phase A voltage.
10: Phase B voltage.
11: reserved (same as VTOIC[1:0] = 00).
0: the NIRMS register (Address 0x43C9) contains the rms value of the neutral current.
1: the NIRMS register contains the rms value of ISUM, the instantaneous value of the sum
of all three phase currents, IA, IB, and IC.
Reserved. This bit does not manage any functionality.
Rev. 0 | Page 114 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Table 54. MMODE Register (Address 0xE700)
Bits
0
Bit Name
REVAPSEL
Default Value
0
1
REVRPSEL
0
2
PEAKSEL[0]
1
3
PEAKSEL[1]
1
4
PEAKSEL[2]
1
[7:5]
Reserved
000
Description
This bit specifies whether the total active power or the fundamental active power on
Phase A, Phase B, or Phase C is used to trigger a bit in the STATUS0 register. Phase A triggers
Bit 6 (REVAPA), Phase B triggers Bit 7 (REVAPB), and Phase C triggers Bit 8 (REVAPC).
0: The total active power is used to trigger the bits in the STATUS0 register.
1: The fundamental active power is used to trigger the bits in the STATUS0 register.
This bit specifies whether the total reactive power or the fundamental reactive power on
Phase A, Phase B, or Phase C is used to trigger a bit in the STATUS0 register. Phase A triggers
Bit 10 (REVRPA), Phase B triggers Bit 11 (REVRPB), and Phase C triggers Bit 12 (REVRPC).
0: The total reactive power is used to trigger the bits in the STATUS0 register.
1: The fundamental reactive power is used to trigger the bits in the STATUS0 register.
0: Phase A is not included in the voltage and current peak detection.
1: Phase A is included in the voltage and current peak detection.
0: Phase B is not included in the voltage and current peak detection.
1: Phase B is included in the voltage and current peak detection.
0: Phase C is not included in the voltage and current peak detection.
1: Phase C is included in the voltage and current peak detection.
Reserved. These bits do not manage any functionality.
Table 55. ACCMODE Register (Address 0xE701)
Bits
[1:0]
Bit Name
WATTACC[1:0]
Default Value
00
[3:2]
VARACC[1:0]
00
[5:4]
CONSEL[1:0]
00
6
SAGCFG
0
7
Reserved
0
Description
These bits determine how the active power is accumulated in the watthour registers and
how the CFx frequency output is generated as a function of the total and fundamental
active powers.
00: signed accumulation mode of the total and fundamental active powers. The active
energy registers and the CFx pulses are generated in the same way.
01: positive only accumulation mode of the total and fundamental active powers. The total
and fundamental active energy registers are accumulated in positive only mode, but the
CFx pulses are generated in signed accumulation mode.
10: reserved (same as WATTACC[1:0] = 00).
11: absolute accumulation mode of the total and fundamental active powers. The total and
fundamental active energy registers and the CFx pulses are generated in the same way.
These bits determine how the reactive power is accumulated in the var-hour registers and
how the CFx frequency output is generated as a function of the total and fundamental
active and reactive powers.
00: signed accumulation mode of the total and fundamental reactive powers. The reactive
energy registers and the CFx pulses are generated in the same way.
01: reserved (same as VARACC[1:0] = 00).
10: the total and fundamental reactive powers are accumulated depending on the sign of
the total and fundamental active powers. If the active power is positive, the reactive power
is accumulated as is; if the active power is negative, the reactive power is accumulated with a
reversed sign. The total and fundamental reactive energy registers and the CFx pulses are
generated in the same way.
11: absolute accumulation mode of the total and fundamental reactive powers. The total and
fundamental reactive energy registers and the CFx pulses are generated in the same way.
These bits select the inputs to the energy accumulation registers. IA’, IB’, and IC’ are IA, IB,
and IC shifted by −90° (see Table 56).
00: 3-phase, 4-wire with three voltage sensors.
01: 3-phase, 3-wire delta connection.
10: reserved.
11: 3-phase, 4-wire delta connection.
This bit manages how the sag flag status bit in the STATUS1 register is generated.
0: the flag is set to 1 when any phase voltage is below the SAGLVL threshold.
1: the flag is set to 1 when any phase voltage goes below and then above the SAGLVL
threshold.
Reserved. This bit does not manage any functionality.
Rev. 0 | Page 115 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
Table 56. CONSEL[1:0] Bits in Energy Registers1
Energy Registers
AWATTHR, AFWATTHR
BWATTHR, BFWATTHR
CONSEL[1:0] = 00
VA × IA
VB × IB
CWATTHR, CFWATTHR
AVARHR, AFVARHR
BVARHR, BFVARHR
VC × IC
VA × IA’
VB × IB’
CVARHR, CFVARHR
AVAHR
BVAHR
VC × IC’
VA rms × IA rms
VB rms × IB rms
CVAHR
VC rms × IC rms
1
CONSEL[1:0] = 01
VA × IA
VB = VA − VC
VB × IB1
VC × IC
VA × IA’
VB = VA − VC
VB × IB’1
VC × IC’
VA rms × IA rms
VB rms × IB rms1
VB = VA − VC
VC rms × IC rms
CONSEL[1:0] = 11
VA × IA
VB = −VA
VB × IB
VC × IC
VA × IA’
VB = −VA
VB × IB’
VC × IC’
VA rms × IA rms
VB rms × IB rms
VB = −VA
VC rms × IC rms
In a 3-phase, 3-wire configuration (CONSEL[1:0] = 01), the ADE7978 computes the rms value of the line voltage between Phase A and Phase C and stores the result in
the BVRMS register (see the Voltage RMS in Delta Configurations section). The Phase B current value provided after the HPF is 0. Consequently, the powers associated with
Phase B are 0. To avoid any errors in the frequency output pins (CF1, CF2, or CF3) related to the powers associated with Phase B, disable the contribution of Phase B
to the energy-to-frequency converters by setting the TERMSEL1[1], TERMSEL2[1], or TERMSEL3[1] bit to 0 in the COMPMODE register. For more information, see the
Energy-to-Frequency Conversion section.
Table 57. LCYCMODE Register (Address 0xE702)
Bits
0
Bit Name
LWATT
Default Value
0
1
LVAR
0
2
LVA
0
3
ZXSEL[0]
1
4
ZXSEL[1]
1
5
ZXSEL[2]
1
6
RSTREAD
1
7
PFMODE
0
Description
0: the watthour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) are configured for regular accumulation mode.
1: the watthour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) are configured for line cycle accumulation mode.
0: the var-hour accumulation registers (AVARHR, BVARHR, CVARHR, AFVARHR, BFVARHR,
and CFVARHR) are configured for regular accumulation mode.
1: the var-hour accumulation registers (AVARHR, BVARHR, CVARHR, AFVARHR, BFVARHR,
and CFVARHR) are configured for line cycle accumulation mode.
0: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are configured for
regular accumulation mode.
1: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are configured for line
cycle accumulation mode.
0: Phase A is not selected for zero-crossing counts in line cycle accumulation mode.
1: Phase A is selected for zero-crossing counts in line cycle accumulation mode. If more
than one phase is selected for zero-crossing detection, the accumulation time is shortened
accordingly.
0: Phase B is not selected for zero-crossing counts in line cycle accumulation mode.
1: Phase B is selected for zero-crossing counts in line cycle accumulation mode. If more
than one phase is selected for zero-crossing detection, the accumulation time is shortened
accordingly.
0: Phase C is not selected for zero-crossing counts in line cycle accumulation mode.
1: Phase C is selected for zero-crossing counts in line cycle accumulation mode. If more
than one phase is selected for zero-crossing detection, the accumulation time is shortened
accordingly.
0: disables read with reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR
registers. Clear this bit to 0 when Bits[2:0] (LVA, LVAR, and LWATT) are set to 1.
1: enables read with reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR
registers. When this bit is set to 1, a read of these registers resets them to 0.
0: power factor calculation uses instantaneous values of various phase powers used in its
expression.
1: power factor calculation uses phase energy values calculated using line cycle accumulation mode. The LWATT and LVA bits (Bit 0 and Bit 2) must be enabled for the power factors
to be computed correctly. The update rate of the power factor measurement is the integral
number of half line cycles that is programmed in the LINECYC register.
Rev. 0 | Page 116 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
Table 58. HSDC_CFG Register (Address 0xE706)
Bits
0
Bit Name
HCLK
Default Value
0
1
HSIZE
0
2
HGAP
0
[4:3]
HXFER[1:0]
00
5
HSAPOL
0
[7:6]
Reserved
00
Description
0: HSCLK is 8 MHz.
1: HSCLK is 4 MHz.
0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first.
1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.
0: no gap is introduced between packages.
1: a gap of seven HCLK cycles is introduced between packages.
00: HSDC transmits sixteen 32-bit words in the following order: IAWV, VAWV, IBWV, VBWV,
ICWV, VCWV, INWV, AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and CVAR.
01: HSDC transmits seven instantaneous values of currents and voltages in the following
order: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, and INWV.
10: HSDC transmits nine instantaneous values of phase powers in the following order:
AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and CVAR.
11: reserved (same as HXFER[1:0] = 00).
0: SS/HSA output pin is active low.
1: SS/HSA output pin is active high.
Reserved. These bits do not manage any functionality.
Table 59. CONFIG3 Register (Address 0xE708)
Bits
0
Bit Name
VA2_EN
Default Value
1
1
VB2_EN
1
2
VC2_EN
1
3
VN2_EN
1
[5:4]
6
Reserved
CLKOUT_DIS
00
0
7
ADE7933_
SWRST
0
Description
This bit configures V2P or temperature measurement on the Phase A ADE7933/ADE7932.
0: temperature sensor is measured on the second voltage channel of the Phase A ADE7933/
ADE7932. On the ADE7932, the temperature sensor is always sensed by the second voltage
channel, but this bit must still be cleared to 0 to enable the temperature measurement.
1: V2P input is sensed on the second voltage channel of the Phase A ADE7933.
This bit configures V2P or temperature measurement on the Phase B ADE7933/ADE7932.
0: temperature sensor is measured on the second voltage channel of the Phase B ADE7933/
ADE7932. On the ADE7932, the temperature sensor is always sensed by the second voltage
channel, but this bit must still be cleared to 0 to enable the temperature measurement.
1: V2P input is sensed on the second voltage channel of the Phase B ADE7933.
This bit configures V2P or temperature measurement on the Phase C ADE7933/ADE7932.
0: temperature sensor is measured on the second voltage channel of the Phase C ADE7933/
ADE7932. On the ADE7932, the temperature sensor is always sensed by the second voltage
channel, but this bit must still be cleared to 0 to enable the temperature measurement.
1: V2P input is sensed on the second voltage channel of the Phase C ADE7933.
This bit configures V2P or temperature measurement on the neutral line ADE7933/ADE7932.
0: temperature sensor is measured on the second voltage channel of the neutral line ADE7933/
ADE7932. On the ADE7932, the temperature sensor is always sensed by the second voltage
channel, but this bit must still be cleared to 0 to enable the temperature measurement.
1: V2P input is sensed on the second voltage channel of the neutral line ADE7933.
Reserved. These bits do not manage any functionality.
0: ADE7933/ADE7932 CLKOUT pin is enabled.
1: ADE7933/ADE7932 CLKOUT pin is set high and no clock is generated.
When this bit is set to 1, a software reset of the ADE7933/ADE7932 devices is initiated. See
the ADE7933/ADE7932 Software Reset section for more information.
Table 60. CONFIG2 Register (Address 0xEA00)
Bits
0
Bit Name
I2C_LOCK
Default Value
0
[7:1]
Reserved
000 0000
Description
When this bit is set to 0, the SS/HSA pin can be toggled three times to activate the SPI
serial port. If I2C is the selected serial port, set this bit to 1 to lock the selection. After a 1 is
written to this bit, the ADE7978 ignores spurious toggling of the SS/HSA pin. If SPI is the
selected serial port, any write to the CONFIG2 register locks the selection. The communication protocol can be changed only after a power-down or hardware reset operation.
Reserved. These bits do not manage any functionality.
Rev. 0 | Page 117 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.18
5.10
5.00 SQ
4.90
22
0.50
BSC
1
21
EXPOSED
PAD
3.40
3.30 SQ
3.20
15
0.50
0.40
0.30
TOP VIEW
0.80
0.75
0.70
7
14
8
0.20 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
PIN 1
INDICATOR
28
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
05-23-2012-B
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-3.
Figure 129. 28-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-28-6)
Dimensions shown in millimeters
15.40
15.30
15.20
1.93 REF
20
11
7.60
7.50
7.40
10.51
10.31
10.11
PIN 1
MARK
2.64
2.54
2.44
2.44
2.24
0.30
0.20
0.10
COPLANARITY
0.1
0.71
0.50
0.31
0.25 BSC
GAGE
PLANE
45°
SEATING
PLANE
1.27 BSC
1.01
0.76
0.51
0.46
0.36
COMPLIANT TO JEDEC STANDARDS MS-013
0.32
0.23
8°
0°
11-15-2011-A
10
1
Figure 130. 20-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-20-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADE7978ACPZ
ADE7978ACPZ-RL
ADE7933ARIZ
ADE7933ARIZ-RL
ADE7932ARIZ
ADE7932ARIZ-RL
EVAL-ADE7978EBZ
EVAL-SDP-CB1Z
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
28-Lead LFCSP_WQ
28-Lead LFCSP_WQ, 13” Tape and Reel
20-Lead SOIC_IC
20-Lead SOIC_IC, 13” Tape and Reel
20-Lead SOIC_IC
20-Lead SOIC_IC, 13” Tape and Reel
Evaluation Board
Evaluation System Controller Board
Package Option
CP-28-6
CP-28-6
RI-20-1
RI-20-1
RI-20-1
RI-20-1
Z = RoHS Compliant Part.
The EVAL-SDP-CB1Z is the controller board that manages the EVAL-ADE7978EBZ evaluation board. Both boards must be ordered together.
Rev. 0 | Page 118 of 120
Data Sheet
ADE7978/ADE7933/ADE7932
NOTES
Rev. 0 | Page 119 of 120
ADE7978/ADE7933/ADE7932
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11116-0-11/13(0)
Rev. 0 | Page 120 of 120
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