AD AD5170BRM50-RL7 256-position two-time programmable i2c digital potentiometer Datasheet

256-Position Two-Time Programmable
I2C Digital Potentiometer
AD5170
FUNCTIONAL BLOCK DIAGRAM
256-position
TTP (two-time programmable) set-and-forget resistance
setting allows second-chance permanent programming
Unlimited adjustments prior to OTP (one-time
programming) activation
OTP overwrite allows dynamic adjustments with user
defined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Fast settling time: tS = 5 µs typ in power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins AD0 and AD1
Single-supply 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power, IDD = 6 µA maximum
Wide operating temperature: –40°C to +125°C
Evaluation board and software are available
Software replaces µC in factory programming applications
A
VDD
1
AD1
SDA
SCL
FUSE
LINKS
B
2
RDAC
REGISTER
GND
AD0
W
ADDRESS
DECODE
/8
SERIAL INPUT
REGISTER
04104-0-001
FEATURES
Figure 1.
APPLICATIONS
Systems calibration
Electronics level setting
Mechanical Trimmers® replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL OVERVIEW
The AD5170 is a 256-position, two-time programmable (TTP)
digital potentiometer1 that employs fuse link technology to
enable two opportunities at permanently programming the
resistance setting. OTP is a cost-effective alternative to EEMEM
for users who do not need to program the digital potentiometer
setting in memory more than once. This device performs the
same electronic adjustment function as mechanical
potentiometers or variable resistors with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance.
The AD5170 is programmed using a 2-wire, I2C® compatible
digital interface. Unlimited adjustments are allowed before
permanently (there are actually two opportunities) setting the
resistance value. During OTP activation, a permanent blow fuse
command freezes the wiper position (analogous to placing
epoxy on a mechanical trimmer).
Unlike traditional OTP digital potentiometers, the AD5170 has
a unique temporary OTP overwrite feature that allows for new
adjustments even after the fuse has been blown. However, the
OTP setting is restored during subsequent power-up
conditions. This feature allows users to treat these digital
potentiometers as volatile potentiometers with a programmable
preset.
For applications that program the AD5170 at the factory,
Analog Devices offers device programming software running
on Windows NT®, 2000, and XP® operating systems. This
software effectively replaces any external I2C controllers, thus
enhancing the time-to-market of the user’s systems.
1
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5170
TABLE OF CONTENTS
Electrical Characteristics — 2.5 kΩ ............................................... 3
Terminal Voltage Operating Range ......................................... 14
Electrical Characteristics — 10 kΩ, 50 kΩ, 100 kΩ Versions..... 4
Power-Up Sequence ................................................................... 14
Timing Characteristics — 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Versions.............................................................................................. 5
Power Supply Considerations................................................... 14
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 11
Theory of Operation ...................................................................... 12
One-Time Programming (OTP) .............................................. 12
Programming the Variable Resistor and Voltage ................... 12
Layout Considerations............................................................... 15
Evaluation Software/Hardware..................................................... 16
Software Programming ............................................................. 16
I2C Interface .................................................................................... 18
I2C Compatible 2-Wire Serial Bus ........................................... 20
Pin Configuration and Function Descriptions........................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
Programming the Potentiometer Divider ............................... 13
ESD Protection ........................................................................... 14
REVISION HISTORY
11/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Electrical Characteristics Table 1 ............................... 3
Changes to Electrical Characteristics Table 2 ............................... 4
Changes to One-Time Programming ......................................... 12
Changes to Figure 37, Figure 38, and Figure 39 ........................ 14
Changes to Power Supply Considerations................................... 14
Changes to Figure 40...................................................................... 15
Changes to Layout Considerations .............................................. 15
11/03—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD5170
ELECTRICAL CHARACTERISTICS — 2.5 kΩ
VDD = 5 V ± 10% or 3 V ±10%, VA = +VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
R-DNL
RWB, VA = no connect
Resistor Integral Nonlinearity2
R-INL
RWB, VA = no connect
Nominal Resistor Tolerance3
∆RAB
TA = 25°C
Resistance Temperature Coefficient
(∆RAB/RAB)/∆T VAB = VDD, Wiper = no connect
RWB (Wiper Resistance)
RWB
Code = 0x00, VDD = 5 V
DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Differential Nonlinearity4
DNL
Integral Nonlinearity4
INL
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T
Code = 0x80
Full-Scale Error
VWFSE
Code = 0xFF
Zero-Scale Error
VWZSE
Code = 0x00
RESISTOR TERMINALS
Voltage Range5
VA,VB,VW
Capacitance6 A, B
CA, CB
f = 1 MHz, measured to GND, code = 0x80
Capacitance W
CW
f = 1 MHz, measured to GND, code = 0x80
Shutdown Supply Current7
IA_SD
VDD = 5.5 V
Common-Mode Leakage
ICM
VA = VB = VDD/2
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
VDD = 5 V
Input Logic Low
VIL
VDD = 5 V
Input Logic High
VIH
VDD = 3 V
Input Logic Low
VIL
VDD = 3 V
Input Current
IIL
VIN = 0 V or 5 V
Input Capacitance5
CIL
POWER SUPPLIES
Power Supply Range
VDD RANGE
OTP Supply Voltage
VDD_OTP
TA = 25°C
Supply Current
IDD
VIH = 5 V or VIL = 0 V
OTP Supply Current
IDD_OTP
VDD_OTP = 5.5 V, TA = 25°C
Power Dissipation8
PDISS
VIH = 5 V or VIL = 0 V, VDD = 5 V
Power Supply Sensitivity
PSS
VDD = 5 V ± 10%, Code = midscale
9
DYNAMIC CHARACTERISTICS
Bandwidth –3 dB
BW_2.5K
Code = 0x80
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz
VW Settling Time
tS
VA = 5 V, VB = 0 V, ±1 LSB error band
Resistor Noise Voltage Density
eN_WB
RWB = 1.25 kΩ, RS = 0
1
Min
Typ1
Max
Unit
–2
–6
–20
±0.1
±0.75
+2
+6
+55
LSB
LSB
%
ppm/°C
Ω
35
160
–1.5
–2
–10
0
±0.1
±0.6
15
–2.5
2
GND
200
+1.5
+2
0
10
VDD
45
60
0.01
1
1
2.4
0.8
2.1
0.6
±1
5
2.7
5.25
3.5
5.5
5.5
6
±0.02
30
±0.08
100
4.8
0.1
1
3.2
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
µA
nA
V
V
V
V
µA
pF
V
V
µA
mA
µW
%/%
MHz
%
µs
nV/√Hz
Typical specifications represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
VAB = VDD, Wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use VDD = 5 V.
2
Rev. A | Page 3 of 24
AD5170
ELECTRICAL CHARACTERISTICS — 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD; VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
R-DNL
RWB, VA = no connect
R-INL
RWB, VA = no connect
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
∆RAB
TA = 25°C
Resistance Temperature Coefficient
(∆RAB/RAB)/∆T
VAB = VDD, wiper = no connect
RWB (Wiper Resistance)
RWB
Code = 0x00, VDD = 5 V
DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Differential Nonlinearity4
DNL
INL
Integral Nonlinearity4
Code = 0x80
Voltage Divider Temperature
(∆VW/VW)/∆T
Coefficient
Full-Scale Error
VWFSE
Code = 0xFF
Zero-Scale Error
VWZSE
Code = 0x00
RESISTOR TERMINALS
Voltage Range5
VA,VB,VW
Capacitance6 A, B
f = 1 MHz, measured to GND, code = 0x80
CA, CB
CW
f = 1 MHz, measured to GND, code = 0x80
Capacitance6 W
Shutdown Supply Current7
IA_SD
VDD = 5.5 V
Common-Mode Leakage
ICM
VA = VB = VDD/2
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
VDD = 5 V
Input Logic Low
VIL
VDD = 5 V
Input Logic High
VIH
VDD = 3 V
Input Logic Low
VIL
VDD = 3 V
Input Current
IIL
VIN = 0 V or 5 V
CIL
Input Capacitance6
POWER SUPPLIES
Power Supply Range
VDD RANGE
OTP Supply Voltage8
VDD_OTP
Supply Current
IDD
VIH = 5 V or VIL = 0 V
OTP Supply Current9
IDD_OTP
VDD_OTP = 5.5 V, TA = 25°C
Power Dissipation10
PDISS
VIH = 5 V or VIL = 0 V, VDD = 5 V
Power Supply Sensitivity
PSS
VDD = 5 V ± 10%, code = midscale
DYNAMIC CHARACTERISTICS11
Bandwidth –3 dB
BW
RAB = 10 kΩ, code = 0x80
RAB = 50 kΩ, code = 0x80
RAB = 100 kΩ, code = 0x80
Total Harmonic Distortion
THDW
VA =1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ
VW Settling Time
tS
VA = 5 V, VB = 0 V, ±1 LSB error band
(10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage Density
eN_WB
RWB = 5 kΩ, RS = 0
1
Min
Typ1
Max
Unit
–1
–2.5
–20
±0.1
±0.25
+1
+2.5
+20
LSB
LSB
%
ppm/°C
Ω
35
160
200
–1
–1
±0.1
±0.3
15
+1
+1
LSB
LSB
ppm/°C
–2.5
0
–1
1
0
2.5
LSB
LSB
VDD
V
pF
pF
µA
nA
GND
45
60
0.01
1
1
2.4
0.8
2.1
0.6
±1
5
2.7
5.25
3.5
5.5
5.5
6
±0.02
30
±0.08
100
V
V
V
V
µA
pF
V
V
µA
mA
µW
%/%
600
100
40
0.1
2
kHz
kHz
kHz
%
µs
9
nV/√Hz
Typical specifications represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
VAB = VDD, Wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
Different from operating power supply, power supply OTP is used one time only.
9
Different from operating current, supply current for OTP lasts approximately 400 ms for one time only.
10
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
11
All dynamic characteristics use VDD = 5 V.
2
Rev. A | Page 4 of 24
AD5170
TIMING CHARACTERISTICS — 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD; VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
I2C INTERFACE TIMING CHARACTERISTICS1 (Specifications apply to all parts)
SCL Clock Frequency
fSCL
tBUF Bus Free Time between STOP and START
t1
tHD;STA Hold Time (Repeated START)
t2
After this period, the first clock
pulse is generated.
tLOW Low Period of SCL Clock
t3
tHIGH High Period of SCL Clock
t4
tSU;STA Setup Time for Repeated START Condition
t5
tHD;DAT Data Hold Time2
t6
tSU;DAT Data Setup Time
t7
tF Fall Time of Both SDA and SCL Signals
t8
tR Rise Time of Both SDA and SCL Signals
t9
tSU;STO Setup Time for STOP Condition
t10
1
2
See timing diagrams for locations of measured values.
The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Rev. A | Page 5 of 24
Min
Typ
Max
Unit
400
kHz
µs
µs
1.3
0.6
1.3
0.6
0.6
0.9
100
300
300
0.6
µs
µs
µs
µs
ns
ns
ns
µs
AD5170
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to GND
VA, VB, VW to GND
Terminal Current, Ax–Bx, Ax–Wx, Bx–Wx1
Pulsed
Continuous
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Thermal Resistance2 θJA: MSOP-10
Value
–0.3 V to +7 V
VDD
±20 mA
±5 mA
0 V to 7 V
–40°C to +125°C
150°C
–65°C to +150°C
300°C
230°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
Maximum terminal current is bound by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation = (TJMAX – TA)/θJA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 24
AD5170
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
0.5
TA = 25°C
RAB = 10kΩ
1.0
VDD = 2.7V
0.5
0
VDD = 5.5V
–0.5
RAB = 10kΩ
0.4
POTENTIOMETER MODE DNL (LSB)
–1.0
–1.5
0.3
0.2
0.1
VDD = 2.7V; TA = –40°C, +25°C, +85°C, +125°C
0
–0.1
–0.2
–0.3
32
64
96
128
160
192
224
256
CODE (DECIMAL)
–0.5
04104-0-002
0
0
32
128
160
192
224
256
Figure 5. DNL vs. Code vs. Temperature
0.5
1.0
TA = 25°C
RAB = 10kΩ
0.3
0.2
VDD = 2.7V
0.1
0
–0.1
–0.2
VDD = 5.5V
–0.3
TA = 25°C
RAB = 10kΩ
0.8
POTENTIOMETER MODE INL (LSB)
0.4
–0.4
0.6
0.4
VDD = 5.5V
0.2
0
VDD = 2.7V
–0.2
–0.4
–0.6
–0.8
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
–1.0
04104-0-003
–0.5
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
Figure 3. R-DNL vs. Code vs. Supply Voltages
04104-0-006
RHEOSTAT MODE DNL (LSB)
96
CODE (DECIMAL)
Figure 2. R-INL vs. Code vs. Supply Voltages
Figure 6. INL vs. Code vs. Supply Voltages
0.5
0.5
RAB = 10kΩ
0.4
TA = 25°C
RAB = 10kΩ
0.3
POTENTIOMETER MODE DNL (LSB)
0.4
VDD = 5.5V
TA = –40°C, +25°C, +85°C, +125°C
0.2
0.1
0
–0.1
VDD = 2.7V
TA = –40°C, +25°C, +85°C, +125°C
–0.2
–0.3
–0.4
0.3
0.2
0.1
VDD = 2.7V
0
–0.1
VDD = 5.5V
–0.2
–0.3
–0.4
–0.5
0
32
64
96
128
160
192
CODE (DECIMAL)
224
256
04104-0-004
POTENTIOMETER MODE INL (LSB)
64
04104-0-005
–0.4
–2.0
Figure 4. INL vs. Code vs. Temperature
–0.5
0
32
64
96
128
160
192
224
CODE (DECIMAL)
Figure 7. DNL vs. Code vs. Supply Voltages
Rev. A | Page 7 of 24
256
04104-0-007
RHEOSTAT MODE INL (LSB)
1.5
AD5170
2.0
4.50
RAB = 10kΩ
1.0
0.5
0
VDD = 5.5V
TA = –40°C, +25°C, +85°C, +125°C
–0.5
–1.0
–1.5
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
3.00
2.25
VDD = 2.7V, VA = 2.7V
1.50
VDD = 5.5V, VA = 5.0V
0.75
0
–40
04104-0-008
–2.0
3.75
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 8. R-INL vs. Code vs. Temperature
Figure 11. Zero-Scale Error vs. Temperature
0.5
10
RAB = 10kΩ
0.4
0.3
0.2
IDD, SUPPLY CURRENT (µA)
RHEOSTAT MODE DNL (LSB)
–25
04104-0-011
ZSE, ZERO-SCALE ERROR (LSB)
RHEOSTAT MODE INL (LSB)
RAB = 10kΩ
VDD = 2.7V
TA = –40°C, +25°C, +85°C, +125°C
1.5
VDD = 2.7V, 5.5V; TA = –40°C, +25°C, +85°C, +125°C
0.1
0
–0.1
–0.2
VDD = 5V
1
VDD = 3V
–0.3
32
64
96
128
160
192
224
256
CODE (DECIMAL)
0.1
–40
–7
26
59
92
Figure 12. Supply Current vs. Temperature
Figure 9. R-DNL vs. Code vs. Temperature
120
2.0
RAB = 10kΩ
RAB = 10kΩ
RHEOSTAT MODE TEMPCO (ppm/°C)
1.0
0.5
0
VDD = 5.5V, VA = 5.0V
–0.5
VDD = 2.7V, VA = 2.7V
–1.0
–1.5
–25
–10
5
20
35
50
65
80
95
TEMPERATURE (°C)
110
125
04104-0-010
FSE, FULL-SCALE ERROR (LSB)
1.5
–2.0
–40
125
TEMPERATURE (°C)
100
80
60
VDD = 2.7V
TA = –40°C TO +85°C, –40°C TO +125°C
40
VDD = 5.5V
TA = –40°C TO +85°C, –40°C TO +125°C
20
0
–20
0
32
64
96
128
160
192
224
CODE (DECIMAL)
Figure 13. Rheostat Mode Tempco ∆RWB/∆T vs. Code
Figure 10. Full-Scale Error vs. Temperature
Rev. A | Page 8 of 24
256
04104-0-013
0
04104-0-009
–0.5
04104-0-012
–0.4
AD5170
0
RAB = 10kΩ
0x80
–6
40
0x40
–12
30
0x20
–18
VDD = 2.7V
TA = –40°C TO +85°C, –40°C TO +125°C
GAIN (dB)
20
10
0
0x10
–24
0x08
–30
0x04
–36
0x02
–42
–10
0x01
VDD = 5.5V
TA = –40°C TO +85°C, –40°C TO +125°C
–48
–20
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
–60
1k
1M
Figure 17. Gain vs. Frequency vs. Code, RAB = 50 kΩ
0
0
0x80
–6
0x80
–6
0x40
–12
0x40
–12
0x20
–18
–24
GAIN (dB)
0x08
0x04
–30
0x20
–18
0x10
–36
0x10
–24
0x08
–30
0x04
–36
0x02 0x01
–42
0x02
–42
–48
–54
–54
–60
10k
100k
1M
10M
FREQUENCY (Hz)
–60
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 15. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ
04104-0-018
0x01
–48
04104-0-015
Figure 18. Gain vs. Frequency vs. Code, RAB = 100 kΩ
0
0
0x80
–6
–12
0x40
–18
0x20
–6
–12
100kΩ
60kHz
–18
50kΩ
120kHz
GAIN (dB)
0x10
–24
0x08
–30
0x04
–36
0x02
0x01
–42
–24
–36
–42
–48
–54
–54
–60
10k
100k
FREQUENCY (Hz)
1M
04104-0-016
–48
1k
10kΩ
570kHz
2.5kΩ
2.2MHz
–30
Figure 16. Gain vs. Frequency vs. Code, RAB = 10 kΩ
–60
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 19. –3 dB Bandwidth at Code = 0x80
Rev. A | Page 9 of 24
10M
04104-0-019
GAIN (dB)
100k
FREQUENCY (Hz)
Figure 14. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
GAIN (dB)
10k
04104-0-017
–54
–30
04104-0-014
POTENTIOMETER MODE TEMPCO (ppm/°C)
50
AD5170
10
1
VDD = 5.5V
VW
0.1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
DIGITAL INPUT VOLTAGE (V)
4.0
4.5
5.0
Figure 22. Midscale Glitch, Code 0x80 to 0x7F
Figure 20. IDD vs. Input Voltage
VW
VW
SCL
SCL
04104-0-023
0
04104-0-020
0.01
04104-0-025
VDD = 2.7V
04104-0-021
IDD, SUPPLY CURRENT (mA)
TA = 25°C
Figure 21. Digital Feedthrough
Figure 23. Large Signal Settling Time
Rev. A | Page 10 of 24
AD5170
TEST CIRCUITS
Figure 24 to Figure 29 illustrate the test circuits that define the
test conditions used in the product specification tables.
V+ = VDD ± 10%
∆VMS
PSRR (dB) = 20 LOG
∆VDD
∆VMS%
PSS (%/%) =
∆VDD%
W
∆VDD
W
V+
B
Figure 24. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
VMS
Figure 27. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
NO CONNECT
DUT
A
DUT
IW
A W
VIN
04104-0-027
Figure 28. Test Circuit for Gain vs. Frequency
NC
DUT
W
VOUT
–15V
2.5V
Figure 25. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
VMS2
AD8610
B
B
A
+15V
W
OFFSET
GND
VMS
)
04104-0-030
VMS
04104-0-026
B
A
04104-0-029
(
DUT
IW = VDD/RNOMINAL
DUT
VW
A
B
RW = [VMS1 – VMS2]/IW
VMS1
04104-0-028
VDD
W
GND
B
NC
Figure 26. Test Circuit for Wiper Resistance
ICM
VCM
NC = NO CONNECT
04104-0-032
V+
VA
V+ = VDD
1LSB = V+/2N
DUT
A
Figure 29. Test Circuit for Common-Mode Leakage Current
Rev. A | Page 11 of 24
AD5170
THEORY OF OPERATION
A
SCL
SDA
I2C
INTERFACE
DECODER
MUX
DAC
REG.
W
B
COMPARATOR
FUSES
EN
FUSE
REG.
04103-0-026
ONE-TIME
PROGRAM/TEST
CONTROL BLOCK
Figure 30. Detailed Functional Block Diagram
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
The AD5170 is a 256-position, digitally controlled variable
resistor (VR) that employs fuse link technology to achieve
memory retention of resistance setting.
Rheostat Operation
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5170 presets to midscale during
initial power-on. After the wiper is set at the desired position,
the resistance can be permanently set by programming the T bit
high along with the proper coding (see Table 7 and Table 8) and
one time VDD_OTP. Note that fuse link technology of the
AD517x family of digital pots requires VDD_OTP between 5.25 V
and 5.5 V to blow the fuses to achieve a given nonvolatile
setting. On the other hand, VDD can be 2.7 V to 5.5 V during
operation. As a result, system supply that is lower than 5.25 V
requires external supply for one-time programming. Note that
the user is allowed only one attempt in blowing the fuses. If the
user fails to blow the fuses at the first attempt, the fuses’
structures may have changed such that they may never be
blown regardless of the energy applied at subsequent events. For
details, see the Power Supply Considerations section.
The device control circuit has two validation bits, E1 and E0,
that can be read back to check the programming status (see
Table 7). Users should always read back the validation bits to
ensure that the fuses are properly blown. After the fuses have
been blown, all fuse latches are enabled upon subsequent
power-on; therefore, the output corresponds to the stored
setting. Figure 30 shows a detailed functional block diagram.
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal, plus the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of 256
possible settings.
A
A
W
B
A
W
B
W
B
04103-0-027
An internal power-on preset places the wiper at midscale
during power-on. If the OTP function has been activated, the
device powers up at the user-defined permanent setting.
Figure 31. Rheostat Mode Configuration
Assuming a 10 kΩ part is used, the wiper’s first connection
starts at the B terminal for data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between Terminal W and
Terminal B. The second connection is the first tap point, which
corresponds to 139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω)
for data 0x01. The third connection is the next tap point, representing 178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on.
Each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached at 10,100 Ω (RAB + 2 × RW).
Rev. A | Page 12 of 24
AD5170
For RAB = 10 kΩ and the B terminal open-circuited, the
following output resistance, RWA, is set for the RDAC latch
codes, as shown in Table 6.
A
SD BIT
RS
Table 6. Codes and Corresponding RWA Resistance
RS
D (Dec.)
255
128
1
0
RS
W
04104-0-034
RS
B
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
Figure 32. AD5170 Equivalent RDAC Circuit
The general equation that determines the digitally programmed
output resistance between Terminal W and Terminal B is
RWB(D ) =
D
× RAB + 2 × RW
128
(1)
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A–B, W–A, and W–B can be at either
polarity.
where D is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register, RAB is the end-to-end resistance, and
RW is the wiper resistance contributed by the on resistance of
the internal switch.
VI
A
W
Figure 33. Potentiometer Mode Configuration
Table 5. Codes and Corresponding RWB Resistance
RWB (Ω)
9,961
5,060
139
100
Output State
Full Scale (RAB – 1 LSB + RW)
Midscale
1 LSB
Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
between Terminal W and Terminal B in this state to a maximum
pulse current of no more than 20 mA. Otherwise, degradation
or possible destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper, Terminal W, and Terminal A also
produces a digitally controlled complementary resistance, RWA.
When these terminals are used, the B terminal can be opened.
Setting the resistance value for RWA starts at a maximum value
of resistance and decreases as the data loaded in the latch
increases in value. The general equation for this operation is
RWA(D ) =
256 – D
× RAB + 2 × RW
128
VO
B
In summary, if RAB = 10 kΩ and the A terminal is opencircuited, the output resistance RWB is set for the RDAC latch
codes, as shown in Table 5.
D (Dec.)
255
128
1
0
Output State
Full Scale
Midscale
1 LSB
Zero Scale
Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. Since the resistance element is processed using thin film technology, the change in RAB with
temperature has a very low 35 ppm/°C temperature coefficient.
RDAC
LATCH
AND
DECODER
RWA (Ω)
139
5,060
9,961
10,060
04104-0-035
D7
D6
D5
D4
D3
D2
D1
D0
(2)
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to Terminal A and Terminal B is
VW ( D) =
D
256 − D
VA +
VB
256
256
(3)
For a more accurate calculation, which includes the effect of
wiper resistance, VW can be found as
VW (D) =
R (D )
RWB (D)
V A + WA
VB
R AB
R AB
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RWA and RWB, and not the absolute values. Thus, the temperature drift reduces to 15 ppm/°C.
Rev. A | Page 13 of 24
AD5170
ESD PROTECTION
All digital inputs—SDA, SCL, AD0, and AD1—are protected
with a series input resistor and parallel Zener ESD structures, as
shown in Figure 34 and Figure 35.
340Ω
GND
04104-0-037
LOGIC
Figure 34. ESD Protection of Digital Pins
fuse programming supply (either an on-board regulator or
rack-mount power supply) must be rated at 5.25 V to 5.5 V and
able to provide a 100 mA current for 400 ms for successful onetime programming. Once fuse programming is completed, the
VDD_OTP supply must be removed to allow normal operation at
2.7 V to 5.5 V and the device will consume current in µA range.
Figure 37 shows the simplest implementation of a dual supply
requirement by using a jumper. This approach saves one voltage
supply, but draws additional current and requires manual
configuration.
R1
04104-0-038
GND
CONNECT J1 HERE
FOR OTP
5.5V
A, B, W
50kΩ
VDD
C1
10µF
R2
C2
1nF
AD5170
250kΩ
CONNECT J1 HERE
AFTER OTP
Figure 35. ESD Protection of Resistor Terminals
The AD5170 VDD to GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer operation. Supply signals present on Terminal A, Terminal B, and
Terminal W that exceed VDD or GND will be clamped by the
internal forward-biased diodes (see Figure 36).
VDD
04104-0-049
TERMINAL VOLTAGE OPERATING RANGE
Figure 37. Power Supply Requirement
An alternate approach in 3.5 V to 5.25 V systems adds a signal
diode between the system supply and the OTP supply for
isolation, as shown in Figure 38.
5.5V
A
APPLY FOR OTP ONLY
D1
VDD
3.5V–5.25V
W
C1
1µF
04104-0-050
GND
AD5170
04104-0-039
B
C2
1nF
Figure 36. Maximum Terminal Voltages Set by VDD and GND
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 36), it is
important to power VDD/GND before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
will be forward biased such that VDD is powered unintentionally
and may affect the rest of the user’s circuit. The ideal power-up
sequence is GND, VDD, the digital inputs, and then VA/VB/VW.
The relative order of powering VA, VB, VW, and the digital
inputs is not important as long as they are powered after
VDD/GND.
Figure 38. Isolate 5.5 V OTP Supply from 3.5 V to 5.25 V Normal Operating
Supply. The VDD_OTP must be removed once OTP is completed.
R1
10kΩ
VDD
2.7V
P1
P2
C1
10µF
C2
1nF
AD5170
P1=P2=FDV302P, NDS0610
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time programming and normal operating voltage supplies share the
same VDD terminal of the AD5170. The AD5170 employs fuse
link technology that requires 5.25 V to 5.5 V for blowing the
internal fuses to achieve a given setting, but normal VDD can be
anywhere between 2.7 V and 5.5 V after the fuse programming
process. As a result, dual voltage supplies and isolation are
needed if system VDD is lower than the required VDD_OTP. The
APPLY FOR OTP ONLY
5.5V
04104-0-051
POWER-UP SEQUENCE
Figure 39. Isolate 5.5 V OTP Supply from 2.7 V Normal Operating Supply.
The VDD_OTP supply must be removed once OTP is completed.
For users who operate their systems at 2.7 V, use of the
bidirectional low threshold P-Ch MOSFETs is recommended
for the supply’s isolation. As shown in Figure 39, this assumes
Rev. A | Page 14 of 24
AD5170
LAYOUT CONSIDERATIONS
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Note that the digital ground should also be joined remotely to
the analog ground at one point to minimize the ground bounce.
AD5170 achieves the OTP function through blowing internal
fuses. Users should always apply the 5.25 V to 5.5 V one-time
program voltage requirement at the first fuse programming
attempt. Failure to comply with this requirement may lead to a
change in the fuse structures, rendering programming
inoperable.
Poor PCB layout introduces parasitics that may affect the fuse
programming. Therefore, it is recommended to add a 10 µF
tantalum capacitor in parallel with a 1 nF ceramic capacitor as
close as possible to the VDD pin. The type and value chosen for
both capacitors are important. This combination of capacitor
values provides both a fast response and larger supply current
handling with minimum supply droop during transients. As a
result, these capacitors increase the OTP programming success
by not inhibiting the proper energy needed to blow the internal
fuses. Additionally, C1 minimizes transient disturbance and low
frequency ripple while C2 reduces high frequency noise during
normal operation.
Rev. A | Page 15 of 24
VDD
C1
10µF
+
VDD
C2
1nF
AD5170
GND
04104-0-040
the 2.7 V system voltage is applied first, and the P1 and P2 gates
are pulled to ground, thus turning on P1 and subsequently P2.
As a result, VDD of the AD5170 approaches 2.7 V. When the
AD5170 setting is found, the factory tester applies the VDD_OTP
to both the VDD and the MOSFETs gates turning off P1 and P2.
The OTP command is executed at this time to program the
AD5170 while the 2.7 V source is protected. Once the fuse
programming is completed, the tester withdraws the VDD_OTP
and the setting for AD5170 is permanently fixed.
Figure 40. Power Supply Bypassing
AD5170
EVALUATION SOFTWARE/HARDWARE
Figure 41. AD5170 Computer Software Interface
There are two ways of controlling the AD5170. Users can either
program the devices with computer software or external I2C
controllers.
SOFTWARE PROGRAMMING
Due to the advantages of the one-time programmable feature,
users may consider programming the device in the factory
before shipping the final product to end-users. ADI offers
device programming software that can be implemented in the
factory on PCs running Windows® 95 or later. As a result,
external controllers are not required, which significantly
reduces development time. The program is an executable file
that does not require knowledge of any programming languages
or programming skills. It is easy to set up and to use. Figure 41
shows the software interface. The software can be downloaded
from www.analog.com.
The AD5170 starts at midscale after power-up prior to OTP
programming. To increment or decrement the resistance, the
user may simply move the scrollbars on the left. To write any
specific value, the user should use the bit pattern in the upper
screen and press the Run button. The format of writing data to
the device is shown in Table 7. Once the desired setting is
found, the user presses the Program Permanent button to blow
the internal fuse links.
To read the validation bits and data from the device, the user
simply presses the Read button. The format of the read bits is
shown in Table 8.
To apply the device programming software in the factory, users
must modify a parallel port cable and configure Pin 2, Pin 3,
Pin 15, and Pin 25 for SDA_write, SCL, SDA_read, and DGND,
respectively, for the control signals (Figure 42). Users should
also lay out the PCB of the AD5170 with SCL and SDA pads, as
shown in Figure 43, such that pogo pins can be inserted for
factory programming.
Rev. A | Page 16 of 24
AD5170
AD5170
13
25
12
24
11
23
10
22
9
21
8
04104-0-043
W
NC
AD1
SDA
SCL
Figure 43. Recommended AD5170 PCB Layout. The SCL and SDA pads allow
pogo pins to be inserted so that signals can be communicated through the
parallel port for programming (Figure 42).
R3
100Ω
R2 READ
100Ω
SCL
SDA
R1 WRITE
100Ω
04104-0-042
20
7
19
6
18
5
17
4
16
3
15
2
14
1
B
A
AD0
GND
VDD
Figure 42. Parallel Port Connection. Pin 2 = SDA_write, Pin 3 = SCL,
Pin 15 = SDA_read, and Pin 25 = DGND.
Rev. A | Page 17 of 24
AD5170
I2C INTERFACE
Table 7. Write Mode
S
0
1
0 1 1 AD1 AD0 W
Slave Address Byte
A
2T SD
T
0 OW X
Instruction Byte
X
X
A
D7 D6 D5 D4 D3 D2 D1 D0
Instruction Byte
A
D7 D6 D5 D4 D3 D2 D1 D0
Data Byte
A
P
A
E1
A
P
Table 8. Read Mode
S
0
1
0 1 1 AD1 AD0 R
Slave Address Byte
S = Start Condition.
E0
X
X X X
Data Byte
X
X
T = OTP Programming Bit. Logic 1 permanently programs the
wiper.
P = Stop Condition.
OW = Overwrite the fuse setting and program the digital
potentiometer to a different setting. Note that upon power-up,
the digital potentiometer presets to either midscale or fuse
setting depending on whether the fuse link has been blown.
A = Acknowledge.
AD0, AD1 = Package Pin Programmable Address Bits.
X = Don’t Care.
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.
W = Write.
E1, E0 = OTP Validation Bits.
R = Read.
0, 0 = Ready to Program.
2T = Second fuse link array for two-time programming. Logic 0
corresponds to first trim. Logic 1 corresponds to second trim.
Note that blowing trim #2 before trim #1 effectively disables
trim #1 and in turn only allows one-time programming.
SD = Shutdown connects wiper to B terminal and open circuits
the A terminal. It does not change the contents of the wiper
register.
1, 0 = Fatal Error. Some fuses not blown. Do not retry.
Discard this unit.
1, 1 = Programmed Successfully. No further adjustments are
possible.
Rev. A | Page 18 of 24
AD5170
t8
t6
t2
t9
SCL
t4
t3
t2
t8
t7
t10
t5
t9
04104-0-044
SDA
t1
P
S
S
P
Figure 44. I2C Interface Detailed Timing Diagram
1
9
1
9
1
9
SDA
0
1
0
1
1
AD1 AD0 R/W
A0
SD
T
0
OW
X
X
ACK BY
AD5170
START BY
MASTER
X
D7
D6
D5
D4
D3
D2
D1
D0
ACK BY
AD5170
ACK BY
AD5170
STOP BY
MASTER
FRAME 3
DATA BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
SLAVE ADDRESS BYTE
04104-0-045
SCL
Figure 45. Writing to the RDAC Register
9
1
1
9
1
9
SDA
0
1
0
1
1
AD1 AD0 R/W
D7
D6
D5
D4
D3
D2
ACK BY
AD5170
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
D1
D0
E1
E0
X
X
X
FRAME 2
INSTRUCTION BYTE
Figure 46. Reading Data from the RDAC Register
Rev. A | Page 19 of 24
X
X
X
NO ACK
BY MASTER
ACK BY
MASTER
FRAME 3
DATA BYTE
04104-0-046
SCL
STOP BY
MASTER
AD5170
I2C COMPATIBLE 2-WIRE SERIAL BUS
The 2-wire I2C serial bus protocol operates as follows:
1.
The fifth MSB, OW, is an overwrite bit. When raised to a
logic high, OW allows the RDAC setting to be changed
even after the internal fuses have been blown. However,
once OW is returned to a logic zero, the position of the
RDAC returns to the setting prior to overwrite. Because
OW is not static, if the device is powered off and on, the
RDAC presets to midscale or to the setting at which the
fuses were blown, depending on whether the fuses have
been permanently set.
The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 45). The
following byte is the slave address byte, which consists of
the slave address followed by an R/W bit (this bit determines whether data is read from, or written to, the slave
device). AD0 and AD1 are configurable address bits which
allow up to four devices on one bus (see Table 7).
The remainder of the bits in the instruction byte are Don’t
Care bits (see Figure 45).
The slave address corresponding to the transmitted address
bits responds by pulling the SDA line low during the ninth
clock pulse (this is termed the Acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to, or read from,
its serial register. If the R/W bit is high, the master will read
from the slave device. If the R/W bit is low, the master will
write to the slave device.
2.
In the write mode, the second byte is the instruction byte.
The first bit (MSB), 2T, of the instruction byte is the
second trim enable bit. A logic low selects the first array of
fuses, and a logic high selects the second array. This means
that after blowing the fuses with trim#1, the user still has
another chance to blow them again with trim#2. Note that
using trim#2 before trim#1 effectively disables trim#1 and,
in turn, only allows one-time programming.
The second MSB, SD, is a shutdown bit. A logic high causes
an open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost 0 Ω in rheostat
mode or 0 V in potentiometer mode. It is important to
note that the shutdown operation does not disturb the
contents of the register. When brought out of shutdown,
the previous setting is applied to the RDAC. Also, during
shutdown, new settings can be programmed. When the
part is returned from shutdown, the corresponding VR
setting is applied to the RDAC.
The third MSB, T, is the OTP (one-time programmable)
programming bit. A logic high blows the poly fuses and
programs the resistor setting permanently. For example, if
the user wanted to blow the first array of fuses, the
instruction byte would be 00100XXX. To blow the second
array of fuses, the instruction byte would be 10100XXX. A
logic low of the T bit simply allows the device to act as a
typical volatile digital potentiometer.
The fourth MSB must always be at Logic 0.
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an Acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see
Figure 44).
3.
In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference from the write mode, with eight
data bits followed by an Acknowledge bit). Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 46).
Following the data byte, the validation byte contains two
validation bits, E0 and E1. These bits signify the status of
the one-time programming (see Figure 46).
4.
After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10th clock pulse to establish a STOP
condition (see Figure 45). In read mode, the master issues a
No Acknowledge for the 9th clock pulse (i.e., the SDA line
remains high). The master then brings the SDA line low
before the 10th clock pulse, which goes high to establish a
STOP condition (see Figure 46).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowledged
its slave address and instruction bytes in the write mode, the
RDAC output updates on each successive byte. If different
instructions are needed, the write/read mode has to start again
with a new slave address, instruction, and data byte. Similarly, a
repeated read function of the RDAC is also allowed.
Rev. A | Page 20 of 24
AD5170
5V
Table 9. Validation Status
1
E0
0
0
1
Status
Ready for Programming.
Fatal Error. Some fuses not blown. Do not retry.
Discard this unit.
Successful. No further programming is possible.
RP
SDA
MASTER
SCL
5V
5V
SDA
Multiple Devices on One Bus
Figure 47 shows four AD5170s on the same serial bus. Each has
a different slave address because the states of their AD0 and
AD1 pins are different. This allows each device on the bus to be
written to, or read from, independently. The master device
output bus line drivers are open-drain pull-downs in a fully I2C
compatible interface.
Rev. A | Page 21 of 24
SCL
SDA
SCL
5V
SDA
SCL
SDA
SCL
AD1
AD1
AD1
AD1
AD0
AD0
AD0
AD0
AD5170
AD5170
AD5170
AD5170
Figure 47. Multiple AD5170s on One I2C Bus
04104-0-047
E1
0
1
RP
AD5170
B 1
10
W
A 2
9
NC
AD0 3
AD5170
8
AD1
GND 4
TOP VIEW
7
SDA
6
SCL
VDD 5
04104-0-048
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 48. Pin Configuration
Table 10. Pin Function Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
Mnemonic
B
A
AD0
GND
VDD
SCL
SDA
AD1
NC
W
Description
B Terminal.
A Terminal.
Programmable Address Bit 0 for Multiple Package Decoding.
Digital Ground.
Positive Power Supply.
Serial Clock Input. Positive Edge Triggered.
Serial Data Input/Output.
Programmable Address Bit 1 for Multiple Package Decoding.
No Connect.
W Terminal.
Rev. A | Page 22 of 24
AD5170
OUTLINE DIMENSIONS
3.00 BSC
10
6
4.90 BSC
3.00 BSC
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
0.15
0.00
1.10 MAX
0.27
0.17
SEATING
PLANE
0.23
0.08
8°
0°
0.80
0.60
0.40
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 49. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5170BRM2.5
AD5170BRM2.5-RL7
AD5170BRM10
AD5170BRM10-RL7
AD5170BRM50
AD5170BRM50-RL7
AD5170BRM100
AD5170BRM100-RL7
AD5170EVAL1
1
RAB (kΩ)
2.5
2.5
10
10
50
50
100
100
Temperature
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
Evaluation Board
Package Option
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
Rev. A | Page 23 of 24
Branding
D0Y
D0Y
D0Z
D0Z
D0W
D0W
D0X
D0X
AD5170
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04104–0–11/04(A)
Rev. A | Page 24 of 24
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