Sharp LH28F320S3TD-L10 32 m-bit (2 mb x 8/1 mb x 16 x 2-bank) smart 3 dual work flash memory Datasheet

LH28F320S3TD-L10
LH28F320S3TD-L10
32 M-bit (2 MB x 8/1 MB x 16 x 2-Bank)
Smart 3 Dual Work Flash Memory
DESCRIPTION
The LH28F320S3TD-L10 Dual Work flash memory
with Smart 3 technology is a high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications, having high programming
performance is achieved through highly-optimized
page buffer operations. Its symmetrically-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for resident flash arrays, SIMMs and
memory cards. Its enhanced suspend capabilities
provide for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F320S3TD-L10 offers three levels of
protection : absolute protection with VPP at GND,
selective hardware block locking, or flexible
software block locking. These alternatives give
designers ultimate control of their code security
needs. LH28F320S3TD-L10 is conformed to the
flash Scalable Command Set (SCS) and the
Common Flash Interface (CFI) specification which
enable universal and upgradable interface, enable
the highest system/device data transfer rates and
minimize device and system-level implementation
costs.
FEATURES
• Smart 3 Dual Work technology
– 2.7 V or 3.3 V VCC
– 2.7 V, 3.3 V or 5 V VPP
– Capable of performing erase, write and read
for each bank independently (Impossible to
perform read from both banks at a time).
• High-speed write performance
– Two 32-byte page buffers/bank
– 2.7 µs/byte write transfer rate
• Common Flash Interface (CFI)
– Universal & upgradable interface
• Scalable Command Set (SCS)
• High performance read access time
– 100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)
• Enhanced automated suspend options
– Write suspend to read
– Block erase suspend to write
– Block erase suspend to read
• Enhanced data protection features
– Absolute protection with VPP = GND
– Flexible block locking
– Erase/write lockout during power transitions
• SRAM-compatible write interface
• User-configurable x8 or x16 operation
• High-density symmetrically-blocked architecture
– Sixty-four 64 k-byte erasable blocks
• Enhanced cycling capability
– 100 000 block erase cycles
– 3.2 million block erase cycles/bank
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases Icc
in static mode
• Automated write and erase
– Command user interface
– Status register
• ETOXTM∗ V nonvolatile flash technology
• Package
– 56-pin TSOP Type I (TSOP056-P-1420)
Normal bend
∗ ETOX is a trademark of Intel Corporation.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
LH28F320S3TD-L10
PIN CONNECTIONS
56-PIN TSOP (Type I)
NC
BE1L#
BE1H#
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
BE0#
VPP
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
TOP VIEW
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
(TSOP056-P-1420)
-2-
WP#
WE#
OE#
STS
DQ15
DQ7
DQ14
DQ6
GND
DQ13
DQ5
DQ12
DQ4
VCC
GND
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
NC
NC
LH28F320S3TD-L10
BLOCK DIAGRAM
Bank1
DQ0-DQ15
INPUT
BUFFER
I/O
LOGIC
QUERY
ROM
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
REGISTER
OUTPUT
MULTIPLEXER
OUTPUT
BUFFER
DATA
REGISTER
Bank0
WE#
COMMAND
USER
INTERFACE
OE#
RP#
MULTIPLEXER
WP#
DATA
COMPARATOR
A0-A20
INPUT
BUFFER
ADDRESS
LATCH
Y
DECODER
X
DECODER
Y GATING
VCC
BYTE#
WRITE
STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
STS
VPP
VCC
32
64 k-BYTE
BLOCKS
GND
ADDRESS
COUNTER
-3-
BE0#
BE1H#
BE0#
BE1L#
LH28F320S3TD-L10
PIN DESCRIPTION
SYMBOL
TYPE
A0-A20
INPUT
DQ0-DQ15
INPUT/
OUTPUT
BE0#,
BE1L#, BE1H#
INPUT
RP#
INPUT
OE#
INPUT
WE#
INPUT
STS
OPEN
DRAIN
OUTPUT
WP#
INPUT
BYTE#
INPUT
VPP
SUPPLY
VCC
SUPPLY
GND
NC
SUPPLY
NAME AND FUNCTION
ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
A0 : Byte Select Address. Not used in x16 mode (can be floated).
A1-A4 : Column Address. Selects 1 of 16-bit lines.
A5-A15 : Row Address. Selects 1 of 2 048-word lines.
A16-A20 : Block Address.
DATA INPUT/OUTPUTS :
DQ0-DQ7 : Inputs data and commands during CUI write cycles; outputs data during
memory array, status register, query, and identifier code read cycles. Data pins float to
high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle.
DQ8-DQ15 : Inputs data during CUI write cycles in x16 mode; outputs data during
memory array read cycles in x16 mode; not used for status register, query and identifier
code read mode. Data pins float to high-impedance when the chip is deselected, outputs
are disabled, or in x8 mode (BYTE# = VIL). Data is internally latched during a write cycle.
BANK ENABLE : Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. When BE0# and BE1L# "low", bank0 is in active. When BE0# and BE1H# are
"low", bank1 is in active. BE0# and BE1L#, BE1H# must not be low at the same time.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP# VIH enables normal operation. When driven VIL, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OUTPUT ENABLE : Gates the device’s outputs during a read cycle.
WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#) : Indicates the status of the internal WSM. When configured in level
mode (default mode) , it acts as a RY/BY# pin. When low, the WSM is performing an
internal operation (block erase, bank erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
ease is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of
the STATUS pin, see the Configuration command (Table 3 and Section 4.14).
WRITE PROTECT : Master control for block locking. When VIL, locked blocks can not
be erased and programmed, and block lock-bits can not be set and reset.
BYTE ENABLE : BYTE# VIL places device in x8 mode. All data are then input or output
on DQ0-7, and DQ8-15 float. BYTE# VIH places the device in x16 mode, and turns off the
A0 input buffer.
BLOCK ERASE, BANK ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-BIT
CONFIGURATION POWER SUPPLY : For erasing array blocks, writing bytes or
configuring block lock-bits. With VPP ≤ VPPLK, memory contents cannot be altered. Block
erase, bank erase, word/byte write, and block lock-bit configuration with an invalid VPP
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V or 3.3 V
operation. To switch from one voltage to another, ramp VCC down to GND and then ramp
VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write attempts
to the flash memory are inhibited. Device operations at invalid VCC voltage (see Section
6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted.
GROUND : Do not float any ground pins.
NO CONNECT : Lead is not internal connected; recommend to be floated.
-4-
LH28F320S3TD-L10
1 INTRODUCTION
This datasheet contains LH28F320S3TD-L10
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the memory
organization and functionality. Section 6 covers
electrical specifications. The LH28F320S3TD-L10
flash memory documentation also includes ordering
information which is referenced in Section 7.
1.1
A block erase operation erases one of the device’s
64 k-byte blocks typically within 0.41 second (3.3 V
VCC, 5 V VPP) independent of other blocks. Each
block can be independently erased 100 000 times
(3.2 million block erases per bank). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.
Product Overview
The LH28F320S3TD-L10 is a high-performance
32 M-bit Smart 3 Dual Work flash memory
organized as 2 MB x8/1 MB x 16 x 2-Bank. The
4 MB of data is arranged in sixty-four 64 k-byte
blocks which are individually erasable, lockable,
and unlockable in-system. The memory map is
shown in Fig. 1.
A word/byte write is performed in byte increments
typically within 12.95 µs (3.3 V VCC, 5 V VPP). A
multi word/byte write has high speed write
performance of 2.7 µs/byte (3.3 V VCC, 5 V VPP).
(Multi) word/byte write suspend mode enables the
system to read data from, or write data to any other
flash memory array location.
Smart 3 technology provides a choice of VCC and
VPP combinations, as shown in Table 1, to meet
system performance and power expectations. VPP
at 2.7 V, 3.3 V and 5 V eliminates the need for a
separate 12 V converter. In addition to flexible
erase and program voltages, the dedicated VPP pin
gives complete data protection when VPP ≤ VPPLK.
Individual block locking uses a combination of bits
and WP#, sixty-four block lock-bits per bank, to lock
and unlock blocks. Block lock-bits gate block erase,
bank erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.
Table 1 VCC and VPP Voltage Combinations
Offered by Smart 3 Technology
VCC VOLTAGE
VPP VOLTAGE
2.7 V
2.7 V, 3.3 V, 5 V
The status register indicates when the WSM’s block
erase, bank erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
3.3 V
3.3 V, 5 V
Internal VCC and VPP detection circuitry automatically configures the device for optimized read
and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, bank erase, (multi) word/byte write and
block lock-bit configuration operations.
-5-
The STS output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using STS
minimizes both CPU overhead and system power
consumption. STS pin can be configured to
different states using the Configuration command.
The STS pin defaults to RY/BY# operation. When
low, STS indicates that the WSM is performing a
block erase, bank erase, (multi) word/byte write or
block lock-bit configuration. STS High Z indicates
that the WSM is ready for a new command, block
erase is suspended and (multi) word/byte write are
LH28F320S3TD-L10
inactive, (multi) word/byte write are suspended, or
the device is in deep power-down mode. The other
3 alternate configurations are all pulse mode for
use as a system interrupt.
The access time is 100 ns (tAVQV) at the VCC
supply voltage range of 3.0 to 3.6 V over the
temperature range, 0 to +70°C. At 2.7 to 3.6 V
VCC, the access time is 120 ns.
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 3 mA at
2.7 V and 3.3 V VCC.
-6-
When either BE0# or BE1L#, BE1H# and RP# pins
are at VCC, the ICC CMOS standby mode is
enabled. When the RP# pin is at GND, deep
power-down mode is enabled which minimizes
power consumption and provides write protection
during reset. A reset time (tPHQV) is required from
RP# switching high until outputs are valid. Likewise,
the device has a wake time (tPHEL) from RP#-high
until writes to the CUI are recognized. With RP# at
GND, the WSM is reset and the status register is
cleared.
LH28F320S3TD-L10
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
64 k-Byte Block
31
64 k-Byte Block
30
64 k-Byte Block
29
64 k-Byte Block
28
64 k-Byte Block
27
64 k-Byte Block
26
64 k-Byte Block
25
64 k-Byte Block
24
64 k-Byte Block
23
64 k-Byte Block
22
64 k-Byte Block
21
64 k-Byte Block
20
64 k-Byte Block
19
64 k-Byte Block
18
64 k-Byte Block
17
64 k-Byte Block
16
64 k-Byte Block
15
64 k-Byte Block
14
64 k-Byte Block
13
64 k-Byte Block
12
64 k-Byte Block
11
64 k-Byte Block
10
64 k-Byte Block
9
64 k-Byte Block
8
64 k-Byte Block
7
64 k-Byte Block
6
64 k-Byte Block
5
64 k-Byte Block
4
64 k-Byte Block
3
64 k-Byte Block
2
64 k-Byte Block
1
64 k-Byte Block
0
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
64 k-Byte Block
31
64 k-Byte Block
30
64 k-Byte Block
29
64 k-Byte Block
28
64 k-Byte Block
27
64 k-Byte Block
26
64 k-Byte Block
25
64 k-Byte Block
24
64 k-Byte Block
23
64 k-Byte Block
22
64 k-Byte Block
21
64 k-Byte Block
20
64 k-Byte Block
19
64 k-Byte Block
18
64 k-Byte Block
17
64 k-Byte Block
16
64 k-Byte Block
15
64 k-Byte Block
14
64 k-Byte Block
13
64 k-Byte Block
12
64 k-Byte Block
11
64 k-Byte Block
10
64 k-Byte Block
9
64 k-Byte Block
8
64 k-Byte Block
7
64 k-Byte Block
6
64 k-Byte Block
5
64 k-Byte Block
4
64 k-Byte Block
3
64 k-Byte Block
2
64 k-Byte Block
1
64 k-Byte Block
0
Bank1
(BE0# = BE1H# = "L")
Bank0
(BE0# = BE1L# = "L")
Fig. 1 Memory Map
-7-
LH28F320S3TD-L10
2 PRINCIPLES OF OPERATION
The LH28F320S3TD-L10 Smart 3 Dual Work flash
memory includes an on-chip WSM to manage
block erase, bank erase, (multi) word/byte write and
block lock-bit configuration functions. It allows for :
100% TTL-level control inputs, fixed power supplies
during block erase, bank erase, (multi) word/byte
write and block lock-bit configuration, and minimal
processor overhead with RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see Table 2.1 and Table 2.2
"Bus Operations"), the device defaults to read
array mode. Manipulation of external memory
control pins allow array read, standby, and output
disable operations.
Status register, query structure and identifier codes
can be accessed through the CUI independent of
the VPP voltage. High voltage on VPP enables
successful block erase, bank erase, (multi)
word/byte write and block lock-bit configuration. All
functions associated with altering memory
contents—lock erase, bank erase, (multi) word/byte
write and block lock-bit configuration, status, query
and identifier codes—are accessed via the CUI and
verified through the status register.
Commands are written using standard microprocessor write timings. The CUI contents serve as
input to the WSM, which controls the block erase,
bank erase, (multi) word/byte write and block lockbit configuration. The internal algorithms are
regulated by the WSM, including pulse repetition,
internal verification, and margining of data.
Addresses and data are internally latched during
write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes,
outputs query structure or outputs status register
data.
-8-
Interface software that initiates and polls progress
of block erase, bank erase, (multi) word/byte write
and block lock-bit configuration can be stored in
any block. This code is copied to and executed
from system RAM during flash memory updates.
After successful completion, reads are again
possible via the Read Array command. Block erase
suspend allows system software to suspend a
block erase to read/write data from/to blocks other
than that which is suspended. Write suspend allows
system software to suspend a (multi) word/byte
write to read data from any other flash memory
array location.
2.1
Data Protection
Depending on the application, the system designer
may choose to make the VPP power supply
switchable (available only when block erase, bank
erase, (multi) word/byte write and block lock-bit
configuration are required) or hardwired to
VPPH1/2/3. The device accommodates either design
practice and encourages optimization of the
processor-memory interface.
When VPP ≤ VPPLK, memory contents cannot be
altered. The CUI, with multi-step block erase, bank
erase, (multi) word/byte write and block lock-bit
configuration command sequences, provides
protection from unwanted operations even when
high voltage is applied to VPP. All write functions
are disabled when VCC is below the write lockout
voltage VLKO or when RP# is at VIL. The device’s
block locking capability provides additional
protection from inadvertent code or data alteration
by gating block erase, bank erase and (multi)
word/byte write operations.
LH28F320S3TD-L10
3 BUS OPERATION
The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1
Read
Information can be read from any block, identifier
codes, query structure, or status register
independent of the VPP voltage. RP# must be at
VIH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes,
Query or Read Status Register) to the CUI. Upon
initial device power-up or after exit from deep
power-down mode, the device automatically resets
to read array mode. Five control pins dictate the
data flow in and out of the component : BE# (BE0#,
BE1L#, BE1H#), OE#, WE#, RP# and WP#. BE0#,
BE1L#, BE1H# and OE# must be driven active to
obtain data at the outputs. BE0#, BE1L#, BE1H# is
the device selection control, and when active
enables the selected memory device. OE# is the
data output (DQ0-DQ15) control and when active
drives the selected memory data onto the I/O bus.
WE# and RP# must be at VIH. Fig. 15 and Fig. 16
illustrate a read cycle.
3.2
Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0-DQ15 are
placed in a high-impedance state.
3.3
Standby
Either BE0# or BE1L#, BE1H# at a logic-high level
(VIH) places the device in standby mode which
substantially reduces device power consumption.
DQ0-DQ15 outputs are placed in a high-impedance
state independent of OE#. If deselected during
block erase, bank erase, (multi) word/byte write and
block lock-bit configuration, the device continues
functioning, and consuming active power until the
operation completes.
-9-
3.4
Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time tPHQV is required
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.
During block erase, bank erase, (multi) word/byte
write or block lock-bit configuration modes, RP#-low
will abort the operation. STS remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be
partially erased or written. Time tPHWL is required
after RP# goes to logic-high (VIH) before another
command can be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
bank erase, (multi) word/byte write and block lockbit configuration. If a CPU reset occurs with no
flash memory reset, proper CPU initialization may
not occur because the flash memory may be
providing status information instead of array data.
SHARP’s flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets
the system CPU.
LH28F320S3TD-L10
3.5
Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacture code, device code, block status codes
for each block (see Fig. 2). Using the manufacture
and device codes, the system CPU can
1FFFFF
automatically match the device with its proper
algorithms. The block status codes identify locked
or unlocked block setting and erase completed or
erase uncompleted condition.
1FFFFF
Reserved for
Future Implementation
1F0006
1F0005
1F0004
1F0003
Reserved for
Future Implementation
1F0006
1F0005
1F0004
1F0003
Block 31 Status Code
Reserved for
Future Implementation
1F0000
1EFFFF
Block 31
Block 31 Status Code
Reserved for
Future Implementation
1F0000
1EFFFF
(Blocks 2 through 30)
(Blocks 2 through 30)
020000
01FFFF
020000
01FFFF
Reserved for
Future Implementation
Reserved for
Future Implementation
010006
010005
010004
010003
010000
00FFFF
010006
010005
010004
010003
Block 1 Status Code
Reserved for
Future Implementation
Block 1
Block 1 Status Code
Reserved for
Future Implementation
010000
00FFFF
Reserved for
Future Implementation
000006
000005
000004
000003
000002
000001
000000
Block 31
Reserved for
Future Implementation
Block 0 Status Code
Device Code
Manufacture Code
Block 1
Block 0
000006
000005
000004
000003
000002
000001
000000
Block 0 Status Code
Device Code
Manufacture Code
Bank0
(BE0# = BE1L# = "L")
Block 0
Bank1
(BE0# = BE1H# = "L")
Fig. 2 Device Identifier Code Memory Map
3.6
Query Operation
3.7
The query operation outputs the query structure.
Query database is stored in the 48-byte ROM per
bank. Query structure allows system software to
gain critical information for controlling the flash
component. Query structures are always presented
on the lowest-order data output (DQ0-DQ7) only.
Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
VCC = VCC1/2 and VPP = VPPH1/2/3, the CUI
additionally controls block erase, bank erase, (multi)
word/byte write and block lock-bit configuration.
- 10 -
LH28F320S3TD-L10
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word/Byte Write command requires
the command and address of the location to be
written. Set Block Lock-Bit command requires the
command and block address within the device
(Block Lock) to be locked. The Clear Block LockBits command requires the command and address
within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and BE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
MODE
Bank0
Read
Bank1
Disable
Output Disable
Bank0
Standby
Bank1
Bank0, 1
Deep Power-Down
Bank0
Read
Bank1
Identifier
Disable
Codes
Query
Write
Bank0
Bank1
Bank0, 1
BE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 17 and
Fig. 18 illustrate WE# and BE#-controlled write
operations.
4 COMMAND DEFINITIONS
When the VPP voltage VPPLK, read operations from
the status register, identifier codes, query, or blocks
are enabled. Placing VPPH1/2/3 on VPP enables
successful block erase, bank erase, (multi)
word/byte write and block lock-bit configuration
operations. Device operations are selected by
writing specific commands into the CUI. Table 3
defines these commands.
3
Table 2.1 Bus Operations (BYTE# = VIH)
RP#
BE0# BE1L# BE1H# OE#
WE# ADDRESS
VIL
VIL
VIH
VIH
VIL
VIH
VIL
VIL
VIH
X
VIL
VIL
VIL
VIH
VIL
VIL
VIL
VIH
VIH
X
3
VIH
4
VIL
9, 10
VIH
9, 10
3, 7,
8, 9
NOTE
1, 2, 3,
9, 10
VIH
VIL
X
VIH
X
VIH
X
VIL
VIL
VIL
X
VIL
VIH
VIL
X
VIH
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIL
VIL
VIH
VIL
VPP
DQ0-15
STS
X
DOUT
X
X
High Z
X
X
X
X
X
X
High Z
X
X
X
X
High Z High Z
VIL
VIH
See
Fig. 2
X
(NOTE 5) High Z
VIL
VIL
VIH
See Table
6 through 10
X
(NOTE 6) High Z
VIH
VIL
VIL
VIH
VIL
X
X
DIN
X
NOTES :
1.
2.
3.
Refer to Section 6.2.3 "DC CHARACTERISTICS".
When VPP ≤ VPPLK, memory contents can be read, but
not altered.
X can be VIL or VIH for control pins and addresses, and
VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC
CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages.
STS is VOL (if configured to RY/BY# mode) when the
WSM is executing internal block erase, bank erase,
(multi) word/byte write or block lock-configuration
algorithms. It is floated during when the WSM is not
busy, in block erase suspend mode with (multi)
word/byte write inactive, (multi) word/byte write suspend
mode, or deep power-down mode.
4.
RP# at GND±0.2 V ensures the lowest deep powerdown current.
5. See Section 4.2 for read identifier code data.
6. See Section 4.5 for query data.
7. Command writes involving block erase, bank erase,
(multi) word/byte write or block lock-bit configuration are
reliably executed when VPP = VPPH1/2/3 and VCC =
VCC1/2.
8. Refer to Table 3 for valid DIN during a write operation.
9. Don’t use the timing both OE# and WE# are VIL.
10. Impossible to perform simultaneous read from both
banks at a time. Both BE0# and BE1L#, BE1H# must not
be low at the same time.
- 11 -
LH28F320S3TD-L10
Table 2.2 Bus Operations (BYTE# = VIL)
MODE
Read
Bank0
Bank1
Disable
Output Disable
NOTE
RP#
BE0#
OE#
WE#
ADDRESS
VPP
DQ0-7
STS
VIH
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIH
X
X
DOUT
X
3
VIH
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
X
X
High Z
X
3
VIH
VIH
VIL
X
VIH
X
VIH
X
X
X
X
High Z
X
4
VIL
X
VIL
X
X
X
X
X
X
High Z High Z
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
X
(NOTE 5) High Z
VIL
VIL
VIL
VIL
VIL
VIL
VIH
X
(NOTE 6) High Z
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIH
VIL
VIL
VIL
1, 2, 3,
9, 10
Bank0
Standby
Bank1
Bank0, 1
Deep Power-Down
Bank0
Read
Identifier
Codes
Bank1
Disable
Query
9, 10
Bank0
Write
9, 10
Bank1
Bank0, 1
3, 7,
8, 9
VIH
VIH
VIH
BE1L# BE1H#
See
Fig. 2
See Table
6 through 10
X
X
DIN
X
NOTES :
1.
2.
3.
Refer to Section 6.2.3 "DC CHARACTERISTICS".
When VPP ≤ VPPLK, memory contents can be read, but
not altered.
X can be VIL or VIH for control pins and addresses, and
VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC
CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages.
STS is VOL (if configured to RY/BY# mode) when the
WSM is executing internal block erase, bank erase,
(multi) word/byte write or block lock-configuration
algorithms. It is floated during when the WSM is not
busy, in block erase suspend mode with (multi)
word/byte write inactive, (multi) word/byte write suspend
mode, or deep power-down mode.
4.
RP# at GND±0.2 V ensures the lowest deep powerdown current.
5. See Section 4.2 for read identifier code data.
6. See Section 4.5 for query data.
7. Command writes involving block erase, bank erase,
(multi) word/byte write or block lock-bit configuration are
reliably executed when VPP = VPPH1/2/3 and VCC =
VCC1/2.
8. Refer to Table 3 for valid DIN during a write operation.
9. Don’t use the timing both OE# and WE# are VIL.
10. Impossible to perform simultaneous read from both
banks at a time. Both BE0# and BE1L#, BE1H# must not
be low at the same time.
- 12 -
LH28F320S3TD-L10
Table 3 Command Definitions (NOTE 10)
FIRST BUS CYCLE
SECOND BUS CYCLE
BUS CYCLES
COMMAND
NOTE
REQ’D.
Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3)
Read Array/Reset
1
Write
X
FFH
Read Identifier Codes
≥2
4
Write
X
90H
Read
IA
ID
Query
≥2
Write
X
98H
Read
QA
QD
Read Status Register
2
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
Block Erase Setup/Confirm
2
5
Write
BA
20H
Write
BA
D0H
Bank Erase Setup/Confirm
2
Write
X
30H
Write
X
D0H
Word/Byte Write Setup/Write
2
5, 6
Write
WA
40H
Write
WA
WD
Alternate Word/Byte Write
2
5, 6
Write
WA
10H
Write
WA
WD
Setup/Write
Multi Word/Byte Write
≥4
9
Write
WA
E8H
Write
WA
N–1
Setup/Confirm
Block Erase and (Multi)
1
5
Write
X
B0H
Word/Byte Write Suspend
Confirm and Block Erase and
1
5
Write
X
D0H
(Multi) Word/Byte Write Resume
Block Lock-Bit Set
2
7
Write
BA
60H
Write
BA
01H
Setup/Confirm
Block Lock-Bit Reset
2
8
Write
X
60H
Write
X
D0H
Setup/Confirm
STS Configuration
Level-Mode for Erase
2
Write
X
B8H
Write
X
00H
and Write (RY/BY# Mode)
STS Configuration
2
Write
X
B8H
Write
X
01H
Pulse-Mode for Erase
STS Configuration
2
Write
X
B8H
Write
X
02H
Pulse-Mode for Write
STS Configuration Pulse-Mode
2
Write
X
B8H
Write
X
03H
for Erase and Write
NOTES :
1.
2.
3.
4.
BUS operations are defined in Table 2.1 and Table 2.2.
X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
QA = Query offset address.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
SRD = Data read from status register. See Table 13.1
for a description of the status register bits.
WD = Data to be written at location WA. Data is latched
on the rising edge of WE# or BE# (whichever
goes high first).
ID = Data read from identifier codes.
QD = Data read from query database.
Following the Read Identifier Codes command, read
operations access manufacture, device and block status
codes. See Section 4.2 for read identifier code data.
5.
If the block is locked, WP# must be at VIH to enable
block erase or (multi) word/byte write operations.
Attempts to issue a block erase or (multi) word/byte write
to a locked block while RP# is VIH.
6. Either 40H or 10H is recognized by the WSM as the
byte write setup.
7. A block lock-bit can be set while WP# is VIH.
8. WP# must be at VIH to clear block lock-bits. The clear
block lock-bits operation simultaneously clears all block
lock-bits.
9. Following the Third Bus Cycle, inputs the write address
and write data of "N" times. Finally, input the confirm
command "D0H".
10. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.
- 13 -
LH28F320S3TD-L10
4.1
NOTE :
Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, bank erase, (multi) word/byte write or
block lock-bit configuration, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is
suspended via an Erase Suspend and (Multi)
Word/Byte Write Suspend command. The Read
Array command functions independently of the VPP
voltage and RP# must be VIH.
4.2
Read Identifier Codes Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture, device, block
lock configuration and block erase status (see
Table 4 for identifier code values). To terminate the
operation, write another valid command. Like the
Read Array command, the Read Identifier Codes
command functions independently of the VPP
voltage and RP# must be VIH. Following the Read
Identifier Codes command, the following information
can be read :
Table 4 Identifier Codes
CODE
ADDRESS
00000H
Manufacture Code
00001H
00002H
Device Code
00003H
X0004H (NOTE 1)
Block Status Code
X0005H (NOTE 1)
• Block is Unlocked
• Block is Locked
• Last erase operation
completed successfully
• Last erase operation did
not completed successfully
• Reserved for Future Use
DATA
B0
1.
X selects the specific block status code to be read. See
Fig. 2 for the device identifier code memory map.
4.3
Read Status Register Command
The status register may be read to determine when
a block erase, bank erase, (multi) word/byte write
or block lock-bit configuration is complete and
whether the operation completed successfully (see
Table 13.1). It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
BE0# or BE1# (Either BE1L# or BE1H#), whichever
occurs. OE# or BE0# or BE1# (Either BE1L# or
BE1H#) must toggle to VIH before further reads to
update the status register latch. The Read Status
Register command functions independently of the
VPP voltage. RP# must be VIH.
The extended status register may be read to
determine multi byte write availability (see Table
13.2). The extended status register may be read at
any time by writing the Multi Byte Write command.
After writing this command, all subsequent read
operations output data from the extended status
register, until another valid command is written. The
contents of the extended status register are latched
on the falling edge of OE# or BE0# or BE1# (Either
BE1L# or BE1H#), whichever occurs last in the read
cycle. Multi Byte Write command must be re-issued
to update the extended status register latch.
D0
4.4
DQ0 = 0
DQ0 = 1
DQ1 = 0
DQ1 = 1
DQ2-7
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 13.1).
By allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
- 14 -
LH28F320S3TD-L10
sequence) may be performed. The status register
may be polled to determine if an error occurs
during the sequence.
assigned to any information or reserved for future
use are set to "0". This command functions
independently of the VPP voltage. RP# must be VIH.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied VPP voltage. RP#
must be VIH. This command is not functional during
block erase, bank erase, (multi) word/byte write,
block lock-bit configuration, block erase suspend or
(multi) word/byte write suspend modes.
Table 5 Example of Query Structure Output
4.5
MODE
Query data of each bank are always presented on
the low-byte data output (DQ0-DQ7). In x16 mode,
high-byte (DQ8-DQ15) outputs 00H. The bytes not
DQ15-8
DQ7-0
x8 mode
1, 0, 0, 0, 0, 0 (20H)
1, 0, 0, 0, 0, 1 (21H)
High Z
High Z
"Q"
"Q"
1, 0, 0, 0, 1, 0 (22H)
High Z
"R"
1, 0, 0, 0, 1, 1 (23H)
A5, A4, A3, A2, A1
High Z
"R"
x16 mode
1, 0, 0, 0, 0 (10H)
1, 0, 0, 0, 1 (11H)
00H
00H
"Q"
"R"
4.5.1 BLOCK STATUS REGISTER
This field provides lock configuration and erase
status for the specified block. These informations
are only available when device is ready (SR.7 = 1).
If block erase or bank erase operation is finished
irregularly, block erase status bit will be set to "1". If
bit 1 is "1", this block is invalid.
Table 6 Query Block Status Register
OFFSET
(Word Address)
(BA+2)H
LENGTH
01H
DESCRIPTION
Block Status Register
bit0 Block Lock Configuration
0 = Block is unlocked
1 = Block is locked
bit1 Block Erase Status
0 = Last erase operation completed successfully
1 = Last erase operation not completed successfully
bit2-7 Reserved for future use
NOTE :
1.
OUTPUT
A5, A4, A3, A2, A1, A0
Query Command
Query database of each bank can be read by
writing Query command (98H). Following the
command write, read cycle from address shown in
Table 6 through Table 10 retrieve the critical
information to write, erase and otherwise control the
flash component. A0 of query offset address is
ignored when x8 mode (BYTE# = VIL).
OFFSET ADDRESS
BA = The beginning of a Block Address.
- 15 -
LH28F320S3TD-L10
4.5.2 CFI QUERY IDENTIFICATION STRING
The identification string provides verification that the
component supports the Common Flash Interface
specification. Additionally, it indicates which version
of the spec and which vendor-specified command
set(s) is(are) supported.
Table 7 CFI Query Identification String
OFFSET
(Word Address)
10H, 11H, 12H
LENGTH
03H
13H, 14H
02H
15H, 16H
02H
17H, 18H
02H
19H, 1AH
02H
DESCRIPTION
Query Unique ASCII string "QRY"
51H, 52H, 59H
Primary Vendor Command Set and Control Interface ID Code
01H, 00H (SCS ID Code)
Address for Primary Algorithm Extended Query Table
31H, 00H (SCS Extended Query Table Offset)
Alternate Vendor Command Set and Control Interface ID Code
0000H (0000H means that no alternate exists)
Address for Alternate Algorithm Extended Query Table
0000H (0000H means that no alternate exists)
4.5.3 SYSTEM INTERFACE INFORMATION
The following device information can be useful in optimizing system interface software.
Table 8 System Information String
OFFSET
(Word Address)
1BH
LENGTH
01H
1CH
01H
1DH
01H
1EH
01H
1FH
01H
20H
01H
21H
01H
22H
01H
23H
01H
24H
01H
25H
01H
26H
01H
DESCRIPTION
VCC Logic Supply Minimum Write/Erase voltage
27H (2.7 V)
VCC Logic Supply Maximum Write/Erase voltage
55H (5.5 V)
VPP Programming Supply Minimum Write/Erase voltage
27H (2.7 V)
VPP Programming Supply Maximum Write/Erase voltage
55H (5.5 V)
Typical Time-Out per Single Byte/Word Write
03H (23 = 8 µs)
Typical Time-Out for Maximum Size Buffer Write (32 Bytes)
06H (26 = 64 µs)
Typical Time-Out per Individual Block Erase
0AH (0AH = 10, 210 = 1 024 ms)
Typical Time-Out for Bank Erase
0FH (0FH = 15, 215 = 32 768 ms)
Maximum Time-Out per Single Byte/Word Write, 2N times of typical.
04H (24 = 16, 8 µs x 16 = 128 µs)
Maximum Time-Out per Maximum Size Buffer Write, 2N times of typical.
04H (24 = 16, 64 µs x 16 = 1 024 µs)
Maximum Time-Out per Individual Block Erase, 2N times of typical.
04H (24 = 16, 1 024 ms x 16 = 16 384 ms)
Maximum Time-Out for Bank Erase, 2N times of typical.
04H (24 = 16, 32 768 ms x 16 = 524 288 ms)
- 16 -
LH28F320S3TD-L10
4.5.4 DEVICE GEOMETRY DEFINITION
This field provides critical details of the flash device geometry.
Table 9 Device Geometry Definition
OFFSET
(Word Address)
27H
LENGTH
DESCRIPTION
01H
Device Size
28H, 29H
02H
15H (15H = 21, 221 = 2 097 152 = 2 M Bytes)
Flash Device Interface Description
2AH, 2BH
02H
02H, 00H (x8/x16 supports x8 and x16 via BYTE#)
Maximum Number of Bytes in Multi Word/Byte Write
05H, 00H (25 = 32 Bytes )
2CH
01H
Number of Erase Block Regions within Device
01H (symmetrically blocked)
2DH, 2EH
02H
The Number of Erase Blocks
1FH, 00H (1FH = 31 ⇒ 31 + 1 = 32 Blocks)
2FH, 30H
02H
The Number of "256 Bytes" Cluster in a Erase Block
00H, 01H (0100H = 256 ⇒ 256 Bytes x 256 = 64 k Bytes in a Erase Block)
- 17 -
LH28F320S3TD-L10
4.5.5 SCS OEM SPECIFIC EXTENDED QUERY
TABLE
Certain flash features and commands may be
optional in a vendor-specific algorithm specification.
The optional vendor-specific query table(s) may be
used to specify this and other types of information.
These structures are defined solely by the flash
vendor(s).
Table 10 SCS OEM Specific Extended Query Table
OFFSET
(Word Address)
31H, 32H, 33H
LENGTH
DESCRIPTION
03H
PRI
34H
01H
50H, 52H, 49H
31H (1) Major Version Number , ASCII
35H
36H, 37H,
01H
04H
30H (0) Minor Version Number, ASCII
0FH, 00H, 00H, 00H
38H, 39H
Optional Command Support
bit0 = 1 : Bank Erase Supported
bit1 = 1 : Suspend Erase Supported
bit2 = 1 : Suspend Write Supported
bit3 = 1 : Lock/Unlock Supported
bit4 = 0 : Queued Erase Not Supported
bit5-31 = 0 : Reserved for future use
3AH
01H
01H
Supported Functions after Suspend
bit0 = 1 : Write Supported after Erase Suspend
3BH, 3CH
02H
bit1-7 = 0 : Reserved for future use
03H, 00H
Block Status Register Mask
bit0 = 1 : Block Status Register Lock Bit [BSR.0] active
bit1 = 1 : Block Status Register Valid Bit [BSR.1] active
3DH
01H
bit2-15 = 0 : Reserved for future use
VCC Logic Supply Optimum Write/Erase voltage (highest performance)
50H (5.0 V)
3EH
01H
3FH
reserved
VPP Programming Supply Optimum Write/Erase voltage (highest performance)
50H (5.0 V)
Reserved for future versions of the SCS specification
- 18 -
LH28F320S3TD-L10
4.6
Block Erase Command
4.7
Bank Erase Command
Block erase is executed one block at a time and
initiated by a two-cycle command. A block erase
setup is first written, followed by a block erase
confirm. This command sequence requires
appropriate sequencing and an address within the
block to be erased (erase changes all block data to
FFH). Block preconditioning, erase and verify are
handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence
is written, the device automatically outputs status
register data when read (see Fig. 3). The CPU can
detect block erase completion by analyzing the
output data of the STS pin or status register bit
SR.7.
This command followed by a confirm command
(D0H) erases all of the unlocked blocks. A bank
erase setup is first written, followed by a bank
erase confirm. After a confirm command is written,
device erases the all unlocked blocks from block 0
to block 31 block by block. This command
sequence requires appropriate sequencing. Block
preconditioning, erase and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle bank erase sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect bank
erase completion by analyzing the output data of
the STS pin or status register bit SR.7.
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
When the bank erase is complete, status register
bit SR.5 should be checked. If erase error is
detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued. If error is detected on a
block during bank erase operation, WSM stops
erasing. Reading the block valid status by issuing
Read ID Codes command or Query command
informs which blocks failed to its erase.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when VCC =
VCC1/2 and VPP = VPPH1/2/3. In the absence of this
high voltage, block contents are protected against
erasure. If block erase is attempted while VPP ≤
VPPLK, SR.3 and SR.5 will be set to "1". Successful
block erase requires that the corresponding block
lock-bit be cleared or if set, that WP# = VIH. If block
erase is attempted when the corresponding block
lock-bit is set and WP# = VIL, SR.1 and SR.5 will
be set to "1".
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Bank Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable bank erasure can only occur when VCC =
VCC1/2 and VPP = VPPH1/2/3. In the absence of this
high voltage, block contents are protected against
erasure. If bank erase is attempted while VPP ≤
VPPLK, SR.3 and SR.5 will be set to "1". When
WP# = VIH, all blocks are erased independent of
block lock-bits status. When WP# = VIL, only
unlocked blocks are erased. In this case, SR.1 and
SR.4 will not be set to "1". Bank erase can not be
suspended.
- 19 -
LH28F320S3TD-L10
4.8
Word/Byte Write Command
Word/byte write is executed by a two-cycle
command sequence. Word/Byte Write setup
(standard 40H or alternate 10H) is written, followed
by a second write that specifies the address and
data (latched on the rising edge of WE#). The
WSM then takes over, controlling the word/byte
write and write verify algorithms internally. After the
word/byte write sequence is written, the device
automatically outputs status register data when
read (see Fig. 5). The CPU can detect the
completion of the word/byte write event by
analyzing the STS pin or status register bit SR.7.
When word/byte write is complete, status register
bit SR.4 should be checked. If word/byte write error
is detected, the status register should be cleared.
The internal WSM verify only detects errors for "1"s
that do not successfully write to "0"s. The CUI
remains in read status register mode until it
receives another command.
Reliable word/byte writes can only occur when VCC
= VCC1/2 and VPP = VPPH1/2/3. In the absence of
this high voltage, memory contents are protected
against word/byte writes. If word/byte write is
attempted while VPP ≤ VPPLK, status register bits
SR.3 and SR.4 will be set to "1". Successful
word/byte write requires that the corresponding
block lock-bit be cleared or, if set, that WP# = VIH.
If word/byte write is attempted when the
corresponding block lock-bit is set and WP# = VIL,
SR.1 and SR.4 will be set to "1". Word/byte write
operations with VIL < WP# < VIH produce spurious
results and should not be attempted.
4.9
Multi Word/Byte Write Command
Multi word/byte write is executed by at least fourcycle or up to 35-cycle command sequence. Up to
32 bytes in x8 mode (16 words in x16 mode) can
be loaded into the buffer and written to the flash
array. First, multi word/byte write setup (E8H) is
written with the write address. At this point, the
device automatically outputs extended status
register data (XSR) when read (see Fig. 6 and
Fig. 7). If extended status register bit XSR.7 is 0,
no Multi Word/Byte Write command is available and
multi word/byte write setup which just has been
written is ignored. To retry, continue monitoring
XSR.7 by writing multi word/byte write setup with
write address until XSR.7 transitions to "1". When
XSR.7 transitions to "1", the device is ready for
loading the data to the buffer. A word/byte count
(N)–1 is written with write address. After writing a
word/byte count (N)–1, the device automatically
turns back to output status register data. The
word/byte count (N)–1 must be less than or equal
to 1FH in x8 mode (0FH in x16 mode). On the next
write, device start address is written with buffer
data. Subsequent writes provide additional device
address and data, depending on the count. All
subsequent address must lie within the start
address plus the count. After the final buffer data is
written, write confirm (D0H) must be written. This
initiates WSM to begin copying the buffer data to
the flash array. An invalid Multi Word/Byte Write
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". For
additional multi word/byte write, write another multi
word/byte write setup and check XSR.7. The Multi
Word/Byte Write command can be queued while
WSM is busy as long as XSR.7 indicates "1",
because LH28F320S3TD-L10 has two buffers. If an
error occurs while writing, the device will stop
writing and flush next Multi Word/Byte Write
command loaded in Multi Word/Byte Write
command. Status register bit SR.4 will be set to "1".
No Multi Word/Byte Write command is available if
either SR.4 or SR.5 is set to "1". SR.4 and SR.5
should be cleared before issuing Multi Word/Byte
Write command. If a Multi Word/Byte Write
command is attempted past an erase block
boundary, the device will write the data to flash
array up to an erase block boundary and then stop
writing. Status register bits SR.4 and SR.5 will be
set to "1".
- 20 -
LH28F320S3TD-L10
Reliable multi byte writes can only occur when VCC
= VCC1/2 and VPP = VPPH1/2/3. In the absence of
this high voltage, memory contents are protected
against multi word/byte writes. If multi word/byte
write is attempted while VPP ≤ VPPLK, status
register bits SR.3 and SR.4 will be set to "1".
Successful multi word/byte write requires that the
corresponding block lock-bit be cleared or, if set,
that WP# = VIH. If multi byte write is attempted
when the corresponding block lock-bit is set and
WP# = VIL, SR.1 and SR.4 will be set to "1".
4.10 Block Erase Suspend Command
The Block Erase Suspend command allows block
erase interruption to read or (multi) word/byte write
data in another block of memory. Once the block
erase process starts, writing the Block Erase
Suspend command requests that the WSM
suspend the block erase sequence at a
predetermined point in the algorithm. The device
outputs status register data when read after the
Block Erase Suspend command is written. Polling
status register bits SR.7 and SR.6 can determine
when the block erase operation has been
suspended (both will be set to "1"). STS will also
transition to High Z. Specification tWHRH2 defines
the block erase suspend latency.
At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A (Multi) Word/Byte Write
command sequence can also be issued during
erase suspend to program data in other blocks.
Using the (Multi) Word/Byte Write Suspend
command (see Section 4.11), a (multi) word/byte
write operation can also be suspended. During a
(multi) word/byte write operation with block erase
suspended, status register bit SR.7 will return to "0"
and the STS (if set to RY/BY#) output will transition
to VOL. However, SR.6 will remain "1" to indicate
block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and STS will return to VOL. After the Erase Resume
command is written, the device automatically
outputs status register data when read (see Fig. 8).
VPP must remain at VPPH1/2/3 (the same VPP level
used for block erase) while block erase is
suspended. RP# must also remain at VIH. Block
erase cannot resume until (multi) word/byte write
operations initiated during block erase suspend
have completed.
4.11 (Multi) Word/Byte Write Suspend
Command
The (Multi) Word/Byte Write Suspend command
allows (multi) word/byte write interruption to read
data in other flash memory locations. Once the
(multi) word/byte write process starts, writing the
(Multi) Word/Byte Write Suspend command
requests that the WSM suspend the (multi)
word/byte write sequence at a predetermined point
in the algorithm. The device continues to output
status register data when read after the (Multi)
Word/Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the (multi) word/byte write
operation has been suspended (both will be set to
"1"). STS will also transition to High Z. Specification
tWHRH1 defines the (multi) word/byte write suspend
latency.
At this point, a Read Array command can be
written to read data from locations other than that
which is suspended. The only other valid
commands while (multi) word/byte write is
suspended are Read Status Register and (Multi)
Word/Byte Write Resume. After (Multi) Word/Byte
Write Resume command is written to the flash
memory, the WSM will continue the (multi)
word/byte write process. Status register bits SR.2
- 21 -
LH28F320S3TD-L10
and SR.7 will automatically clear and STS will
return to VOL. After the (Multi) Word/Byte Write
command is written, the device automatically
outputs status register data when read (see Fig. 9).
VPP must remain at VPPH1/2/3 (the same VPP level
used for (multi) word/byte write) while in (multi)
word/byte write suspend mode. WP# must also
remain at VIH or VIL.
In the absence of this high voltage, block lock-bit
contents are protected against alteration.
A successful set block lock-bit operation requires
WP# = VIH. If it is attempted with WP# = VIL, SR.1
and SR.4 will be set to "1" and the operation will
fail. Set block lock-bit operations with WP# < VIH
produce spurious results and should not be
attempted.
4.12 Set Block Lock-Bit Command
A flexible block locking and unlocking scheme is
enabled via block lock-bits. The block lock-bits gate
program and erase operations. With WP# = VIH,
individual block lock-bits can be set using the Set
Block Lock-Bit command. See Table 12 for a
summary of hardware and software write protection
options.
4.13 Clear Block Lock-Bits Command
Set block lock-bit is executed by a two-cycle
command sequence. The set block lock-bit setup
along with appropriate block or device address is
written followed by either the set block lock-bit
confirm (and an address within the block to be
locked). The WSM then controls the set block lockbit algorithm. After the sequence is written, the
device automatically outputs status register data
when read (see Fig. 10). The CPU can detect the
completion of the set block lock-bit event by
analyzing the STS pin output or status register bit
SR.7.
Clear block lock-bits operation is executed by a
two-cycle command sequence. A clear block lockbits setup is first written. After the command is
written, the device automatically outputs status
register data when read (see Fig. 11). The CPU
can detect completion of the clear block lock-bits
event by analyzing the STS pin output or status
register bit SR.7.
When the set block lock-bit operation is complete,
status register bit SR.4 should be checked. If an
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until a new command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally set. An invalid Set Block Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations
occur only when VCC = VCC1/2 and VPP = VPPH1/2/3.
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With WP# = VIH,
block lock-bits can be cleared using only the Clear
Block Lock-Bits command. See Table 12 for a
summary of hardware and software write protection
options.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bits
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block LockBits command sequence will result in status register
bits SR.4 and SR.5 being set to "1". Also, a reliable
clear block lock-bits operation can only occur when
VCC = VCC1/2 and VPP = VPPH1/2/3. If a clear block
lock-bits operation is attempted while VPP ≤ VPPLK,
SR.3 and SR.5 will be set to "1". In the absence of
this high voltage, the block lock-bit contents are
- 22 -
LH28F320S3TD-L10
protected against alteration. A successful clear
block lock-bits operation requires WP# = VIH. If it is
attempted with WP# = VIL, SR.1 and SR.5 will be
set to "1" and the operation will fail. Clear block
lock-bits operation with VIH < RP# produce spurious
results and should not be attempted.
If a clear block lock-bits operation is aborted due to
VPP or VCC transition out of valid range or RP#
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values.
configurations are all pulse mode for use as a
system interrupt. The STS Configuration command
functions independently of the VPP voltage and
RP# must be VIH.
Table 11 STS Configuration Coding Description
CONFIGURATION
BITS
4.14 STS Configuration Command
Set STS pin to default level mode
00H
(RY/BY#). RY/BY# in the default
level-mode of operation will indicate
WSM status condition.
Set STS pin to pulsed output signal
for specific erase operation. In this
01H
The Status (STS) pin can be configured to different
states using the STS Configuration command.
Once the STS pin has been configured, it remains
in that configuration until another configuration
command is issued, the device is powered down or
RP# is set to VIL. Upon initial device power-up and
after exit from deep power-down mode, the STS
pin defaults to RY/BY# operation where STS low
indicates that the WSM is busy. STS High Z
indicates that the WSM is ready for a new
operation.
EFFECTS
mode, STS provides low pulse at the
completion of Block Erase, Bank
Erase and Clear Block Lock-Bits
operations.
Set STS pin to pulsed output signal
02H
for a specific write operation. In this
mode, STS provides low pulse at the
completion of (Multi) Byte Write and
Set Block Lock-Bit operation.
Set STS pin to pulsed output signal
for specific write and erase operation.
03H
To reconfigure the STS pin to other modes, the
STS Configuration is issued followed by the
appropriate configuration code. The three alternate
STS provides low pulse at the
completion of Block Erase, Bank
Erase, (Multi) Word/Byte Write and
Block Lock-Bit Configuration operations.
Table 12 Write Protection Alternatives
OPERATION
Block Erase or
(Multi) Word/Byte
Write
Bank Erase
BLOCK
WP#
EFFECT
LOCK-BIT
0
VIL or VIH Block Erase and (Multi) Word/Byte Write Enabled
1
0, 1
X
Set Block Lock-Bit
X
Clear Block Lock-Bits
X
VIL
Block is Locked. Block Erase and (Multi) Word/Byte Write Disabled
VIH
VIL
Block Lock-Bit Override. Block Erase and (Multi) Word/Byte Write Enabled
All unlocked blocks are erased, locked blocks are not erased
VIH
VIL
All blocks are erased
Set Block Lock-Bit Disabled
VIH
Set Block Lock-Bit Enabled
VIL
Clear Block Lock-Bits Disabled
Clear Block Lock-Bits Enabled
VIH
- 23 -
LH28F320S3TD-L10
Table 13.1 Status Register Definition
WSMS
7
BESS
6
ECBLBS
5
WSBLBS
4
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS
(ECBLBS)
1 = Error in Erase or Clear Block Lock-Bits
0 = Successful Erase or Clear Block Lock-Bits
VPPS
3
WSS
2
DPS
1
R
0
NOTES :
Check STS or SR.7 to determine block erase, bank erase,
(multi) word/byte write or block lock-bit configuration
completion.
SR.6-0 are invalid while SR.7 = "0".
If both SR.5 and SR.4 are "1"s after a block erase, bank
erase, (multi) word/byte write, block lock-bit configuration or
STS configuration attempt, an improper command sequence
was entered.
SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only after
block erase, bank erase, (multi) word/byte write or block lockbit configuration command sequences. SR.3 is not guaranteed
to reports accurate feedback only when VPP ≠ VPPH1/2/3.
SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS
(WSBLBS)
1 = Error in Write or Set Block Lock-Bit
0 = Successful Write or Set Block Lock-Bit
SR.1 does not provide a continuous indication of block lock-bit
values. The WSM interrogates block lock-bit, and WP# only
after block erase, bank erase, (multi) word/byte write or block
lock-bit configuration command sequences. It informs the
system, depending on the attempted operation, if the block
lock-bit is set and/or WP# is not VIH. Reading the block lock
configuration codes after writing the Read Identifier Codes
command indicates block lock-bit status.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = WRITE SUSPEND STATUS (WSS)
1 = Write Suspended
0 = Write in Progress/Completed
SR.0 is reserved for future use and should be masked out
when polling the status register.
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Block Lock-Bit and/or WP# Lock Detected,
Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Table 13.2 Extended Status Register Definition
SMS
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
NOTES :
XSR.7 = STATE MACHINE STATUS (SMS)
After issue a Multi Word/Byte Write command : XSR.7
indicates that a next Multi Word/Byte Write command is
available.
1 = Multi Word/Byte Write available
0 = Multi Word/Byte Write not available
XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
XSR.6-0 are reserved for future use and should be masked
out when polling the extended status register.
- 24 -
LH28F320S3TD-L10
BUS
COMMAND
OPERATION
Start
Write
Write 70H
Read
Status Register
SR.7 =
Read Status
Register
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write
Erase Setup
Data = 20H
Addr = Within Block to be Erased
Write
Erase
Confirm
Data = D0H
Addr = Within Block to be Erased
1
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write D0H,
Block Address
Read
Status Register
No
SR.7 =
0
Suspend Block
Erase Loop
Suspend
Block Erase
Data = 70H
Addr = X
Read
0
Write 20H,
Block Address
COMMENTS
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after
a sequence of block erasures.
Yes
Write FFH after the last block erase operation to place device
in read array mode.
1
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
BUS
COMMAND
OPERATION
1
SR.3 =
SR.1 =
Standby
Check SR.1
1 = Device Protect Detect
WP# = VIL, Block Lock-Bit is Set
Only required for systems implementing block lock-bit configuration
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Block Erase Error
Device Protect Error
1
SR.4, 5 =
Command Sequence
Error
0
0
Check SR.3
1 = VPP Error Detect
1
0
SR.5 =
Standby
VPP Range Error
0
1
Block Erase
Error
COMMENTS
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple blocks
are erased before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
Block Erase
Successful
Fig. 3 Automated Block Erase Flowchart
- 25 -
LH28F320S3TD-L10
BUS
COMMAND
OPERATION
Start
Write
Write 70H
Read Status
Register
0
1
Write 30H
Write D0H
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write
Bank Erase
Setup
Data = 30H
Addr = X
Write
Bank Erase
Setup
Data = D0H
Addr = X
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Full full status check can be done after each bank erase.
Write FFH after the last bank erase operation to place bank
in read array mode.
Read
Status Register
SR.7 =
Data = 70H
Addr = X
Read
Read
Status Register
SR.7 =
COMMENTS
0
1
Full Status
Check if Desired
Bank Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
BUS
COMMAND
OPERATION
VPP Range Error
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Bank Erase Error
0
SR.4, 5 =
1
Command Sequence
Error
0
SR.5 =
1
Bank Erase Error
COMMENTS
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple blocks are
erased before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
0
Bank Erase
Successful
Fig. 4 Automated Bank Erase Flowchart
- 26 -
LH28F320S3TD-L10
BUS
COMMAND
OPERATION
Start
Write
Write 70H
Read Status
Register
0
1
Write 40H or 10H,
Address
Write Word/Byte
Data and Address
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
No
0
Write
Setup Word/
Byte Write
Data = 40H or 10H
Addr = Location to be Written
Write
Word/Byte
Write
Data = Data to be Written
Addr = Location to be Written
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent word/byte writes.
Read
Status Register
SR.7 =
Data = 70H
Addr = X
Read
Read
Status Register
SR.7 =
COMMENTS
Suspend Word/Byte
Write Loop
Suspend
Word/Byte
Write
Yes
SR full status check can be done after each word/byte write
or after a sequence of word/byte writes.
Write FFH after the last word/byte write operation to place
device in read array mode.
1
Full Status
Check if Desired
Word/Byte Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
BUS
COMMAND
OPERATION
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
WP# = VIL, Block Lock-Bit is Set
Only required for systems implementing block lock-bit configuration
Standby
Check SR.4
1 = Data Write Error
1
SR.3 =
VPP Range Error
0
SR.1 =
1
Device Protect Error
0
1
SR.4 =
0
Word/Byte Write
Error
COMMENTS
SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are
written before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
Word/Byte Write
Successful
Fig. 5 Automated Word/Byte Write Flowchart
- 27 -
LH28F320S3TD-L10
BUS
COMMAND
OPERATION
Start
Write E8H,
Start Address
Write
COMMENTS
Setup Multi
Data = E8H
Word/Byte Write Addr = Start Address
Read
Extended Status Register Data
Standby
Check XSR.7
1 = Multi Word/Byte Ready
0 = Multi Word/Byte Busy
Write
(NOTE 1)
Data = Word or Count (N) _1
Addr = Start Address
Write
(NOTE 2, 3)
Data = Buffer Data
Addr = Start Address
Write
(NOTE 4, 5)
Data = Buffer Data
Addr = Start Address
Write Buffer
Start Address
Write
Data = D0H
Addr = X
X=0
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read
Status Register
No
XSR.7 =
0
Write Buffer
Time-Out
Yes
1
Write Word or Byte Count (N)_1,
Start Address
Abort
Buffer Write
Command?
No
Yes
Write Buffer Data,
Device Address
Yes
Write Another
Block Address
NOTES :
1. Byte or word count values on DQ 0-7 are loaded into the
count register.
2. Write buffer contents will be programmed at the start
address.
3. Align the start address on a write buffer boundary for
maximum programming performance.
4. The device aborts the Multi Word/Byte Write command if
the current address is outside of the original block address.
5. The status register indicates an "improper command
sequence" if the Multi Word/Byte Write command is aborted.
Follow this with a Clear Status Register command.
Multi Word/Byte
Write Abort
X=N
No
X=X+1
SR full status check can be done after each multi word/byte
write or after a sequence of multi word/byte writes.
Write D0H
Write FFH after the last multi word/byte write operation to
place device in read array mode.
Another
Yes
Buffer
Write ?
No
Read
Status Register
SR.7 =
0
1
No Suspend Multi Word/Byte
Write Loop
Suspend
Yes
Multi Word/Byte
Write
Full Status
Check if Desired
Multi Word/Byte
Write Complete
Fig. 6 Automated Multi Word/Byte Write Flowchart
- 28 -
LH28F320S3TD-L10
FULL STATUS CHECK PROCEDURE FOR
MULTI WORD/BYTE WRITE OPERATION
BUS
COMMAND
OPERATION
Read Status Register
SR.3 =
1
SR.1 =
1
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
WP# = VIL, Block Lock-Bit is Set
Only required for systems implementing block lock-bit configuration
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.4
1 = Data Write Error
VPP Range Error
0
Device Protect Error
0
SR.4, 5 =
1
Command Sequence
Error
0
SR.4 =
1
Multi Word/Byte
Write Error
COMMENTS
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple locations
are written before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
0
Multi Word/Byte Write
Successful
Fig. 7 Full Status Check Procedure for Automated Multi Word/Byte Write
- 29 -
LH28F320S3TD-L10
BUS
OPERATION
Start
Write
Write B0H
COMMAND
Erase
Suspend
Status Register Data
Addr = X
Read
Status Register
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
0
Standby
Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed
1
Write
0
SR.6 =
Erase
Resume
Block Erase
Completed
1
Read Array Data
Data = B0H
Addr = X
Read
SR.7 =
Read
COMMENTS
(Multi) Word/Byte Write
Read or
Write?
No
(Multi) Word/Byte Write
Loop
Done?
Yes
Write D0H
Write FFH
Block Erase
Resumed
Read
Array Data
Fig. 8 Block Erase Suspend/Resume Flowchart
- 30 -
Data = D0H
Addr = X
LH28F320S3TD-L10
BUS
OPERATION
Start
Write
Write B0H
Read
Status Register
COMMAND
(Multi) Word/Byte Data = B0H
Write Suspend Addr = X
Read
Status Register Data
Addr = X
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.2
1 = (Multi) Word/Byte Write
Suspended
0 = (Multi) Word/Byte Write
Completed
0
SR.7 =
1
0
SR.2 =
(Multi) Word/Byte Write
Completed
Write
Read
1
Write
Write FFH
COMMENTS
Read Array
Data = FFH
Addr = X
Read array locations other
than that being written.
(Multi) Word/Byte Data = D0H
Write Resume Addr = X
Read
Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
(Multi) Word/Byte Write
Resumed
Read
Array Data
Fig. 9 (Multi) Word/Byte Write Suspend/Resume Flowchart
- 31 -
LH28F320S3TD-L10
BUS
OPERATION
Start
Write
Write 60H,
Block Address
Write
Write 01H,
Block Address
Read
Status Register
COMMENTS
COMMAND
Set Block
Lock-Bit Setup
Data = 60H
Addr = Block Address
Data = 01H
Set Block
Lock-Bit Confirm Addr = Block Address
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block set operations.
Full status check can be done after each block lock-bit set
operation or after a sequence of block lock-bit set operations.
0
SR.7 =
Write FFH after the last block lock-bit set operation to place
device in read array mode.
1
Full Status
Check if Desired
Set Block Lock-Bit
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
BUS
COMMAND
OPERATION
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
WP# = VIL
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.4
1 = Set Block Lock-Bit Error
VPP Range Error
0
SR.1 =
1
Device Protect Error
0
SR.4, 5 =
1
Command Sequence
Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple block
lock-bits are set before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
0
SR.4 =
COMMENTS
1
Set Block Lock-Bit
Error
0
Set Block Lock-Bit
Successful
Fig. 10 Set Block Lock-Bit Flowchart
- 32 -
LH28F320S3TD-L10
BUS
OPERATION
Start
Write 60H
Write
Clear Block
Lock-Bits
Setup
Data = 60H
Addr = X
Write
Clear Block
Lock-Bits
Confirm
Data = D0H
Addr = X
Write D0H
Read
Status Register
SR.7 =
COMMENTS
COMMAND
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write FFH after the last clear block lock-bits operation to
place device in read array mode.
0
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
BUS
COMMAND
OPERATION
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
WP# = VIL
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Clear Block Lock-Bits Error
VPP Range Error
0
SR.1 =
1
Device Protect Error
0
SR.4, 5 =
1
Command Sequence
Error
0
SR.5 =
1
COMMENTS
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command.
If error is detected, clear the status register before attempting
retry or other error recovery.
Clear Block Lock-Bits
Error
0
Clear Block Lock-Bits
Successful
Fig. 11 Clear Block Lock-Bits Flowchart
- 33 -
LH28F320S3TD-L10
5 DESIGN CONSIDERATIONS
5.3
5.1
Three-Line Output Control
The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Threeline control provides for :
a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention
will not occur.
To use these control inputs efficiently, an address
decoder should enable BE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.4
5.2
STS and Block Erase, Bank Erase,
(Multi) Word/Byte Write and Block
Lock-Bit Configuration Polling
STS is an open drain output that should be
connected to VCC by a pullup resistor to provide a
hardware method of detecting block erase, bank
erase, (multi) word/byte write and block lock-bit
configuration completion. In default mode, it
transitions low after block erase, bank erase, (multi)
word/byte write or block lock-bit configuration
commands and returns to VOH when the WSM has
finished executing the internal algorithm. For
alternate STS pin configurations, see the Configuration command (Table 3 and Section 4.14).
STS can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
STS, in default mode, is also High Z when the
device is in block erase suspend (with (multi)
word/byte write inactive), (multi) word/byte write
suspend or deep power-down modes.
Power Supply Decoupling
Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current
issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of BE# and OE#. Transient current
magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 µF ceramic capacitor connected
between its VCC and GND and between its VPP
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at
the array’s power supply connection between VCC
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
VPP Trace on Printed Circuit Boards
Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the VPP power supply
trace. The VPP pin supplies the memory cell current
for block erase, bank erase, (multi) word/byte write
and block lock-bit configuration. Use similar trace
widths and layout considerations given to the VCC
power bus. Adequate VPP supply traces and
decoupling will decrease VPP voltage spikes and
overshoots.
5.5
VCC, VPP, RP# Transitions
Block erase, bank erase, (multi) word/byte write
and block lock-bit configuration are not guaranteed
if VPP falls outside of a valid VPPH1/2/3 range, VCC
falls outside of a valid VCC1/2 range, or RP# = VIL.
If VPP error is detected, status register bit SR.3 is
set to "1" along with SR.4 or SR.5, depending on
the attempted operation. If RP# transitions to VIL
during block erase, bank erase, (multi) word/byte
write or block lock-bit configuration, STS (if set to
- 34 -
LH28F320S3TD-L10
RY/BY# mode) will remain low until the reset
operation is complete. Then, the operation will abort
and the device will enter deep power-down. The
aborted operation may leave data partially altered.
Therefore, the command sequence must be
repeated after normal operation is restored. Device
power-off or RP# transitions to VIL clear the status
register.
The CUI latches commands issued by system
software and is not altered by VPP or BE#
transitions or WSM actions. Its state is read array
mode upon power-up, after exit from deep powerdown or after VCC transitions below VLKO.
After block erase, bank erase, (multi) word/byte
write or block lock-bit configuration, even after VPP
transitions down to VPPLK, the CUI must be placed
in read array mode via the Read Array command if
subsequent access to the memory array is desired.
5.6
Power-Up/Down Protection
5.7
Power Consumption
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when
system power is applied. For example, portable
computing products and other power sensitive
applications that use an array of devices for solidstate storage can consume negligible power by
lowering RP# to VIL standby or sleep modes. If
access is again needed, the devices can be read
following the tPHQV and tPHWL wake-up cycles
required after RP# is first raised to VIH. See Section
6.2.4 through 6.2.6 "AC CHARACTERISTICS READ-ONLY and WRITE OPERATIONS" and
Fig. 15, Fig. 16, Fig. 17 and Fig. 18 for more
information.
The device is designed to offer protection against
accidental block and bank erasure, (multi)
word/byte writing or block lock-bit configuration
during power transitions. Upon power-up, the
device is indifferent as to which power supply (VPP
or VCC) powers-up first. Internal circuitry resets the
CUI to read array mode at power-up.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WE# and BE# must be low for a
command write, driving either to VIH will inhibit
writes. The CUI’s two-step command sequence
architecture provides added level of protection
against data alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP# = VIL regardless of its control inputs
state.
- 35 -
LH28F320S3TD-L10
6 ELECTRICAL SPECIFICATIONS
NOTICE : The specifications are subject to
change without notice. Verify with your local
SHARP sales office that you have the latest
datasheet before finalizing a design.
Absolute Maximum Ratings∗
6.1
Operating Temperature
During Read, Erase, Write and
Block Lock-Bit Configuration ... 0 to +70°C (NOTE 1)
Temperature under Bias ............. –10 to +80°C
Storage Temperature ........................ –65 to +125°C
Voltage On Any Pin
(except VCC, VPP).... –0.5 V to VCC+0.5 V (NOTE 2)
∗WARNING : Stressing the device beyond the
"Absolute
Maximum Ratings" may cause
permanent damage. These are stress ratings only.
Operation beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device reliability.
NOTES :
VCC
Supply Voltage ................ –0.2 to +7.0 V (NOTE 2)
VPP Update Voltage during
Erase, Write and
Block Lock-Bit Configuration.. –0.2 to +7.0 V (NOTE 2)
1.
2.
Output Short Circuit Current................100 mA (NOTE 3)
3.
6.2
Operating temperature is for commercial product defined
by this specification.
All specified voltages are with respect to GND. Minimum
DC voltage is –0.5 V on input/output pins and –0.2 V on
VCC and VPP pins. During transitions, this level may
undershoot to –2.0 V for periods < 20 ns. Maximum DC
voltage on input/output pins and VCC is VCC+0.5 V
which, during transitions, may overshoot to VCC+2.0 V
for periods < 20 ns.
Output shorted for no more than one second. No more
than one output shorted at a time.
Operating Conditions
SYMBOL
PARAMETER
TA
Operating Temperature
MIN.
0
MAX.
+70
UNIT
˚C
VCC1
VCC Supply Voltage (2.7 to 3.6 V)
2.7
3.6
V
VCC2
VCC Supply Voltage (3.3±0.3 V)
3.0
3.6
V
TEST CONDITION
Ambient Temperature
6.2.1 CAPACITANCE (NOTE 1)
TA = +25˚C, f = 1 MHz
SYMBOL
CIN
COUT
PARAMETER
NOTE
TYP.
MAX.
UNIT
2
14
20
pF
VIN = 0.0 V
18
24
pF
VOUT = 0.0 V
Input Capacitance
Output Capacitance
NOTES :
1.
2.
Sampled, not 100% tested.
BE0# and BE1L#, BE1H# have half the value of this.
- 36 -
TEST CONDITION
LH28F320S3TD-L10
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
2.7
1.35
INPUT
TEST POINTS
1.35 OUTPUT
0.0
AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output
timing ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 12 Transient Input/Output Reference Waveform for VCC = 2.7 to 3.6 V
3.0
1.5
INPUT
TEST POINTS
1.5
OUTPUT
0.0
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output
timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 13 Transient Input/Output Reference Waveform for VCC = 3.3±0.3 V
Test Configuration Capacitance Loading Value
TEST CONFIGURATION
VCC = 3.3±0.3 V, 2.7 to 3.6 V
1.3 V
1N914
RL = 3.3 kΩ
DEVICE
UNDER
TEST
OUT
CL
CL Includes Jig
Capacitance
Fig. 14 Transient Equivalent Testing
Load Circuit
- 37 -
CL (pF)
50
LH28F320S3TD-L10
6.2.3 DC CHARACTERISTICS
Following is the supply current of one bank. For the supply current of one device total, refer to NOTE 8.
SYMBOL
PARAMETER
NOTE
VCC = 2.7 to 3.6 V VCC = 3.3±0.3 V
UNIT
TYP.
MAX.
TYP.
MAX.
20
100
20
100
µA
1
4
1
4
mA
15
15
µA
25
25
mA
30
30
mA
—
17
17
—
17
17
mA
mA
mA
mA
mA
mA
VCC = VCC Max.
VIN = VCC or GND
VCC = VCC Max.
VOUT = VCC or GND
CMOS Inputs
VCC = VCC Max.
BE# = RP# = VCC±0.2 V
TTL Inputs
VCC = VCC Max.
BE# = RP# = VIH
RP# = GND±0.2 V
IOUT (STS) = 0 mA
CMOS Inputs
VCC = VCC Max.
BE# = GND
f = 5 MHz, IOUT = 0 mA
TTL Inputs
VCC = VCC Max.
BE# = VIL
f = 5 MHz, IOUT = 0 mA
VPP = 2.7 to 3.6 V
VPP = 3.3±0.3 V
VPP = 5.0±0.5 V
VPP = 2.7 to 3.6 V
VPP = 3.3±0.3 V
VPP = 5.0±0.5 V
ILI
Input Load Capacitance
1
±0.5
±0.5
µA
ILO
Output Leakage Capacitance
1
±0.5
±0.5
µA
ICCS
ICCD
ICCR
ICCW
ICCE
ICCWS
ICCES
IPPS
IPPR
IPPD
IPPW
IPPE
IPPWS
IPPES
VCC Standby Current
VCC Deep Power-Down
Current
VCC Read Current
VCC Write Current
((Multi) W/B Write or
Set Block Lock-Bit)
VCC Erase Current
(Block Erase, Bank Erase,
Clear Block Lock-Bits)
VCC Write or Block Erase
Suspend Current
VPP Standby Current
VPP Read Current
VPP Deep Power-Down
Current
VPP Write Current
((Multi) W/B Write or
Set Block Lock-Bit)
VPP Erase Current
(Block Erase, Bank Erase,
Clear Block Lock-Bits)
VPP Write or Block Erase
Suspend Current
TEST
CONDITIONS
1, 3,
6, 8
1
1, 5,
6, 8
1, 7, 8
1, 7, 8
17
17
17
17
17
17
—
—
1, 2, 8
1
6
1
6
µA
BE# = VIH
1, 8
1
±2
10
±15
200
±2
10
±15
200
µA
µA
VPP ≤ VCC
VPP > VCC
1
0.1
5
0.1
5
mA
RP# = GND±0.2 V
80
80
80
40
40
40
—
—
80
80
—
40
40
mA
mA
mA
mA
mA
mA
VPP
VPP
VPP
VPP
VPP
VPP
200
10
200
µA
VPP = VPPH1/2/3
1, 7, 8
1, 7, 8
1, 8
10
- 38 -
—
=
=
=
=
=
=
2.7 to 3.6 V
3.3±0.3 V
5.0±0.5 V
2.7 to 3.6 V
3.3±0.3 V
5.0±0.5 V
LH28F320S3TD-L10
6.2.3 DC CHARACTERISTICS (contd.)
SYMBOL
VIL
PARAMETER
Input Low Voltage
NOTE
7
VIH
Input High Voltage
7
VOL
Output Low Voltage
3, 7
VOH1
Output High Voltage
(TTL)
3, 7
VOH2
VPPLK
VPPH1
VPPH2
VPPH3
VLKO
Output High Voltage
(CMOS)
VPP Lockout Voltage
during Normal Operations
VPP Voltage during Write
or Erase Operations
VPP Voltage during Write
or Erase Operations
VPP Voltage during Write
or Erase Operations
VCC Lockout Voltage
3, 7
VCC = 2.7 to 3.6 V VCC = 3.3±0.3 V
MIN.
–0.5
MAX.
0.8
2.0
VCC
+0.5
MAX.
0.8
2.0
VCC
+0.5
V
0.4
V
0.4
2.4
2.4
0.85
0.85
VCC
VCC
VCC
–0.4
VCC
–0.4
4, 7
UNIT
MIN.
–0.5
1.5
V
V
V
V
1.5
VCC = VCC Min.
IOL = 2 mA
VCC = VCC Min.
IOH = –2.5 mA
VCC = VCC Min.
IOH = –2.5 mA
VCC = VCC Min.
IOH = –100 µA
V
2.7
3.6
3.0
3.6
3.0
3.6
V
4.5
5.5
4.5
5.5
V
2.0
TEST
CONDITIONS
V
2.0
V
NOTES :
1.
2.
3.
4.
All currents are in RMS unless otherwise noted. Typical
values at nominal VCC voltage and TA = +25°C.
ICCWS and ICCES are specified with the device deselected. If reading or (multi) word/byte writing in erase
suspend mode, the device’s current draw is the sum of
ICCWS or ICCES and ICCR or ICCW, respectively.
Includes STS.
Block erases, bank erases, (multi) word/byte writes and
block lock-bit configurations are inhibited when VPP ≤
VPPLK, and not guaranteed in the range between VPPLK
(max.) and VPPH1 (min.), between VPPH1 (max.) and
VPPH2 (min.), between VPPH2 (max.) and VPPH3 (min.)
and above VPPH3 (max.).
5.
6.
7.
8.
- 39 -
Automatic Power Saving (APS) reduces typical ICCR to
3 mA at 2.7 V and 3.3 V VCC in static operation.
CMOS inputs are either VCC±0.2 V or GND±0.2 V. TTL
inputs are either VIL or VIH.
Sampled, not 100% tested.
These are the values of the current which is consumed
within one bank area. The value for the bank0 and
bank1 should added in order to calculate the value for
the whole chip. If the bank0 is in write state and bank1
is in read state, the ICC = ICCW + ICCR. If both banks are
in standby mode, the value for the device is 2 times the
value in the above table.
LH28F320S3TD-L10
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C
SYMBOL
tAVAV
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tOH
tFLQV
tFHQV
tFLQZ
tELFL
tELFH
VERSION
PARAMETER
NOTE
Read Cycle Time
Address to Output Delay
BE# to Output Delay
RP# High to Output Delay
OE# to Output Delay
BE# to Output in Low Z
BE# High to Output in High Z
OE# to Output in Low Z
OE# High to Output in High Z
Output Hold from Address, BE# or OE# Change,
Whichever Occurs First
2
2
3
3
3
3
3
LH28F320S3TD-L10
TYP.
MAX.
120
120
120
600
50
0
50
0
20
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BYTE# to Output Delay
3
120
ns
BYTE# to Output in High Z
3
30
ns
BE# Low to BYTE# High or Low
3
5
ns
• VCC = 3.3±0.3 V, TA = 0 to +70˚C
SYMBOL
tAVAV
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tOH
tFLQV
tFHQV
tFLQZ
tELFL
tELFH
VERSION
PARAMETER
NOTE
Read Cycle Time
Address to Output Delay
BE# to Output Delay
RP# High to Output Delay
OE# to Output Delay
BE# to Output in Low Z
BE# High to Output in High Z
OE# to Output in Low Z
OE# High to Output in High Z
Output Hold from Address, BE# or OE# Change,
Whichever Occurs First
2
2
3
3
3
3
3
LH28F320S3TD-L10
TYP.
MAX.
100
100
100
600
45
0
50
0
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BYTE# to Output Delay
3
100
ns
BYTE# to Output in High Z
3
30
ns
BE# Low to BYTE# High or Low
3
5
ns
NOTES :
1.
2.
3.
UNIT
See AC Input/Output Reference Waveform (Fig. 12 and Fig. 13) for maximum allowable input slew rate.
OE# may be delayed up to tELQV-tGLQV after the falling edge of BE# without impact on tELQV.
Sampled, not 100% tested.
- 40 -
LH28F320S3TD-L10
VIH
Standby
Device
Address Selection
Data Valid
Address Stable
ADDRESSES (A)
VIL
tAVAV
VIH
BEX# (E)
tEHQZ
VIL
VIH
OE# (G)
tGHQZ
VIL
VIH
WE# (W)
tGLQV
tELQV
VIL
VOH
DATA (D/Q)
tGLQX
tELQX
High Z
tOH
Valid Output
VOL
High Z
tAVQV
VCC
tPHQV
VIH
RP# (P)
VIL
NOTE :
BEX# is defined as the latter of BE0# and BE1L#, BE1H# going Low or the first of BE0# and BE1L#, BE1H# going High.
Fig. 15 AC Waveform for Read Operations
- 41 -
LH28F320S3TD-L10
VIH
Standby
ADDRESSES (A)
Device
Address Selection
Data Valid
Address Stable
VIL
tAVAV
VIH
BEX# (E)
tEHQZ
VIL
tAVFL = tELFL
VIH
OE# (G)
tGHQZ
tELFL
VIL
tFLQV = tAVQV
VIH
BYTE# (F)
tGLQV
VIL
VOH
DATA (D/Q)
(DQ0-DQ7)
tELQV
tGLQX
tELQX
tOH
High Z
VOL
Data Output
Valid
Output
High Z
tAVQV
tFLQZ
VOH
DATA (D/Q)
(DQ8-DQ15)
High Z
Data
Output
VOL
High Z
NOTE :
BEX# is defined as the latter of BE0# and BE1L#, BE1H# going Low or the first of BE0# and BE1L#, BE1H# going High.
Fig. 16 BYTE# Timing Waveforms
- 42 -
LH28F320S3TD-L10
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C
SYMBOL
tAVAV
tPHWL
tELWL
tWLWH
tSHWH
tVPWH
tAVWH
tDVWH
tWHDX
tWHAX
tWHEH
tWHWL
tWHRL
tWHGL
tQVVL
tQVSL
VERSION
PARAMETER
NOTE
Write Cycle Time
RP# High Recovery to WE# Going Low
BE# Setup to WE# Going Low
WE# Pulse Width
WP# VIH Setup to WE# Going High
VPP Setup to WE# Going High
Address Setup to WE# Going High
Data Setup to WE# Going High
Data Hold from WE# High
Address Hold from WE# High
BE# Hold from WE# High
WE# Pulse Width High
WE# High to STS Going Low
Write Recovery before Read
VPP Hold from Valid SRD, STS High Z
WP# VIH Hold from Valid SRD, STS High Z
2
2
2
3
3
2, 4
2, 4
LH28F320S3TD-L10
MIN.
MAX.
120
1
10
50
100
100
50
50
5
5
10
30
100
0
0
0
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
• VCC = 3.3±0.3 V, TA = 0 to +70˚C
SYMBOL
tAVAV
tPHWL
tELWL
tWLWH
tSHWH
tVPWH
tAVWH
tDVWH
tWHDX
tWHAX
tWHEH
tWHWL
tWHRL
tWHGL
tQVVL
tQVSL
VERSION
PARAMETER
NOTE
Write Cycle Time
RP# High Recovery to WE# Going Low
BE# Setup to WE# Going Low
WE# Pulse Width
WP# VIH Setup to WE# Going High
VPP Setup to WE# Going High
Address Setup to WE# Going High
Data Setup to WE# Going High
Data Hold from WE# High
Address Hold from WE# High
BE# Hold from WE# High
WE# Pulse Width High
WE# High to STS Going Low
Write Recovery before Read
VPP Hold from Valid SRD, STS High Z
WP# VIH Hold from Valid SRD, STS High Z
2
2
2
3
3
2, 4
2, 4
LH28F320S3TD-L10
MIN.
MAX.
100
1
10
50
100
100
50
50
5
5
10
30
100
0
0
0
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES :
1.
2.
Read timing characteristics during block erase, bank
erase, (multi) word/byte write and block lock-bit
configuration operations are the same as during readonly operations. Refer to Section 6.2.4 "AC
CHARACTERISTICS" for read-only operations.
Sampled, not 100% tested.
3.
4.
- 43 -
Refer to Table 3 for valid AIN and DIN for block erase,
bank erase, (multi) word/byte write or block lock-bit
configuration.
VPP should be held at VPPH1/2/3 until determination of
block erase, bank erase, (multi) word/byte write or block
lock-bit configuration success (SR.1/3/4/5 = 0).
LH28F320S3TD-L10
(NOTE 1) (NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH
AIN
ADDRESSES (A)
VIL
AIN
tAVAV
tAVWH tWHAX
VIH
BEX# (E)
VIL
tELWL
tWHEH
tWHGL
VIH
OE# (G)
VIL
tWHQV1/2/3/4
tWHWL
VIH
WE# (W)
tWLWH
tDVWH
tWHDX
VIL
VIH
DATA (D/Q)
High Z
VIL
DIN
DIN
tPHWL
Valid
SRD
DIN
tWHRL
High Z
STS (R)
VOL
tSHWH
tQVSL
VIH
WP# (S)
VIL
VIH
RP# (P)
VIL
tVPWH
tQVVL
VPPH1/2/3
VPP (V)
VPPLK
VIL
NOTES :
1.
2.
3.
4.
5.
6.
7.
VCC power-up and standby.
Write erase or write setup.
Write erase confirm or valid address and data.
Automated erase or program delay.
Read status register data.
Write Read Array command.
BEX# is defined as the latter of BE0# and BE1L#, BE1H# going Low or the first of BE0# and BE1L#, BE1H# going
High.
Fig. 17 AC Waveform for WE#-Controlled Write Operations
- 44 -
LH28F320S3TD-L10
6.2.6 ALTERNATIVE BE#-CONTROLLED WRITES (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C
VERSION
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
tPHEL
RP# High Recovery to BE# Going Low
tWLEL
WE# Setup to BE# Going Low
tELEH
BE# Pulse Width
tSHEH
WP# VIH Setup to BE# Going High
tVPEH
VPP Setup to BE# Going High
tAVEH
Address Setup to BE# Going High
tDVEH
Data Setup to BE# Going High
tEHDX
Data Hold from BE# High
tEHAX
Address Hold from BE# High
tEHWH WE# Hold from BE# High
tEHEL
BE# Pulse Width High
tEHRL
BE# High to STS Going Low
tEHGL
Write Recovery before Read
tQVVL
VPP Hold from Valid SRD, STS High Z
tQVSL
WP# VIH Hold from Valid SRD, STS High Z
NOTE
2
2
2
3
3
2, 4
2, 4
• VCC = 3.3±0.3 V, TA = 0 to +70˚C
VERSION
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
tPHEL
RP# High Recovery to BE# Going Low
tWLEL
WE# Setup to BE# Going Low
tELEH
BE# Pulse Width
tSHEH
WP# VIH Setup to BE# Going High
tVPEH
VPP Setup to BE# Going High
tAVEH
Address Setup to BE# Going High
tDVEH
Data Setup to BE# Going High
tEHDX
Data Hold from BE# High
tEHAX
Address Hold from BE# High
tEHWH WE# Hold from BE# High
tEHEL
BE# Pulse Width High
tEHGL
BE# High to STS Going Low
tEHRL
Write Recovery before Read
tQVVL
VPP Hold from Valid SRD, STS High Z
tQVSL
WP# VIH Hold from Valid SRD, STS High Z
NOTE
2
2
2
3
3
2, 4
2, 4
LH28F320S3TD-L10
MIN.
MAX.
120
1
0
70
100
100
50
50
5
5
0
25
100
0
0
0
LH28F320S3TD-L10
MIN.
MAX.
100
1
0
70
100
100
50
50
5
5
0
25
100
0
0
0
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES :
1.
2.
In systems where BE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold
and inactive WE# times should be measured relative to
the BE# waveform.
Sampled, not 100% tested.
3.
4.
- 45 -
Refer to Table 3 for valid AIN and DIN for block erase,
bank erase, (multi) word/byte write or block lock-bit
configuration.
VPP should be held at VPPH1/2/3 until determination of
block erase, bank erase, (multi) word/byte write or block
lock-bit configuration success (SR.1/3/4/5 = 0).
LH28F320S3TD-L10
(NOTE 1) (NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH
AIN
ADDRESSES (A)
VIL
AIN
tAVAV
tAVEH
tEHAX
VIH
WE# (W)
VIL
tWLEL
tEHWH
tEHGL
VIH
OE# (G)
VIL
tEHQV1/2/3/4
tEHEL
VIH
BEX# (E)
tELEH
tDVEH
tEHDX
VIL
VIH
DATA (D/Q)
High Z
VIL
DIN
DIN
tPHEL
Valid
SRD
DIN
tEHRL
High Z
STS (R)
VOL
tSHEH
tQVSL
VIH
WP# (S)
VIL
VIH
RP# (P)
VIL
tVPEH
tQVVL
VPPH1/2/3
VPP (V)
VPPLK
VIL
NOTES :
1.
2.
3.
4.
5.
6.
7.
VCC power-up and standby.
Write erase or write setup.
Write erase confirm or valid address and data.
Automated erase or program delay.
Read status register data.
Write Read Array command.
BEX# is defined as the latter of BE0# and BE1L#, BE1H# going Low or the first of BE0# and BE1L#, BE1H# going
High.
Fig. 18 AC Waveform for BE#-Controlled Write Operations
- 46 -
LH28F320S3TD-L10
6.2.7 RESET OPERATIONS
High Z
STS (R)
VOL
VIH
RP# (P)
VIL
tPLPH
(A) Reset During Read Array Mode
High Z
STS (R)
VOL
tPLRH
VIH
RP# (P)
VIL
tPLPH
(B) Reset During Block Erase, Bank Erase, (Multi) Word/Byte Write
or Block Lock-Bit Configuration
2.7 V/3.3 V
VCC
VIL
t23VPH
VIH
RP# (P)
VIL
(C) VCC Power Up Timing
Fig. 19 AC Waveform for Reset Operation
Reset AC Specifications
SYMBOL
tPLPH
tPLRH
t23VPH
PARAMETER
NOTE
RP# Pulse Low Time (If RP# is tied to VCC,
VCC = 2.7 to 3.6 V
MIN.
MAX.
100
this specification is not applicable)
RP# Low to Reset during Block Erase,
Bank Erase, (Multi) Word/Byte Write
1, 2
or Block Lock-Bit Configuration
VCC 2.7 V to RP# High
3
VCC 3.0 V to RP# High
VCC = 3.3±0.3 V
MIN.
MAX.
100
21.5
100
ns
21.1
100
UNIT
µs
ns
NOTES :
1.
2.
If RP# is asserted while a block erase, bank erase,
(multi) word/byte write or block lock-bit configuration
operation is not executing, the reset will complete within
100 ns.
A reset time, tPHQV, is required from the latter of STS
going High Z or RP# going high until outputs are valid.
3.
- 47 -
When the device power-up, holding RP#-low minimum
100 ns is required after VCC has been in predefined
range and also has been in stable there.
LH28F320S3TD-L10
6.2.8 BLOCK ERASE, BANK ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK LOCK-BIT
CONFIGURATION PERFORMANCE (NOTE 3)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C
SYMBOL
PARAMETER
NOTE
VPP = 2.7 to 3.6 V
MIN. TYP.(NOTE 1) MAX.
VPP = 3.3±0.3 V
MIN. TYP.(NOTE 1) MAX.
tWHQV1
Word/Byte Write Time
(using W/B write,
2
22.17
22.17
13.2
µs
2
19.89
19.89
13.2
µs
2
5.76
5.76
2.76
µs
2
0.91
0.91
0.44
s
2
1.63
1.63
0.87
s
2
0.37
0.37
0.18
s
2
0.56
0.56
0.42
s
17.9
17.9
13.3
s
2
22.17
22.17
13.2
µs
2
0.56
0.56
0.42
s
tEHQV1
tWHQV1
tEHQV1
VPP = 5.0±0.5 V
UNIT
MIN. TYP.(NOTE 1) MAX.
in word mode)
Word/Byte Write Time
(using W/B write,
in byte mode)
Word/Byte Write Time
(using multi word/byte
write)
Block Write Time
(using W/B write,
in word mode)
Block Write Time
(using W/B write,
in byte mode)
Block Write Time
(using multi word/byte
write)
tWHQV2
tEHQV2
Block Erase Time
Bank Erase Time
tWHQV3 Set Block Lock-Bit
tEHQV3 Time
tWHQV4 Clear Block Lock-Bits
tEHQV4
Time
tWHRH1 Write Suspend Latency
tEHRH1 Time to Read
7.24
10.2
7.24
10.2
6.73
9.48
µs
tWHRH2 Erase Suspend Latency
tEHRH2 Time to Read
15.5
21.5
15.5
21.5
12.54 17.54
µs
Typical values measured at TA = +25˚C and nominal
voltages. Assumes corresponding block lock-bits are not
set. Subject to change based on device characterization.
2.
3.
NOTES :
1.
- 48 -
Excludes system-level overhead.
Sampled, not 100% tested.
LH28F320S3TD-L10
6.2.8 BLOCK ERASE, BANK ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK LOCK-BIT
CONFIGURATION PERFORMANCE (contd.) (NOTE 3)
• VCC = 3.3±0.3 V, TA = 0 to +70˚C
SYMBOL
PARAMETER
NOTE
VPP = 3.3±0.3 V
VPP = 5.0±0.5 V
MIN. TYP.(NOTE 1) MAX.
MIN. TYP.(NOTE 1) MAX.
UNIT
tWHQV1 Word/Byte Write Time
(using W/B write, in word mode)
2
21.75
12.95
µs
tWHQV1 Word/Byte Write Time
tEHQV1 (using W/B write, in byte mode)
2
19.51
12.95
µs
2
5.66
2.7
µs
2
0.89
0.43
s
2
1.6
0.85
s
2
0.36
0.18
s
2
0.55
0.41
s
17.6
13.1
s
tEHQV1
Word/Byte Write Time
(using multi word/byte write)
Block Write Time
(using W/B write, in word mode)
Block Write Time
(using W/B write, in byte mode)
Block Write Time
(using multi word/byte write)
tWHQV2
Block Erase Time
tEHQV2
Bank Erase Time
tWHQV3
tEHQV3
tWHQV4
tEHQV4
Set Block Lock-Bit Time
2
21.75
12.95
µs
Clear Block Lock-Bits Time
2
0.55
0.41
s
tWHRH1
Write Suspend Latency Time to Read
tEHRH1
tWHRH2
tEHRH2
Erase Suspend Latency Time to Read
7.1
10
6.6
9.3
µs
15.2
21.1
12.3
17.2
µs
NOTES :
1.
Typical values measured at TA = +25˚C and nominal
voltages. Assumes corresponding block lock-bits are not
set. Subject to change based on device characterization.
2.
3.
- 49 -
Excludes system-level overhead.
Sampled, not 100% tested.
LH28F320S3TD-L10
7 ORDERING INFORMATION
Product line designator for all SHARP Flash products
L H 2 8 F 3 2 0 S 3 T D - L 1 0
Device Density
320 = 32 M-bit
Access Speed (ns)
10 : 100 ns (3.3±0.3 V), 120 ns (2.7 to 3.6 V)
Architecture
S = Symmetrical Block
Power Supply Type
3 = Smart 3 Technology
Dual Work technology
Package
T = 56-pin TSOP (I) (TSOP056-P-1420) Normal bend
Operating Temparature = 0 to +70°C
OPTION
1
ORDER CODE
LH28F320S3TD-L10
VALID OPERATIONAL COMBINATIONS
VCC = 3.3±0.3 V
VCC = 2.7 to 3.6 V
50 pF load,
50 pF load,
1.35 V I/O Levels
120 ns
- 50 -
1.5 V I/O Levels
100 ns
20.0 ±0.3
18.4±0.2
19.0 ±0.3
1.2MAX.
0.10
14.0 ±0.2
56 _ 0.2 ±0.08
29
0.995 ±0.1
0.5TYP.
28
0.435
M
56
0.125
0.08
1
0.115 ±0.1
0.125 ±0.05
PACKAGING
56 TSOP (TSOP056-P-1420)
Package base plane
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