Cirrus CS4245-DQZ 104 db, 24-bit, 192 khz stereo audio codec Datasheet

CS4245
104 dB, 24-Bit, 192 kHz Stereo Audio CODEC
D/A Features
A/D Features
 Multi-bit Delta Sigma Modulator
 Multi-bit Delta Sigma Modulator
 104 dB Dynamic Range
 104 dB Dynamic Range
 -90 dB THD+N
 -95 dB THD+N
 Up to 192 kHz Sampling Rates
 Stereo 6:1 Input Multiplexer
 Single-Ended Analog Architecture
 Programmable Gain Amplifier (PGA)
 Volume Control with Soft Ramp
–
–
–
–
0.5 dB Step Size
Zero Crossing, Click-Free Transitions
 Popguard® Technology




 Stereo Microphone Inputs
– Minimizes the Effects of Output Transients
Filtered Line-Level Outputs
Selectable Serial Audio Interface Formats
– Left-Justified up to 24-bit
– I²S up to 24-bit
– Right-Justified 16-, 18-, 20-, and 24-bit
Selectable 50/15 µs De-Emphasis
Control Output for External Muting
Reset
Serial
Audio
Output
PCM Serial Interface
Level
Translator
http://www.cirrus.com
+32 dB Gain Stage
Low-Noise Bias Supply
 Up to 192 kHz Sampling Rates
 Selectable Serial Audio Interface Formats
–
–
Left-Justified up to 24-bit
I²S up to 24-bit
 High-Pass Filter or DC Offset Calibration
Volume
Control
Volume
Control
Interpolation
Filter
Interpolation
Filter
3.3 V to 5 V
Multibit
ΔΣ Modulator
Switched Capacitor
DAC and Filter
Multibit
ΔΣ Modulator
Switched Capacitor
DAC and Filter
Left DAC Output
Mute
Control
Register Configuration
High Pass
Filter
High Pass
Filter
Low-Latency
Anti-Alias Filter
Low-Latency
Anti-Alias Filter
Mute Control
Right DAC Output
MUX
PCM Serial Interface
ADC Overflow
Level Translator
Interrupt
Level
Translator
I2C/SPI
Control Data
–
–
3.3 V to 5 V
1.8 V to 5 V
Serial
Audio
Input
± 12 dB Gain, 0.5 dB Step Size
Zero Crossing, Click-Free Transitions
Left Aux Output
Right Aux Output
Internal Voltage
Reference
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
Stereo Input 1
Stereo Input 2
Stereo Input 3
PGA
MUX
PGA
+32 dB
Stereo Input 4 /
Mic Input 1 & 2
+32 dB
Stereo Input 5
Stereo Input 6
AUGUST '07
DS656F2
CS4245
System Features
General Description
 Direct Interface with 1.8 V to 5 V Logic Levels
The CS4245 is a highly integrated stereo audio
CODEC. The CS4245 performs stereo analog-to-digital
(A/D) and digital-to-analog (D/A) conversion of up to
24-bit serial values at sample rates up to 192 kHz.
 Optional Asynchronous Serial Port Operation
–
Each Serial Port Supports Master or Slave
Operation
 Selectable Auxiliary Analog Output
–
Allows Analog Monitoring of Either the ADC
Input Signal after PGA or DAC Output
Signal
 Internal Digital Loopback
 Power-Down Mode
–
Available for A/D, D/A, CODEC, Mic
Preamplifier
 +3.3 V to +5 V Analog Power Supply
 +3.3 V to +5 V Digital Power Supply
 Supports I²C® and SPITM Control Port
Interfaces
 Pin-Compatible with CS5345
A 6:1 stereo input multiplexer is included for selecting
between line-level or microphone-level inputs. The microphone input path includes a +32 dB gain stage and
a low-noise bias voltage supply. The PGA is available
for line or microphone inputs and provides gain/attenuation of ±12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the
serial audio interface at rates from 4 kHz to 192 kHz in
either Slave or Master Mode.
The D/A converter is based on a 4th-order multi-bit delta
sigma modulator with an ultra-linear low-pass filter and
offers a volume control that operates with a 0.5 dB step
size. It incorporates selectable soft ramp and zero
crossing transition functions to eliminate clicks and
pops.
Standard 50/15 μs de-emphasis is available for a
44.1 kHz sample rate for compatibility with digital audio
programs mastered using the 50/15 μs pre-emphasis
technique.
Integrated level translators allow easy interfacing between the CS4245 and other devices operating over a
wide range of logic levels.
The CS4245 is available in a 48-pin LQFP package in
both Commercial (-10° to +70° C) and Automotive (-40°
to +105° C) grade. The CDB4245 Customer Demonstration board is also available for device evaluation and
implementation suggestions. Please see “Ordering Information” on page 57 for complete details.
2
DS656F2
CS4245
TABLE OF CONTENTS
1. PIN DESCRIPTIONS
........................................................................................................................ 6
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8
SPECIFIED OPERATING CONDITIONS ............................................................................................. 8
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 8
DAC ANALOG CHARACTERISTICS ................................................................................................... 9
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................ 10
ADC ANALOG CHARACTERISTICS ................................................................................................. 12
ADC ANALOG CHARACTERISTICS ................................................................................................. 14
ADC DIGITAL FILTER CHARACTERISTICS ..................................................................................... 15
AUXILIARY OUTPUT ANALOG CHARACTERISTICS ...................................................................... 16
AUXILIARY OUTPUT ANALOG CHARACTERISTICS ...................................................................... 17
AUXILIARY OUTPUT ANALOG CHARACTERISTICS ...................................................................... 18
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 19
DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 20
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 1 .......................................................... 21
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 2 .......................................................... 23
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................ 26
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 27
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 28
4. APPLICATIONS ................................................................................................................................... 29
4.1 Recommended Power-Up Sequence ............................................................................................. 29
4.2 System Clocking ............................................................................................................................. 29
4.2.1 Synchronous / Asynchronous Mode ...................................................................................... 29
4.2.2 Master Clock ......................................................................................................................... 29
4.2.3 Master Mode ......................................................................................................................... 30
4.2.4 Slave Mode ........................................................................................................................... 30
4.3 High-Pass Filter and DC Offset Calibration .................................................................................... 31
4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................ 32
4.5 Input Connections ........................................................................................................................... 32
4.6 Output Connections ........................................................................................................................ 32
4.7 Output Transient Control ................................................................................................................ 33
4.7.1 Power-Up .............................................................................................................................. 33
4.7.2 Power-Down .......................................................................................................................... 33
4.7.3 Serial Interface Clock Changes ............................................................................................. 33
4.8 Auxiliary Analog Output .................................................................................................................. 33
4.9 De-Emphasis Filter ......................................................................................................................... 33
4.10 Internal Digital Loopback .............................................................................................................. 34
4.11 Mute Control ................................................................................................................................. 34
4.12 Control Port Description and Timing ............................................................................................. 35
4.12.1 SPI Mode ............................................................................................................................. 35
4.12.2 I²C Mode .............................................................................................................................. 36
4.13 Interrupts and Overflow ................................................................................................................ 37
4.14 Reset ............................................................................................................................................ 38
4.15 Synchronization of Multiple Devices ............................................................................................. 38
4.16 Grounding and Power Supply Decoupling .................................................................................... 38
5. REGISTER QUICK REFERENCE ........................................................................................................ 39
6. REGISTER DESCRIPTION .................................................................................................................. 40
6.1 Chip ID - Register 01h .................................................................................................................... 40
6.2 Power Control - Address 02h ......................................................................................................... 40
6.2.1 Freeze (Bit 7) ......................................................................................................................... 40
6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 40
6.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 40
DS656F2
3
CS4245
6.2.4 Power-Down DAC (Bit 1) ....................................................................................................... 41
6.2.5 Power-Down Device (Bit 0) ................................................................................................... 41
6.3 DAC Control - Address 03h ............................................................................................................ 41
6.3.1 DAC Functional Mode (Bits 7:6) ............................................................................................ 41
6.3.2 DAC Digital Interface Format (Bits 5:4) ................................................................................. 41
6.3.3 Mute DAC (Bit 2) ................................................................................................................... 41
6.3.4 De-Emphasis Control (Bit 1) .................................................................................................. 42
6.3.5 DAC Master / Slave Mode (Bit 0) .......................................................................................... 42
6.4 ADC Control - Address 04h ............................................................................................................ 42
6.4.1 ADC Functional Mode (Bits 7:6) ............................................................................................ 42
6.4.2 ADC Digital Interface Format (Bit 4) ...................................................................................... 43
6.4.3 Mute ADC (Bit 2) ................................................................................................................... 43
6.4.4 ADC High-Pass Filter Freeze (Bit 1) ..................................................................................... 43
6.4.5 ADC Master / Slave Mode (Bit 0) .......................................................................................... 43
6.5 MCLK Frequency - Address 05h .................................................................................................... 43
6.5.1 Master Clock 1 Frequency (Bits 6:4) ..................................................................................... 43
6.5.2 Master Clock 2 Frequency (Bits 2:0) ..................................................................................... 44
6.6 Signal Selection - Address 06h ...................................................................................................... 44
6.6.1 Auxiliary Output Source Select (Bits 6:5) .............................................................................. 44
6.6.2 Digital Loopback (Bit 1) ......................................................................................................... 44
6.6.3 Asynchronous Mode (Bit 0) ................................................................................................... 44
6.7 Channel B PGA Control - Address 07h .......................................................................................... 45
6.7.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 45
6.8 Channel A PGA Control - Address 08h .......................................................................................... 45
6.8.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 45
6.9 ADC Input Control - Address 09h ................................................................................................... 45
6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 45
6.9.2 Analog Input Selection (Bits 2:0) ........................................................................................... 46
6.10 DAC Channel A Volume Control - Address 0Ah ........................................................................... 46
6.11 DAC Channel B Volume Control - Address 0Bh ........................................................................... 46
6.11.1 Volume Control (Bits 7:0) .................................................................................................... 46
6.12 DAC Control 2 - Address 0Ch ...................................................................................................... 47
6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6) ................................................................ 47
6.12.2 Invert DAC Output (Bit 5) .................................................................................................... 47
6.12.3 Active High/Low (Bit 0) ........................................................................................................ 48
6.13 Interrupt Status - Address 0Dh ..................................................................................................... 48
6.13.1 ADC Clock Error (Bit 3) ....................................................................................................... 48
6.13.2 DAC Clock Error (Bit 2) ....................................................................................................... 48
6.13.3 ADC Overflow (Bit 1) ........................................................................................................... 48
6.13.4 ADC Underflow (Bit 0) ......................................................................................................... 48
6.14 Interrupt Mask - Address 0Eh ....................................................................................................... 48
6.15 Interrupt Mode MSB - Address 0Fh .............................................................................................. 49
6.16 Interrupt Mode LSB - Address 10h ............................................................................................... 49
7. PARAMETER DEFINITIONS ................................................................................................................ 50
8. DAC FILTER PLOTS
.................................................................................................................... 51
9. ADC FILTER PLOTS ......................................................................................................................... 53
10. PACKAGE DIMENSIONS .................................................................................................................. 55
11. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................. 55
12. ORDERING INFORMATION
..................................................................................................... 56
13. REVISION HISTORY .......................................................................................................................... 56
LIST OF FIGURES
Figure 1.DAC Output Test Load ................................................................................................................ 11
4
DS656F2
CS4245
Figure 2.Maximum DAC Loading .............................................................................................................. 11
Figure 3.Master Mode Timing - Serial Audio Port 1 .................................................................................. 22
Figure 4.Slave Mode Timing - Serial Audio Port 1 .................................................................................... 22
Figure 5.Master Mode Timing - Serial Audio Port 2 .................................................................................. 24
Figure 6.Slave Mode Timing - Serial Audio Port 2 .................................................................................... 24
Figure 7.Format 0, Left-Justified up to 24-Bit Data ................................................................................... 25
Figure 8.Format 1, I²S up to 24-Bit Data ................................................................................................... 25
Figure 9.Format 2, Right-Justified 16-Bit Data.
Format 3, Right-Justified 24-Bit Data. ....................................................................................................... 25
Figure 10.Control Port Timing - I²C Format ............................................................................................... 26
Figure 11.Control Port Timing - SPI Format .............................................................................................. 27
Figure 12.Typical Connection Diagram ..................................................................................................... 28
Figure 13.Master Mode Clocking .............................................................................................................. 30
Figure 14.Analog Input Architecture .......................................................................................................... 32
Figure 15.De-Emphasis Curve .................................................................................................................. 34
Figure 16.Suggested Active-Low Mute Circuit .......................................................................................... 35
Figure 17.Control Port Timing in SPI Mode .............................................................................................. 36
Figure 18.Control Port Timing, I²C Write ................................................................................................... 36
Figure 19.Control Port Timing, I²C Read ................................................................................................... 37
Figure 20.De-Emphasis Curve .................................................................................................................. 42
Figure 21.DAC Single-Speed Stopband Rejection ................................................................................... 51
Figure 22.DAC Single-Speed Transition Band .......................................................................................... 51
Figure 23.DAC Single-Speed Transition Band .......................................................................................... 51
Figure 24.DAC Single-Speed Passband Ripple ........................................................................................ 51
Figure 25.DAC Double-Speed Stopband Rejection .................................................................................. 51
Figure 26.DAC Double-Speed Transition Band ........................................................................................ 51
Figure 27.DAC Double-Speed Transition Band ........................................................................................ 52
Figure 28.DAC Double-Speed Passband Ripple ...................................................................................... 52
Figure 29.DAC Quad-Speed Stopband Rejection ..................................................................................... 52
Figure 30.DAC Quad-Speed Transition Band ........................................................................................... 52
Figure 31.DAC Quad-Speed Transition Band ........................................................................................... 52
Figure 32.DAC Quad-Speed Passband Ripple ......................................................................................... 52
Figure 33.ADC Single-Speed Stopband Rejection ................................................................................... 53
Figure 34.ADC Single-Speed Stopband Rejection ................................................................................... 53
Figure 35.ADC Single-Speed Transition Band (Detail) ............................................................................. 53
Figure 36.ADC Single-Speed Passband Ripple ........................................................................................ 53
Figure 37.ADC Double-Speed Stopband Rejection .................................................................................. 53
Figure 38.ADC Double-Speed Stopband Rejection .................................................................................. 53
Figure 39.ADC Double-Speed Transition Band (Detail) ............................................................................ 54
Figure 40.ADC Double-Speed Passband Ripple ...................................................................................... 54
Figure 41.ADC Quad-Speed Stopband Rejection ..................................................................................... 54
Figure 42.ADC Quad-Speed Stopband Rejection ..................................................................................... 54
Figure 43.ADC Quad-Speed Transition Band (Detail) .............................................................................. 54
Figure 44.ADC Quad-Speed Passband Ripple ......................................................................................... 54
LIST OF TABLES
Table 1. Speed Modes .............................................................................................................................. 29
Table 2. Common Clock Frequencies ....................................................................................................... 30
Table 3. Slave Mode Serial Bit Clock Ratios ............................................................................................. 31
Table 4. Device Revision .......................................................................................................................... 40
Table 5. Freeze-able Bits .......................................................................................................................... 40
Table 6. Functional Mode Selection ......................................................................................................... 41
Table 7. DAC Digital Interface Formats .................................................................................................... 41
DS656F2
5
CS4245
Table 8. De-Emphasis Control .................................................................................................................. 42
Table 9. Functional Mode Selection .......................................................................................................... 42
Table 10. ADC Digital Interface Formats .................................................................................................. 43
Table 11. MCLK 1 Frequency ................................................................................................................... 43
Table 12. MCLK 2 Frequency ................................................................................................................... 44
Table 13. Auxiliary Output Source Selection ............................................................................................. 44
Table 14. Example Gain and Attenuation Settings ................................................................................... 45
Table 15. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 46
Table 16. Analog Input Multiplexer Selection ............................................................................................ 46
Table 17. Digital Volume Control Example Settings ................................................................................. 47
Table 18. DAC Soft Cross or Zero Cross Mode Selection ........................................................................ 47
6
DS656F2
CS4245
SDIN
SCLK2
LRCK2
MCLK2
SDOUT
SCLK1
LRCK1
MCLK1
DGND
VD
INT
OVFL
1. PIN DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
SDA/CDOUT
1
36
VLS
SCL/CCLK
2
35
MUTEC
AD0/CS
3
34
AOUTB
AD1/CDIN
4
33
AOUTA
VLC
5
32
AGND
RESET
6
31
AGND
AIN3A
7
30
VA
AIN3B
8
29
AUXOUTB
AIN2A
9
28
AUXOUTA
AIN2B
10
27
AIN6B
AIN1A
11
26
AIN6A
AIN1B
12
25
MICBIAS
CS4245
AIN5B
AIN5A
AIN4B/MICIN2
AIN4A/MICIN1
FILT2+
FILT1+
VQ2
VQ1
AFILTB
AFILTA
VA
AGND
13 14 15 16 17 18 19 20 21 22 23 24
Pin Name
#
Pin Description
SDA/CDOUT
1
Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDOUT is the output data line for
the control port interface in SPI Mode.
SCL/CCLK
2
Serial Control Port Clock (Input) - Serial clock for the serial control port.
AD0/CS
3
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode;
CS is the chip-select signal for SPI format.
AD1/CDIN
4
Address Bit 1 (I²C) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in I²C Mode;
CDIN is the input data line for the control port interface in SPI Mode.
VLC
5
Control Port Power (Input) - Determines the required signal level for the control port interface. Refer
to the Recommended Operating Conditions for appropriate voltages.
RESET
6
Reset (Input) - The device enters a low power mode when this pin is driven low.
AIN3A
AIN3B
7, 8
Stereo Analog Input 3 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
AIN2A
AIN2B
9, 10
Stereo Analog Input 2 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
AIN1A
AIN1B
11, 12
Stereo Analog Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
DS656F2
7
CS4245
AGND
13
Analog Ground (Input) - Ground reference for the internal analog section.
VA
14
Analog Power (Input) - Positive power for the internal analog section.
AFILTA
15
Antialias Filter Connection (Output) - Antialias filter connection for the channel A ADC input.
AFILTB
16
Antialias Filter Connection (Output) - Antialias filter connection for the channel B ADC input.
VQ1
17
Quiescent Voltage 1 (Output) - Filter connection for the internal quiescent reference voltage.
VQ2
18
Quiescent Voltage 2 (Output) - Filter connection for the internal quiescent reference voltage.
FILT1+
19
Positive Voltage Reference 1 (Output) - Positive reference voltage for the internal sampling circuits.
FILT2+
20
Positive Voltage Reference 2 (Output) - Positive reference voltage for the internal sampling circuits.
AIN4A/MICIN1
Stereo Analog Input 4 / Microphone Input 1 & 2 (Input) - The full-scale level is specified in the ADC
21, 22
AIN4B/MICIN2
Analog Characteristics specification table.
AIN5A
AIN5B
MICBIAS
23, 24
25
Stereo Analog Input 5 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
Microphone Bias Supply (Output) - Low-noise bias supply for external microphone. Electrical characteristics are specified in the DC Electrical Characteristics specification table.
AIN6A
AIN6B
26, 27
Stereo Analog Input 6 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
AUXOUTA
AUXOUTB
28, 29
Auxiliary Analog Audio Output (Output) - Analog output from either the DAC, the PGA block, or high
impedance. See “Auxiliary Output Source Select (Bits 6:5)” on page 45.
VA
30
Analog Power (Input) - Positive power for the internal analog section.
AGND
31, 32 Analog Ground (Input) - Ground reference for the internal analog section.
AOUTA
AOUTB
33, 34
MUTEC
35
Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master
clock to left/right clock frequency ratio is incorrect, or power-down.
VLS
36
Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages.
SDIN
37
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK2
38
Serial Port 2 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 2.
LRCK2
39
Serial Port 2 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
active on the serial audio input data line.
MCLK2
40
Master Clock 2 (Input) - Optional asynchronous clock source for the DAC’s delta-sigma modulators.
SDOUT
41
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
SCLK1
42
Serial Port 1 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 1.
LRCK1
43
Serial Port 1 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
active on the serial audio output data line.
MCLK1
44
Master Clock 1 (Input) - Clock source for the ADC’s delta-sigma modulators. By default, this signal
also clocks the DAC’s delta-sigma modulators.
DGND
45
Digital Ground (Input) - Ground reference for the internal digital section.
VD
46
Digital Power (Input) - Positive power for the internal digital section.
INT
47
Interrupt (Output) - Indicates an interrupt condition has occurred.
OVFL
48
ADC Overflow (Output) - Indicates an ADC overflow condition is present.
8
DAC Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table.
DS656F2
CS4245
2. CHARACTERISTICS AND SPECIFICATIONS
SPECIFIED OPERATING CONDITIONS
AGND = DGND = 0 V; All voltages with respect to ground.
Parameters
Symbol
Min
Nom
Max
Units
Analog
Digital
Logic - Serial Port
Logic - Control Port
Ambient Operating Temperature (Power Applied)
Commercial
Automotive
VA
VD
VLS
VLC
TA
TA
3.13
3.13
1.71
1.71
-10
-40
5.0
3.3
3.3
3.3
-
5.25
(Note 1)
5.25
5.25
+70
+105
V
V
V
V
°C
°C
DC Power Supplies:
Notes:
1. Maximum of VA+0.25 V or 5.25 V, whichever is less.
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V All voltages with respect to ground. (Note 2)
Parameter
DC Power Supplies:
Input Current
Analog
Digital
Logic - Serial Port
Logic - Control Port
(Note 3)
Analog Input Voltage
Symbol
Min
Max
Units
VA
VD
VLS
VLC
Iin
-0.3
-0.3
-0.3
-0.3
+6.0
+6.0
+6.0
+6.0
V
V
V
V
-
±10
mA
VINA
AGND-0.3
VA+0.3
V
VIND-S
VIND-C
-0.3
-0.3
VLS+0.3
VLC+0.3
V
V
Ambient Operating Temperature (Power Applied)
TA
-50
+125
°C
Storage Temperature
Tstg
-65
+150
°C
Digital Input Voltage
Logic - Serial Port
Logic - Control Port
2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
DS656F2
9
CS4245
DAC ANALOG CHARACTERISTICS
Test Conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; TA = -10° to +70° C for Commercial or -40° to
+85° C for Automotive; Output test signal: 997 Hz full-scale sine wave; Test load RL = 3 kΩ, CL = 10 pF (see
Figure 1), Fs = 48/96/192 kHz. Measurement Bandwidth 10 Hz to 20 kHz Synchronous mode; All Connections as
shown in Figure 12 on page 29.
Commercial Grade
Parameter
Symbol
Automotive Grade
Min
Typ
Max
Min
Typ
Max
Unit
98
95
90
87
104
101
96
93
-
96
93
88
85
104
101
96
93
-
dB
dB
dB
dB
-
-90
-81
-41
-93
-73
-33
-84
-87
-
-
-90
-81
-41
-93
-73
-33
-82
-85
-
dB
dB
dB
dB
dB
dB
95
92
88
85
101
98
93
90
-
93
90
86
83
101
98
93
90
-
dB
dB
dB
dB
-
-87
-78
-38
-90
-70
-30
-79
-82
-
-
-87
-78
-38
-90
-70
-30
-77
-80
-
dB
dB
dB
dB
dB
dB
-
100
-
-
100
-
dB
Interchannel Gain Mismatch
-
0.1
0.25
-
0.1
0.25
dB
Gain Drift
-
100
-
-
100
-
ppm/°C
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range
18 to 24-Bit
16-Bit
(Note 4)
A-Weighted
unweighted
A-Weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
(Note 4)
0 dB
-20 dB
-60 dB THD+N
0 dB
-20 dB
-60 dB
16-Bit
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
18 to 24-Bit
16-Bit
(Note 4)
A-Weighted
unweighted
A-Weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
Interchannel Isolation
(Note 4)
0 dB
-20 dB
-60 dB THD+N
0 dB
-20 dB
-60 dB
(1 kHz)
DC Accuracy
Analog Output
Full Scale Output Voltage
0.60*VA 0.65*VA 0.70*VA 0.60*VA 0.65*VA 0.70*VA
Vpp
DC Current draw from an AOUT pin
(Note 5)
IOUT
-
-
10
-
-
10
μA
AC-Load Resistance
(Note 6)
RL
3
-
-
3
-
-
kΩ
Load Capacitance
(Note 6)
CL
-
-
100
-
-
100
pF
ZOUT
-
150
-
-
150
-
Ω
Output Impedance
4. One-half LSB of triangular PDF dither added to data.
5. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin
due to typical leakage through the electrolytic DC blocking capacitors.
10
DS656F2
CS4245
6. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and
maximum capacitance required for the internal op-amp’s stability. CL affects the dominant pole of the
internal output amp; increasing CL beyond 100 pF can cause the internal op-amp to become unstable.
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 7,10)
Symbol
Combined Digital and On-chip Analog Filter Response
Passband (Note 7)
Min
Typ
Max
Unit
Single-Speed Mode
to -0.1 dB corner
to -3 dB corner
0
0
-
0.35
0.4992
Fs
Fs
Frequency Response 10 Hz to 20 kHz
-0.175
-
+0.01
dB
StopBand
0.5465
-
-
Fs
50
-
-
dB
-
10/Fs
-
s
-
-
+0.05/-0.25
dB
StopBand Attenuation
(Note 8)
Group Delay
De-emphasis Error (Note 9)
tgd
Fs = 44.1 kHz
Combined Digital and On-chip Analog Filter Response
Passband (Note 7)
Double-Speed Mode
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
(Note 8)
Group Delay
tgd
0
0
-
0.22
0.501
Fs
Fs
-0.15
-
+0.15
dB
0.5770
-
-
Fs
55
-
-
dB
-
5/Fs
-
s
Combined Digital and On-chip Analog Filter Response
Quad-Speed Mode
Passband (Note 7)
0
0
-
0.110
0.469
Fs
Fs
-0.12
-
0
dB
0.7
-
-
Fs
51
-
-
dB
-
2.5/Fs
-
s
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
(Note 8)
Group Delay
tgd
7. Filter response is guaranteed by design.
8. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.
9. De-emphasis is available only in Single-Speed Mode.
10. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this
data (Figures 21 to 30) have been normalized to Fs and can be de-normalized by multiplying the X-axis
scale by Fs.
DS656F2
11
CS4245
3.3 µF
V
out
AOUTx
R
L
AGND
C
L
Capacitive Load -- C L (pF)
125
100
75
25
2.5
3
Figure 1. DAC Output Test Load
12
Safe Operating
Region
50
5
10
15
20
Resistive Load -- RL (kΩ )
Figure 2. Maximum DAC Loading
DS656F2
CS4245
ADC ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; TA = -10° to +70° C for Commercial or -40° to
+85° C for Automotive; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz;
Fs = 48/96/192 kHz. Synchronous mode; All connections as shown in Figure 12 on page 29.
Line-Level Inputs
Commercial Grade
Parameter
Symbol
Dynamic Performance for VA = 4.75 V to 5.25 V
Automotive Grade
Min
Typ
Max
Min
Typ
Max
Unit
98
95
-
104
101
98
-
96
93
-
104
101
98
-
dB
dB
dB
92
89
-
98
95
92
-
90
87
-
98
95
92
-
dB
dB
dB
-
-95
-81
-41
-92
-89
-
-
-95
-81
-41
-92
-87
-
dB
dB
dB
dB
-
-92
-75
-35
-89
-86
-
-
-92
-75
-35
-89
-84
-
dB
dB
dB
dB
93
90
-
101
98
95
-
91
88
-
101
98
95
-
dB
dB
dB
89
86
-
95
92
89
-
87
84
-
95
92
89
-
dB
dB
dB
-
-92
-78
-38
-84
-86
-
-
-92
-78
-38
-84
-84
-
dB
dB
dB
dB
-
-89
-72
-32
-81
-83
-
-
-89
-72
-32
-81
-81
-
dB
dB
dB
dB
Dynamic Range
(Note 13)
(Note 13)
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
(Note 12)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 13)
40 kHz bandwidth
-1 dB THD+N
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 13)
40 kHz bandwidth
-1 dB
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
(Note 13)
(Note 13)
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
(Note 12)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 13)
40 kHz bandwidth
-1 dB THD+N
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 13)
40 kHz bandwidth
-1 dB
DS656F2
13
CS4245
Line-Level Inputs
Commercial Grade
Parameter
Symbol
Interchannel Isolation
Automotive Grade
Min
Typ
Max
Min
Typ
Max
Unit
-
90
-
-
90
-
dB
-
±100
-
±10
-
-
±100
-
±10
-
%
ppm/°C
DC Accuracy
Gain Error
Gain Drift
Line-Level Input Characteristics
Full-scale Input Voltage
Input Impedance
(Note 11)
Maximum Interchannel Input Impedance
Mismatch
0.51*VA 0.57*VA 0.63*VA 0.51*VA 0.57*VA 0.63*VA
6.12
6.8
7.48
5.44
6.8
8.16
-
5
-
-
5
-
Vpp
kΩ
%
Line-Level and Microphone-Level Inputs
Commercial Grade
Parameter
Symbol
Automotive Grade
Min
Typ
Max
Min
Typ
Max
Unit
-
0.1
-
-
0.1
-
dB
-
0.5
-
0.4
-
0.5
-
0.4
dB
dB
DC Accuracy
Interchannel Gain Mismatch
Programmable Gain Characteristics
Gain Step Size
Absolute Gain Step Error
11. Valid for the selected input pair.
14
DS656F2
CS4245
ADC ANALOG CHARACTERISTICS
(Continued)
Microphone-Level Inputs
Commercial Grade
Parameter
Symbol
Dynamic Performance for VA = 4.75 V to 5.25 V
Automotive Grade
Min
Typ
Max
Min
Typ
Max
Unit
77
74
83
80
-
75
72
83
80
-
dB
dB
65
62
71
68
-
63
60
71
68
-
dB
dB
-
-80
-60
-20
-74
-
-
-80
-60
-20
-72
-
dB
dB
dB
-
-68
-
-
-68
-
dB
77
74
83
80
-
75
72
83
80
-
dB
dB
65
62
71
68
-
63
60
71
68
-
dB
dB
-
-80
-60
-20
-74
-
-
-80
-60
-20
-72
-
dB
dB
dB
-
-68
80
-
-
-68
80
-
dB
dB
-
±300
±5
-
-
±300
±5
-
%
ppm/°C
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 12)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
THD+N
-60 dB
PGA Setting: +12 dB
-1 dB
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 12)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
THD+N
-60 dB
PGA Setting: +12 dB
-1 dB
Interchannel Isolation
DC Accuracy
Gain Error
Gain Drift
Microphone-Level Input Characteristics
Full-scale Input Voltage
Input Impedance
(Note 14)
0.013*VA 0.017*VA 0.021*VA 0.013*VA 0.017*VA 0.021*VA
60
60
-
Vpp
kΩ
12. Referred to the typical line-level full-scale input voltage
13. Valid for Double- and Quad-Speed Modes only.
14. Valid when the microphone-level inputs are selected.
DS656F2
15
CS4245
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Notes 15, 17)
Symbol
Min
Typ
Max
Unit
0
-
0.4896
Fs
-
-
0.035
dB
0.5688
-
-
Fs
70
-
-
dB
-
12/Fs
-
s
0
-
0.4896
Fs
-
-
0.025
dB
Single-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
tgd
Double-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
tgd
0.5604
-
-
Fs
69
-
-
dB
-
9/Fs
-
s
0
-
0.2604
Fs
-
-
0.025
dB
Quad-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
tgd
0.5000
-
-
Fs
60
-
-
dB
-
5/Fs
-
s
-
1
20
-
Hz
Hz
-
10
-
Deg
-
0
dB
High-Pass Filter Characteristics
Frequency Response
Phase Deviation
-3.0 dB
-0.13 dB
(Note 16)
@ 20 Hz
(Note 16)
Passband Ripple
Filter Settling Time
-
105/Fs
s
15. Filter response is guaranteed by design.
16. Response shown is for Fs = 48 kHz.
17. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 33 to 44) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
16
DS656F2
CS4245
AUXILIARY OUTPUT ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; TA = -10° to +70° C for Commercial or -40° to
+85° C for Automotive; Input test signal: 1 kHz sine wave; Measurement bandwidth: 10 Hz to 20 kHz;
Fs = 48/96/192 kHz; Synchronous mode; All connections as shown in Figure 12 on page 29.
VA = 4.75 V to 5.25 V
Commercial Grade
Parameter
Symbol Min
Typ
Max
Dynamic Performance with PGA Output Selected, Line Level Input
Automotive Grade
Min
Typ
Max
Unit
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 19)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB THD+N
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
98
95
104
101
-
96
93
104
101
-
dB
dB
92
89
98
95
-
90
87
98
95
-
dB
dB
-
-80
-81
-41
-74
-
-
-80
-81
-41
-72
-
dB
dB
dB
-
-80
-75
-35
-74
-
-
-80
-75
-35
-72
-
dB
dB
dB
Dynamic Performance with PGA Output Selected, Mic Level Input
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 19)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB THD+N
-60 dB
PGA Setting: +12 dB
-1 dB
77
74
83
80
-
75
72
83
80
-
dB
dB
65
62
71
68
-
63
60
71
68
-
dB
dB
-
-74
-60
-20
-68
-
-
-74
-60
-20
-66
-
dB
dB
dB
-
-68
-
-
-68
-
dB
98
95
90
87
104
101
96
93
-
96
93
88
85
104
101
96
93
-
dB
dB
dB
dB
-
-80
-81
-41
-80
-73
-33
-74
-74
-
-
-80
-81
-41
-80
-73
-33
-72
-72
-
dB
dB
dB
dB
dB
dB
Dynamic Performance with DAC Output Selected
Dynamic Range
18 to 24-Bit
(Notes 18)
A-weighted
unweighted
16-Bit
A-Weighted
unweighted
Total Harmonic Distortion + Noise (Notes 18, 20)
18 to 24-Bit
0 dB
-20 dB
-60 dB THD+N
16-Bit
0 dB
-20 dB
-60 dB
DS656F2
17
CS4245
AUXILIARY OUTPUT ANALOG CHARACTERISTICS
(Continued)
VA = 3.13 V to 3.46 V
Commercial Grade
Parameter
Symbol Min
Typ
Max
Dynamic Performance with PGA Output Selected, Line Level Input
Automotive Grade
Min
Typ
Max
Unit
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 19)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB THD+N
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
93
90
101
98
-
91
88
101
98
-
dB
dB
89
86
95
92
-
87
84
95
92
-
dB
dB
-
-80
-78
-38
-74
-
-
-80
-78
-38
-72
-
dB
dB
dB
-
-80
-72
-32
-74
-
-
-80
-72
-32
-72
-
dB
dB
dB
Dynamic Performance with PGA Output Selected, Mic Level Input
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 19)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB THD+N
-60 dB
PGA Setting: +12 dB
-1 dB
77
74
83
80
-
75
72
83
80
-
dB
dB
65
62
71
68
-
63
60
71
68
-
dB
dB
-
-74
-60
-20
-68
-
-
-74
-60
-20
-66
-
dB
dB
dB
-
-68
-
-
-68
-
dB
95
92
88
85
101
98
93
90
-
93
90
86
83
101
98
93
90
-
dB
dB
dB
dB
-
-80
-78
-38
-80
-70
-30
-74
-74
-
-
-80
-78
-38
-80
-70
-30
-72
-72
-
dB
dB
dB
dB
dB
dB
Dynamic Performance with DAC Output Selected
Dynamic Range
18 to 24-Bit
(Notes 18)
A-Weighted
unweighted
16-Bit
A-Weighted
unweighted
Total Harmonic Distortion + Noise (Notes 18, 20)
18 to 24-Bit
0 dB
-20 dB
-60 dB THD+N
16-Bit
0 dB
-20 dB
-60 dB
18. One-half LSB of triangular PDF dither added to data.
19. Referred to the typical Line-Level Full-Scale Input Voltage.
18
DS656F2
CS4245
20. Referred to the typical DAC Full-Scale Output Voltage.
AUXILIARY OUTPUT ANALOG CHARACTERISTICS
(Continued)
VA = 3.13 V to 5.25 V
Commercial Grade
Automotive Grade
Parameter
Symbol Min
DC Accuracy with PGA Output Selected, Line Level Input
Typ
Max
Min
Typ
Max
Unit
Interchannel Gain Mismatch
Gain Error
Gain Drift
-
0.1
±5
±100
-
-
0.1
±5
±100
-
dB
%
ppm/°C
-
0.3
±5
±300
-
-
0.3
±5
±300
-
dB
%
ppm/°C
-
±100
0.1
-
-
±100
0.1
-
dB
ppm/°C
-0.1dB
100
-
180
-
180
-
+0.1dB
1
20
dB
deg
μA
kΩ
pF
DC Accuracy with PGA Output Selected, Mic Level Input
Interchannel Gain Mismatch
Gain Error
Gain Drift
DC Accuracy with DAC Output Selected
Interchannel Gain Mismatch
Gain Drift
Analog Output
Frequency Response 10 Hz to 20 kHz
Analog In to Analog Out Phase Shift
DC Current draw from an AUXOUT pin
AC-Load Resistance
Load Capacitance
(Note 22)
(Note 21)
IOUT
RL
CL
+0.1dB -0.1dB
1
100
20
-
21. Valid only when PGA output is selected.
22. Guaranteed by design.
DS656F2
19
CS4245
DC ELECTRICAL CHARACTERISTICS
AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode.
Parameter
Symbol
Min
Typ
Max
Unit
V
V
V
V
IA
IA
ID
ID
-
41
37
39
23
50
45
47
28
mA
mA
mA
mA
VA = 5 V
VLS, VLC, VD=5 V
IA
ID
-
0.50
0.54
-
mA
mA
Power Consumption
(Normal Operation)
VA, VD, VLS, VLC = 5 V
(Power-Down Mode)
VA, VD, VLS, VLC = 3.3 V
VA, VD, VLS, VLC = 5 V
-
-
400
198
4.2
485
241
-
mW
mW
mW
PSRR
-
55
-
dB
VQ1
-
0.5 x VA
-
VDC
IQ1
-
-
1
μA
ZQ1
-
23
-
kΩ
VQ2
-
0.5 x VA
-
VDC
IQ2
-
-
1
μA
VQ2 Output Impedance
ZQ2
-
4.5
-
kΩ
FILT1+ Nominal Voltage
FILT1+
-
VA
-
VDC
FILT2+ Nominal Voltage
FILT2+
-
VA
-
VDC
Microphone Bias Voltage
MICBIAS
-
0.8 x VA
-
VDC
IMB
-
-
2
mA
Power Supply Current
(Normal Operation)
VA = 5
VA = 3.3
VD, VLS, VLC = 5
VD, VLS, VLC = 3.3
Power Supply Current
(Power-Down Mode) (Note 23)
Power Supply Rejection Ratio (1 kHz)
(Note 24)
VQ Characteristics
Quiescent Voltage 1
DC Current from VQ1
(Note 25)
VQ1 Output Impedance
Quiescent Voltage 2
DC Current from VQ2
Current from MICBIAS
(Note 25)
23. Power-Down Mode is defines as RESET = Low with all clock and data lines held static and no analog
input.
24. Valid with the recommended capacitor values on FILT1+, FILT2+, VQ1 and VQ2 as shown in the Typical Connection Diagram.
25. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage
through the electrolytic de-coupling capacitors.
20
DS656F2
CS4245
DIGITAL INTERFACE CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 1.71 V to 5.25 V.
Parameters (Note 26)
Symbol
Min
Typ
Max
Units
VIH
VIH
VIH
VIH
VIL
VIL
VOH
VOH
VOH
VOL
VOL
VOL
Iin
0.8xVLS
0.8xVLC
0.7xVLS
0.7xVLC
VLS-1.0
VLC-1.0
VA-1.0
-
3
0.2xVLS
0.2xVLC
0.4
0.4
0.4
±10
1
-
V
V
V
V
V
V
V
V
V
V
V
V
μA
pF
mA
-
-
μs
High-Level Input Voltage
VL = 1.71 V
VL > 2.0 V
Low-Level Input Voltage
High-Level Output Voltage at Io = 2 mA
Low-Level Output Voltage at Io = 2 mA
Input Leakage Current
Input Capacitance
Maximum MUTEC Drive Current
Minimum OVFL Active Time
Serial Port
Control Port
Serial Port
Control Port
Serial Port
Control Port
Serial Port
Control Port
MUTEC
Serial Port
Control Port
MUTEC
(Note 27)
6
10
-------------------LRCK1
26. Serial Port signals include: MCLK1, MCLK2, SCLK1, SCLK2, LRCK1, LRCK2, SDIN, SDOUT.
Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, RESET, INT, OVFL.
27. Guaranteed by design.
DS656F2
21
CS4245
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 1
Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, CL = 20 pF. (Note 28)
Parameter
Sample Rate
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Symbol
Min
Typ
Max
Unit
Fs
Fs
Fs
4
50
100
-
50
100
200
kHz
kHz
kHz
fmclk
tclkhl
1.024
8
-
51.200
-
MHz
ns
tslr
tsdo
-10
0
50
50
-
10
36
%
%
ns
ns
40
50
60
%
-
-
ns
-
-
ns
MCLK Specifications
MCLK1 Input Frequency
MCLK1 Input Pulse Width High/Low
Master Mode
LRCK1 Duty Cycle
SCLK1 Duty Cycle
SCLK1 falling to LRCK1 edge
SCLK1 falling to SDOUT valid
Slave Mode
LRCK1 Duty Cycle
SCLK1 Period
9
Single-Speed Mode
tsclkw
10
--------------------( 128 )Fs
Double-Speed Mode
tsclkw
10
-----------------( 64 )Fs
Quad-Speed Mode
tsclkw
10
-----------------( 64 )Fs
-
-
ns
tsclkh
tsclkl
tslr
tsdo
30
48
-10
0
-
10
36
ns
ns
ns
ns
SCLK1 Pulse Width High
SCLK1 Pulse Width Low
SCLK1 falling to LRCK1 edge
SCLK1 falling to SDOUT valid
9
9
28. See Figure 3 and Figure 4 on page 23.
22
DS656F2
CS4245
LRCK1
Output
t
slr
SCLK1
Output
t
sdo
SDOUT
Figure 3. Master Mode Timing - Serial Audio Port 1
LRCK1
Input
t
slr
t
sclkh
t
sclkl
SCLK1
Input
t
sdo
t
sclkw
SDOUT
Figure 4. Slave Mode Timing - Serial Audio Port 1
DS656F2
23
CS4245
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 2
Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, CL = 20 pF. (Note 29)
Parameter
Sample Rate
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Symbol
Min
Typ
Max
Unit
Fs
Fs
Fs
4
50
100
-
50
100
200
kHz
kHz
kHz
fmclk
tclkhl
1.024
8
-
51.200
-
MHz
ns
tslr
tsdis
tsdih
-10
16
20
50
50
-
10
-
%
%
ns
ns
ns
40
50
60
%
-
-
ns
-
-
ns
MCLK Specifications
MCLK2 Input Frequency
MCLK2 Input Pulse Width High/Low
Master Mode
LRCK2 Duty Cycle
SCLK2 Duty Cycle
SCLK2 falling to LRCK edge
SDIN valid to SCLK2 rising setup time
SCLK2 rising to SDIN hold time
Slave Mode
LRCK2 Duty Cycle
SCLK2 Period
9
Single-Speed Mode
tsclkw
10
--------------------( 128 )Fs
Double-Speed Mode
tsclkw
10
-----------------( 64 )Fs
Quad-Speed Mode
tsclkw
10
-----------------( 64 )Fs
-
-
ns
tsclkh
tsclkl
tslr
tsdis
tsdih
30
48
-10
16
20
-
10
-
ns
ns
ns
ns
ns
SCLK2 Pulse Width High
SCLK2 Pulse Width Low
SCLK2 falling to LRCK2 edge
SDIN valid to SCLK2 rising setup time
SCLK2 rising to SDIN hold time
9
9
29. See Figure 5 and Figure 6 on page 25.
24
DS656F2
CS4245
LRCK2
Output
t
slr
SCLK2
Output
t
sdis
t
sdih
SDIN
Figure 5. Master Mode Timing - Serial Audio Port 2
LRCK2
Input
t
t
sclkh
slr
t
sclkl
SCLK2
Input
t
sclkw
t
sdis
t
sdih
SDIN
Figure 6. Slave Mode Timing - Serial Audio Port 2
DS656F2
25
CS4245
Channel B - Right
Channel A - Left
LRCK
SCLK
SDATA
MSB -1
-2
-3
-4
-5
+5 +4
+3 +2
+1 LSB
MSB -1
-2
-3
+5
-4
+4 +3
+2 +1 LSB
Figure 7. Format 0, Left-Justified up to 24-Bit Data
Channel A - Left
LRCK
Channel B - Right
SCLK
SDATA
MSB -1
-2
-3
-4
-5
+5 +4 +3 +2 +1 LSB
MSB -1
-2
-3
+5 +4 +3 +2 +1 LSB
-4
Figure 8. Format 1, I²S up to 24-Bit Data
LRCK
Channel B - Right
Channel A - Left
SCLK
SDATA
LSB
MSB -1
-2 -3 -4 -5 -6
+6 +5 +4 +3 +2 +1 LSB
MSB -1
-2 -3 -4 -5 -6
+6 +5 +4 +3 +2 +1 LSB
Figure 9. Format 2, Right-Justified 16-Bit Data.
Format 3, Right-Justified 24-Bit Data.
26
DS656F2
CS4245
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RESET Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
-
1
µs
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 30)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
(Note 31)
trc, trd
Fall Time SCL and SDA
(Note 31)
tfc, tfd
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
30. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
31. Guaranteed by design.
RST
t
irs
Stop
R e p e ate d
Sta rt
Start
t rd
t fd
Stop
SDA
t
buf
t
t
hdst
t
high
t fc
hdst
t susp
SCL
t
lo w
t
hdd
t sud
t ack
t sust
t rc
Figure 10. Control Port Timing - I²C Format
DS656F2
27
CS4245
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF.
Parameter
Symbol
Min
Max
Units
CCLK Clock Frequency
fsck
-
6.0
MHz
RESET Rising Edge to CS Falling
tsrs
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
μs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
tdh
15
-
ns
CCLK Falling to CDOUT Stable
tpd
-
50
ns
Rise Time of CDOUT
tr1
-
25
ns
Fall Time of CDOUT
tf1
-
25
ns
CCLK Rising to DATA Hold Time
(Note 32)
Rise Time of CCLK and CDIN
(Note 33)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 33)
tf2
-
100
ns
32. Data must be held for sufficient time to bridge the transition time of CCLK.
33. For fsck <1 MHz.
t srs
RST
CS
t scl
t css
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu
t dh
t pd
CDOUT
Figure 11. Control Port Timing - SPI Format
28
DS656F2
CS4245
3. TYPICAL CONNECTION DIAGRAM
+3.3V to +5V
10 µF
VD
+1.8V
to +5V
0.1 µF
0.1 µF
0.1 µF
0.1 µF
+3.3V to +5V
10 µF
VA
VA
3.3 µF
AUXOUTA
VLS
3.3 µF
AUXOUTB
MCLK2
SCLK2
Digital Audio
Playback
Mute
Drive
MUTEC
LRCK2
3.3 µF
SDIN
AOUTA
MCLK1
SCLK1
Digital Audio
Capture
*
C
10 kΩ
*
C
AIN1A
CS4245
1800 pF *
INT
OVFL
AIN1B
R ext
Optional
Analog
Muting
R ext
470 Ω
3.3 µF
SDOUT
1800 pF
*
Left Analog Input 1
10 µF 100 Ω
100 kΩ
10 µF
100 kΩ
100 Ω
Right Analog Input 1
RESET
MicroController
AIN2A
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AIN2B
AD0/CS
AIN3A
2 kΩ
2 kΩ
See Note 1
+1.8V
to +5V
10 kΩ
AOUTB
LRCK1
See Note 2
470 Ω
VLC
AIN3B
0.1 µF
AIN4A/MICIN1
Note 1: Resistors are required for I²C control
port operation
AIN4B/MICIN2
Note 2 :
1800 pF *
1800 pF
*
1800 pF *
1800 pF
*
1800 pF *
1800 pF
*
Left Analog Input 2
10 µF 100 Ω
100 kΩ
10 µF
100 kΩ
100 Ω
Right Analog Input 2
Left Analog Input 3
10 µF 100 Ω
100 kΩ
10 µF
100 kΩ
100 Ω
Right Analog Input 3
Left Analog Input 4
10 µF 100 Ω
100 kΩ
10 µF
100 kΩ
100 Ω
Right Analog Input 4
For best response to Fs/2 :
C=
R ext + 470
4π Fs (R ext × 470 )
AIN5A
This circuitry is intended for applications where
the CS4245 connects directly to an unbalanced
output of the design . For internal routing
applications please see the DAC Analog Output
Characteristics section for loading limitations .
AIN5B
AIN6A
VQ1
FILT1+
10 µF
0.1 µF
47 µF
AIN6B
0.1 µF
0.1 µF
47 µF
0.1 µF
AGND
AGND
FILT2+
VQ2
Note 3: The value of R L is dictated by the
microphone carteridge.
1800 pF
*
1800 pF *
1800 pF
*
DGND
Left Analog Input 5
10 µF 100 Ω
100 kΩ
10 µF
100 kΩ
100 Ω
Right Analog Input 5
Left Analog Input 6
10 µF 100 Ω
100 kΩ
10 µF
100 kΩ
100 Ω
Right Analog Input 6
Note 3
MICBIAS
AGND
10 µF
1800 pF *
47 µF
*
AFILTA
AFILTB
RL
*
2.2nF 2.2nF
* Capacitors must be C0G or equivalent
Figure 12. Typical Connection Diagram
DS656F2
29
CS4245
4. APPLICATIONS
4.1
Recommended Power-Up Sequence
1. Hold RESET low until the power supply,MCLK1, MCLK2 (if used), LRCK1 and LRCK2 are stable. In this
state, the Control Port is reset to its default settings.
2. Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The control port will be accessible.
3. The desired register settings can be loaded while the PDN bit remains set.
4. Clear the PDN bit to initiate the power-up sequence.
4.2
System Clocking
The CS4245 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three
speed modes as shown in Table 1.
Mode
Sampling Frequency
Single-Speed
4-50 kHz
Double-Speed
50-100 kHz
Quad-Speed
100-200 kHz
Table 1. Speed Modes
The CS4245 has two serial ports which may be operated synchronously or asynchronously. Serial port 1
consists of the SCLK1 and LRCK1 signals and clocks the serial audio output, SDOUT. Serial port 2 consists
of the SCLK2 and LRCK2 signals and clocks the serial audio input, SDIN.
Each serial port may be independently placed into Single, Double, or Quad Speed mode. The serial ports
may also be independently placed into Master or Slave mode.
4.2.1
Synchronous / Asynchronous Mode
By default, the CS4245 operates in Synchronous Mode with both serial ports synchronous to MCLK1. In
this mode, the serial ports may operate at different synchronous rates as set by the ADC_FM and
DAC_FM bits, and MCLK2 does not need to be provided (the MCLK2 pin may be left unconnected).
If the Asynch bit is set (see “Asynchronous Mode (Bit 0)” on page 45), the CS4245 will operate in asynchronous mode. The serial ports will operate asynchronously with Serial Port 1 clocked from MCLK1 and
Serial Port 2 clocked from MCLK2. In this mode, the serial ports may operate at different asynchronous
rates.
4.2.2
Master Clock
In Asynchronous Mode, MCLK1/LRCK1 and MCLK2/LRCK2 must maintain an integer ratio. In synchronous mode MCLK1/LRCK1 and MCLK1/LRCK2 must maintain an integer ratio. Some common ratios are
shown in Table 2.The LRCK frequency is equal to Fs, the frequency at which audio samples for each
channel are clocked into or out of the device. The ADC_FM and DAC_FM bits and the MCLK Freq bits
(See “MCLK Frequency - Address 05h” on page 44.) configure the device to generate the proper clocks
30
DS656F2
CS4245
in Master Mode and receive the proper clocks in Slave Mode. Table 2 illustrates several standard audio
sample rates and the required MCLK and LRCK frequencies.
LRCK
(kHz)
MCLK (MHz)
64x
96x
128x
192x
256x
384x
512x
768x
1024x
32
-
-
-
-
8.1920
12.2880
16.3840
24.5760
32.7680
44.1
-
-
-
-
11.2896
16.9344
22.5792
33.8680
45.1584
48
-
-
-
-
12.2880
18.4320
24.5760
36.8640
49.1520
64
-
-
8.1920
12.2880
16.3840
24.5760
32.7680
-
-
88.2
-
-
11.2896
16.9344
22.5792
33.8680
45.1584
-
-
96
-
-
12.2880
18.4320
24.5760
36.8640
49.1520
-
-
128
8.1920
12.2880
16.3840
24.5760
32.7680
-
-
-
-
176.4
11.2896
16.9344
22.5792
33.8680
45.1584
-
-
-
-
192
12.2880
18.4320
24.5760
36.8640
49.1520
-
-
-
-
Mode
DSM
QSM
SSM
Table 2. Common Clock Frequencies
4.2.3
Master Mode
As a clock master, LRCK and SCLK will operate as outputs. The two serial ports may be independently
placed into Master or Slave mode. Each LRCK and SCLK is internally derived from its respective MCLK
with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 13.
MCLK1 Freq Bits
MCLK1
÷1
000
÷1.5
001
÷2
010
÷3
011
÷4
100
MCLK2 Freq Bits
÷128
01
÷64
10
LRCK1
÷4
00
÷2
01
÷1
10
÷256
00
÷128
01
÷64
10
SCLK1
ASynch Bit
÷1
000
÷1.5
001
÷2
010
÷3
011
1
÷4
00
ADC_FM Bits
0
MCLK2
÷256
LRCK2
DAC_FM Bits
÷4
00
÷2
01
÷1
10
SCLK2
100
Figure 13. Master Mode Clocking
4.2.4
Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. Each serial port may be independently placed into
Slave Mode. The Left/Right clock signal must be equal to the sample rate, Fs. If operating in Asynchronous Mode, LRCK1 must be synchronously derived from MCLK1 and LRCK2 must be synchronously derived from MCLK2. If operating in Synchronous Mode, LRCK1, and LRCK2 must be synchronously
DS656F2
31
CS4245
derived from MCLK1. For more information on Synchronous and Asynchronous Modes, see “Synchronous / Asynchronous Mode” on page 30.
For each serial port, the serial bit clock must be equal to 128x, 64x, 48x or 32x Fs, depending on the desired speed mode. If operating in Asynchronous Mode, the serial bit clock SCLK1 must be synchronously
derived from MCLK1 and SCLK2 must be synchronously derived from MCLK2. If operating in Synchronous Mode, SCLK1, and SCLK2 must be synchronously derived from MCLK1. Refer to Table 3 for required serial bit clock to Left/Right clock ratios.
SCLK/LRCK Ratio
Single-Speed
Double-Speed
Quad-Speed
32x, 48x, 64x, 128x
32x, 48x, 64x
32x, 48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
4.3
High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS4245, a small DC offset may be driven
into the A/D converter. The CS4245 includes a high-pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPFFreeze bit (See “ADC High-Pass Filter Freeze (Bit 1)” on page 44.) is set during normal operation, the current value of the DC offset for the each channel is frozen and this DC offset will continue to
be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by:
1. Running the CS4245 with the high-pass filter enabled until the filter settles. See the ADC Digital Filter
Characteristics section for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS4245.
32
DS656F2
CS4245
4.4
Analog Input Multiplexer, PGA, and Mic Gain
The CS4245 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier
(PGA). The input multiplexer can select one of six possible stereo analog input sources and route it to the
PGA. Analog inputs 4A and 4B are able to insert a +32 dB gain stage before the input multiplexer, allowing
them to be used for microphone-level signals without the need for any external gain. The PGA stage provides ±12 dB of gain or attenuation in 0.5 dB steps. Figure 14 shows the architecture of the input multiplexer, PGA, and microphone gain stages.
AIN1A
AIN2A
AIN3A
AIN4A/MICIN1
MUX
PGA
Out to ADC
Channel A
+32 dB
AIN5A
AIN6A
Channel A
PGA Gain Bits
Analog Input
Selection Bits
AIN1B
AIN2B
Channel B
PGA Gain Bits
AIN3B
AIN4B/MICIN2
MUX
PGA
Out to ADC
Channel B
+32 dB
AIN5B
AIN6B
Figure 14. Analog Input Architecture
The ““Analog Input Selection (Bits 2:0)” on page 47” outlines the bit settings necessary to control the input
multiplexer and mic gain. “Channel B PGA Control - Address 07h” on page 46 and “Channel A PGA Control
- Address 08h” on page 46 outline the register settings necessary to control the PGA. By default, linelevel input 1 is selected, and the PGA is set to 0 dB.
4.5
Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are
(n × 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram
for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capacitors which have a large voltage coefficient (such as general-purpose ceramics) must be avoided since
these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
4.6
Output Connections
The CS4245 DACs implement a switched-capacitor filter, followed by a continuous time low-pass filter. Its
response, combined with that of the digital interpolator, is shown in Section 8. “DAC Filter Plots” on
page 52”. The recommended external analog circuitry is shown in the Typical Connection Diagram.
The CS4245 DAC does not include phase or amplitude compensation for an external filter. Therefore, the
DAC system phase and amplitude response is dependent on the external analog circuitry.
DS656F2
33
CS4245
4.7
Output Transient Control
The CS4245 uses Popguard® technology to minimize the effects of output transients during power-up and
power-down. This technique eliminates the audio transients commonly produced by single-ended, singlesupply converters when it is implemented with external DC-blocking capacitors connected in series with the
audio outputs. To make best use of this feature, it is necessary to understand its operation.
4.7.1
Power-Up
When the device is initially powered-up, the audio outputs AOUTA and AOUTB are clamped to VQ2,
which is initially low. After the PDN bit is released (set to ‘0’), the DAC outputs begin to ramp with VQ2
towards the nominal quiescent voltage. This ramp takes approximately 200 ms to complete. The gradual
voltage ramping allows time for the external DC-blocking capacitors to charge to VQ2, effectively blocking
the quiescent DC voltage. Audio output will begin after approximately 2000 sample periods.
4.7.2
Power-Down
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turning off the power. In order to do this, either the PDN bit should be set or the device should be reset about
250 ms before removing power. During this time, the voltage on VQ2 and the DAC outputs discharge
gradually to GND. If power is removed before this 250 ms time period has passed, a transient will occur
when the VA supply drops below that of VQ2. There is no minimum time for a power cycle; power may be
re-applied at any time.
4.7.3
Serial Interface Clock Changes
When changing the DAC clock ratio or sample rate, it is recommended that zero data (or near zero data)
be present on SDIN for at least 10 LRCK samples before the change is made. During the clocking change,
the DAC outputs will always be in a zero data state. If non-zero serial audio input is present at the time of
switching, a slight click or pop may be heard as the DAC output automatically goes to its zero data state.
4.8
Auxiliary Analog Output
The CS4245 includes an auxiliary analog output through the AUXOUT pins. These pins can be configured
to output the analog input to the ADC as selected with the input MUX and gained or attenuated with the
PGA, the analog output of the DAC, or alternatively they may be set to high-impedance. See “Section 6.6.1
“Auxiliary Output Source Select (Bits 6:5)” on page 45” for information on configuring the auxiliary analog
output.
The auxiliary analog output can source very little current. As current from the AUXOUT pins increases, distortion will increase. For this reason, a high input impedance buffer must be used on the AUXOUT pins to
achieve full performance. Refer to the table in “Auxiliary Output Analog Characteristics” on page 17 for acceptable loading conditions.
4.9
De-Emphasis Filter
The CS4245 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter response is shown in Figure 15. The frequency response of the de-emphasis curve scales proportionally with
changes in sample rate, Fs. Please see Section 6.3.4 “De-Emphasis Control (Bit 1)” on page 43 for de-emphasis control.
The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 μs pre-emphasis
equalization as a means of noise reduction.
34
DS656F2
CS4245
De-emphasis is only available in Single-Speed Mode.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 15. De-Emphasis Curve
4.10
Internal Digital Loopback
The CS4245 supports an internal digital loopback mode in which the output of the ADC is routed to the input
of the DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (See Section 6.6 “Signal Selection - Address 06h” on page 45). To use this mode, the ADC and DAC must be operating at the same synchronous sample rate.
When this bit is set, the status of the DAC_DIF[1:0] bits in register 03h will be disregarded by the CS4245.
Any changes made to the DAC_DIF[1:0] bits while the LOOP bit is set will have no impact on operation until
the LOOP bit is cleared, at which time the Digital Interface Format of the DAC will operate according to the
format selected by the DAC_DIF[1:0] bits. While the LOOP bit is set, data will be present on the SDOUT pin
in the format selected by the ADC_DIF bit in register 04h.
4.11
Mute Control
The MUTEC pin becomes active during power-up initialization, reset, and muting if the MCLK2 to LRCK2
ratio is incorrect in Asynchronous Mode or the MCLK1 to LRCK2 ratio is incorrect in Synchronous Mode,
and during power-down. The MUTEC pin is intended to be used as control for an external mute circuit in
order to add off-chip mute capability.
Use of the Mute Control function is not mandatory, but recommended, for designs requiring the absolute
minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system de-
DS656F2
35
CS4245
signer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
The MUTEC pin is an active-low CMOS driver. See Figure 16 for a suggested active-low mute circuit.
+VEE
AC
Couple
AOUT
560 Ω
LPF
Audio
Out
47 kΩ
CS4245
-VEE
+VA
MMUN2111LT1
MUTEC
2 kΩ
10 kΩ
-VEE
Figure 16. Suggested Active-Low Mute Circuit
4.12
Control Port Description and Timing
The control port is used to access the registers, allowing the CS4245 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port has two modes: SPI and I²C, with the CS4245 acting as a slave device. SPI Mode is selected if there is a high-to-low transition on the AD0/CS pin, after the RESET pin has been brought high. I²C
Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently
selecting the desired AD0 bit address state.
4.12.1 SPI Mode
In SPI Mode, CS is the CS4245 chip-select signal; CCLK is the control port bit clock (input into the CS4245
from the microcontroller); CDIN is the input data line from the microcontroller; CDOUT is the output data
line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 17 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data that will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 kΩ resistor, if desired.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip ad-
36
DS656F2
CS4245
dress and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the
addressed register (CDOUT will leave the high-impedance state).
For both read and write cycles, the memory address pointer will automatically increment following each
data byte in order to facilitate block reads and writes of successive registers.
CS
CC LK
C H IP
ADDRESS
MAP
1001111
C D IN
C H IP
ADDRESS
DATA
1001111
LSB
MSB
R/W
b y te 1
R/W
b y te n
High Impedance
LSB MSB
MSB
CDOUT
LSB
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 17. Control Port Timing in SPI Mode
4.12.2 I²C Mode
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should
be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the
CS4245 is being reset.
The signal timings for a read and write cycle are shown in Figure 18 and Figure 19. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4245
after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write).
The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS4245, the chip
address field, which is the first byte sent to the CS4245, should match 10011 followed by the settings of
the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is
the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a
read, the contents of the register pointed to by the MAP will be output. Following each data byte, the memory address pointer will automatically increment to facilitate block reads and writes of successive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS4245 after each
input byte is read, and is input to the CS4245 from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
1
SDA
0
0
1
MAP BYTE
1 AD1 AD0 0
6
ACK
6
5
4
3
2
1
0
7
ACK
6
1
DATA +n
DATA +1
DATA
0
7
ACK
START
6
1
0
7
6
1
0
ACK
STOP
Figure 18. Control Port Timing, I²C Write
DS656F2
37
CS4245
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
1
0
0
1
STOP
MAP BYTE
7
1 AD1 AD0 0
6
5
4
3
2
1
CHIP ADDRESS (READ)
1
0
0
0
1
ACK
ACK
START
DATA
1 AD1 AD0 1
START
7
ACK
DATA +1
0
7
ACK
0
DATA + n
7
0
NO
ACK
STOP
Figure 19. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 19, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
4.13
Interrupts and Overflow
The CS4245 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an
active low open-drain driver (see “Active High/Low (Bit 0)” on page 49). When configured as active low
open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hook-ups with
multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an external
pull-up resistor must be placed on the INT pin for proper operation.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see “Interrupt
Status - Address 0Dh” on page 49). Each source may be masked off through mask register bits. In addition,
each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option of levelsensitive or edge-sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer.
The CS4245 also has a dedicated overflow output. The OVFL pin functions as active low open drain and
has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR
of the ADCOverflow and ADCUnderflow conditions available in the Interrupt Status register; however, these
conditions do not need to be unmasked for proper operation of the OVFL pin.
38
DS656F2
CS4245
4.14
Reset
When RESET is low, the CS4245 enters a low-power mode and all internal states are reset, including the
control port and registers, the outputs are muted. When RESET is high, the control port becomes operational, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control register will then cause the part to leave the low-power state and begin operation.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RESET pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT1+ and FILT2+
pins. During this voltage reference ramp delay, both SDOUT and DAC outputs will be automatically muted.
It is recommended that RESET be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power-glitch-related issues.
4.15
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the master clocks and left/right clocks must be the same for all of the
CS4245s in the system. If only one master clock source is needed, one solution is to place one CS4245 in
Master Mode, and slave all of the other CS4245s to the one master. If multiple master clock sources are
needed, a possible solution would be to supply all clocks from the same external source and time the
CS4245 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on
the same clock edge.
4.16
Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS4245 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 12 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the
system logic supply (VLS or VLC) or may be powered from the analog supply (VA) via a resistor. In this
case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as
near to the CS4245 as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT1+, FILT2+, VQ1 and VQ2 pins in order to avoid unwanted
coupling into the modulators. The FILT1+, FILT2+, VQ1 and VQ2 decoupling capacitors, particularly the
0.1 µF, must be positioned to minimize the electrical path from FILT1+ and FILT2+ and AGND. The CS4245
evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital
noise, connect the CS4245 digital outputs only to CMOS inputs.
DS656F2
39
CS4245
5. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
Addr
Function
01h Chip ID
02h Power Control
7
6
5
4
3
2
1
0
PART3
PART2
PART1
PART0
REV3
REV2
REV1
REV0
1
1
0
0
0
0
0
1
Reserved
PDN_MIC
PDN_ADC
PDN_DAC
PDN
0
0
0
0
1
Reserved
MuteDAC
DeEmph
DAC_M/S
Freeze
0
Reserved Reserved
0
0
03h DAC Control 1 DAC_FM1 DAC_FM0 DAC_DIF1 DAC_DIF0
0
04h ADC Control
05h MCLK
Frequency
0
0
ADC_FM1 ADC_FM0 Reserved
1
0
0
0
Reserved
MuteADC
HPFFreeze
ADC_M/S
0
0
0
0
0
0
0
0
Reserved
MCLK1
Freq2
MCLK1
Freq1
MCLK1
Freq0
Reserved
MCLK2
Freq2
MCLK2
Freq1
MCLK2
Freq0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
LOOP
ASynch
06h Signal Selection
Reserved AOutSel1 AOutSel0
07h PGA Ch B
Gain Control
Reserved Reserved
08h PGA Ch A
Gain Control
Reserved Reserved
0
0
0
09h Analog Input
Control
0
ADC_DIF
1
0
0
0
0
0
0
0
0
Gain5
Gain4
Gain3
Gain2
Gain1
Gain0
0
0
0
0
0
0
Gain5
Gain4
Gain3
Gain2
Gain1
Gain0
0
0
0
0
0
0
PGASoft
PGAZero
Sel2
Sel1
Sel0
Reserved Reserved Reserved
0
0
0
1
1
0
0
1
0Ah DAC Ch A Volume Control
Vol7
Vol6
Vol5
Vol4
Vol3
Vol2
Vol1
Vol0
0
0
0
0
0
0
0
0
0Bh DAC Ch B Volume Control
Vol7
Vol6
Vol5
Vol4
Vol3
Vol2
Vol1
Vol0
0
0
0
0Ch DAC Control 2
DACSoft
0
0
0
0
0
Reserved
Reserved
Reserved
Active_H/L
0
0
0
0
0
0Dh Interrupt Status Reserved Reserved Reserved
Reserved
ADCClkErr
DACClkErr
ADCOvfl
ADCUndrfl
0
0
0
0
0
0
ADCOvflM
ADCUndrflM
0
0
ADCOvfl1
ADCUndrfl1
1
0Eh Interrupt Mask
DACZero InvertDAC Reserved
1
0
0
0
Reserved Reserved Reserved
0
0
0
0Fh Interrupt Mode
MSB
Reserved Reserved Reserved
10h Interrupt Mode
LSB
Reserved Reserved Reserved
0
0
40
0
0
0
0
Reserved ADCClkErrM DACClkErrM
0
0
0
Reserved ADCClkErr1 DACClkErr1
0
0
0
Reserved ADCClkErr0 DACClkErr0
0
0
0
0
0
ADCOvfl0
ADCUndrfl0
0
0
DS656F2
CS4245
6. REGISTER DESCRIPTION
6.1
Chip ID - Register 01h
7
PART3
6
PART2
5
PART1
4
PART0
3
REV3
2
REV2
1
REV1
0
REV0
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1100b (0Ch), and the remaining
bits (3 through 0) indicate the device revision as shown in Table 4 below.
REV[2:0]
Revision
001
A
010
B, C0
011
C1
Table 4. Device Revision
6.2
Power Control - Address 02h
7
Freeze
6.2.1
6
Reserved
5
Reserved
4
Reserved
3
PDN_MIC
2
PDN_ADC
1
PDN_DAC
0
PDN
Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking effect
until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the
Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed
in Table 5.
Name
Register
Bit(s)
MuteDAC
03h
2
MuteADC
04h
2
Gain[5:0]
07h
5:0
Gain[5:0]
08h
5:0
Vol[7:0]
0Ah
7:0
Vol[7:0]
0Bh
7:0
Table 5. Freeze-able Bits
6.2.2
Power-Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
6.2.3
Power-Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
DS656F2
41
CS4245
6.2.4
Power-Down DAC (Bit 1)
Function:
The DAC pair will remain in a reset state whenever this bit is set.
6.2.5
Power-Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and
must be cleared before normal operation can occur. The contents of the control registers are retained
when the device is in power-down.
6.3
DAC Control - Address 03h
7
6
5
4
3
2
1
0
DAC_FM1
DAC_FM0
DAC_DIF1
DAC_DIF0
Reserved
MuteDAC
DeEmph
DAC_M/S
6.3.1
DAC Functional Mode (Bits 7:6)
Function:
Selects the required range of input sample rates.
DAC_FM1
DAC_FM0
Mode
0
0
Single-Speed Mode: 4 to 50 kHz sample rates
0
1
Double-Speed Mode: 50 to 100 kHz sample rates
1
0
Quad-Speed Mode: 100 to 200 kHz sample rates
1
1
Reserved
Table 6. Functional Mode Selection
6.3.2
DAC Digital Interface Format (Bits 5:4)
Function:
The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital Interface Format and the options are detailed in Table 7 and Figures 7-9.
DAC_DIF1 DAC_DIF0
Description
0
0
Left Justified, up to 24-bit data (default)
0
1
I²S, up to 24-bit data
1
0
Right-Justified, 16-bit Data
1
1
Right-Justified, 24-bit Data
Format
0
1
2
3
Figure
7
8
9
9
Table 7. DAC Digital Interface Formats
6.3.3
Mute DAC (Bit 2)
Function:
The DAC outputs will mute and the MUTEC pin will become active when this bit is set. Though this bit is
active high, it should be noted that the MUTEC pin is active low. The common mode voltage on the outputs
will be retained when this bit is set. The muting function is effected, similar to attenuation changes, by the
DACSoft and DACZero bits in the DAC Control 2 register.
42
DS656F2
CS4245
6.3.4
De-Emphasis Control (Bit 1)
Function:
The standard 50/15 μs digital de-emphasis filter response, Figure 20, may be implemented for a sample
rate of 44.1 kHz when the DeEmph bit is configured as shown in Table 8. NOTE: De-emphasis is available
only in Single-Speed Mode.
DeEmph
0
1
Description
Disabled (default)
44.1 kHz de-emphasis
Table 8. De-Emphasis Control
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 20. De-Emphasis Curve
6.3.5
DAC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 2. Setting this bit will select Master
Mode, while clearing this bit will select Slave Mode.
6.4
ADC Control - Address 04h
7
6
5
4
3
2
1
0
ADC_FM1
ADC_FM0
Reserved
ADC_DIF
Reserved
MuteADC
HPFFreeze
ADC_M/S
6.4.1
ADC Functional Mode (Bits 7:6)
Function:
Selects the required range of output sample rates.
ADC_FM1
ADC_FM0
0
0
Single-Speed Mode: 4 to 50 kHz sample rates
Mode
0
1
Double-Speed Mode: 50 to 100 kHz sample rates
1
0
Quad-Speed Mode: 100 to 200 kHz sample rates
1
1
Reserved
Table 9. Functional Mode Selection
DS656F2
43
CS4245
6.4.2
ADC Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK1, SCLK1 and SDOUT is defined by the ADC Digital Interface
Format bit. The options are detailed in Table 10 and may be seen in Figure 7 and Figure 8.
ADC_DIF
Description
Format
Figure
0
1
Left-Justified, up to 24-bit data (default)
0
7
I²S, up to 24-bit data
1
8
Table 10. ADC Digital Interface Formats
6.4.3
Mute ADC (Bit 2)
Function:
When this bit is set, the serial audio output of the both ADC channels is muted.
6.4.4
ADC High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled.The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See “High-Pass Filter and DC Offset Calibration” on
page 32.
6.4.5
ADC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 1. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
6.5
MCLK Frequency - Address 05h
7
Reserved
6.5.1
6
MCLK1
Freq2
5
MCLK1
Freq1
4
MCLK1
Freq0
3
2
MCLK2
Freq2
Reserved
1
MCLK2
Freq1
0
MCLK2
Freq0
Master Clock 1 Frequency (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK1 signal. See Table 11 for the appropriate settings.
MCLK1 Divider
MCLK1 Freq2 MCLK1 Freq1 MCLK1 Freq0
÷1
0
0
0
÷ 1.5
0
0
1
÷2
0
1
0
÷3
0
1
1
÷4
1
0
0
Reserved
1
0
1
Reserved
1
1
x
Table 11. MCLK 1 Frequency
44
DS656F2
CS4245
6.5.2
Master Clock 2 Frequency (Bits 2:0)
Function:
These bits set the frequency of the supplied MCLK2 signal. See Table 12 for the appropriate settings.
MCLK2 Divider
MCLK2 Freq2 MCLK2 Freq1 MCLK2 Freq0
÷1
0
0
0
÷ 1.5
0
0
1
÷2
0
1
0
÷3
0
1
1
÷4
1
0
0
Reserved
1
0
1
Reserved
1
1
x
Table 12. MCLK 2 Frequency
6.6
Signal Selection - Address 06h
7
6
5
4
3
2
1
0
Reserved
AOutSel1
AOutSel0
Reserved
Reserved
Reserved
LOOP
ASynch
6.6.1
Auxiliary Output Source Select (Bits 6:5)
Function:
These bits are used to select the analog output source. Please refer to Table 13.
AOutSel1
0
0
1
1
AOutSel0
0
1
0
1
Auxiliary Output Source
High Impedance
DAC Output
PGA Output
Reserved
Table 13. Auxiliary Output Source Selection
6.6.2
Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC are enabled. Please refer to
“Internal Digital Loopback” on page 35.
6.6.3
Asynchronous Mode (Bit 0)
Function:
When this bit is set, the DAC and ADC may be operated at independent asynchronous sample rates derived from MCLK1 and MCLK2. When this bit is cleared, the DAC and ADC must operate at synchronous
sample rates derived from MCLK1.
DS656F2
45
CS4245
6.7
Channel B PGA Control - Address 07h
7
Reserved
6.7.1
6
Reserved
5
Gain5
4
Gain4
3
Gain3
2
Gain2
1
Gain1
0
Gain0
3
Gain3
2
Gain2
1
Gain1
0
Gain0
Channel B PGA Gain (Bits 5:0)
Function:
See “Channel A PGA Gain (Bits 5:0)” on page 46.
6.8
Channel A PGA Control - Address 08h
7
Reserved
6.8.1
6
Reserved
5
Gain5
4
Gain4
Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See Table 14 for example settings.
Gain[5:0]
Setting
101000
-12 dB
000000
0 dB
011000
+12 dB
Table 14. Example Gain and Attenuation Settings
6.9
ADC Input Control - Address 09h
7
Reserved
6.9.1
6
Reserved
5
Reserved
4
PGASoft
3
PGAZero
2
Sel2
1
Sel1
0
Sel0
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See Table 15.
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See Table 15.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
46
DS656F2
CS4245
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 15.
PGASoft
0
0
1
1
PGAZeroCross
0
1
0
1
Mode
Changes to affect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled (default)
Table 15. PGA Soft Cross or Zero Cross Mode Selection
6.9.2
Analog Input Selection (Bits 2:0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 16.
Sel2
Sel1
Sel0
PGA/ADC Input
0
0
0
Microphone-Level Inputs (+32 dB Gain Enabled)
0
0
1
Line-Level Input Pair 1
0
1
0
Line-Level Input Pair 2
0
1
1
Line-Level Input Pair 3
1
0
0
Line-Level Input Pair 4
1
0
1
Line-Level Input Pair 5
1
1
0
Line-Level Input Pair 6
1
1
1
Reserved
Table 16. Analog Input Multiplexer Selection
6.10
DAC Channel A Volume Control - Address 0Ah
See 6.11 DAC Channel B Volume Control - Address 0Bh.
6.11
DAC Channel B Volume Control - Address 0Bh
7
Vol7
6.11.1
6
Vol6
5
Vol5
4
Vol4
3
Vol3
2
Vol2
1
Vol1
0
Vol0
Volume Control (Bits 7:0)
Function:
The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to -127 dB.
The Vol0 bit activates a 0.5 dB attenuation when set, and no attenuation when cleared. The Vol[7:1] bits
activate attenuation equal to their decimal equivalent (in dB). Example volume settings are decoded as
DS656F2
47
CS4245
shown in Table 17. The volume changes are implemented as dictated by the DACSoft and DACZeroCross bits in the DAC Control 2 register (see Section 6.12.1).
Binary Code
Volume Setting
00000000
0 dB
00000001
-0.5 dB
00101000
-20 dB
00101001
-20.5 dB
11111110
-127 dB
11111111
-127.5 dB
Table 17. Digital Volume Control Example Settings
6.12
DAC Control 2 - Address 0Ch
7
6
5
4
3
2
1
0
DACSoft
DACZero
InvertDAC
Reserved
Reserved
Reserved
Reserved
Active_H/L
6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See Table 18.
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See Table 18.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 18.
DACSoft
DACZeroCross
Mode
0
0
Changes to affect immediately
0
1
Zero Cross enabled
1
0
Soft Ramp enabled
1
1
Soft Ramp and Zero Cross enabled (default)
Table 18. DAC Soft Cross or Zero Cross Mode Selection
6.12.2 Invert DAC Output (Bit 5)
Function:
When this bit is set, the output of the DAC is inverted.
48
DS656F2
CS4245
6.12.3 Active High/Low (Bit 0)
Function:
When this bit is set, the INT pin functions as an active high CMOS driver.
When this bit is cleared, the INT pin functions as an active low open drain driver and will require an external pull-up resistor for proper operation.
6.13
Interrupt Status - Address 0Dh
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
ADCClkErr
2
DACClkErr
1
ADCOvfl
0
ADCUndrfl
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last
reading of the register. Status bits that are masked off in the associated mask register will always be ‘0’ in
this register. This register defaults to 00h.
6.13.1 ADC Clock Error (Bit 3)
Function:
Indicates the occurrence of an ADC clock error condition.
6.13.2 DAC Clock Error (Bit 2)
Function:
Indicates the occurrence of a DAC clock error condition.
6.13.3 ADC Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
6.13.4 ADC Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
6.14
Interrupt Mask - Address 0Eh
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
ADCClkErrM
2
DACClkErrM
1
ADCOvflM
0
ADCUndrflM
Function:
The bits of this register serve as a mask for the Status sources found in the register “Interrupt Status - Address 0Dh” on page 49. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect
the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence
will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Status register.
DS656F2
49
CS4245
6.15
Interrupt Mode MSB - Address 0Fh
6.16
Interrupt Mode LSB - Address 10h
7
Reserved
Reserved
6
Reserved
Reserved
5
Reserved
Reserved
4
Reserved
Reserved
3
ADCClkErr1
ADCClkErr0
2
DACClkErr1
DACClkErr0
1
ADCOvfl1
ADCOvfl0
0
ADCUndrfl1
ADCUndrfl0
Function:
The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There are
three ways to set the INT pin active in accordance with the interrupt condition. In the Rising-Edge Active
Mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling-Edge Active Mode,
the INT pin becomes active on the removal of the interrupt condition. In Level-Active Mode, the INT pin remains active during the interrupt condition.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
50
DS656F2
CS4245
7. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full scale. This
technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
DS656F2
51
CS4245
8. DAC FILTER PLOTS
Figure 21. DAC Single-Speed Stopband Rejection
Figure 22. DAC Single-Speed Transition Band
0
-1
0.05
-2
0
-3
-0.05
Amplitude dB
Amplitude dB
-4
-5
-6
-0. 1
-0.15
-7
-0. 2
-8
-0.25
-9
-10
0.45
52
0.46
0.47
0.48
0.49
0.5
0.51
Frequency (normalized to Fs)
0.52
0.53
0.54
0.5 5
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (normalized to Fs)
0.35
0.4
0.45
Figure 23. DAC Single-Speed Transition Band
Figure 24. DAC Single-Speed Passband Ripple
Figure 25. DAC Double-Speed Stopband Rejection
Figure 26. DAC Double-Speed Transition Band
0.5
DS656F2
CS4245
1
0.8
0
0.7
-1
0.6
-2
0.5
Amplitude dB
Amplitude dB
-3
-4
-5
0.4
0.3
0.2
-6
0.1
-7
0
-8
-0. 1
-9
- 10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency (normalized to Fs)
0.52
0.53
0.54
-0. 2
0.55
0
Figure 27. DAC Double-Speed Transition Band
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 28. DAC Double-Speed Passband Ripple
0
0
-10
-10
-20
-20
-30
Amplitude (dB)
Amplitude (dB)
-40
-50
-60
-30
-40
-70
-50
-80
-60
-90
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
0.9
1
0.35
Figure 29. DAC Quad-Speed Stopband Rejection
0.4
0.45
0.5
0.55
0.6
Frequency(normalized to Fs)
0.65
0.7
0.75
Figure 30. DAC Quad-Speed Transition Band
0
0
-5
-10
-15
Amplitude dB
Amplitude (dB)
-0. 5
-20
-25
-30
-1
-35
-40
-45
-50
0.4
0.45
0.5
0.55
0.6
Frequency(normalized to Fs)
0.65
Figure 31. DAC Quad-Speed Transition Band
DS656F2
0.7
-1. 5
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 32. DAC Quad-Speed Passband Ripple
53
CS4245
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
Amplitude (dB)
Amplitude (dB)
9. ADC FILTER PLOTS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.40 0.42 0.44
Frequency (norm alized to Fs)
0
0.10
-1
0.08
-2
0.06
-3
0.04
-4
-5
-6
-7
0.58
0.60
0.00
-0.04
-0.06
-0.08
-0.10
0.46 0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0
0.55
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Figure 36. ADC Single-Speed Passband Ripple
Amplitude (dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.1
0.05
Frequency (norm alized to Fs)
Figure 35. ADC Single-Speed Transition Band (Detail)
Amplitude (dB)
0.56
-0.02
-9
Frequency (norm alized to Fs)
0.9
1.0
Frequency (norm alized to Fs)
Figure 37. ADC Double-Speed Stopband Rejection
54
0.54
0.02
-8
0.0
0.52
Figure 34. ADC Single-Speed Stopband Rejection
Amplitude (dB)
Amplitude (dB)
Figure 33. ADC Single-Speed Stopband Rejection
-10
0.45
0.46 0.48 0.50
Frequency (norm alized to Fs)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.40 0.42 0.44
0.46 0.48 0.50
0.52
0.54
0.56
0.58
0.60
Frequency (norm alized to Fs)
Figure 38. ADC Double-Speed Stopband Rejection
DS656F2
0
0.10
-1
0.08
-2
0.06
-3
0.04
Amplitude (dB)
Amplitude (dB)
CS4245
-4
-5
-6
-7
0.02
0.00
-0.02
-0.04
-8
-0.06
-9
-0.08
-10
0.46
0.47
0.48
0.49
0.50
0.51
-0.10
0.00 0.05
0.52
Frequency (norm alized to Fs)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.15
0.20 0.25 0.30 0.35 0.40 0.45 0.50
Figure 40. ADC Double-Speed Passband Ripple
Amplitude (dB)
Amplitude (dB)
Figure 39. ADC Double-Speed Transition Band (Detail)
0.0
0.10
Frequency (norm alized to Fs)
0.9
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
1.0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 41. ADC Quad-Speed Stopband Rejection
Figure 42. ADC Quad-Speed Stopband Rejection
0
0.10
-1
0.08
-3
0.06
-4
0.04
Amplitude (dB)
Amplitude (dB)
-2
-5
-6
-7
-8
-0.04
-0.08
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (norm alized to Fs)
Figure 43. ADC Quad-Speed Transition Band (Detail)
DS656F2
0.00
-0.02
-0.06
-9
-10
0.10
0.02
-0.10
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (norm alized to Fs)
Figure 44. ADC Quad-Speed Passband Ripple
55
CS4245
10.PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
B
∝
A
A1
L
DIM
A
A1
B
D
D1
E
E1
e*
L
MIN
--0.002
0.007
0.343
0.272
0.343
0.272
0.016
0.018
0.000°
∝
* Nominal pin pitch is 0.50 mm
INCHES
NOM
MAX
MIN
0.055
0.063
--0.004
0.006
0.05
0.009
0.011
0.17
0.354
0.366
8.70
0.28
0.280
6.90
0.354
0.366
8.70
0.28
0.280
6.90
0.020
0.024
0.40
0.24
0.030
0.45
4°
7.000°
0.00°
*Controlling dimension is mm.
MILLIMETERS
NOM
MAX
1.40
1.60
0.10
0.15
0.22
0.27
9.0 BSC
9.30
7.0 BSC
7.10
9.0 BSC
9.30
7.0 BSC
7.10
0.50 BSC
0.60
0.60
0.75
4°
7.00°
*JEDEC Designation: MS022
11.THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters
Package Thermal Resistance (Note 1)
Allowable Junction Temperature
48-LQFP
Symbol
Min
Typ
Max
Units
θJA
θJC
-
48
15
-
125
°C/Watt
°C/Watt
°C
1. θJA is specified according to JEDEC specifications for multi-layer PCBs.
56
DS656F2
CS4245
12.ORDERING INFORMATION
Product
CS4245
CS4245
CDB4245
Description
24-bit, 192 kHz
Stereo Audio CODEC
24-bit, 192 kHz
Stereo Audio CODEC
Package Pb-Free
48-LQFP
48-LQFP
CS4245 Evaluation Board
Yes
Grade
Commercial
Temp Range
-10° to +70° C
Yes
Automotive
-40° to +105° C
No
-
-
Container
Order #
Tray
CS4245-CQZ
Tape & Reel
CS4245-CQZR
Tray
CS4245-DQZ
Tape & Reel
CS4245-DQZR
-
CDB4245
13.REVISION HISTORY
Release
F1
F2
Changes
– Removed the MAP auto-increment functional description from the Control Port Description and Timing section
beginning on page 36.
– Added device revision information to the Chip ID - Register 01h description on page 41.
– Updated the VQ1 Output Impedance specification in the DC Electrical Characteristics table on page 20.
– Updated the Microphone Interchannel Isolation specification in the ADC Analog Characteristics table on page 15.
– Added Automotive Grade
– Changed MCLK1 and MCLK2 to input only in the Pin Descriptions table on page 7.
– Updated the DAC Analog Characteristics table on page 10.
– Updated the ADC Analog Characteristics table on page 13.
– Updated the Auxiliary Output Analog Characteristics table on page 17.
– Updated the DC Electrical Characteristics table on page 20.
– Updated the Digital Interface Characteristics table on page 21.
– Updated the Switching Characteristics - Serial Audio Port 1 table on page 22.
– Updated the Switching Characteristics - Control Port - SPI Format table on page 28.
– Updated the Typical Connection Diagram on page 29.
– Switched Channel B PGA Control - Address 07h on page 46 and Channel A PGA Control - Address 08h on
page 46.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
DS656F2
57
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