LM5000
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SNVS176D – MAY 2004 – REVISED MARCH 2007
LM5000 High Voltage Switch Mode Regulator
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FEATURES
1
•
•
•
2
•
•
•
•
•
80V internal switch
Operating input voltage range of 3.1V to 40V
Pin selectable operating frequency
–
300kHz/700kHz (-3)
–
600kHz/1.3MHz (-6)
Adjustable output voltage
External compensation
Input undervoltage lockout
Softstart
Current limit
•
•
•
Over temperature protection
External shutdown
Small 16-Lead TSSOP or 16-Lead LLP package
APPLICATIONS
•
•
•
•
•
Flyback Regulator
Forward Regulator
Boost Regulator
DSL Modems
Distributed Power Converters
DESCRIPTION
The LM5000 is a monolithic integrated circuit specifically designed and optimized for flyback, boost or forward
power converter applications. The internal power switch is rated for a maximum of 80V, with a current limit set to
2A. Protecting the power switch are current limit and thermal shutdown circuits. The current mode control
scheme provides excellent rejection of line transients and cycle-by-cycle current limiting. An external
compensation pin and the built-in slope compensation allow the user to optimize the frequency compensation.
Other distinctive features include softstart to reduce stresses during start-up and an external shutdown pin for
remote ON/OFF control. There are two operating frequency ranges available. The LM5000-3 is pin selectable for
either 300kHz (FS Grounded) or 700kHz (FS Open). The LM5000-6 is pin selectable for either 600kHz (FS
Grounded) or 1.3MHz (FS Open). The device is available in a low profile 16-lead TSSOP package or a thermally
enhanced 16-lead LLP package.
Typical Application Circuit
Figure 1. LM5000 Flyback Converter
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
LM5000
SNVS176D – MAY 2004 – REVISED MARCH 2007
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Connection Diagram
Figure 2. Top View
Pin Functions
Pin Descriptions
Pin
Name
1
COMP
2
FB
Function
Compensation network connection. Connected to the output of the voltage error amplifier. The RC
compenstion network should be connected from this pin to AGND. An additional 100pF high frequency
capacitor to AGND is recommended.
Output voltage feedback input.
3
SHDN
Shutdown control input, Open = enable, Ground = disable.
4
AGND
Analog ground, connect directly to PGND.
5
PGND
Power ground.
6
PGND
Power ground.
7
PGND
Power ground.
8
PGND
Power ground.
9
SW
Power switch input. Switch connected between SW pins and PGND pins
10
SW
Power switch input. Switch connected between SW pins and PGND pins
11
SW
Power switch input. Switch connected between SW pins and PGND pins
12
BYP
Bypass-Decouple Capacitor Connection, 0.1µF ceramic capacitor recommended.
13
VIN
Analog power input. A small RC filter is recommended, to suppress line glitches. Typical values of 10Ω
and ≥ 0.1µF are recommended.
14
SS
Softstart Input. External capacitor and internal current source sets the softstart time.
15
FS
Switching frequency select input. Open = Fhigh. Ground = Flow
16
TEST
-
Exposed Pad
underside of LLP
package
Factory test pin, connect to ground.
Connect to system ground plane for reduced thermal resistance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings
(1)
VIN
-0.3V to 40V
SW Voltage
-0.3V to 80V
FB Voltage
-0.3V to 5V
COMP Voltage
-0.3V to 3V
All Other Pins
-0.3V to 7V
Maximum Junction Temperature
150°C
Power Dissipation (2)
Internally Limited
Lead Temperature
216°C
Infrared (15 sec.)
ESD Susceptibility
235°C
(3)
Human Body Model
2kV
Machine Model
200V
−65°C to +150°C
Storage Temperature
(1)
(2)
(3)
Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test
conditions, see the Electrical Characteristics.
The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. See the Electrical Characteristics table for the thermal resistance of various layouts.
The maximum allowable power dissipation at any ambient temperature is calculated using: PD (MAX) = (TJ(MAX) − TA)/θJA. Exceeding
the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF
capacitor discharged directly into each pin.
Operating Conditions
Operating Junction Temperature Range
(1)
−40°C to +125°C
Supply Voltage
(1)
(1)
3.1V to 40V
Supply voltage, bias current product will result in aditional device power dissipation. This power may be significant. The thermal
dissipation design should take this into account.
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Electrical Characteristics
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating
Temperature Range (TJ = −40°C to +125°C) Unless otherwise specified. VIN = 12V and IL = 0A, unless otherwise specified.
Symbol
IQ
Typ
Max
(1)
Units
FB = 2V (Not Switching)
FS = 0V
2.0
2.5
mA
FB = 2V (Not Switching)
FS = Open
2.1
2.5
mA
Parameter
Quiescent Current
Min
Conditions
(1)
(2)
VSHDN = 0V
VFB
Feedback Voltage
ICL
Switch Current Limit
%VFB/ΔVIN
Feedback Voltage Line
Regulation
IB
FB Pin Bias Current
BV
Output Switch Breakdown
Voltage
18
30
µA
1.2330
1.259
1.2840
V
1.35
2.0
2.7
A
0.001
0.04
%/V
55
200
nA
3.1V ≤ VIN ≤ 40V
(3)
TJ = 25°C, ISW = 0.1µA
80
TJ = -40°C to + 125°C, ISW =
0.5µA
76
VIN
Input Voltage Range
gm
Error Amp Transconductance
AV
Error Amp Voltage Gain
DMAX
Maximum Duty Cycle
LM5000-3
FS = 0V
Maximum Duty Cycle
LM5000-6
FS = 0V
V
3.1
ΔI = 5µA
150
410
40
V
750
µmho
280
V/V
85
90
%
85
90
%
165
ns
TMIN
Minimum On Time
fS
Switching Frequency LM50003
FS = 0V
240
300
360
FS = Open
550
700
840
Switching Frequency LM50006
FS = 0V
485
600
715
1.055
1.3
1.545
MHz
ISHDN
Shutdown Pin Current
VSHDN = 0V
−1
-2
µA
IL
Switch Leakage Current
VSW = 80V
0.008
5
µA
RDSON
Switch RDSON
ISW = 1A
160
445
mΩ
ThSHDN
SHDN Threshold
Output High
FS = Open
0.9
Output Low
UVLO
V
2.92
3.10
V
Off Threshold
2.60
2. 77
2.96
V
14
µA
ISS
Softstart Current
θJA
Thermal Resistance
4
0.3
2.74
VCOMP Trip
(2)
(3)
V
0.6
On Threshold
OVP
(1)
0.6
kHz
0.67
8
11
TSSOP, Package only
150
LLP, Package only
45
V
°C/W
All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits
are 100% production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control
(SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely norm.
Bias current flows into FB pin.
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Typical Performance Characteristics
Iq (non-switching)
vs
VIN @ fSW = 300kHz
Iq (non-switching)
vs
VIN @ fSW = 700kHz
3.000
3.000
2.800
2.800
2.600
2.600
2.400
-40oC
2.200
2.000
Iq (mA)
Iq (mA)
2.400
25oC
1.800
125oC
2.000
25oC
1.800
125oC
1.600
1.600
1.400
1.400
1.200
1.200
1.000
1.000
0
10
5
15
20
25
35
30
40
-40oC
2.200
0
5
10
15
VIN (V)
25
35
30
40
Iq (switching)
vs
VIN @ fSW = 700kHz
10
10
9
9
8
8
7
7
Iq (mA)
Iq (mA)
Iq (switching)
vs
VIN @ fSW = 300kHz
6
-40oC
5
4
20
VIN (V)
125oC
-40oC
25oC
125oC
6
5
4
25oC
3
3
2
2
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
VIN (V)
VIN (V)
Vfb
vs
Temperature
RDS(ON)
vs
VIN @ ISW =1A
1.2800
35
40
400
300
RDS(ON) (m:)
FEEDBACK VOLTAGE (V)
350
1.2700
1.2600
1.2500
125oC
250
200
25oC
150
100
o
-40 C
1.2400
50
1.2300
-40 -20
0
20
40
60
80 100 120
TEMPERATURE (oC)
0
0
5
10
15
20
25
30
35
40
VIN (V)
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Typical Performance Characteristics (continued)
Current Limit
vs
Temperature
Current Limit
vs
VIN
2
2
1.95
1.95
1.9
CURRENT LIMIT (A)
CURRENT LIMIT (A)
1.9
1.85
1.8
1.75
1.7
1.65
1.85
1.8
1.75
1.7
1.65
1.6
1.6
1.55
1.55
1.5
-40 -20
1.5
0
20
40
0
80 100 120
60
5
10
15
o
TEMPERATURE ( C)
VIN
fSW
vs.
@ FS = Low (-3)
VIN
770
310
750
FREQUENCY (KHZ)
315
305
fsw (kHz)
20
25
30
35
40
VIN (V)
300
295
290
fSW
vs.
@ FS = OPEN (-3)
730
710
690
670
650
285
630
0
5
10
15
20
25
30
35
40
0
5
10
15
VIN (V)
20
25
30
35
40
VIN (V)
fSW
vs.
Temperature @ FS = Low (-3)
fSW
vs.
Temperature @ FS = OPEN (-3)
330
770
320
750
730
fsw (kHz)
fSW (kHz)
310
300
710
690
290
670
280
270
-40
650
630
-20
0
20
40
60
80
-40 -20
100 120
20
40
60
80 100 120
TEMPERATURE (oC)
TEMPERATURE (oC)
6
0
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Typical Performance Characteristics (continued)
fSW
vs.
Temperature @ FS = OPEN (-6)
640
1.38
620
1.34
600
1.30
fSW (kHz)
fSW (kHz)
fSW
vs.
Temperature @ FS = Low (-6)
580
1.26
560
1.22
540
1.18
520
-40
-20
0
20
40
60
80
1.14
-40
100 120
-20
o
20
40
60
80
100 120
o
TEMPERATURE ( C)
TEMPERATURE ( C)
Error Amp. Transconductance
vs
Temp.
BYP Pin Voltage
vs
VIN
600
8
550
7
125oC
6
BYP PIN VOLTAGE (V)
500
Gm [Pmho]
0
450
400
350
300
-40oC
25oC
5
4
3
2
1
0
250
-40 -20
0
20
40
60
80 100 120
0
5
TEMPERATURE (oC)
10
15
20
25
30
35
40
VIN (V)
Figure 3. 300 kHz operation, 48V output
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Figure 4. 700 kHz operation, 48V output
Block Diagram
Boost Regulator Operation
The LM5000 utilizes a PWM control scheme to regulate the output voltage over all load conditions. The operation
can best be understood referring to the block diagram and Figure 5. At the start of each cycle, the oscillator sets
the driver logic and turns on the NMOS power device conducting current through the inductor, cycle 1 of Figure 5
(a). During this cycle, the voltage at the COMP pin controls the peak inductor current. The COMP voltage will
increase with larger loads and decrease with smaller. This voltage is compared with the summation of the SW
volatge and the ramp compensation.The ramp compensation is used in PWM architectures to eliminate the subharmonic oscillations that occur during duty cycles greater than 50%. Once the summation of the ramp
compensation and switch voltage equals the COMP voltage, the PWM comparator resets the driver logic turning
off the NMOS power device. The inductor current then flows through the output diode to the load and output
capacitor, cycle 2 of Figure 5 (b). The NMOS power device is then set by the oscillator at the end of the period
and current flows through the inductor once again.
8
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The LM5000 has dedicated protection circuitry running during the normal operation to protect the IC. The
Thermal Shutdown circuitry turns off the NMOS power device when the die temperature reaches excessive
levels. The UVP comparator protects the NMOS power device during supply power startup and shutdown to
prevent operation at voltages less than the minimum input voltage. The OVP comparator is used to prevent the
output voltage from rising at no loads allowing full PWM operation over all load conditions. The LM5000 also
features a shutdown mode. An external capacitor sets the softstart time by limiting the error amp output range,
as the capacitor charges up via an internal 10µA current source.
The LM5000 is available in two operating frequency ranges. The LM5000-3 is pin selectable for either 300kHz
(FS Grounded) or 700kHz (FS Open). The LM5000-6 is pin selectable for either 600kHz (FS Grounded) or
1.3MHz (FS Open)
Operation
Figure 5. Simplified Boost Converter Diagram
(a) First Cycle of Operation (b) Second Cycle Of Operation
CONTINUOUS CONDUCTION MODE
The LM5000 is a current-mode, PWM regulator. When used as a boost regulator the input voltage is stepped up
to a higher output voltage. In continuous conduction mode (when the inductor current never reaches zero at
steady state), the boost regulator operates in two cycles.
In the first cycle of operation, shown in Figure 5 (a), the transistor is closed and the diode is reverse biased.
Energy is collected in the inductor and the load current is supplied by COUT.
The second cycle is shown in Figure 5 (b). During this cycle, the transistor is open and the diode is forward
biased. The energy stored in the inductor is transferred to the load and output capacitor.
The ratio of these two cycles determines the output voltage. The output voltage is defined approximately as:
VOUT =
VIN
1-D
, D' = (1-D) =
VIN
VOUT
(1)
where D is the duty cycle of the switch, D and D′ will be required for design calculations.
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the feedback pin and a resistor divider connected to the output as shown in
Figure 3. The feedback pin is always at 1.259V, so the ratio of the feedback resistors sets the output voltage.
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RFB1 = RFB2 x
VOUT - 1.259
1.259
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:
(2)
INTRODUCTION TO COMPENSATION
Figure 6. (a) Inductor current. (b) Diode current.
The LM5000 is a current mode PWM regulator. The signal flow of this control scheme has two feedback loops,
one that senses switch current and one that senses output voltage.
To keep a current programmed control converter stable above duty cycles of 50%, the inductor must meet
certain criteria. The inductor, along with input and output voltage, will determine the slope of the current through
the inductor (see Figure 6 (a)). If the slope of the inductor current is too great, the circuit will be unstable above
duty cycles of 50%.
The LM5000 provides a compensation pin (COMP) to customize the voltage loop feedback. It is recommended
that a series combination of RC and CC be used for the compensation network, as shown in Figure 3. The series
combination of RC and CC introduces pole-zero pair according to the following equations:
fZC =
1
Hz
2SRCCC
(3)
1
fPC =
Hz
2S(RC + RO)CC
(4)
where RO is the output impedance of the error amplifier, 850kΩ. For most applications, performance can be
optimized by choosing values within the range 5kΩ ≤ RC ≤ 20kΩ and 680pF ≤ CC ≤ 4.7nF.
10
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COMPENSATION
This section will present a general design procedure to help insure a stable and operational circuit. The designs
in this datasheet are optimized for particular requirements. If different conversions are required, some of the
components may need to be changed to ensure stability. Below is a set of general guidelines in designing a
stable circuit for continuous conduction operation (loads greater than 100mA), in most all cases this will provide
for stability during discontinuous operation as well. The power components and their effects will be determined
first, then the compensation components will be chosen to produce stability.
INDUCTOR SELECTION
To ensure stability at duty cycles above 50%, the inductor must have some minimum value determined by the
minimum input voltage and the maximum output voltage. This equation is:
2
L>
VINRDSON
0.144 fs
( DD') -1
( DD') +1
(in H)
(5)
where fs is the switching frequency, D is the duty cycle, and RDSON is the ON resistance of the internal switch.
This equation is only good for duty cycles greater than 50% (D>0.5).
'iL =
VIND
2Lfs
(in Amps)
(6)
The inductor ripple current is important for a few reasons. One reason is because the peak switch current will be
the average inductor current (input current) plus ΔiL. Care must be taken to make sure that the switch will not
reach its current limit during normal operation. The inductor must also be sized accordingly. It should have a
saturation current rating higher than the peak inductor current expected. The output voltage ripple is also affected
by the total ripple current.
DC GAIN AND OPEN-LOOP GAIN
Since the control stage of the converter forms a complete feedback loop with the power components, it forms a
closed-loop system that must be stabilized to avoid positive feedback and instability. A value for open-loop DC
gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover
frequency and the phase margin. A high phase margin (greater than 45°) is desired for the best stability and
transient response. For the purpose of stabilizing the LM5000, choosing a crossover point well below where the
right half plane zero is located will ensure sufficient phase margin. A discussion of the right half plane zero and
checking the crossover using the DC gain will follow.
OUTPUT CAPACITOR SELECTION
The choice of output capacitors is somewhat more arbitrary. It is recommended that low ESR (Equivalent Series
Resistance, denoted RESR) capacitors be used such as ceramic, polymer electrolytic, or low ESR tantalum.
Higher ESR capacitors may be used but will require more compensation which will be explained later on in the
section. The ESR is also important because it determines the output voltage ripple according to the approximate
equation:
ΔVOUT ≊ 2ΔiLRESR (in Volts)
(7)
After choosing the output capacitor you can determine a pole-zero pair introduced into the control loop by the
following equations:
fP1 =
fZ1 =
1
(in Hz)
2S(RESR + RL)COUT
1
2SRESRCOUT
(8)
(in Hz)
(9)
Where RL is the minimum load resistance corresponding to the maximum load current. The zero created by the
ESR of the output capacitor is generally very high frequency if the ESR is small. If low ESR capacitors are used
it can be neglected. If higher ESR capacitors are used see the High Output Capacitor ESR Compensation
section.
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RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect
of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the
phase, subtracting another 90° in the phase plot. This can cause undesirable effects if the control loop is
influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be
designed to have a bandwidth of ½ the frequency of the RHP zero or less. This zero occurs at a frequency of:
RHPzero =
VOUT(D')2
(in Hz)
2S,LOADL
(10)
where ILOAD is the maximum load current.
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components RC and CC is to set a dominant low frequency pole in
the control loop. Simply choose values for RC and CC within the ranges given in the Introduction to
Compensation section to set this pole in the area of 10Hz to 100Hz. The frequency of the pole created is
determined by the equation:
fPC =
1
(in Hz)
2S(RC + RO)CC
(11)
where RO is the output impedance of the error amplifier, 850kΩ. Since RC is generally much less than RO, it does
not have much effect on the above equation and can be neglected until a value is chosen to set the zero fZC. fZC
is created to cancel out the pole created by the output capacitor, fP1. The output capacitor pole will shift with
different load currents as shown by the equation, so setting the zero is not exact. Determine the range of fP1 over
the expected loads and then set the zero fZC to a point approximately in the middle. The frequency of this zero is
determined by:
fZC =
1
(in Hz)
2SCCRC
(12)
Now RC can be chosen with the selected value for CC. Check to make sure that the pole fPC is still in the 10Hz to
100Hz range, change each value slightly if needed to ensure both component values are in the recommended
range. After checking the design at the end of this section, these values can be changed a little more to optimize
performance if desired. This is best done in the lab on a bench, checking the load step response with different
values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should
produce a stable, high performance circuit. For improved transient response, higher values of RC (within the
range of values) should be chosen. This will improve the overall bandwidth which makes the regulator respond
more quickly to transients. If more detail is required, or the most optimal performance is desired, refer to a more
in depth discussion of compensating current mode DC/DC switching regulators.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control
loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding
another capacitor, CC2, directly from the compensation pin VC to ground, in parallel with the series combination of
RC and CC. The pole should be placed at the same frequency as fZ1, the ESR zero. The equation for this pole
follows:
fPC2 =
1
(in Hz)
2SCC2(RC //RO)
(13)
To ensure this equation is valid, and that CC2 can be used without negatively impacting the effects of RC and CC,
fPC2 must be greater than 10fPC.
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a bandwidth of ½ or less of the frequency of the RHP
zero. This is done by calculating the open-loop DC gain, ADC. After this value is known, you can calculate the
crossover visually by placing a −20dB/decade slope at each pole, and a +20dB/decade slope for each zero. The
point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is
at less than ½ the RHP zero, the phase margin should be high enough for stability. The phase margin can also
be improved some by adding CC2 as discussed earlier in the section. The equation for ADC is given below with
additional equations required for the calculation:
12
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ADC(DB) = 20log10
2fs
Zc #
nD'
(R
RFB2
FB1 + RFB2
gmROD'
)R
{[(ZcLeff)// RL]//RL} (in dB)
DSON
(14)
(in rad/s)
Leff =
L
(D')2
n = 1+
2mc
(no unit)
m1
(15)
(16)
(17)
(18)
mc ≊ 0.072fs (in A/s)
m1 #
VINRDSON
L
(in V/s)
(19)
where RL is the minimum load resistance, VIN is the maximum input voltage, and RDSON is the value chosen from
the graph "RDSON vs. VIN " in the Typical Performance Characteristics section.
SWITCH VOLTAGE LIMITS
In a flyback regulator, the maximum steady-state voltage appearing at the switch, when it is off, is set by the
transformer turns ratio, N, the output voltage, VOUT, and the maximum input voltage, VIN (Max):
VSW(OFF) = VIN (Max) + (VOUT +VF)/N
(20)
where VF is the forward biased voltage of the output diode, and is typically 0.5V for Schottky diodes and 0.8V for
ultra-fast recovery diodes. In certain circuits, there exists a voltage spike, VLL, superimposed on top of the
steady-state voltage . Usually, this voltage spike is caused by the transformer leakage inductance and/or the
output rectifier recovery time. To “clamp” the voltage at the switch from exceeding its maximum value, a transient
suppressor in series with a diode is inserted across the transformer primary.
If poor circuit layout techniques are used, negative voltage transients may appear on the Switch pin. Applying a
negative voltage (with respect to the IC's ground) to any monolithic IC pin causes erratic and unpredictable
operation of that IC. This holds true for the LM5000 IC as well. When used in a flyback regulator, the voltage at
the Switch pin can go negative when the switch turns on. The “ringing” voltage at the switch pin is caused by the
output diode capacitance and the transformer leakage inductance forming a resonant circuit at the
secondary(ies). The resonant circuit generates the “ringing” voltage, which gets reflected back through the
transformer to the switch pin. There are two common methods to avoid this problem. One is to add an RC
snubber around the output rectifier(s). The values of the resistor and the capacitor must be chosen so that the
voltage at the Switch pin does not drop below −0.4V. The resistor may range in value between 10Ω and 1 kΩ,
and the capacitor will vary from 0.001 μF to 0.1 μF. Adding a snubber will (slightly) reduce the efficiency of the
overall circuit.
The other method to reduce or eliminate the “ringing” is to insert a Schottky diode clamp between the SW pin
and the PGND pin. The reverse voltage rating of the diode must be greater than the switch off voltage.
OUTPUT VOLTAGE LIMITATIONS
The maximum output voltage of a boost regulator is the maximum switch voltage minus a diode drop. In a
flyback regulator, the maximum output voltage is determined by the turns ratio, N, and the duty cycle, D, by the
equation:
VOUT ≈ N × VIN × D/(1 − D)
(21)
The duty cycle of a flyback regulator is determined by the following equation:
(22)
Theoretically, the maximum output voltage can be as large as desired—just keep increasing the turns ratio of the
transformer. However, there exists some physical limitations that prevent the turns ratio, and thus the output
voltage, from increasing to infinity. The physical limitations are capacitances and inductances in the LM5000
switch, the output diode(s), and the transformer—such as reverse recovery time of the output diode (mentioned
above).
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Product Folder Links: LM5000
13
LM5000
SNVS176D – MAY 2004 – REVISED MARCH 2007
www.ti.com
INPUT LINE CONDITIONING
A small, low-pass RC filter should be used at the input pin of the LM5000 if the input voltage has an unusually
large amount of transient noise. Additionally, the RC filter can reduce the dissipation within the device when the
input voltage is high.
Flyback Regulator Operation
The LM5000 is ideally suited for use in the flyback regulator topology. The flyback regulator can produce a single
output voltage, or multiple output voltages.
The operation of a flyback regulator is as follows: When the switch is on, current flows through the primary
winding of the transformer, T1, storing energy in the magnetic field of the transformer. Note that the primary and
secondary windings are out of phase, so no current flows through the secondary when current flows through the
primary. When the switch turns off, the magnetic field collapses, reversing the voltage polarity of the primary and
secondary windings. Now rectifier D5 is forward biased and current flows through it, releasing the energy stored
in the transformer. This produces voltage at the output.
The output voltage is controlled by modulating the peak switch current. This is done by feeding back a portion of
the output voltage to the error amp, which amplifies the difference between the feedback voltage and a 1.259V
reference. The error amp output voltage is compared to a ramp voltage proportional to the switch current (i.e.,
inductor current during the switch on time). The comparator terminates the switch on time when the two voltages
are equal, thereby controlling the peak switch current to maintain a constant output voltage.
Figure 7. LM5000 Flyback Converter
ITEM
PART NUMBER
DESCRIPTION
VALUE
C
1
C4532X7R2A105MT
Capacitor, CER, TDK
1µ, 100V
C
2
C4532X7R2A105MT
Capacitor, CER, TDK
1µ, 100V
C
3
C1206C224K5RAC
Capacitor, CER, KEMET
0.22µ, 50V
C
4
C1206C104K5RAC
Capacitor, CER, KEMET
0.1µ, 50V
C
5
C1206C104K5RAC
Capacitor, CER, KEMET
0.1µ, 50V
14
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Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Links: LM5000
LM5000
www.ti.com
SNVS176D – MAY 2004 – REVISED MARCH 2007
ITEM
PART NUMBER
DESCRIPTION
VALUE
C
6
C1206C101K1GAC
Capacitor, CER, KEMET
100p, 100V
C
7
C1206C104K5RAC
Capacitor, CER, KEMET
0.1µ, 50V
C
8
C4532X7S0G686M
Capacitor, CER, TDK
68µ, 4V
C
9
C4532X7S0G686M
Capacitor, CER, TDK
68µ, 4V
C
10
C1206C221K1GAC
Capacitor, CER, KEMET
220p, 100V
C
11
C1206C102K5RAC
Capacitor, CER, KEMET
1000p, 500V
D
1
BZX84C10-NSA
Central, 10V Zener, SOT-23
D
2
CMZ5930B-NSA
Central, 16V Zener, SMA
D
3
CMPD914-NSA
Central, Switching, SOT-23
D
4
CMPD914-NSA
Central, Switching, SOT-23
D
5
CMSH3-40L-NSA
Central, Schottky, SMC
T
1
A0009-A
Coilcraft, Transformer
R
1
CRCW12064992F
Resistor
49.9K
R
2
CRCW12061001F
Resistor
1K
R
3
CRCW12061002F
Resistor
10K
R
4
CRCW12066191F
Resistor
6.19K
R
5
CRCW120610R0F
Resistor
10
R
6
CRCW12062003F
Resistor
200K
R
7
CRCW12061002F
Resistor
10K
Q
1
CXT5551-NSA
Central, NPN, 180V
U
1
LM5000-3
Regulator, National
Submit Documentation Feedback
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Links: LM5000
15
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Samples
(3)
(Requires Login)
LM5000-3MTC
ACTIVE
TSSOP
PW
16
92
TBD
CU SNPB
Level-1-260C-UNLIM
LM5000-3MTC/NOPB
ACTIVE
TSSOP
PW
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5000-3MTCX
ACTIVE
TSSOP
PW
16
2500
TBD
CU SNPB
Level-1-260C-UNLIM
LM5000-3MTCX/NOPB
ACTIVE
TSSOP
PW
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5000SD-3
ACTIVE
WSON
NHQ
16
1000
TBD
CU SNPB
Level-1-260C-UNLIM
LM5000SD-3/NOPB
ACTIVE
WSON
NHQ
16
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5000SD-6
ACTIVE
WSON
NHQ
16
1000
TBD
CU SNPB
Level-1-260C-UNLIM
LM5000SD-6/NOPB
ACTIVE
WSON
NHQ
16
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5000SDX-3
ACTIVE
WSON
NHQ
16
4500
TBD
CU SNPB
Level-1-260C-UNLIM
LM5000SDX-3/NOPB
ACTIVE
WSON
NHQ
16
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5000SDX-6
ACTIVE
WSON
NHQ
16
4500
TBD
CU SNPB
Level-1-260C-UNLIM
LM5000SDX-6/NOPB
ACTIVE
WSON
NHQ
16
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
17-Nov-2012
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LM5000-3MTCX
TSSOP
LM5000-3MTCX/NOPB
LM5000SD-3
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
PW
16
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
TSSOP
PW
16
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
WSON
NHQ
16
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
LM5000SD-3/NOPB
WSON
NHQ
16
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
LM5000SD-6
WSON
NHQ
16
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
LM5000SD-6/NOPB
WSON
NHQ
16
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
LM5000SDX-3
WSON
NHQ
16
4500
330.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
LM5000SDX-3/NOPB
WSON
NHQ
16
4500
330.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
LM5000SDX-6
WSON
NHQ
16
4500
330.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
LM5000SDX-6/NOPB
WSON
NHQ
16
4500
330.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5000-3MTCX
TSSOP
PW
16
2500
349.0
337.0
45.0
LM5000-3MTCX/NOPB
TSSOP
PW
16
2500
349.0
337.0
45.0
LM5000SD-3
WSON
NHQ
16
1000
203.0
190.0
41.0
LM5000SD-3/NOPB
WSON
NHQ
16
1000
203.0
190.0
41.0
LM5000SD-6
WSON
NHQ
16
1000
203.0
190.0
41.0
LM5000SD-6/NOPB
WSON
NHQ
16
1000
203.0
190.0
41.0
LM5000SDX-3
WSON
NHQ
16
4500
349.0
337.0
45.0
LM5000SDX-3/NOPB
WSON
NHQ
16
4500
349.0
337.0
45.0
LM5000SDX-6
WSON
NHQ
16
4500
349.0
337.0
45.0
LM5000SDX-6/NOPB
WSON
NHQ
16
4500
349.0
337.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
NHQ0016A
SDA16A (Rev A)
www.ti.com
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Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
LM5000-3MTC LM5000-3MTC/NOPB LM5000-3MTCX LM5000-3MTCX/NOPB LM5000EVAL LM5000SD-3
LM5000SD-3/NOPB LM5000SD-6 LM5000SD-6/NOPB LM5000SDX-3 LM5000SDX-3/NOPB LM5000SDX-6
LM5000SDX-6/NOPB