ICST ICS9250-27 Frequency generator & integrated buffers for celeron & pii/iiiâ ¢ Datasheet

Integrated
Circuit
Systems, Inc.
ICS9250-27
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Pin Configuration
*FS2//REF0
VDD
X1
X2
GND
GND
3V66-0
3V66-1
3V66-2
VDD
VDD
PCICLK_F
PCICLK0
GND
PCICLK1
PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
VDD
VDD
GND
GND
48MHz_0
48MHz_1
VDD
FS0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ICS9250-27
Recommended Application:
810/810E and 815 type chipset.
Output Features:
•
3 CPU (2.5V) (up to 133MHz achievable through I2C)
•
9 SDRAM (3.3V) (up to 133MHz achievable
through I2C)
•
7 PCI (3.3 V) @33.3MHz
•
2 IOAPIC (2.5V) @ 33.3 MHz
•
3 Hublink clocks (3.3 V) @ 66.6 MHz
•
2 (3.3V) @ 48 MHz (Non spread spectrum)
•
1 REF (3.3V) @ 14.318 MHz
Features:
•
Supports spread spectrum modulation,
0 to -0.5% down spread.
•
I2C support for power management
•
Efficient power management scheme through PD#
•
Uses external 14.138 MHz crystal
•
Alternate frequency selections available through I2C
control.
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
IOAPIC0
IOAPIC1
VDDL
CPUCLK0
VDDL0
CPUCLK1
CPUCLK2
GNDL
GND
SDRAM0
SDRAM1
VDD
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD
SDRAM6
SDRAM7
GND
SDRAM_F
VDD
PD#
SCLK
SDATA
FS1
56-Pin 300mil SSOP
* This input has a 50KΩ pull-down to GND.
Block Diagram
Functionality
X1
X2
XTAL
OSC
REF0
PLL1
Spread
Spectrum
/2
/3
VDDL
3
FS (2:0)
PD#
3
Control
Logic
8
/2
SCLK
6
Config
Reg
3V66 (2:0)
PLL2
2
2
FS0
X
X
0
0
0
1
0
1
0
0
1
1
1
1
0
1
1
1
SDRAM (7:0)
PCICLK (5:0)
PCICLK_F
/2
FS1
CPU66/100/133 (2:0)
SDRAM_F
SDATA
FS2
IOAPIC (1:0)
VDDL
48MHz (1:0)
9250-27 Rev B 02/15/01
Third party brands and names are the property of their respective owners.
Function
Tristate
Test
Active CPU = 66MHz
SDRAM = 100MHz
Active CPU = 100MHz
SDRAM = 100MHz
Active CPU = 133MHz
SDRAM = 133MHz
Active CPU = 133MHz
SDRAM = 100MHz
Power Groups
AVDD = Pin 22 Analog power for PLL
AGND = Pin 23 Analog ground
VDD48 = Pin 27 Analog power for 48MHz PLL
GND = Pin 24 Analog ground for 48MHz PLL
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9250-27
General Description
The ICS9250-27 is a single chip clock solution for 810/810E and 815 type chipset. It provides all necessary clock
signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10
dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS925027 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Pin Configuration
PIN NUMBER
1
P I N NA M E
FS2
IN
Function Select pin. Determines CPU frequency, all output functionality
3
X1
IN
4
X2
OUT
GND
PWR
Ground pins for 3.3V supply
3V66 (2:0)
OUT
3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B
PWR
3.3V power supply
PCICLK_F
OUT
Free running 3.3V PCI clock output
PCICLK (5:0)
OUT
3.3V PCI clock outputs
25
48MHz_0
OUT
3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s f o r U S B
26
48MHz_1
OUT
9, 8, 7
2, 10, 11, 21,
VDD
22, 27, 33, 38, 44
12
20, 19, 18, 16,
15, 13
OUT
DESCRIPTION
3.3V, 14.318MHz reference clock output.
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
5, 6, 14, 17, 23,
24, 35, 41, 47,
48, 56
REF0
TYPE
29, 28
FS (1:0)
IN
3.3V fixed 48MHz clock output. Stronger output for graphics/video
i n t e r fa c e ( m i n i m u m 1 V / n s e d g e r a t e )
Function Select pins. Determines CPU frequency, all output functionality.
Please refer to Functionality table on page 3.
30
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
31
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
32
PD#
IN
SDRAM (7:0)
OUT
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
3.3V output running 100MHz. All SDRAM outputs can be turned off
t h r o u g h I 2C
SDRAM_F
OUT
3.3V free running 100MHz SDRAM, cannot be turned off through I2C
CPUCLK (2:0)
OUT
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS pins.
51, 53
VDDL
PWR
2.5V power suypply for CPU & IOAPIC
54, 55
IOAPIC (1:0)
OUT
2.5V clock outputs running at 33.3MHz.
36, 37, 39, 40,
42, 43, 45, 46
34
49, 50, 52
2
ICS9250-27
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
All static inputs = Vddq3 or GND
815
Condition
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 3.465V
All static inputs = Vddq3 or GND
Powerdown Mode
(PWRDWN# = 0
10mA
10mA
Full Active 66MHz
FS[2:0] = 010
70mA
280mA
Full Active 100MHz
FS[2:0] = 011
100mA
280mA
Full Active 133MHz
FS[2:0] = 111
Clock Enable Configuration
PD#
CPUCLK
SDRAM
IOAPIC
66MHz
PCICLK
REF,
48MHz
Osc
VCOs
0
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
1
ON
ON
ON
ON
ON
ON
ON
ON
3
ICS9250-27
Truth Table
FS2
FS1
FS0
CPU
SDRAM
3V66
PCI
48MHz
REF
IOAPIC
X
0
0
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
X
0
1
TCLK/2
TCLK/2
TCLK/3
TCLK/6
TCLK/2
TCLK
TCLK/6
0
1
0
66.6 MHz
100 MHz
66.6 MHz
33.3 MHz
48 MHz
14.318 MHz
33.3 MHz
0
1
1
100 MHz
100 MHz
66.6 MHz
33.3 MHz
48 MHz
14.318 MHz
33.3 MHz
1
1
0
133 MHz
133 MHz
66.6 MHz
33.3 MHz
48 MHz
14.318 MHz
33.3 MHz
1
1
1
133 MHz
100 MHz
66.6 MHz
33.3 MHz
48 MHz
14.318 MHz
33.3 MHz
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Pin#
Bit 3
Bit 2
Bit 1
Bit 0
26
25
49
Name
Reserved ID
Reserved ID
Reserved ID
Reserved ID
SpreadSpectrum
(1=On/0=Off)
48MHz 1
48MHz 0
CPUCLK2
PWD
0
0
0
0
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
1
(Active/Inactive)
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Note: Reserved ID bits must be wirtten as "0".
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
36
37
39
40
42
43
45
46
Name
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
PWD
1
1
1
1
1
1
1
1
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
4
ICS9250-27
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
9
20
19
18
16
15
13
-
Name
3V66-2 (AGP)
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Undefined bit
PWD
1
1
1
1
1
1
1
X
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit
Desctiption
PWD
Bit7
ICS Reserved bit (Note 2)
0
Bit6
ICS Reserved bit (Note 2)
0
Bit5
ICS Reserved bit (Note 2)
0
Bit4
ICS Reserved bit (Note 2)
0
Bit3
ICS Reserved bit (Note 2)
0
Bit2
Undefined bit (Note 3)
X
Bit1
Undefined bit (Note 3)
X
Bit 0
CPUCLK SDRAM
MHz
MHz
3V66
MHz
PCICLK IOAPIC
MHz
MHz
Bit 0
FS0
FS1
0
0
0
66.66
100.0
66.66
33.33
33.33
0
1
0
100.0
100.0
66.66
33.33
33.33
0
0
1
133.32
133.32
66.66
33.33
33.33
0
1
1
133.32
100.0
66.66
33.33
33.33
1
0
0
66.66
100.0
66.66
33.33
33.33
1
1
0
100.0
100.0
66.66
33.33
33.33
1
0
1
133.32
133.32
66.66
33.33
33.33
1
1
1
133.32
133.32
66.66
33.33
33.33
0
Note 1
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always with
SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the default 0 to
1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU is at the
133MHz FSB speed as shown in this table. The CPU, 3v66, PCI, and IOAPIC clocks will be glitch free during this
transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "O".
Note3: Undefined bits can be written either as "1 or 0"
5
ICS9250-27
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
0
0
0
0
0
0
0
0
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
PWD
0
0
0
0
0
0
0
0
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 5: Reserved Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
Group Timing Relationship Table1
Group
CPU 66MHz
SDRAM 100MHz
CPU 100MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 133MHz
Offset
Tolerance
Offset
Tolerance
Offset
Tolerance
Offset
Tolerance
CPU to SDRAM
2.5ns
500ps
5.0ns
500ps
0.0ns
500ps
3.75ns
500ps
CPU to 3V66
7.5ns
500ps
5.0ns
500ps
0.0ns
500ps
0.0ns
500ps
SDRAM to 3V66
0.0ns
500ps
0.0ns
500ps
0.0ns
500ps
3.75ns
500ps
3V66 to PCI
1.5-3.5ns
N/A
1.5-3.5ns
N/A
1.5-3.5ns
N/A
1.5 -3.5ns
N/A
IOAPIC to PCI
USB & DOT
0.0ns
Asynch
1.0ns
N/A
0.0ns
Asynch
1.0ns
N/A
0.0ns
Asynch
1.0ns
N/A
0.0ns
Asynch
1.0ns
N/A
6
ICS9250-27
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Input High Voltage
VIH
2
VSS-0.3
Input Low Voltage
VIL
VIN = VDD
-5
Input High Current
IIH
VIN = 0 V; Inputs with no pull-up resistors
-5
2
IIL1
Input Low Current
VIN = 0 V; Inputs with pull-up resistors
-200
-100
IIL2
97
CL = 0 pF; Select @ 66 MHz
91
CL = 0 pF; Select @ 100 MHz
100
CL = 0 pF; Select @ 133 MHz
IDD3.3OP
295
CL = Max loads; Select @ 66 MHz
280
CL = Max loads; Select @ 100 MHz
Operating Supply
Current
IDD2.5OP
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance1
1
Transition time
1
Settling time
Clk Stabilization1
Delay1
IDD3.3PD
IDD.25PD
Fi
Lpin
CIN
COUT
CINX
MAX
VDD+0.3
0.8
5
µA
115
110
165
330
320
CL = Max loads; Select @ 133 MHz
CL = 0 pF; Select @ 66 MHz
CL = 0 pF; Select @ 100 MHz
CL = 0 pF; Select @ 133 MHz
CL = Max loads; Select @ 66 MHz
CL = Max loads; Select @ 100 MHz
300
16
25
26
19
34
395
19
35
40
30
50
CL = Max loads; Select @ 133 MHz
CL = Max loads
Input address VDD or GND
40
220
<1
70
400
10
14.318
7
16
12
mA
mA
mA
mA
µA
45
MHz
nH
pF
pF
pF
To 1st crossing of target frequency
5
ms
Ts
From 1st crossing to 1% target frequency
5
ms
TSTAB
tPZH,tPZL
tPHZ,tPLZ
From VDD = 3.3 V to 1% target frequency
Output enable delay (all outputs)
Output disable delay (all outputs)
5
10
10
ms
ns
ns
Ttrans
VDD = 3.3 V
UNITS
V
V
µA
Logic Inputs
Output pin capacitance
X1 & X2 pins
5
6
27
1
Guaranteed by design, not 100% tested in production.
7
1
1
ICS9250-27
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
1
RDSN2B
VOH2B
VOL2B
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
13.5
22
45
Ω
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @ MIN = 1.0 V
VOH @ MAX = 2.375 V
VOL @ MIN = 1.2 V
VOL @ MAX = 0.3 V
13.5
2
23
45
Ω
V
V
-27
-68
-9
54
11
0.4
Output High Current
IOH2B
Output Low Current
IOL2B
Rise Time1
tr2B
VOL = 0.4 V, VOH = 2.0 V
0.4
1.1
1.6
ns
1
tf2B
VOH = 2.0 V, VOL = 0.4 V
0.4
1.1
1.6
ns
Duty Cycle1
dt2B
VT = 1.25 V, 66, 100 MHz
VT = 1.25 V, 133 MHz
45
45
50
53
55
55
%
Skew window1
Jitter, Cycle-to-cycle1
tsk2B
VT = 1.25 V
118
175
ps
tjcyc-cyc2B
VT = 1.25 V
148
250
ps
Fall Time
1
RDSP2B
1
27
-27
30
mA
mA
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
1
RDSN1
VOH1
VOL1
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
12
17
55
Ω
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
12
2.4
18
55
Ω
V
V
-33
-108
-9
95
29
0.55
Output High Current
IOH1
Output Low Current
IOL1
Rise Time1
tr1
VOL = 0.4 V, VOH = 2.4 V
0.4
1.2
1.8
ns
Fall Time1
tf1
dt1
VOH = 2.4 V, VOL = 0.4 V
0.4
1.3
1.8
ns
VT = 1.5 V
45
50
55
%
tsk1
VT = 1.5 V
82
175
ps
tjcyc-cyc1
VT = 1.5 V
123
500
ps
1
Duty Cycle
Skew window1
Jitter, Cycle-to-cycle1
1
RDSP1
1
30
Guaranteed by design, not 100% tested in production.
8
-33
38
mA
mA
ICS9250-27
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
RDSP4B
Output Impedance
Output High Voltage
Output Low Voltage
1
RDSN4B
VOH4B
VOL4B
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
9
21.5
30
Ω
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @ MIN = 1.0 V
VOH @ MAX = 2.375 V
VOL @ MIN = 1.2 V
VOL @ MAX = 0.3 V
9
2
23
30
Ω
V
V
-27
-68
-9
54
11
0.4
Output High Current
IOH4B
Output Low Current
IOL4B
Rise Time1
tr4B
VOL = 0.4 V, VOH = 2.0 V
0.4
1.1
1.6
ns
1
tf4B
dt4B
VOH = 2.0 V, VOL = 0.4 V
0.4
1.1
1.6
ns
VT = 1.25 V
45
50
55
%
123
500
ps
Fall Time
1
Duty Cycle
Jitter, Cycle-to-cycle1
1
1
tjcyc-cyc4B
27
VT = 1.25 V
-27
30
mA
mA
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
RDSP3
Output Impedance
Output High Voltage
Output Low Voltage
1
RDSN3
VOH3
VOL3
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
10
14
24
Ω
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @ MIN = 2.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.0 V
VOL @ MAX = 0.4 V
10
2.4
18
24
Ω
V
V
-54
-92
-16
68
29
0.4
Output High Current
IOH3
Output Low Current
IOL3
Rise Time1
tr3
VOL = 0.4 V, VOH = 2.4 V
0.4
1
1.6
ns
1
tf3
dt3
VOH = 2.4 V, VOL = 0.4 V
0.4
1.5
1.6
ns
VT = 1.5 V
45
52
55
%
tsk3
VT = 1.5 V
164
250
ps
VT = 1.5 V, 66, 100 MHz
180
250
ps
Fall Time
1
Duty Cycle
Skew window1
Jitter, Cycle-to-cycle
1
1
1
tjcyc-cyc3
54
Guaranteed by design, not 100% tested in production.
9
-46
53
mA
mA
ICS9250-27
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
1
RDSN1
VOH1
VOL1
MIN
TYP
VO = VDD*(0.5)
12
14
55
Ω
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
12
2.4
18
55
Ω
V
V
-33
-106
-14
94
29
IOH1
Output Low Current
IOL1
Rise Time1
tr1
VOL = 0.4 V, VOH = 2.4 V
0.4
1.3
Fall Time1
tf1
dt1
VOH = 2.4 V, VOL = 0.4 V
0.4
VT = 1.5 V
45
tsk1
tjcyc-cyc1
Duty Cycle
Skew window1
Jitter, Cycle-to-cycle1
MAX UNITS
0.55
Output High Current
1
1
RDSP1
1
30
-33
38
mA
mA
2
ns
1.4
2
ns
52
55
%
VT = 1.5 V
304
500
ps
VT = 1.5 V
170
500
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 25)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
1
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
20
32.6
60
Ω
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
20
2.4
31
60
Ω
V
V
-29
Output Impedance
Output High Voltage
Output Low Voltage
RDSN5
VOH15
VOL5
Output High Current
IOH5
Output Low Current
IOL5
Rise Time1
tr5
VOL = 0.4 V, VOH = 2.4 V
0.4
1.4
4
ns
1
tf5
dt5
VOH = 2.4 V, VOL = 0.4 V
0.4
1.7
4
ns
VT = 1.5 V
45
53
55
%
tjcyc-cyc5
VT = 1.5 V, Fixed clocks
215
500
ps
tjcyc-cyc5
VT = 1.5 V, Ref clocks
930
1000
ps
Fall Time
1
Duty Cycle
Jitter, Cycle-to-cycle1
Jitter, Cycle-to-cycle1
1
RDSP5
1
0.55
29
Guaranteed by design, not 100% tested in production.
10
-54
-11
54
16
-23
27
mA
mA
ICS9250-27
Electrical Characteristics - 48MHz_1 (Pin 26)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-15 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
1
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
10
16.7
24
Ω
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @ MIN = 2.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.0 V
VOL @ MAX = 0.4 V
10
2.4
18.4
24
Ω
V
V
-54
Output Impedance
Output High Voltage
Output Low Voltage
RDSN3
VOH3
VOL3
Output High Current
IOH3
Output Low Current
IOL3
Rise Time1
tr3
VOL = 0.4 V, VOH = 2.4 V
0.4
1.1
1.6
ns
1
tf3
dt3
tsk3
VOH = 2.4 V, VOL = 0.4 V
0.4
1.1
1.6
ns
VT = 1.5 V
VT = 1.5 V
45
51
116
55
250
%
ps
196
500
ps
Fall Time
1
Duty Cycle
Skew
Jitter, Cycle-to-cycle1
1
RDSP3
1
tjcyc-cyc3B
0.55
54
VT = 1.5 V
Guaranteed by design, not 100% tested in production.
11
-82
-20
95
28
-46
53
mA
mA
ICS9250-27
0ns
10ns
20ns
30ns
Cycle Repeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
SDRAM 133MHz
3.3V 66MHz
PCI 33MHz
IOAPIC 33MHz
REF 14.318MHz
USB 48MHz
Group Offset Waveforms
12
40ns
ICS9250-27
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ICS (Slave/Receiver)
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
13
ICS9250-27
SY MBOL
In Millimeters
COMMON DIMENSIONS
MIN
MA X
In Inches
COMMON DIMENSIONS
MIN
MA X
A
2.413
2.794
.095
.110
A1
0.203
0.406
.008
.016
b
0.203
0.343
.008
.0135
c
D
0.127
0.254
SEE V A RIA TIONS
.005
.010
SEE V A RIA TIONS
E
10.033
10.668
.395
.420
E1
7.391
7.595
.291
.299
e
0.635 BA SIC
h
0.381
L
0.508
1.016
SEE V A RIA TIONS
N
α
0.635
0°
0.025 BA SIC
.015
.025
.020
.040
SEE V A RIA TIONS
8°
0°
8°
MIN
MA X
MIN
MA X
28
9.398
9.652
.370
.380
34
11.303
11.557
.445
.455
48
15.748
16.002
.620
.630
56
18.288
18.542
.720
.730
20.828
21.082
V A RIA TIONS
D mm.
N
64
D (inch)
.820
.830
J EDEC M O- 118
6/ 1/ 00
DOC# 10- 0034
REV B
Ordering Information
ICS9250yF-27-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
14
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
Similar pages